Texas Instruments | TLV5614-EP | Datasheet | Texas Instruments TLV5614-EP Datasheet

Texas Instruments TLV5614-EP Datasheet
µ SGLS355 − JUNE 2006
D Controlled Baseline
D
D
D
D
D
D
D
D
D
D
D
− One Assembly
− One Test Site
− One Fabrication Site
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
Four 12-Bit Digital-to-Analog Converters
(DACs)
Programmable Settling Time of Either 3 µs
or 9 µs (Typ)
TMS320E DSP Family, (Q)SPI, and
Microwire Compatible Serial Interface
Internal Power-On Reset
Low Power Consumption:
8 mW, Slow Mode − 5-V Supply
3.6 mW, Slow Mode − 3-V Supply
Reference Input Buffer
Voltage Output Range . . . 2× the Reference
Input Voltage
D Monotonic Overtemperature
D Dual 2.7-V to 5.5-V Supply (Separate Digital
and Analog Supplies)
D Hardware Power Down (10 nA)
D Software Power Down (10 nA)
D Simultaneous Update
applications
D
D
D
D
D
D
Battery-Powered Test Instruments
Digital Offset and Gain Adjustment
Industrial Process Controls
Machine and Motion Control Devices
Communications
Arbitrary Waveform Generation
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
PW PACKAGE
(TOP VIEW)
description
DVDD
PD
LDAC
DIN
SCLK
CS
FS
DGND
1
16
AVDD
REFINAB
OUTA
OUTB
OUTC
OUTD
REFINCD
AGND
15
2
The TLV5614 is a quadruple 12-bit voltage output
14
3
digital-to-analog converter (DAC) with a flexible
13
4
four-wire serial interface. The four-wire serial
12
5
interface allows glueless interface to TMS320
11
6
DSP family, SPI, QSPI, and Microwire serial
10
7
ports. The TLV5614 is programmed with a 16-bit
9
8
serial word comprised of a DAC address,
individual DAC control bits, and a 12-bit DAC
value. The device has provision for two supplies
– one digital supply for the serial interface (via pins
DVDD and DGND), and one for the DACs,
reference buffers, and output buffers (via pins AVDD and AGND). Each supply is independent of the other and
can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC is
controlled via a microprocessor operating on a 3-V supply (also used on pins DVDD and DGND), with the DACs
operating on a 5-V supply. The digital and analog supplies can be tied together.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
Copyright  2006, Texas Instruments Incorporated
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%$,$", /$""$%0 "!,'&%! )"!&(1 ,!( !% (&($"+0 &+',(
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description (continued)
The resistor string output voltage is buffered by a 2× gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode
makes it ideal for single-voltage, battery-based applications. The settling time of the DAC is programmable to
allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits
within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD
terminals to reduce the need for a low source-impedance drive to the terminal. REFINAB and REFINCD allow
DAC A and B to have a different reference voltage than DAC C and D.
The TLV5614 is implemented with a CMOS process and is available in a 16-terminal TSSOP package. The
TLV5614M is characterized for operation from −55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
2
TA
TSSOP (PW)
−55°C to 125°C
TLV5614MPWREP
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functional block diagram
AVDD
REFINAB
15
DVDD
16
1
DAC A
+
_
Power-On
Reset
DIN
4
Serial
Input
Register
14
+
_
14-Bit
Data
and
Control
Register
12
12-Bit
DAC
Latch
2
2-Bit
Control
Data
Latch
14
OUTA
10
2
2
Power Down/
Speed Control
2
7
FS
SCLK
CS
REFINCD
5
6
DAC Select/
Control
Logic
13
DAC B
DAC C
12
DAC D
11
OUTB
OUTC
10
3
9
AGND
OUTD
2
8
DGND
LDAC
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PD
3
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Terminal Functions
TERMINAL
NAME
NO.
AGND
9
AVDD
CS
16
DGND
8
DIN
4
DVDD
1
6
I/O
DESCRIPTION
Analog ground
Analog supply
I
Chip select. This terminal is active low.
Digital ground
I
Serial data input
Digital supply
7
I
Frame synchronization. The falling edge of the frame synchronization pulse indicates the start of a serial data frame
shifted out to the TLV5614.
2
I
Power down. Powers down all DACs (overriding their individual power down settings) and all output stages. This
terminal is active low.
3
I
Load DAC. When LDAC is high, no DAC output updates occur when the input digital data is read into the serial
interface. The DAC outputs are only updated when LDAC is low.
REFINAB
15
I
Voltage reference input for DAC A and B
REFINCD
10
I
Voltage reference input for DAC C and D
FS
PD
LDAC
SCLK
5
I
Serial clock input
OUTA
14
O
DAC A
OUTB
13
O
DAC B
OUTC
12
O
DAC C
OUTD
11
O
DAC D
10000
Wirebond Voiding Fail Mode
Years Estimated Life
1000
100
Electromigration Fail Mode
10
1
80
90
100
110
120
Continuous TJ − 5C
Figure 1. Operating Life Derating Chart
4
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130
140
150
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, (DVDD, AVDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Supply voltage difference (AVDD to DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2.8 V to 2.8 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Supply voltage, AVDD, DVDD
High-level digital input voltage, VIH
Low-level digital input voltage, VIL
Reference voltage, Vref to REFINAB, REFINCD terminal
MIN
NOM
MAX
5-V supply
4.5
5
5.5
3-V supply
2.7
3
3.3
DVDD = 2.7 V
2
DVDD = 5.5 V
2.4
0.6
DVDD = 5.5 V
1
5-V supply, See Note 1
0
2.048
3-V supply, See Note 1
0
1.024
2
10
Load capacitance, CL
Serial clock rate, SCLK
Operating free-air temperature
−55
Package thermal resistance, junction to ambient, θJA
V
V
DVDD = 2.7 V
Load resistance, RL
UNIT
108.4
VDD − 1.5
VDD − 1.5
V
V
kΩ
100
pF
20
MHz
125
°C/W
°C/W
NOTE 1: Voltages greater than AVDD/2 cause output saturation for large DAC codes.
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electrical characteristics over recommended operating free-air temperature range, Vref = 2.048 V,
AVDD = DVDD = 5 V and Vref = 1.024 V for AVDD = DVDD = 3 V (unless otherwise noted)
static DAC specifications
PARAMETER
TEST CONDITIONS
MIN
Resolution
EZS
EG
TYP
MAX
UNIT
±4
LSB
±1
LSB
12
bits
Integral nonlinearity (INL), end point adjusted
See Note 1
±1.5
Differential nonlinearity (DNL)
See Note 2
±0.5
Zero-scale error (offset error at zero scale)
See Note 3
Zero-scale error temperature coefficient
See Note 4
Gain error
See Note 5
Gain-error temperature coefficient
See Note 6
±12
10
±0.7
Zero scale
PSRR
Power-supply rejection ratio
Full scale
See Note 7 and Note 8
mV
ppm/°C
% of FS
voltage
10
ppm/°C
−80
dB
−80
dB
NOTES: 1. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
2. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal
1-LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) − EZS (Tmin)E/Vref × 106/(Tmax − Tmin).
5. Gain error is the deviation from the ideal output (2 Vref − 1 LSB) with an output load of 10 kΩ, excluding the effects of the zero error.
6. Gain temperature coefficient is given by: EG TC = [EG(Tmax) − EG (Tmin)]/Vref × 106/(Tmax − Tmin).
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the AVDD from 5 ± 0.5 V and 3 ± 0.3 V dc, and measuring the
proportion of this signal imposed on the zero-code output voltage.
8. Full-scale rejection ratio (EG-RR) is measured by varying the AVDD from 5 ± 0.5 V and 3 ± 0.3 V dc and measuring the proportion
of this signal imposed on the full-scale output voltage after subtracting the zero-scale change.
individual DAC output specifications
PARAMETER
VO
TEST CONDITIONS
Voltage output range
RL = 10 kΩ
Output load regulation accuracy
RL = 2 kΩ vs 10 kΩ
MIN
TYP
0
MAX
AVDD−0.4
0.1
UNIT
V
0.25
% of FS
voltage
MAX
UNIT
reference inputs (REFINAB, REFINCD)
PARAMETER
VI
RI
Input voltage range
CI
Input capacitance
TEST CONDITIONS
MIN
See Note 1
TYP
0
Input resistance
Reference feed through
REFIN = 1 VPP at 1 kHz + 1.024 Vdc
(see Note 2)
Reference input bandwidth
REFIN = 0.2 VPP + 1.024-Vdc large signal
AVDD−1.5
V
10
MΩ
5
pF
−75
dB
Slow
0.5
Fast
1
MHz
NOTES: 1. Reference input voltages greater than VDD/2 cause output saturation for large DAC codes.
2. Reference feedthrough is measured at the DAC output, with an input code = 000 hex and a Vref (REFINAB or REFINCD)
input = 1.024 Vdc + 1 VPP at 1 kHz.
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electrical characteristics over recommended operating free-air temperature range, Vref = 2.048 V,
AVDD = DVDD = 5 V and Vref = 1.024 V for AVDD = DVDD = 3 V (unless otherwise noted) (continued)
digital inputs (DIN, CS, LDAC, PD)
PARAMETER
IIH
IIL
High-level digital input current
CI
Input capacitance
TEST CONDITIONS
MIN
TYP
VI = VDD
VI = 0 V
Low-level digital input current
MAX
UNIT
±1
µA
±1
µA
3
pF
power supply
PARAMETER
IDD
TEST CONDITIONS
Power-supply current
TYP
MAX
5-V supply,
No load, Clock running,
All inputs 0 V or VDD
Slow
MIN
1.6
2.4
Fast
3.8
5.6
3-V supply,
No load, Clock running,
All inputs 0 V or DVDD
Slow
1.2
1.8
Fast
3.2
4.8
UNIT
mA
Power-down supply current (see Figure 13)
10
nA
analog output dynamic performance
PARAMETER
SR
Output slew rate
TEST CONDITIONS
TYP
UNIT
CL = 100 pF, RL = 10 kΩ,
VO = 10% to 90%,
Vref = 2.048 V, 1024 V
Fast
5
V/µs
Slow
1
V/µs
3
Output settling time
To ±0.5 LSB, CL = 100 pF,
RL = 10 kΩ, See Note 1
Fast
ts
Slow
9
1
Output settling time, code to code
To ±0.5 LSB, CL = 100 pF,
RL = 10 kΩ, See Note 2
Fast
ts(c)
Slow
2
Glitch energy
Code transition from 7FF to 800
SNR
Signal-to-noise ratio
S/(N+D)
Signal-to-noise + distortion
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range
Sine wave generated by DAC,
Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
fs = 400 KSPS, fOUT = 1.1-kHz sine wave,
CL = 100 pF, RL = 10 kΩ, BW = 20 kHz
µss
µss
10
nV-s
74
dB
66
dB
−68
dB
70
dB
NOTES: 1. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of FFF hex to 080 hex for 080 hex to FFF hex.
2. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of one count.
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electrical characteristics over recommended operating free-air temperature range, Vref = 2.048 V,
AVDD = DVDD = 5 V and Vref = 1.024 V for AVDD = DVDD = 3 V (unless otherwise noted) (continued)
digital input timing requirements
MIN
tsu(CS−FS)
tsu(FS−CK)
Setup time, CS low before FS↓
Setup time, FS low before first negative SCLK edge
NOM
MAX
UNIT
10
ns
8
ns
tsu(C16−FS)
Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before
rising edge of FS
10
ns
tsu(C16−CS)
Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS
is used instead of the SCLK positive edge to update the DAC, then the setup time is between
the FS rising edge and CS rising edge.
10
ns
twH
twL
Pulse duration, SCLK high
25
ns
Pulse duration, SCLK low
25
ns
tsu(D)
Setup time, data ready before SCLK falling edge
8
ns
th(D)
twH(FS)
Hold time, data held valid after SCLK falling edge
5
ns
Pulse duration, FS high
60
ns
PARAMETER MEASUREMENT INFORMATION
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
SCLK
1
2
tsu(D)
DIN
twH
twL
3
4
5
15
16
th(D)
D15
D14
D13
D12
tsu(FS-CK)
D1
D0
tsu(C16-CS)
tsu(CS-FS)
CS
twH(FS)
tsu(C16-FS)
FS
Figure 2. Timing Diagram
8
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
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TYPICAL CHARACTERISTICS
LOAD REGULATION
LOAD REGULATION
0.2
0.35
VDD = 3 V
Vref = 1 V
VO = Full Scale
0.18
0.16
0.30
0.25
VO − Output − V
0.14
VO − Output − V
VDD = 5 V
Vref = 2 V
VO = Full Scale
3-V Slow Mode, Sink
0.12
0.10
3-V Fast Mode, Sink
0.08
0.06
5-V Slow Mode, Sink
0.20
5-V Fast Mode, Sink
0.15
0.10
0.04
0.05
0.02
0
0
0
0.01 0.02 0.05 0.1
0.2
0.5
0.8
1
2
0
Load Current − mA
0.02 0.04 0.1 0.2 0.4 0.8
Load Current − mA
Figure 3
1
2
4
Figure 4
LOAD REGULATION
LOAD REGULATION
4.01
2.0015
5-V Slow Mode, Source
3-V Slow Mode, Source
2.001
4.005
2.0005
VO − Output − V
VO − Output − V
2.000
4
5-V Fast Mode, Source
3.995
3-V Fast Mode, Source
1.9995
1.999
1.9985
1.998
3.99
1.9975
VDD = 5 V
Vref = 2 V
VO = Full Scale
1.997
3.985
0
0.02 0.04 0.1 0.2 0.4 0.8
Load Current − mA
1
2
VDD = 3 V
Vref = 1 V
VO = Full Scale
4
1.9965
0
0.01 0.02 0.05 0.1 0.2 0.5
Load Current − mA
Figure 5
0.8
1
2
Figure 6
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
TEMPERATURE
4
3.5
I DD − Supply Current − mA
3.5
I DD − Supply Current − mA
4
VDD = 3 V
Vref = 1.024 V
VO Full Scale
(Worst Case for IDD)
Fast Mode
3
2.5
2
1.5
1
3
−20
0
20
VDD = 5 V
Vref = 1.024 V
VO Full Scale
(Worst Case for IDD)
2.5
2
1.5
Slow Mode
0.5
−40
Fast Mode
Slow Mode
1
40
60
80
0.5
−40
100
−20
T − Temperature − °C
Figure 7
100
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
0
Vref = 1-V dc + 1-VPP Sine Wave
Output Full Scale
−10
THD − Total Harmonic Distortion − dB
THD − Total Harmonic Distortion − dB
80
Figure 8
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
−20
−30
−−40
−50
−60
Fast Mode
−70
−80
0
5
10
20
30
50
100
Vref = 1-V dc + 1-VPP Sine Wave
Output Full Scale
−10
−20
−30
−−40
−50
−60
Slow Mode
−70
−80
0
5
f − Frequency − kHz
10
20
Figure 10
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f − Frequency − kHz
Figure 9
10
0
20
40
60
T − Temperature − °C
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50
100
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TYPICAL CHARACTERISTICS
Vref = 1-V dc + 1-VPP Sine Wave
Output Full Scale
−10
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
THD − Total Harmonic Distortion And Noise − dB
0
−20
−30
−−40
−50
Fast Mode
−60
−70
−80
0
Vref = 1-V dc + 1-VPP Sine Wave,
Output Full Scale
−10
−20
−30
−−40
−50
Slow Mode
−60
−70
−80
0
5
10
30
20
50
100
0
5
10
f − Frequency − kHz
20
30
50
100
f − Frequency − kHz
Figure 11
Figure 12
SUPPLY CURRENT
vs
TIME
(WHEN ENTERING POWER-DOWN MODE)
4000
3500
I DD − Supply Current − µ A
THD − Total Harmonic Distortion And Noise − dB
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
3000
2500
2000
1500
1000
500
0
0
200
400
600
800
1000
t − Time − ns
Figure 13
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DNL − Differential Nonlinearity − LSB
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
0.3
0.25
0.2
0.15
0.1
0.05
0
−0.05
−0.1
−0.15
−0.2
−0.25
−0.3
VCC = 5 V, Vref = 2 V, SCLK = 1 MHz)
0
256 512
768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096
Digital Code
Figure 14
INL − Integral Nonlinearity − LSB
INTEGRAL NONLINEARITY
1
VCC = 5 V, Vref = 2 V,
SCLK = 1 MHz
0.5
0
−0.5
−1
−1.5
0
256 512
768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096
Digital Code
Figure 15
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APPLICATION INFORMATION
general function
The TLV5614 is a 12-bit single-supply DAC based on a resistor string architecture. The device consists of a
serial interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail
output buffer.
The output voltage (full scale determined by external reference) is given by:
2 REF CODE
[V]
2n
where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n−1, where
n = 12 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data
format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS
starts shifting the data bit per bit (starting with the MSB) to the internal register on the falling edges of SCLK.
After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which
updates the voltage output to the new level.
The serial interface of the TLV5614 can be used in two basic modes:
D Four wire (with chip select)
D Three wire (without chip select)
Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of
the data source (DSP or microcontroller). The interface is compatible with the TMS320 DSP family. Figure 16
shows an example with two TLV5614s connected directly to a TMS320 DSP.
TLV5614
TLV5614
CS FS DIN SCLK
CS FS DIN SCLK
TMS320
DSP
XF0
XF1
FSX
DX
CLKX
Figure 16. TMS320E Interface
TMS320 is a trademark of Texas Instruments.
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APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 17 shows
an example of how to connect the TLV5614 to a TMS320, SPI, or Microwire port using only three pins.
TMS320
DSP
TLV5614
FSX
SPI
FS
DIN
DX
CLKX
TLV5614
FS
DIN
SS
MOSI
SCLK
SCLK
Microwire
FS
DIN
I/O
SO
SK
SCLK
CS
TLV5614
SCLK
CS
CS
Figure 17. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5614. After the write operation(s), the DAC output is updated automatically
on the next positive clock edge, following the sixteenth falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
SCLKmax
+
t
wH(min)
1
)t
+ 20 MHz
wL(min)
The maximum update rate is:
f
UPDATEmax
+
1
ǒ wH(min) ) twL(min)Ǔ
+ 1.25 MHz
16 t
Note that the maximum update rate is a theoretical value for the serial interface, since the settling time of the
TLV5614 has to be considered also.
data format
The 16-bit data word for the TLV5614 consists of two parts:
D Control bits
D New DAC value
D15
D14
D13
D12
A1
A0
PWR
SPD
X: Don’t care
SPD: Speed control bit:
PWR: Power control bit:
14
(D15 . . . D12)
(D11 . . . D0)
D11
1 → fast mode
1 → power down
D10
D9
D8
D7
D6
D5
D4
New DAC value (12 bits)
0 → slow mode
0 → normal operation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
D3
D2
D1
D0
µ SGLS355 − JUNE 2006
APPLICATION INFORMATION
data format (continued)
In power-down mode, all amplifiers within the TLV5614 are disabled. A particular DAC (A, B, C, D) of the
TLV5614 is selected by A1 and A0 within the input word.
A1
A0
DAC
0
0
A
0
1
B
1
0
C
1
1
D
TLV5614 interfaced to TMS320C203 DSP
hardware interfacing
Figure 18 shows an example of how to connect the TLV5614 to a TMS320C203 DSP. The serial port is
configured in burst mode, with FSX generated by the TMS320C203 to provide the frame synchronization (FS)
input to the TLV5614. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The
general-purpose input/output port bits, IO0 and IO1, are used to generate the chip select (CS) and DAC latch
update (LDAC) inputs to the TLV5614. The active-low power down (PD) is pulled high all the time to ensure the
DACs are enabled.
TMS320C203
TLV5614
SDIN
DX
SCLK
CLKX
FSX
FS
I/O 0
CS
I/O 1
LDAC
VDD
PD
VOUTA
VOUTB
REF
REFINAB
VOUTC
REFINCD
VOUTD
VSS
Figure 18. TLV5614 Interfaced With TMS320C203
software
The application example outputs a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and
its quadrature (cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses
LDAC low to update all four DACs simultaneously, then fetches and writes the next sample to all four DACs.
The samples are stored in a look-up table, which describes two full periods of a sine wave.
The synchronous serial port of the DSP is used in burst mode. In this mode, the processor generates an FS
pulse preceding the MSB of every data word. If multiple, contiguous words are transmitted, a violation of the
tsu(C16−FS) timing requirement occurs. To avoid this, the program waits until the transmission of the previous
word has been completed.
POST OFFICE BOX 655303
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15
µ SGLS355 − JUNE 2006
APPLICATION INFORMATION
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Processor: TMS320C203 running at 40 MHz
;
; Description:
;
; This program generates a differential in−phase (sine) on (OUTA−OUTB) and it’s
; quadrature (cosine) as a differential signal on (OUTC−OUTD).
;
; The DAC codes for the signal samples are stored as a table of 64 12−bit values,
; describing 2 periods of a sine function. A rolling pointer is used to address the
; table location in the first period of this waveform, from which the DAC A samples
; are read. The samples for the other 3 DACs are read at an offset to this rolling
; pointer:
; DAC
Function
Offset from rolling pointer
;
A
sine
0
;
B
inverse sine 16
;
C
cosine
8
;
D
inverse cosine24
;
; The on−chip timer is used to generate interrupts at a fixed rate. The interrupt
; service routine first pulses LDAC low to update all DACs simultaneously
; with the values which were written to them in the previous interrupt. Then all
; 4 DAC values are fetched and written out through the synchronous serial interface
; Finally, the rolling pointer is incremented to address the next sample, ready for
; the next interrupt.
;
;  1998, Texas Instruments Inc.
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− I/O and memory mapped regs −−−−−−−−−−−−−−−−−−−−−−−−−−−−−
.include ”regs.asm”
;−−−−−−−jump vectors −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
.ps
0h
b
start
b
int1
b
int23
b
timer_isr;
−−−−−−−−−−− variables −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
temp
.equ
0060h
r_ptr
.equ
0061h
iosr_stat
.equ
0062h
DACa_ptr
.equ
0063h
DACb_ptr
.equ
0064h
DACc_ptr
.equ
0065h
DACd_ptr
.equ
0066h
;−−−−−−−−−−−constants−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; DAC control bits to be OR’ed onto data
; all fast mode
DACa_control .equ
01000h
DACb_control .equ
05000h
DACc_control .equ
09000h
DACd_control .equ
0d000h
;−−−−−−−−−−− tables −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
.ds
02000h
sinevals
.word 00800h
.word 0097Ch
.word 00AE9h
.word 00C3Ah
.word 00D61h
.word 00E53h
.word 00F07h
.word 00F76h
.word 00F9Ch
.word 00F76h
.word 00F07h
.word 00E53h
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SGLS355 − JUNE 2006
APPLICATION INFORMATION
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
00D61h
00C3Ah
00AE9h
0097Ch
00800h
00684h
00517h
003C6h
0029Fh
001ADh
000F9h
0008Ah
00064h
0008Ah
000F9h
001ADh
0029Fh
003C6h
00517h
00684h
00800h
0097Ch
00AE9h
00C3Ah
00D61h
00E53h
00F07h
00F76h
00F9Ch
00F76h
00F07h
00E53h
00D61h
00C3Ah
00AE9h
0097Ch
00800h
00684h
00517h
003C6h
0029Fh
001ADh
000F9h
0008Ah
00064h
0008Ah
000F9h
001ADh
0029Fh
003C6h
00517h
00684h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
µ SGLS355 − JUNE 2006
APPLICATION INFORMATION
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Main Program
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
.ps
1000h
.entry
start
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; disable interrupts
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
setc
INTM
; disable maskable interrupts
splk
#0ffffh, IFR; clear all interrupts
splk
#0004h, IMR; timer interrupts unmasked
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; set up the timer
; timer period set by values in PRD and TDDR
; period = (CLKOUT1 period) x (1+PRD) x (1+TDDR)
; examples for TMS320C203 with 40MHz main clock
; Timer rate
TDDR
PRD
; 80 kHz
9
24 (18h)
; 50 kHz
9
39 (27h)
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
prd_val.equ
0018h
tcr_val.equ
0029h
splk
#0000h, temp; clear timer
out
temp, TIM
splk
#prd_val, temp; set PRD
out
temp, PRD
splk
#tcr_val, temp; set TDDR, and TRB=1 for auto−reload
out
temp, TCR
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Configure IO0/1 as outputs to be :
; IO0 CS − and set high
; IO1 LDAC
− and set high
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
in
temp, ASPCR; configure as output
lacl
temp
or
#0003h
sacl
temp
out
temp, ASPCR
in
temp, IOSR; set them high
lacl
temp
or
#0003h
sacl
temp
out
temp, IOSR
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; set up serial port for
; SSPCR.TXM=1
Transmit mode − generate FSX
; SSPCR.MCM=1
Clock mode − internal clock source
; SSPCR.FSM=1
Burst mode
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
splk
#0000Eh, temp
out
temp, SSPCR; reset transmitter
splk
#0002Eh, temp
out
temp,SSPCR
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; reset the rolling pointer
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
lacl
#000h
sacl
r_ptr
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; enable interrupts
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
clrc
INTM
; enable maskable interrupts
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; loop forever!
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SGLS355 − JUNE 2006
APPLICATION INFORMATION
next
idle
;wait for interrupt
b
next
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; all else fails stop here
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
done
b
done
;hang there
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Interrupt Service Routines
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
int1
ret
; do nothing and return
int23 ret
; do nothing and return
timer_isr:
in
iosr_stat, IOSR; store IOSR value into variable space
lacl
iosr_stat
; load acc with iosr status
and
#0FFFDh
; reset IO1 − LDAC low
sacl
temp
;
out
temp, IOSR
;
or
#0002h
; set IO1 − LDAC high
sacl
temp
;
out
temp, IOSR
;
and
#0FFFEh
; reset IO0 − CS low
sacl
temp
;
out
temp, IOSR
;
lacl
r_ptr
; load rolling pointer to accumulator
add
#sinevals
; add pointer to table start
sacl
DACa_ptr
; to get a pointer for next DAC a sample
add
#08h
; add 8 to get to DAC C pointer
sacl
DACc_ptr
add
#08h
; add 8 to get to DAC B pointer
sacl
DACb_ptr
add
#08h
; add 8 to get to DAC D pointer
sacl
DACd_ptr
mar
*,ar0
; set ar0 as current AR
; DAC A
lar
ar0, DACa_ptr ; ar0 points to DAC a sample
lacl
*
; get DAC a sample into accumulator
or
#DACa_control ; OR in DAC A control bits
sacl
temp
;
out
temp, SDTR
; send data
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; We must wait for transmission to complete before writing next word to the SDTR.;
TLV5614/04 interface does not allow the use of burst mode with the full packet; rate, as
we need a CLKX −ve edge to clock in last bit before FS goes high again,; to allow SPI
compatibility.
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
rpt
#016h
; wait long enough for this configuration
nop
; of MCLK/CLKOUT1 rate
; DAC
lar
lacl
or
sacl
out
rpt
nop
; DAC C
lar
lacl
or
sacl
out
rpt
nop
B
ar0, dacb_ptr ;
*
;
#DACb_control ;
temp
;
temp, SDTR
;
#016h
;
;
ar0, dacc_ptr ;
*
;
#DACc_control ;
temp
;
temp, SDTR;
#016h
;
;
ar0 points to DAC a sample
get DAC a sample into accumulator
OR in DAC B control bits
send data
wait long enough for this configuration
of MCLK/CLKOUT1 rate
ar0 points to dac a sample
get DAC a sample into accumulator
OR in DAC C control bits
send data
wait long enough for this configuration
of MCLK/CLKOUT1 rate
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
µ SGLS355 − JUNE 2006
APPLICATION INFORMATION
; DAC D
lar
lacl
or
sacl
out
lacl
add
and
sacl
rpt
nop
ar0, dacd_ptr; ar0 points to DAC a sample
*
; get DAC a sample into accumulator
#dacd_control ; OR in DAC D control bits
temp
;
temp, SDTR
; send data
r_ptr
#1h
#001Fh
r_ptr
#016h
;
;
;
;
;
;
; now take CS high again
lacl
iosr_stat
;
or
#0001h
;
sacl
temp
;
out
temp, IOSR
;
clrc
intm
;
ret
;
.end
20
load rolling pointer to accumulator
increment rolling pointer
count 0−31 then wrap back round
store rolling pointer
wait long enough for this configuration
of MCLK/CLKOUT1 rate
load acc with iosr status
set IO0 − CS high
re-enable interrupts
return from interrupt
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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APPLICATION INFORMATION
TLV5614 interfaced to MCS51 microcontroller
hardware interfacing
Figure 19 shows an example of how to connect the TLV5614 to an MCS51 Microcontroller. The serial DAC
input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent on the RxD
line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the
DAC latch update (LDAC), chip select (CS) and frame sync (FS) signals for the TLV5614. The active low power
down pin (PD) of the TLV5614 is pulled high to ensure that the DACs are enabled.
MCS®51
TLV5614
RxD
SDIN
TxD
SCLK
P3.3
LDAC
P3.4
CS
P3.4
FS
VDD
PD
VOUTA
VOUTB
REF
REFINAB
VOUTC
REFINCD
VOUTD
VSS
Figure 19. TLV5614 Interfaced With MCS51
software
The example is the same as for the TMS320C203 in this data sheet, but adapted for a MCS51 controller. It
generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and its quadrature (cosine)
signal is the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses
LDAC low to update all four DACs simultaneously, then fetches and writes the next sample to all four DACs.
The samples are stored as a look-up table, which describes one full period of a sine wave.
The serial port of the controller is used in Mode 0, which transmits 8 bits of data on RxD, accompanied by a
synchronous clock on TxD. Two writes, concatenated together, are required to write a complete word to the
TLV5614. The CS and FS signals are provided in the required fashion through control of IO port 3, which has
bit addressable outputs.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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µ SGLS355 − JUNE 2006
APPLICATION INFORMATION
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Processor: 80C51
;
; Description:
;
; This program generates a differential in-phase
(sine) on (OUTA−OUTB) ; and it’s quadrature (cosine)
as a differential signal on (OUTC−OUTD).
;
;  1998, Texas Instruments Inc.
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
NAME
GENIQ
MAIN
SEGMENT
CODE
ISR
SEGMENT
CODE
SINTBL SEGMENT
CODE
VAR1
SEGMENT
DATA
STACK SEGMENT
IDATA
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Code start at address 0, jump to start
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
CSEG AT
0
LJMP
start
; Execution starts at address 0 on power−up.
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Code in the timer0 interrupt vector
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
CSEG AT
0BH
LJMP
timer0isr
; Jump vector for timer 0 interrupt is 000Bh
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Global variables need space allocated
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
RSEG
VAR1
temp_ptr:
DS
1
rolling_ptr: DS
1
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−;
Interrupt service routine for timer 0 interrupts
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
RSEG
ISR
timer0isr:
PUSH
PSW
PUSH
ACC
CLR
INT1
; pulse LDAC low
SETB
INT1
; to latch all 4 previous values at the same time
; 1st thing done in timer isr => fixed period
CLR
T0
; set CS low
;
;
;
;
;
;
The signal to be output on each DAC is a sine function.
One cycle of a sine wave is held in a table @ sinevals
as 32 samples of msb, lsb pairs (64 bytes).
We have ; one pointer which rolls round this table, rolling_ptr,
incrementing by 2 bytes (1 sample) on each interrupt (at the end of
this routine).
; The
; DAC
; A
; B
; C
; D
MOV
MOV
MOV
MOVC
22
DAC samples are read at an offset to this rolling pointer:
Function Offset from rolling_ptr
sine
0
inverse sine 32
cosine
16
inverse cosine48
DPTR,#sinevals; set DPTR to the start of the table
; of sine signal values
R7,rolling_ptr; R7 holds the pointer
;into the sine table
A,R7
A,@A+DPTR
; get DAC A msb
; msb of DAC A is in the ACC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SGLS355 − JUNE 2006
APPLICATION INFORMATION
CLR
MOV
T1
SBUF,A
INC
R7
MOV
A,R7
MOVC
A,@A+DPTR
A_MSB_TX:
JNB
TI,A_MSB_TX
CLR
TI
MOV
SBUF,A
; transmit it − set FS low
; send it out the serial port
; increment the pointer in R7
; to get the next byte from the table
; which is the lsb of this sample, now in ACC
; wait for transmit to complete
; clear for new transmit
; and send out the lsb of DAC A
; DAC C next
; DAC C codes should be taken from 16 bytes (8 samples) further on
; in the sine table − this gives a cosine function
MOV
A,R7
; pointer in R7
ADD
A,#0FH
; add 15 − already done one INC
ANL
A,#03FH
; wrap back round to 0 if > 64
MOV
R7,A
; pointer back in R7
MOVC
ORL
A_LSB_TX:
JNB
SETB
CLR T1
CLR
MOV
INC
MOV
MOVC
C_MSB_TX:
JNB
CLR
MOV
A,@A+DPTR
A,#01H
; get DAC C msb from the table
; set control bits to DAC C address
TI,A_LSB_TX
T1
; wait for DAC A lsb transmit to complete
; toggle FS
TI
SBUF,A
R7
A,R7
A,@A+DPTR
;
;
;
;
;
TI,C_MSB_TX
TI
SBUF,A
; wait for transmit to complete
; clear for new transmit
; and send out the lsb of DAC C
clear for new transmit
and send out the msb of DAC C
increment the pointer in R7
to get the next byte from the table
which is the lsb of this sample, now in ACC
; DAC B next
; DAC B codes should be taken from 16 bytes (8 samples) further on
; in the sine table − this gives an inverted sine function
MOV
A,R7
; pointer in R7
ADD
A,#0FH
; add 15 − already done one INC
ANL
A,#03FH
; wrap back round to 0 if > 64
MOV
R7,A
; pointer back in R7
MOVC
ORL
C_LSB_TX:
JNB
SETB
CLR
CLR
MOV
; get
INC
MOV
MOVC
A,@A+DPTR
A,#02H
; get DAC B msb from the table
; set control bits to DAC B address
TI,C_LSB_TX
T1
T1
TI
SBUF,A
; wait for DAC C lsb transmit to complete
; toggle FS
DAC B LSB
R7
A,R7
A,@A+DPTR
B_MSB_TX:
JNB
TI,B_MSB_TX
CLR
TI
MOV
SBUF,A
; clear for new transmit
; and send out the msb of DAC B
; increment the pointer in R7
; to get the next byte from the table
; which is the lsb of this sample, now in ACC
; wait for transmit to complete
; clear for new transmit
; and send out the lsb of DAC B
; DAC D next
; DAC D codes should be taken from 16 bytes (8 samples) further on
; in the sine table − this gives an inverted cosine function
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
µ SGLS355 − JUNE 2006
APPLICATION INFORMATION
MOV
ADD
ANL
MOV
MOVC
ORL
A,R7
A,#0FH
A,#03FH
R7,A
A,@A+DPTR
A,#03H
;
;
;
;
;
;
B_LSB_TX:
JNB
TI,B_LSB_TX ;
SETB
T1
;
CLR
T1
CLR
TI ; clear for
MOV
SBUF,A
;
INC
MOV
MOVC
D_MSB_TX:
JNB
CLR
MOV
pointer in R7
add 15 − already done one INC
wrap back round to 0 if > 64
pointer back in R7
get DAC D msb from the table
set control bits to DAC D address
wait for DAC B lsb transmit to complete
toggle FS
new transmit
and send out the msb of DAC D
R7
A,R7
A,@A+DPTR
; increment the pointer in R7
; to get the next byte from the table
; which is the lsb of this sample, now in ACC
TI,D_MSB_TX
TI
SBUF,A
; wait for transmit to complete
; clear for new transmit
; and send out the lsb of DAC D
; increment the rolling pointer to point to the next sample
; ready for the next interrupt
MOV
A,rolling_ptr
ADD
A,#02H
; add 2 to the rolling pointer
ANL
A,#03FH
; wrap back round to 0 if > 64
MOV
rolling_ptr,A ; store in memory again
D_LSB_TX:
JNB
TI,D_LSB_TX ; wait for DAC D lsb transmit to complete
CLR
TI
; clear for next transmit
SETB
T1
; FS high
SETB
T0
; CS high
POP
ACC
POP
PSW
RETI
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Stack needs definition
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
RSEG STACK
DS
10h
; 16 Byte Stack!
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Main program code
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
RSEG
MAIN
start:
MOV
SP,#STACK−1 ; first set Stack Pointer
CLR A
MOV
SCON,A
; set serial port 0 to mode 0
MOV
TMOD,#02H
; set timer 0 to mode 2 − auto−reload
MOV
TH0,#038H
; set TH0 for 5kHs interrupts
SETB
INT1
; set LDAC = 1
SETB
T1
; set FS = 1
SETB
T0
; set CS = 1
SETB
ET0
; enable timer 0 interrupts
SETB
EA
; enable all interrupts
MOV
rolling_ptr,A ; set rolling pointer to 0
SETB
TR0
; start timer 0
always:
SJMP
always
; while(1) !
RET
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Table of 32 sine wave samples used as DAC data
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
RSEG
SINTBL
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SGLS355 − JUNE 2006
APPLICATION INFORMATION
sinevals:
DW
01000H
DW
0903EH
DW
05097H
DW
0305CH
DW
0B086H
DW
070CAH
DW
0F0E0H
DW
0F06EH
DW
0F039H
DW
0F06EH
DW
0F0E0H
DW
070CAH
DW
0B086H
DW
0305CH
DW
05097H
DW
0903EH
DW
01000H
DW
06021H
DW
0A0E8H
DW
0C063H
DW
040F9H
DW
080B5H
DW
0009FH
DW
00051H
DW
00026H
DW
00051H
DW
0009FH
DW
080B5H
DW
040F9H
DW
0C063H
DW
0A0E8H
DW 06021H
END
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLV5614MPWREP
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
5614EP
V62/06602-01XE
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
5614EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV5614-EP :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
• Catalog: TLV5614
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLV5614MPWREP
Package Package Pins
Type Drawing
TSSOP
PW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV5614MPWREP
TSSOP
PW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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