Texas Instruments | 12-Bit 250-KSPS Serial CMOS Sampling ADC | Datasheet | Texas Instruments 12-Bit 250-KSPS Serial CMOS Sampling ADC Datasheet

Texas Instruments 12-Bit 250-KSPS Serial CMOS Sampling ADC Datasheet
 ADS8508
SLAS433 – SEPTEMBER 2005
12-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER
FEATURES
APPLICATIONS
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250-kHz Sampling Rate
4-V, 5-V, 10-V, ±3.33-V, ±5-V, and ±10-V Input
Ranges
73-dB SINAD With 45-kHz Input
±0.45 LSB Max INL
±0.45 LSB Max DNL, 12-Bits No Missing
Codes
±1 LSB Bipolar Zero Errors
±0.4 PPM/°C Bipolar Zero Error Drift
Six Specified Input Ranges
SPI Compatible Serial Output with
Daisy-Chain (TAG) Feature
5-V Supply
Pin-Compatible With ADS7808 (Low Speed)
and 16-Bit ADS8509/7809
Uses Internal or External Reference
70-mW Typ Power Dissipation at 250 KSPS
20-Pin SO Package
Simple DSP Interface
Industrial Process Control
Data Acquisition Systems
Digital Signal Processing
Medical Equipment
Instrumentation
DESCRIPTION
The ADS8508 is a complete 12-bit sampling
analog-to-digital (A/D) converter using state-of-the-art
CMOS structures. It contains a complete 12-bit,
capacitor-based, successive approximation register
(SAR) A/D converter with sample-and-hold, reference, clock, and a serial data interface. Data can be
output using the internal clock or can be
synchronized to an external data clock. The ADS8508
also provides an output synchronization pulse for
ease of use with standard DSP processors.
The ADS8508 is specified at a 250-kHz sampling rate
over the full temperature range. Precision resistors
provide various input ranges including ±10 V and 0 V
to 5 V, while the innovative design allows operation
from a single +5-V supply with power dissipation
under 100 mW.
The ADS8508 is available in a 20-pin SO package,
fully specified for operation over the industrial -40°C
to 85°C temperature range.
Successive Approximation Register
Clock
CDAC
9.8 kΩ
R1IN
BUSY
4.9 kΩ
R2IN
2.5 kΩ
R3IN
EXT/INT
10 kΩ
Comparator
CAP
Buffer
Internal
+2.5 V Ref
Serial
Data
Out
&
Control
DATACLK
DATA
R/C
SB/BTC
CS
PWRD
4 kΩ
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
ADS8508
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SLAS433 – SEPTEMBER 2005
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
NO
MISSING
CODE
MINIMUM
SINAD
(dB)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
LEAD
PACKAGE
DESIGNATOR
ADS8508IB
±0.45
12
72
-40°C to 85°C
SO-20
DW
(1)
ORDERING
NUMBER
ADS8508IBDW
ADS8508IBDWR
TRANSPORT
MEDIA, QTY
Tube, 25
Tape and Reel, 2000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
ADS8508
Analog inputs
R1IN
±25 V
R2IN
±25 V
R3IN
±25 V
CAP
+VANA + 0.3 V to AGND2 - 0.3 V
REF
Indefinite short to AGND2, momentary short to VANA
DGND, AGND2
Ground voltage differences
±0.3 V
VANA
6V
VDIG to VANA
0.3 V
VDIG
6V
Digital inputs
-0.3 V to +VDIG + 0.3 V
Maximum junction temperature
165°C
Storage temperature range
–65°C to 150°C
Internal power dissipation
700 mW
Lead temperature (soldering, 10s)
(1)
260°C
All voltage values are with respect to network ground terminal.
ELECTRICAL CHARACTERISTICS
At TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference and fixed resistors (See Figure 28 and
Figure 29) (unless otherwise specified)
PARAMETER
TEST CONDITIONS
ADS8508IB
MIN
TYP
Resolution
MAX
12
UNIT
Bits
ANALOG INPUT
Voltage ranges (1)
Impedance (1)
Capacitance
50
pF
THROUGHPUT SPEED
Conversion cycle
Acquire and convert
Throughput rate
4
250
µs
kHz
DC ACCURACY
INL
Integral linearity error
-0.45
0.45
LSB (2)
DNL
Differential linearity error
-0.45
0.45
LSB
No missing codes
Transition
(1)
(2)
(3)
2
noise (3)
±10 V, 0 V to 5 V, etc. (see Table 3)
LSB means least significant bit. For the ±10-V input range, one LSB is 4.88 mV.
Typical rms noise at worst case transitions and temperatures.
12
Bits
0.1
LSB
ADS8508
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SLAS433 – SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
At TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference and fixed resistors (See Figure 28 and
Figure 29) (unless otherwise specified)
PARAMETER
TEST CONDITIONS
±10 V range
Full-scale
error (4) (5)
All other ranges
Full-scale error drift
MIN
All other ranges
Full-scale error drift
Ext. Ref. with 0.1% external fixed
resistors
0.5
0.5
±7
0.5
-0.5
0.5
±2
-1
-5
5
4 V and 5 V
range
-3
3
Power supply sensitivity
(VDIG = VANA = VD)
1-µF Capacitor to CAP
+4.75 V < VD < +5.25 V
%FS
mV
ppm/°C
10 V range
Recovery to rated accuracy after
power down
%FS
ppm/°C
1
±0.4
Unipolar zero error drift
UNIT
ppm/°C
-0.5
Bipolar zero error drift
Unipolar zero
error (4)
MAX
-0.5
Ext. Ref.
Bipolar zero error (4)
TYP
-0.5
Int. Ref.
±10 V range
Full-scale
error (4) (5)
Int. Ref. with 0.1% external fixed
resistors
ADS8508IB
mV
±2
ppm/°C
1
ms
-0.5
0.5
LSB
AC ACCURACY
SFDR
Spurious-free dynamic range
fI = 45 kHz
THD
Total harmonic distortion
fI = 45 kHz
SINAD
SNR
Signal-to-(noise+distortion)
Signal-to-noise ratio
Full-power
fI = 45 kHz
86
-95
72
–60-dB Input
fI = 45 kHz
72
bandwidth (7)
dB (6)
95
-86
dB
73
dB
32
dB
73
dB
500
kHz
SAMPLING DYNAMICS
Aperture delay
Transient response
5
FS Step
ns
2
Overvoltage recovery (8)
150
µs
ns
REFERENCE
Internal reference voltage
No load
2.48
Internal reference source current
(must use external buffer)
2.52
1
Internal reference drift
2.3
Ext. 2.5-V Ref.
2.5
V
µA
8
External reference voltage range for
specified linearity
External reference current drain
2.5
ppm/°C
2.7
V
100
µA
DIGITAL INPUTS
Logic levels
VIL
Low-level input voltage
-0.3
0.8
V
VIH
High-level input voltage
2.0
VDIG +0.3 V
V
(4)
(5)
(6)
(7)
(8)
As measured with circuit shown in Figure 28 and Figure 29. Adjustable to zero with external potentiometer. Factory calibrated with 0.1%,
0.25-W resistors.
For bipolar input ranges, full-scale error is the worst case of -full-scale or +full-scale uncalibrated deviation from ideal first and last code
transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input
ranges, full-scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset
error.
All specifications in dB are referred to a full-scale ±10-V input.
Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB.
Recovers to specified performance after 2 x FS input overvoltage.
3
ADS8508
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SLAS433 – SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
At TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference and fixed resistors (See Figure 28 and
Figure 29) (unless otherwise specified)
PARAMETER
TEST CONDITIONS
ADS8508IB
MIN
TYP
MAX
UNIT
IIL
Low-level input current
VIL = 0 V
±10
µA
IIH
High-level input current
VIH = 5 V
±10
µA
DIGITAL OUTPUTS
Data format (Serial 16-bits)
Data coding (Binary 2's complement
or straight binary)
Pipeline delay (Conversion results
only available after completed conversion.)
Data clock (Selectable for internal or
external data clock)
Internal clock (output only when
transmitting data)
EXT/INT Low
External clock (can run continually
but not recommended for optimum
performance)
EXT/INT High
VOL
Low-level output voltage
ISINK = 1.6 mA
VOH
High-level output voltage
ISOURCE = 500 µA
Leakage current
Output capacitance
9
0.1
MHz
26
MHz
0.4
V
Hi-Z state,
VOUT = 0 V to VDIG
±5
µA
Hi-Z state
15
pF
V
4
V
POWER SUPPLIES
VDIG
Digital input voltage
VANA
Analog input voltage
IDIG
Digital input current
IANA
Analog input current
Must be ≤ VANA
4.75
5
5.25
4.75
5
5.25
V
4
mA
10
mA
POWER DISSIPATION
PWRD Low
fS = 250 kHz
70
PWRD High
100
50
mW
µW
TEMPERATURE RANGE
Specified performance
-40
85
°C
Derated performance (9)
-55
125
°C
Storage
-65
150
°C
THERMAL RESISTANCE (ΘJA)
SO
(9)
4
75
°C/W
The internal reference may not be started correctly beyond the industrial temperature range (-40°C to 85°C), therefore use of an
external reference is recommended.
ADS8508
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SLAS433 – SEPTEMBER 2005
TIMING REQUIREMENTS, TA = –40°C to 85°C
PARAMETER
MIN
TYP
MAX
6
20
ns
2.2
µs
tw1
Pulse duration, convert
td1
Delay time, BUSY from R/C low
tw2
Pulse duration, BUSY low
td2
Delay time, BUSY, after end of conversion
5
td3
Delay time, aperture
5
tconv
Conversion time
tacq
Acquisition time
tconv + tacq
40
UNIT
ns
ns
ns
2.2
1.8
µs
µs
Cycle time
4
µs
td4
Delay time, R/C Low to internal DATACLK output
270
ns
tc1
Cycle time, internal DATACLK
110
ns
td5
Delay time, data valid to internal DATACLK high
15
35
ns
td6
Delay time, data valid after internal DATACLK low
20
35
ns
tc2
Cycle time, external DATACLK
35
ns
tw3
Pulse duration, external DATACLK high
15
ns
tw4
Pulse duration, external DATACLK low
15
tsu1
Setup time, R/C rise/fall to external DATACLK high
15
tsu2
Setup time, R/C transition to CS transition
10
td7
Delay time, SYNC, after external DATACLK high
3
35
ns
td8
Delay time, data valid
2
20
ns
td9
Delay time, CS to rising edge
td10
tsu3
td11
Delay time, final external DATACLK to BUSY falling edge
tsu3
Setup time, TAG valid
0
ns
th1
Hold time, TAG valid
2
ns
ns
tC2 + 5
ns
ns
10
ns
Delay time, previous data available after CS, R/C low
2
µs
Setup time, BUSY transition to first external DATACLK
5
ns
1
µs
DW PACKAGE
(TOP VIEW)
R1IN 1
AGND1 2
20 VDIG
19 VANA
R2IN 3
R3IN 4
18 PWRD
CAP 5
16 CS
REF 6
15 R/C
AGND2 7
14 TAG
SB/BTC 8
13 DATA
EXT/INT 9
12 DATACLK
DGND 10
17 BUSY
11 SYNC
5
ADS8508
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SLAS433 – SEPTEMBER 2005
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
I/O
AGND1
2
–
Analog ground. Used internally as ground reference point. Minimal current flow.
AGND2
7
–
Analog ground
BUSY
17
O
Busy output. Falls when a conversion is started, and remains low until the conversion is completed and
the data is latched into the output shift register.
CAP
5
–
Reference buffer capacitor. 2.2-µF Tantalum to ground.
CS
16
–
Chip select. Internally ORed with R/C
DATA
13
O
Serial data output. Data is synchronized to DATACLK, with the format determined by the level of SB/BTC.
In the external clock mode, after 16 bits of data, the ADS8508 outputs the level input on TAG as long as
CS is low and R/C is high (see Figure 8 and Figure 9). If EXT/INT is low, data is valid on both the rising
and falling edges of DATACLK, and between conversions DATA stays at the level of the TAG input when
the conversion was started.
DATACLK
12
I/O
Either an input or an output depending on the EXT/INT level. Output data is synchronized to this clock. If
EXT/INT is low, DATACLK transmits 16 pulses after each conversion, and then remains low between
conversions.
DGND
10
–
Digital ground
EXT/INT
9
–
Selects external or internal clock for transmitting data. If high, data is output synchronized to the clock
input on DATACLK. If low, a convert command initiates the transmission of the data from the previous
conversion, along with 16-clock pulses output on DATACLK.
NC
–
–
No connect
PWRD
18
I
Power down input. If high, conversions are inhibited and power consumption is significantly reduced.
Results from the previous conversion are maintained in the output shift register.
R/C
15
I
Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the hold
state and starts a conversion. When EXT/INT is low, this also initiates the transmission of the data results
from the previous conversion. If EXT/INT is high, a rising edge on R/C with CS low, or a falling edge on
CS with R/C high, transmits a pulse on SYNC and initiates the transmission of data from the previous
conversion.
REF
6
I/O
R1IN
1
I
Analog input. See Table 3 for input range connections.
R2IN
3
I
Analog input. See Table 3 for input range connections.
R3IN
4
I
Analog input. See Table 3 for input range connections.
SB/BTC
8
O
Select straight binary or binary 2's complement data output format. If high, data is output in a straight
binary format. If low, data is output in a binary 2's complement format.
SYNC
11
O
Sync output. This pin is used to supply a data synchronization pulse when the EXT level is high and at
least one external clock pulse has occured when not in the read mode. See the external clock modes
desciptions.
TAG
14
I
Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output on
DATA with a delay that is dependent on the external clock mode. See Figure 8 and Figure 9.
VANA
19
I
Analog supply input. Nominally +5 V. Connect directly to pin 20, and decouple to ground with 0.1-µF
ceramic and 10-µF tantalum capacitors.
VDIG
20
I
Digital supply input. Nominally +5 V. Connect directly to pin 19. Must be ≤ VANA.
6
Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system
reference. In both cases, bypass to ground with a 2.2-µF tantalum capacitor.
ADS8508
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SLAS433 – SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION
CS
R/C
R/C
CS
tsu1
tsu1
tsu1
External
DATACLK
tsu1
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
R/C Set Low, Discontinuous Ext DATACLK
BUSY
CS
tsu2
tsu2
tsu3
1
External
DATACLK
R/C
2
CS Set Low, Discontinuous Ext DATACLK
Figure 1. Critical Timing
tw1
tw1
R/C
td1
td1
tw2
tw2
BUSY
td2
td3
STATUS
Nth Conversion
Error
Correction
tconv
td4
td2
td3
td11
(N+1)th Accquisition
td11
Error
(N+1)th Conversion Correction
tconv
tacq
tc1
(N+2)th Accquisition
tacq
td4
Internal
1
DATACLK
TAG = 0
12
1
2
12
td6
td5
DATA
2
D11
D0
(N−1)th Conversion Data
CS, EXT/INT, and TAG are tied low
TAG = 0
D11
D0
TAG = 0
Nth Conversion Data
8 starts READ
Figure 2. Basic Conversion Timing - Internal DATACLK (Read Previous Data During Conversion)
7
ADS8508
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SLAS433 – SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
tw1
tw1
R/C
td1
td1
tw2
tw2
BUSY
td2
td3
STATUS
Error
Correction
Nth Conversion
td2
td3
td11
td11
(N+1)th Accquisition
(N+1)th Conversion
tacq
tconv
(N+2)th Accquisition
tacq
tconv
tsu3
tsu1
Error
Correction
tsu3
tsu1
External
1
DATACLK
12
No more
data to
shift out
DATA TAG = 0
2
1
TAG = 0
1
12
Nth Data
EXT/INT tied high, CS and TAG are tied low
12
No more
data to
shift out
TAG = 0
2
1
TAG = 0
12
(N+1)th Data
TAG = 0
tw1 + tsu1 starts READ
Figure 3. Basic Conversion Timing - External DATACLK
tw1
R/C
td1
tsu1
tw2
td1
BUSY
td2
td3
STATUS
td3
td11
Nth Conversion
Error
Correction
(N+1) th Accquisition
tsu3
tconv
tacq
tc2
External
DATACLK
tsu1
tw4
tw3
0
1
2
3
4
5
7
8
9
10
11
12
SYNC = 0
td8
T00
EXT/INT tied high, CS tied low
D10
D09
D08
D07
D06
D04
D03
D02
D01
D00
Null
T00
Txx
T02
T03
T04
T05
T06
T08
T09
T10
T11
T12
Null
T17
Tyy
th1
tsu3
TAG
td8
Nth Conversion Data
D11
DATA
T01
tw1 + tsu1 starts READ
Figure 4. Read After Conversion (Discontinuous External DATACLK)
8
ADS8508
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SLAS433 – SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
tw1
R/C
td1
tw2
BUSY
td10
td3
td2
Error
Correction
Nth Conversion
STATUS
tsu3
tconv
tc2
tsu1
External
tw3
td11
tw4
1
0
DATACLK
2
3
4
5
8
9
10
11
12
SYNC = 0
td8
Nth Conversion Data
D10
D11
DATA
D09
D08
D07
D06
D04
D03
D02
td8
D01
D00
Rising DATACLK change DATA, tw1 + tsu1 Starts READ
TAG is not recommended for this mode. There is not enough
time to do so without violating td11.
EXT/INT tied high, CS and TAG tied low
Figure 5. Read During Conversion (Discontinuous External DATACLK)
tw1
R/C
td1
tsu1
td1
tsu1
tw2
BUSY
td2
td3
Error
Nth Conversion Correction
STATUS
td3
td11
(N+1)th Accquisition
tconv
tacq
tc2
tsu3
tsu1
External
DATACLK
0
2
1
tsu1
tw4
tw3
3
4
5
6
7
9
10
11
12
13
14
tc2
td7
SYNC =0
td8
Nth Conversion Data
D11
DATA
T00
EXT/INT tied high, CS tied low
D09
D08
D07
D06
D04
D03
D02
D01
D00
Null
T02
T03
T04
T05
T06
T12
T13
T14
T15
T16
T17
T00
Txx
th1
tsu3
TAG
td8
D10
T01
Tyy
tw1 + tsu1 starts READ
Figure 6. Read After Conversion With SYNC (Discontinuous External DATACLK)
9
ADS8508
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SLAS433 – SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
tw1
R/C
td1
tw2
BUSY
td3
td10
td2
Error
Correction
Nth Conversion
STATUS
tsu3
tconv
tsu1
tsu1
External
tw3
tsu1
0
DATACLK
tc2
tw4
1
2
3
td11
4
5
6
7
10
11
12
13
14
td7
tc2
SYNC = 0
td8
EXT/INT tied high, CS and TAG tied low
td8
Nth Conversion Data
D11
DATA
D10
D09
D08
D07
D06
D04
D03
D02
D01
D00
tw1 + tsu1 Starts READ
TAG is not recommended for this mode. There is not enough
time to do so without violating td11.
Figure 7. Read During Conversion With SYNC (Discontinuous External DATACLK)
10
ADS8508
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SLAS433 – SEPTEMBER 2005
Tag 14
Tag 13
Tag 12
Tag 11
Tag 1
TAG
Tag 2
Bit 11 (MSB)
DATA
Tag 0
t c2
t su2
t su1
0
SYNC
BUSY
R/C
CS
External
DATACLK
t w1
t su2
t d1
t w3
t d7
1
t c2
t w4
2
t d8
3
Bit 10
4
Bit 1
13
14
Bit 0 (LSB)
Tag 0
t d9
Tag 1
Tag 15
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Conversion and Read Timing with Continuous External DATACLK (EXT/INT Tied High) Read
After Conversions (Not Recommended)
11
ADS8508
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SLAS433 – SEPTEMBER 2005
Tag 14
Tag 13
Tag 1
TAG
Tag 12
Bit 15 (MSB)
DATA
SYNC
t d1
BUSY
R/C
CS
External
DATACLK
t su2
t w3
t c2
t w1
t w4
t su1
t su1
Tag 0
t c2
t d8
t d10
Bit 0 (LSB)
Tag 0
t d8
Tag 1
Tag 15
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 9. Conversion and Read Timing with Continuous External DATACLK (EXT/INT Tied High) Read
Previous Conversion Result During Conversion (Not Recommended)
12
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SLAS433 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
110
90
80
70
−20
0
20
40
60
−95
−90
−85
−80
−70
−40
80
70
60
50
−75
TA − Free-Air-Temperature − C
fi = 45 kHz
−20
0
20
40
60
40
−40
80
−20
0
20
40
60
80
TA − Free-Air-Temperature − C
TA − Free-Air-Temperature − C
Figure 10.
Figure 11.
Figure 12.
SIGNAL-TO-NOISE AND DISTORTION
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY
70
60
50
SINAD − Signal-to-Noise and Distortion − dB
80
80
SNR − Signal-to-Noise − dB
SINAD − Signal-to-Noise and Distortion − dB
80
SNR − Signal-to-Noise − dB
100
−40
75
70
65
60
55
fi = 45 kHz
40
−40
50
−20
0
20
40
60
80
1
10
100
1000
80
75
70
65
60
55
50
1
fi − Input Frequency − kHz
TA − Free-Air-Temperature − C
10
100
1000
fi − Input Frequency − kHz
Figure 13.
Figure 14.
Figure 15.
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
BIPOLAR ZERO SCALE ERROR
vs
FREE-AIR TEMPERATURE
90
80
70
60
50
−100
5
−90
4
Bipolar Zero Scale Error − mV
100
THD − Total Harmonic Distortion − dB
SFDR − Spurious Free Dynamic Range − dB
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
−100
fi = 45 kHz
THD − Total Harmonic Distortion − dB
SFDR − Spurious Free Dynamic Range − dB
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
−80
−70
−60
−50
−40
−30
−20
−10
10
100
fi − Input Frequency − kHz
Figure 16.
1000
2
1
0
−1
−2
−3
−4
0
1
External Reference,
±10-V Range
3
1
10
100
fi − Input Frequency − kHz
Figure 17.
1000
−5
−40 −25 −10
5
20
35
50
65
80
TA − Free-Air Temperature − C
Figure 18.
13
ADS8508
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SLAS433 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
INTERNAL REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
0.20
0.10
Internal Reference Voltage − V
Full Scale Error − %FSR
0.15
External Reference,
±10 V Range
for 5 Representative
Parts
0.05
0
−0.05
−0.10
−0.15
−0.20
−40 −25 −10 5
20
35
50
65
80
TA − Free-Air Temperature − C
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
2.510
20
2.508
19
2.506
18
2.504
17
Supply Current − mA
FULL SCALE ERROR
vs
FREE-AIR TEMPERATURE
2.502
2.500
2.498
2.496
2.494
16
15
14
13
12
2.492
11
2.490
−55 −35 −15 5
10
−40 −25 −10 5
25
45
65
85
105
Figure 19.
20
Figure 20.
Figure 21.
INL
0.5
fs = 250 KSPS
0.4
0.3
INL − LSBs
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
3072
3584
4096
Code
(Binary 2’s Complement in Decimal)
Figure 22.
DNL
0.5
fs = 250 KSPS
0.4
0.3
DNL − LSBs
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
512
1024
1536
2048
2560
Code
(Binary 2’s Complement in Decimal)
Figure 23.
14
35
50
65
TA − Free-Air Temperature − C
TA − Free-Air Temperature − C
80
ADS8508
www.ti.com
SLAS433 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
FFT (1 kHz Input)
20
8192 Points
fs = 250 KSPS
fi = 1 kHz, 0dB
SINAD = 73.47 dB
THD = −94.03 dB
0
Amplitude − dB
−20
−40
−60
−80
−100
−120
−140
−160
0
25
50
75
100
125
75
100
125
f − Frequency − Hz
Figure 24.
FFT (45 kHz Input)
20
8192 Points
fs = 250 KSPS
fi = 45 kHz, 0dB
SINAD = 73.62 dB
THD = −94.03 dB
0
Amplitude − dB
−20
−40
−60
−80
−100
−120
−140
−160
0
25
50
f − Frequency − Hz
Figure 25.
15
ADS8508
www.ti.com
SLAS433 – SEPTEMBER 2005
BASIC OPERATION
Two signals control conversion in the ADS8508: CS and R/C. These two signals are internally ORed together. To
start a conversion the chip must be selected, CS low, and the conversion signal must be active, R/C low. Either
signal can be brought low first. Conversion starts on the falling edge of the second signal. BUSY goes low when
conversion starts and returns high after the data from that conversion is shifted into the internal storage register.
Sampling begins when BUSY goes high.
To reduce the number of control pins CS can be tied low permanently. The R/C pin now controls conversion and
data reading exclusively. In the external clock mode this means that the ADS8508 will clock out data whenever
R/C is brought high and the external clock is active. In the internal clock mode data is clocked out every convert
cycle regardless of the states of CS and R/C. The ADS8508 provides a TAG input for cascading multiple
converters together.
READING DATA
The conversion result is available as soon as BUSY returns to high therefore, data always represents the
conversion previously completed even when it is read during a conversion. The ADS8508 outputs serial data in
either straight binary or binary two’s compliment format. The SB/BTC pin controls the format. Data is shifted out
MSB first. The first conversion immediately following a power-up will not produce a valid conversion result.
Data can be clocked out with either the internally generated clock or with an external clock. The EXT/INT pin
controls this function. If external clock is used the TAG input can be used to daisy-chain multiple ADS8508 data
pins together.
INTERNAL DATACLK
In the internal clock mode data for the previous conversion is clocked out during each conversion period. The
internal data clock is synchronized to the internal conversion clock so that is does not interfere with the
conversion process.
The DATACLK pin becomes an output when EXT/INT is low. 12 clock pulses are generated at the beginning of
each conversion after timing t8 is satisfied, i.e. you can only read previous conversion result during conversion.
DATACLK returns to low when it is inactive. The 12 bits of serial data are shifted out the DATA pin synchronous
to this clock with each bit available on a rising and then a falling edge. DATA pin returns to the state of TAG pin
input sensed at the start of transmission.
EXTERNAL DATACLK
The external clock mode offers several ways to retrieve conversion results. However, since the external clock
cannot be synchronized to the internal conversion clock care must be taken to avoid corrupting the data.
When EXT/INT is set high, the R/C and CS signals control the read state. When the read state is initiated the
result from the previously completed conversion is shifted out the DATA pin synchronous to the external clock
that is connected to the DATACLK pin. Each bit is available on a falling and then a rising edge. The maximum
external clock speed of 28.5 MHz allows data shifted out quickly either at the beginning of conversion or the
beginning of sampling.
There are several modes of operation available when using an external clock. It is recommended that the
external clock run only while reading data. This is the discontinuous clock mode. Since the external clock is not
synchronized to the internal clock that controls conversion slight changes in the external clock can cause
conflicts that can corrupt the conversion process. Specifications with a continuously running external clock
cannot be guaranteed. It is especially important that the external clock does not run during the second half of the
conversion cycle (approximately the time period specified by td11, see timing table).
In the discontinuous clock mode data can be read during conversion or during sampling, with or without a SYNC
pulse. Data read during a conversion must meet the td11 timing specification. Data read during sampling must be
complete before starting a conversion.
16
ADS8508
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SLAS433 – SEPTEMBER 2005
Whether reading during sampling or during conversion a SYNC pulse is generated whenever at least one rising
edge of the external clock occurs while the part is not in the read state. In the discontinuous external clock with
SYNC mode a SYNC pulse follows the first rising edge after the read command. The data is shifted out after the
SYNC pulse. The first rising clock edge after the read command generates a SYNC pulse. The SYNC pulse can
be detected on the next falling edge and then the next rising edge. Successively, each bit can be read first on the
falling edge and then on the next rising edge. Thus 13 clock pulses after the read command are required to read
on the falling edge, and 14 clock pulses are necessary to read on the rising edge.
Table 2. DATACLK Pulses
DESCRIPTION
DATACLK PULSES REQUIRED
WITH SYNC
WITHOUT SYNC
Read on falling edge of DATACLK
13
12
Read on rising edge of DATACLK
14
13
If the clock is entirely inactive when not in the read state no SYNC pulse is generated. In this case the first rising
clock edge shifts out the MSB. The MSB can be read on the first falling edge or on the next rising edge. In this
discontinuous external clock mode with no SYNC, 12 clocks are necessary to read the data on the falling edge
and 13 clocks for reading on the rising edge. Data always represents the conversion already completed.
TAG FEATURE
The TAG feature allows the data from multiple ADS8508 converters to be read on a single serial line. The
converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs as illustrated in
Figure 26. The DATA pin of the last converter drives the processor's serial data input. Data is then shifted
through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal
clock cannot be used for this configuration.
The preferred timing uses the discontinuous, external, data clock during the sampling period. Data must be read
during the sampling period because there is not sufficient time to read data from multiple converters during a
conversion period without violating the td11 constraint (see the EXTERNAL DATACLOCK section). The sampling
period must be sufficiently long to allow all data words to be read before starting a new conversion.
Note, in Figure 26, that a NULL bit separates the data word from each converter. The state of the DATA pin at
the end of a READ cycle reflects the state of the TAG pin at the start of the cycle. This is true in all READ
modes, including the internal clock mode. For example, when a single converter is used in the internal clock
mode the state of the TAG pin determines the state of the DATA pin after all 12 bits have shifted out. When
multiple converters are cascaded together this state forms the NULL bit that separates the words. Thus, with the
TAG pin of the first converter grounded as shown in Figure 26 the NULL bit becomes a zero between each data
word.
17
ADS8508
www.ti.com
SLAS433 – SEPTEMBER 2005
Processor
ADS8508A
DATA
CS
R/C
DATACLK
TAG
SCLK
ADS 8508B
TAG(A)
DATA
CS
R/C
DATACLK
TAG
TAG(B)
GPIO
GPIO
SDI
Null
D
A00
Q
D
Q
D
Null
D
A11
Q
D
Q
D
B00
DATA (A)
A12
Q
D
Q
D
B11
Q
B12
DATA (B)
Q
DATACLK
R/C
(both A & B)
BUSY
(both A & B)
SYNC
(both A & B)
External
DATACLK
1
2
3
4
12
13
DATA ( A )
A11
A10
A09
A01
A00
DATA ( B )
B11
B10
B09
B01
B00
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
14
15
16
17
Null
TAG(A) = 0
A
Nth Conversion Data
Null A11
A10 A09
B
30
A01
31
32
A00
Null
A
TAG(A) = 0
.
Figure 26. Timing of TAG Feature With Single Conversion (Using External DATACLK)
ANALOG INPUTS
The ADS8508 has six analog input ranges as shown in Table 3. The offset and gain specifications are factory
calibrated with 0.1%, ¼-W, external resistors as shown in Figure 28 and Figure 29. The external resistors can be
omitted if larger gain and offset errors are acceptable or if using software calibration. The hardware trim circuitry
shown in Figure 28 and Figure 29 can reduce the errors to zero.
The analog input pins R1IN, R2IN, and R3IN have ±25-V overvoltage protection. The input signal must be
referenced to AGND1. This will minimized the ground loop problem typical to analog designs. The analog input
should be driven by a low impedance source. A typical driving circuit using OPA627 or OPA132 is shown in
Figure 27.
The ADS8508 can operate with its internal 2.5-V reference or an external reference. An external reference
connected to pin 6 (REF) bypasses the internal reference. The external reference must drive the 4-kΩ resistor
that separates pin 6 from the internal reference (see the illustration on page 1). The load will vary with the
difference between the internal and external reference voltages. The external reference voltage can vary from
2.3 V to 2.7 V. The internal reference will be approximately 2.5 V. The reference, whether internal or external, is
buffered internally with a buffer with its output on pin 5 (CAP).
The ADS8508 is factory tested with 2.2-µF capacitors connected to pins 5 and 6 (CAP and REF). Each capacitor
should be placed as close as possible to its pin. The capacitor on pin 6 band limits the internal reference noise. A
smaller capacitor can be used but it may degrade SNR and SINAD The capacitor on pin 5 stabilizes the
reference buffer and provides switching charge to the CDAC during conversion. Capacitors smaller than 1 µF
can cause the buffer to become unstable may not hold sufficient charge for the CDAC. The parts are tested to
specifications with 2.2 µF so larger capacitors are not necessary. The ESR (equivalent series resistance) of
these compensation capacitors is also critical. Keep the total ESR under 3 Ω. See the TYPICAL CHARACTERISTICS section for how the performance is affected by ESR.
Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade
performance. Any load on the internal reference causes a voltage drop across the 4-kΩ resistor and will affect
gain. The internal buffer is capable of driving ±2-mA loads but any load can cause perturbations of the reference
at the CDAC, degrading performance. It should be pointed out that, unlike other competitor’s parts with similar
input structure, the ADS8508 does not require a second high speed amplifier used as buffer to isolate the CAP
pin from the signal dependent current in the R3IN pin but can tolerate it if one do exist.
18
ADS8508
www.ti.com
SLAS433 – SEPTEMBER 2005
The external reference voltage can vary from 2.3 V to 2.7 V. The reference voltage determines the size of the
least significant bit (LSB). The larger reference voltages produce a larger LSB, which can improve SNR. Smaller
reference voltages can degrade SNR.
+15V
2.2 F
22 pF
ADS8508
200 100 nF
GND
R1IN
1 k
Pin 7
1 k
Pin 2
Vin
22 pF
10 pF
Pin 1
AGND
100 Pin5
−
OPA 627
Pin 6
+
Pin3
R2IN
GND
33.2 k
GND
R3IN
Pin4
CAP
2.2 F
GND
AGND2
2.2 F
GND
100 nF
2.2 F
−15 V
GND
Figure 27. Typical Driving Circuitry (±10 V, No Trim)
Table 3. Input Range Connections (see Figure 28 and Figure 29 for complete
information)
ANALOG
INPUT RANGE
CONNECT R1IN VIA
200 Ω TO
CONNECT R2IN VIA
100 Ω TO
CONNECT
R3 TO
IMPEDANCE
±10 V
VIN
AGND
CAP
11.5 kΩ
±5 V
AGND
VIN
CAP
6.7 kΩ
±3.33 V
VIN
VIN
CAP
5.4 kΩ
0 V to 10 V
AGND
VIN
AGND
6.7 kΩ
0 V to 5 V
AGND
AGND
VIN
5.0 kΩ
0 V to 4 V
VIN
AGND
VIN
5.4 kΩ
Table 4. Control Truth Table
SPECIFIC FUNCTION
CS
R/C
BUSY
EXT/INT
DATACLK
PWRD
SB/BTC
OPERATION
Initiate conversion and output data using internal clock
1>0
0
1
0
Output
0
x
0
1>0
1
0
Output
0
x
Initiates conversion n. Data from conversion n - 1
clocked out on DATA synchronized to 16 clock
pulses output on DATACLK.
Initiate conversion and output data using external clock
1>0
0
1
1
Input
0
x
Initiates conversion n.
0
1>0
1
1
Input
0
x
Initiates conversion n.
1>0
1
1
1
Input
x
x
Outputs a pulse on SYNC followed by data from
conversion n clocked out synchronized to external
DATACLK.
1>0
1
0
1
Input
0
x
0
0>1
0
1
Input
0
x
Outputs a pulse on SYNC followed by data from
conversion n - 1 clocked out synchronized to
external DATACLK. (1) Conversion n in process.
Incorrect conversions
0
0
0>1
x
x
0
x
CS or R/C must be HIGH or a new conversion will
be initiated without time for acquisition.
Power down
x
x
x
x
x
0
x
Analog circuitry powered. Conversion can proceed..
x
x
x
x
x
1
x
Analog circuitry disabled. Data from previous
conversion maintained in output registers.
(1)
See Figure XXX for the constraints on previous data valid during a conversion.
19
ADS8508
www.ti.com
SLAS433 – SEPTEMBER 2005
Table 4. Control Truth Table (continued)
Selecting output format
x
x
x
x
x
x
0
Serial data is output in binary 2s complement
format.
x
x
x
x
x
x
1
Serial data is output in straight binary format.
Table 5. Output Codes and Ideal Input Voltages
DIGITAL OUTPUT
DESCRIPTION
Full-scale
range
BINARY 2's
COMPLEMENTS
(SB/BTC LOW)
ANALOG INPUT
BINARY CODE
HEX CODE
BINARY CODE
HEX CODE
3.99902 V
0111 1111 1111
7FF
1111 1111 1111
FFF
2V
0000 0000 0000
000
1000 0000 0000
800
4.99756 V
1.99902 V
1111 1111 1111
FFF
0111 1111 1111
7FF
0V
0V
1000 0000 0000
800
0000 0000 0000
000
±10
±5
±3.33 V
0 V to 5 V
0 V to 10 V
0 V to 4 V
Least significant bit
(LSB)
4.88 mV
2.44 mV
1.63 mV
1.22 mV
2.44 mV
0.98 mV
Full scale
(FS - 1LSB)
9.99512 V
4.997567 V
3.33171 V
4.99878 V
9.99756 V
Midscale
0V
0V
0V
2.5 V
5V
One LSB
below
midscale
-4.88 mV
-2.44 mV
-1.63 mV
2.49878 V
-Full scale
-10 V
-5 V
-3.333333 V
0V
20
STRAIGHT
BINARY
(SB/BTC HIGH)
ADS8508
www.ti.com
SLAS433 – SEPTEMBER 2005
Input Range
With Trim
(Adjust Offset First at 0 V, Then Adjust Gain)
Without Trim
200 Ω
200 Ω
R1IN
R1IN
AGND1
AGND1
100 Ω
100 Ω
0 V − 10 V
VIN
R2IN
33.2 kΩ
R3IN
R2IN
VIN
33.2 kΩ
2.2 µF
+5V
CAP
+
50 kΩ
2.2 µF
+
R3IN
2.2 µF
+
+5V
CAP
576 kΩ
50 kΩ
REF
REF
+
2.2 µF
AGND2
200 Ω
AGND2
200 Ω
R1IN
R1IN
AGND1
100 Ω
R2IN
33.2 kΩ
VIN
+5 V
CAP
2.2 µF
+
+5 V
50 kΩ
2.2 µF
REF
2.2 µF
R2IN
33.2 kΩ
R3IN
VIN
0V−5V
AGND1
100 Ω
+
+
R3IN
CAP
576 kΩ
50 kΩ
2.2 µF
AGND2
200 Ω
R1IN
VIN
AGND1
100 Ω
100 Ω
R2IN
R2IN
R3IN
R3IN
33.2 kΩ
+5 V
+
33.2 kΩ
+5 V
CAP
2.2 µF
AGND2
R1IN
AGND1
2.2 µF
REF
200 Ω
VIN
0V−4V
+
+
REF
2.2 µF
+
576 kΩ
50 kΩ
50 kΩ
2.2 µF
AGND2
CAP
REF
+
AGND2
Figure 28. Offset/Gain Circuits for Unipolar Input Ranges
21
ADS8508
www.ti.com
SLAS433 – SEPTEMBER 2005
Input Range
With Trim
(Adjust Offset First at 0 V, Then Adjust Gain)
Without Trim
200 Ω
VIN
200 Ω
R1IN
R1IN
VIN
AGND1
AGND1
100 Ω
100 Ω
R2IN
±10 V
R2IN
+5 V
R3IN
33.2 kΩ
+
2.2 F
+
R3IN
+5 V
50 kΩ
CAP
2.2 F
33.2 kΩ
REF
2.2 µF
576 kΩ
+
2.2 µF
+
CAP
REF
50 kΩ
AGND2
AGND2
200 Ω
200 Ω
R1IN
R1IN
AGND1
AGND1
100 Ω
VIN
33.2 kΩ
±5V
R3IN
CAP
50 kΩ
2.2 µF
+
2.2 µF
R2IN
R3IN
+
2.2 µF
+5 V
+5 V
+
100 Ω
VIN
33.2 kΩ
R2IN
CAP
576 kΩ
50 kΩ
REF
REF
+
2.2 µF
AGND2
200 Ω
AGND2
200 Ω
VIN
R1IN
100 Ω
R1IN
VIN
100 Ω
AGND1
AGND1
R2IN
R2IN
R3IN
33.2 kΩ
±3.3 V
33.2 kΩ
2.2 µF
+5 V
CAP
+
+
REF
2.2 F
AGND2
CAP
+5 V
50 kΩ
2.2 F
576 kΩ
50 kΩ
+
2.2 µF
Figure 29. Offset/Gain Circuits for Bipolar Input Ranges
22
R3IN
+
REF
AGND2
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS8508IBDW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8508IB
ADS8508IBDWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8508IB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS8508IBDWR
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
10.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.3
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS8508IBDWR
SOIC
DW
20
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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