Texas Instruments | 1.2-V 12/10/8-Bit 200-KSPS/100-KSPS MICRO-POWER MINIATURE ADC s/Serial Interface | Datasheet | Texas Instruments 1.2-V 12/10/8-Bit 200-KSPS/100-KSPS MICRO-POWER MINIATURE ADC s/Serial Interface Datasheet

Texas Instruments 1.2-V 12/10/8-Bit 200-KSPS/100-KSPS MICRO-POWER MINIATURE ADC s/Serial Interface Datasheet
 ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE
ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Single 1.2-V to 3.6-V Supply Operation
High Throughput
– 200/240/280KSPS for 12/10/8-Bit VDD ≥ 1.6 V
– 100/120/140KSPS for 12/10/8-Bit VDD ≥ 1.2 V
±1.5LSB INL, 12-Bit NMC (ADS7866)
71 dB SNR, –83 dB THD at fIN = 30 kHz
(ADS7866)
Synchronized Conversion with SCLK
SPI Compatible Serial Interface
No Pipeline Delays
Low Power
– 1.39 mW Typ at 200 KSPS, VDD = 3.6 V
– 0.39 mW Typ at 200 KSPS, VDD = 1.6 V
– 0.22 mW Typ at 100 KSPS, VDD = 1.2 V
Auto Power-Down: 8 nA Typ, 300 nA Max
0 V to VDD Unipolar Input Range
6-Pin SOT-23 Package
The minimum conversion time is determined by the
frequency of the serial clock input, SCLK, while the
maximum frequency of SCLK is determined by the
minimum sampling time required to charge the input
capacitance to 12/10/8-bit accuracy for the
ADS7866/67/68,
respectively.
The
maximum
throughput is determined by how often a conversion
is initiated when the minimum sampling time is met
and the maximum SCLK frequency is used. Each
device automatically powers down after each conversion, which allows each device to save power when
the throughput is reduced while using the maximum
SCLK frequency.
The converter reference is taken internally from the
supply. Hence, the analog input range for these
devices is 0 V to VDD.
APPLICATIONS
•
•
•
•
•
•
The sampling, conversion, and activation of digital
output SDO are initiated on the falling edge of CS.
The serial clock SCLK is used for controlling the
conversion rate and shifting data out of the converter.
Furthermore, SCLK provides a mechanism to allow
digital host processors to synchronize with the converter.
These
converters
interface
with
micro-processors or DSPs through a high-speed SPI
compatible serial interface. There are no pipeline
delays associated with the device.
Battery Powered Systems
Isolated Data Acquisition
Medical Instruments
Portable Communication
Portable Data Acquisition Systems
Automatic Test Equipment
These devices are available in a 6-pin SOT-23
package and are characterized over the industrial
–40°C to 85°C temperature range.
REF/VDD
DESCRIPTION
12/10/8 BIT ADC
The ADS7866/67/68 are low power, miniature,
12/10/8-bit A/D converters each with a unipolar,
single-ended input. These devices can operate from a
single 1.6 V to 3.6 V supply with a 200-KSPS
throughput for ADS7866. In addition, these devices
can maintain at least a 100-KSPS throughput with a
supply as low as 1.2 V.
Comparator
VIN
+
_S/H
CDAC
SAR
Conversion
and
Control
Logic
CS
SCLK
SDO
GND
Micro-Power Miniature SAR Converter Family
RESOLUTION/SPEED
< 200 KSPS
1 MSPS – 1.25 MSPS
12-Bit
ADS7866 (1.2 VDD to 3.6 VDD)
ADS7886 (2.35 VDD to 5.25 VDD)
10-Bit
ADS7867 (1.2 VDD to 3.6 VDD)
ADS7887 (2.35 VDD to 5.25 VDD)
8-Bit
ADS7868 (1.2 VDD to 3.6 VDD)
ADS7888 (2.35 VDD to 5.25 VDD)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465 – JUNE 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
MODEL
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
CODES
RESOLULTION
(BIT)
PACKAGE
TYPE
PACKAGE
MARKING
(SYMBOL)
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
ADS7866I
±1.5
–1/+1.5
12
SOT23-6
A66Y
DBV
–40°C to 85°C
ADS7866IDBVT
Small tape and reel, 250
ADS7866I
±1.5
–1/+1.5
12
SOT23-6
A66Y
DBV
–40°C to 85°C
ADS7866IDBVR
Tape and reel, 3000
ADS7867I
±0.5
±0.5
10
SOT23-6
A67Y
DBV
–40°C to 85°C
ADS7867IDBVT
Small tape and reel, 250
ADS7867I
±0.5
±0.5
10
SOT23-6
A67Y
DBV
–40°C to 85°C
ADS7867IDBVR
Tape and reel, 3000
ADS7868I
±0.5
±0.5
8
SOT23-6
A68Y
DBV
–40°C to 85°C
ADS7868IDBVT
Small tape and reel, 250
ADS7868I
±0.5
±0.5
8
SOT23-6
A68Y
DBV
–40°C to 85°C
ADS7868IDBVR
Tape and reel, 3000
(1)
TRANSPORT
MEDIA,
QUANTITY
ORDERING
NUMBER
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
RATING
VDD to GND
–0.3 V to 4.0 V
Analog input voltage to GND
Digital input voltage to GND
Digital output voltage to GND
–0.3 V to VDD + 0.3 V
–0.3 V to 4.0 V
–0.3 V to VDD + 0.3 V
TA
Operating free-air temperature range
–40°C to 85°C
TSTORAGE
Storage temperature range
–65°C to 150°C
TJ
Junction temperature
SOT-23 Package
Lead temperature,
soldering
ESD
2
150°C
θJA Thermal impedance
110.9°C/W
θJC Thermal impedance
22.31°C/W
Vapor phase (10–40 sec)
250°C
Infrared (10–30 sec)
260°C
3 kV
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7866
At –40°C to 85°C, fSAMPLE = 200 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 100 KSPS and fSCLK = 1.7 MHz if
1.2 V ≤ VDD < 1.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
Resolution
12
No missing codes
Integral linearity
Differential linearity
Offset error (2)
Gain error (3)
Total unadjusted error (4)
Bits
12
Bits
–1.5
1.5
LSB (1)
LSB
–1
1.5
1.2 V ≤ VDD < 1.6 V
–2
2
1.6 V ≤ VDD ≤ 3.6 V
–3
3
1.2 V ≤ VDD < 1.6 V
–2
2
1.6 V ≤ VDD ≤ 3.6 V
–2
2
1.2 V ≤ VDD < 1.6 V
–2.5
2.5
1.6 V ≤ VDD ≤ 3.6 V
–3.5
3.5
LSB
LSB
LSB
SAMPLING DYNAMICS (See Timing Characteristics Section)
tCONVERT
Conversion time
fSCLK = 3.4 MHz, 13 SCLK cycles
3.82
tSAMPLE
Acquisition time
fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V
0.64
fSAMPLE
Throughput rate
fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V
µs
µs
200
KSPS
Aperture delay
10
ns
Aperture jitter
40
ps
DYNAMIC CHARACTERISTICS
SINAD
Signal-to-noise
and distortion
SNR
Signal-to-noise ratio
THD
Total harmonic distortion (5)
SFDR
Spurious free dynamic
range
Full-power bandwidth (6)
fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V
fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V
68
69
fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V
fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V
dB
70
70
70
dB
71
fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V
–70
fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V
–83
fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V
75
fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V
85
At 0.1 dB, 1.2 V ≤ VDD < 1.6 V
2
At 0.1 dB, 1.6 V ≤ VDD ≤ 3.6 V
4
At 3 dB, 1.2 V ≤ VDD < 1.6 V
3
At 3 dB, 1.6 V ≤ VDD ≤ 3.6 V
8
dB
dB
MHz
ANALOG INPUT
Full-scale input span (7)
CS
VIN – GND
0
Input capacitance
VDD
12
Input leakage current
V
pF
–1
1
1.2 V ≤ VDD < 1.6 V
0.7×VDD
3.6
1.6 V ≤ VDD < 1.8 V
0.7×VDD
3.6
1.8 V ≤ VDD < 2.5 V
0.7×VDD
3.6
2.5 V ≤ VDD ≤ 3.6 V
2
3.6
µA
DIGITAL INPUT
Logic family , CMOS
VIH
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Input logic high level
V
LSB = Least Significant BIt
The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.
The difference in the last code transition 011...111 to 111...111 from the ideal value of VDD - 1 LSB with the offset error removed.
The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of
offset error and gain error are included.
The 2nd through 10th harmonics are used to determine THD.
Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.
Ideal input span which does not include gain or offset errors.
3
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7866 (continued)
At –40°C to 85°C, fSAMPLE = 200 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 100 KSPS and fSCLK = 1.7 MHz if
1.2 V ≤ VDD < 1.6 V (unless otherwise noted)
PARAMETER
VIL
Input logic low level
ISCLK
SCLK pin leakage current
ICS
CS pin leakage current
CIN
Digital input pin capacitance
TEST CONDITIONS
MIN
TYP
MAX
1.2 V ≤ VDD < 1.6 V
–0.2
0.2×VDD
1.6 V ≤ VDD < 1.8 V
–0.2
0.2×VDD
1.8 V ≤ VDD < 2.5 V
–0.2
0.3×VDD
2.5 V ≤ VDD ≤ 3.6 V
–0.2
Digital input = 0 V or VDD
–1
UNIT
V
0.8
0.02
1
±1
µA
µA
10
pF
V
DIGITAL OUTPUT
VOH
Output logic high level
ISOURCE = 200 µA
VDD–0.2
VDD
VOL
Output logic low level
ISINK = 200 µA
0
0.2
V
ISDO
SDO pin leakage current
Floating output
–1
1
µA
COUT
Digital output pin
capacitance
Floating output
10
pF
3.6
V
Data format, straight binary
POWER SUPPLY REQUIREMENTS
VDD
Supply voltage
1.2
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V
385
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V
193
fSAMPLE = 50 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V
97
fSAMPLE = 20 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V
39
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 3 V
340
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 3 V
170
fSAMPLE = 50 KSPS, fSCLK = 3.4 MHz, VDD = 3 V
85
fSAMPLE = 20 KSPS, fSCLK = 3.4 MHz, VDD = 3 V
IDD
IDD
Supply current,
normal operation
Power-down mode
Digital inputs = 0 V
or VDD
500
µA
µA
35
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 2.5 V
305
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 2.5 V
153
fSAMPLE = 50 KSPS, fSCLK = 3.4 MHz, VDD = 2.5 V
77
fSAMPLE = 20 KSPS, fSCLK = 3.4 MHz, VDD = 2.5 V
31
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 1.8 V
256
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 1.8 V
128
fSAMPLE = 50 KSPS, fSCLK = 3.4 MHz, VDD = 1.8 V
65
fSAMPLE = 20 KSPS, fSCLK = 3.4 MHz, VDD = 1.8 V
26
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V
241
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V
121
fSAMPLE = 50 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V
61
fSAMPLE = 20 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V
25
fSAMPLE = 100 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V
186
fSAMPLE = 50 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V
93
fSAMPLE = 20 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V
37
SCLK on or off
µA
µA
330
µA
250
µA
0.008
0.3
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V
1.39
1.80
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V
0.39
0.53
fSAMPLE = 100 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V
0.22
0.3
SCLK on or off, VDD = 3.6 V
1.08
µA
POWER DISSIPATION
Normal operation
Power-down mode
mW
µW
TEMPERATURE RANGE
Specified performance
4
–40
85
°C
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7867
At –40°C to 85°C, fSAMPLE = 240 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 120 KSPS and fSCLK = 1.7 MHz if
1.2 V ≤ VDD < 1.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
Resolution
10
No missing codes
Integral linearity
Gain error (3)
Total unadjusted error (4)
Bits
–0.5
Differential linearity
Offset error (2)
Bits
10
0.5
LSB (1)
LSB
–0.5
0.5
1.2 V ≤ VDD < 1.6 V
–0.75
0.75
1.6 V ≤ VDD ≤ 3.6 V
–1
1
1.2 V ≤ VDD < 1.6 V
–0.5
0.5
1.6 V ≤ VDD ≤ 3.6 V
–0.5
0.5
1.2 V ≤ VDD < 1.6 V
–2
2
1.6 V ≤ VDD ≤ 3.6 V
–2
2
LSB
LSB
LSB
SAMPLING DYNAMICS (See Timing Characteristics Section)
tCONVERT
Conversion time
fSCLK = 3.4 MHz, 11 SCLK cycles
tSAMPLE
Acquisition time
fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V
fSAMPLE
Throughput rate
fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V
3.235
µs
0.64
µs
240
KSPS
Aperture delay
10
ns
Aperture jitter
40
ps
DYNAMIC CHARACTERISTICS
SINAD
Signal-to-noise
and distortion
SNR
Signal-to-noise ratio
THD
Total harmonic distortion (5)
SFDR
Spurious free dynamic range
Full-power bandwidth (6)
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V
61
61
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V
61.5
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V
61.8
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V
-68
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V
-78
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V
dB
61.7
dB
-72
73
74
dB
80
At 0.1 dB, 1.2 V ≤ VDD < 1.6 V
2
At 0.1 dB, 1.6 V ≤ VDD ≤ 3.6 V
4
At 3 dB, 1.2 V ≤ VDD < 1.6 V
3
At 3 dB, 1.6 V ≤ VDD ≤ 3.6 V
8
dB
MHz
ANALOG INPUT
Full-scale input span (7)
CS
VIN – GND
0
Input capacitance
VDD
12
Input leakage current
V
pF
–1
1
1.2 V ≤ VDD < 1.6 V
0.7×VDD
3.6
1.6 V ≤ VDD < 1.8 V
0.7×VDD
3.6
1.8 V ≤ VDD < 2.5 V
0.7×VDD
3.6
2.5 V ≤ VDD ≤ 3.6 V
2
3.6
µA
DIGITAL INPUT
Logic family, CMOS
VIH
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Input logic high level
V
LSB = Least Significant BIt
The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.
The difference in the last code transition 011...111 to 111...111 from the ideal value of VDD - 1 LSB with the offset error removed.
The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of
offset error and gain error are included.
The 2nd through 10th harmonics are used to determine THD.
Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.
Ideal input span which does not include gain or offset errors.
5
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7867 (continued)
At –40°C to 85°C, fSAMPLE = 240 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 120 KSPS and fSCLK = 1.7 MHz if
1.2 V ≤ VDD < 1.6 V (unless otherwise noted)
PARAMETER
VIL
Input logic low level
ISCLK
SCLK pin leakage current
ICS
CS pin leakage current
CIN
Digital input pin capacitance
TEST CONDITIONS
MIN
TYP
MAX
1.2 V ≤ VDD < 1.6 V
–0.2
0.2×VDD
1.6 V ≤ VDD < 1.8 V
–0.2
0.2×VDD
1.8 V ≤ VDD < 2.5 V
–0.2
0.3×VDD
2.5 V ≤ VDD ≤ 3.6 V
–0.2
Digital input = 0 V or VDD
–1
UNIT
V
0.8
0.02
1
±1
µA
µA
10
pF
V
DIGITAL OUTPUT
VOH
Output logic high level
ISOURCE = 200 µA
VDD–0.2
VDD
VOL
Output logic low level
ISINK = 200 µA
0
0.2
V
ISDO
SDO pin leakage current
Floating output
–1
1
µA
COUT
Digital output pin
capacitance
Floating output
10
pF
3.6
V
Data format, straight binary
POWER SUPPLY REQUIREMENTS
VDD
IDD
IDD
Supply voltage
Supply current,
normal operation
Power-down mode
1.2
fSAMPLE = 240 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V
420
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V
172
Digital Inputs = 0 V fSAMPLE = 240 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V
or VDD
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V
261
fSAMPLE = 120 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V
202
fSAMPLE = 50 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V
83
500
330
107
SCLK on or off
250
0.008
0.3
fSAMPLE = 240 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V
1.51
1.80
fSAMPLE = 240 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V
0.42
0.53
fSAMPLE = 120 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V
0.24
0.30
µA
µA
µA
µA
POWER DISSIPATION
Normal operation
Power-down mode
SCLK on or off, VDD = 3.6 V
mW
1.08
µW
85
°C
TEMPERATURE RANGE
Specified performance
6
–40
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7868
At –40°C to 85°C, fSAMPLE = 280 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 140 KSPS and fSCLK = 1.7 MHz if
1.2 V ≤ VDD < 1.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
Resolution
8
No missing codes
Integral linearity
Differential linearity
Offset error (2)
Gain error (3)
Total unadjusted error (4)
Bits
8
Bits
–0.5
0.5
LSB (1)
LSB
–0.5
0.5
1.2 V ≤ VDD < 1.6 V
–0.5
0.5
1.6 V ≤ VDD ≤ 3.6 V
–0.5
0.5
1.2 V ≤ VDD < 1.6 V
–0.5
0.5
1.6 V ≤ VDD ≤ 3.6 V
–0.5
0.5
1.2 V ≤ VDD < 1.6 V
–1
1
1.6 V ≤ VDD ≤ 3.6 V
–1
1
LSB
LSB
LSB
SAMPLING DYNAMICS (See Timing Characteristics Section)
tCONVERT
Conversion time
fSCLK = 3.4 MHz, 9 SCLK cycles
tSAMPLE
Acquisition time
fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V
fSAMPLE
Throughput rate
fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V
2.647
µs
0.64
µs
280
KSPS
Aperture delay
10
ns
Aperture jitter
40
ps
DYNAMIC CHARACTERISTICS
SINAD
Signal-to-noise
and distortion
SNR
Signal-to-noise ratio
THD
Total harmonic
distortion (5)
SFDR
Spurious free dynamic
range
Full-power bandwidth (6)
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V
49
49
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V
49.4
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V
49.8
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V
–65
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V
–72
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V
dB
49.4
dB
-66
67
66
dB
67
At 0.1 dB, 1.2 V ≤ VDD < 1.6 V
2
At 0.1 dB, 1.6 V ≤ VDD ≤ 3.6 V
4
At 3 dB, 1.2 V ≤ VDD < 1.6 V
3
At 3 dB, 1.6 V ≤ VDD ≤ 3.6 V
8
dB
MHz
ANALOG INPUT
Full-scale input span (7)
CS
VIN – GND
0
Input capacitance
VDD
12
Input leakage current
V
pF
–1
1
1.2 V ≤ VDD < 1.6 V
0.7×VDD
3.6
1.6 V ≤ VDD < 1.8 V
0.7×VDD
3.6
1.8 V ≤ VDD < 2.5 V
0.7×VDD
3.6
2.5 V ≤ VDD ≤ 3.6 V
2
3.6
µA
DIGITAL INPUT
Logic family, CMOS
VIH
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Input logic high level
V
LSB = Least Significant BIt
The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.
The difference in the last code transition 011...111 to 111...111 from the ideal value of VDD - 1 LSB with the offset error removed.
The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of
offset error and gain error are included.
The 2nd through 10th harmonics are used to determine THD.
Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.
Ideal input span which does not include gain or offset errors.
7
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ADS7867
ADS7868
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SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7868 (continued)
At –40°C to 85°C, fSAMPLE = 280 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 140 KSPS and fSCLK = 1.7 MHz if
1.2 V ≤ VDD < 1.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.2 V ≤ VDD < 1.6 V
–0.2
0.2×VDD
1.6 V ≤ VDD < 1.8 V
–0.2
0.2×VDD
1.8 V ≤ VDD < 2.5 V
–0.2
0.3×VDD
2.5 V ≤ VDD ≤ 3.6 V
–0.2
VIL
Input logic low level
ISCLK
SCLK pin leakage current Digital input = 0 V or VDD
ICS
CS pin leakage current
CIN
Digital input pin
capacitance
–1
UNIT
V
0.8
0.02
1
±1
µA
µA
10
pF
V
DIGITAL OUTPUT
VOH
Output logic high level
ISOURCE = 200 µA
VDD–0.2
VDD
VOL
Output logic low level
ISINK = 200 µA
0
0.2
V
ISDO
SDO pin leakage current
Floating output
–1
1
µA
COUT
Digital output pin
capacitance
Floating output
10
pF
3.6
V
Data format, straight
binary
POWER SUPPLY REQUIREMENTS
VDD
IDD
IDD
Supply voltage
Supply current,
normal operation
Power-down mode
1.2
fSAMPLE = 280 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V
439
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V
154
Digital Inputs = 0 V fSAMPLE = 280 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V
or VDD
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V
264
fSAMPLE = 140 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V
201
fSAMPLE = 50 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V
70
500
330
93
SCLK on or off
0.008
250
0.3
µA
µA
µA
µA
POWER DISSIPATION
Normal operation
Power-down mode
fSAMPLE = 280 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V
1.58
1.8
fSAMPLE = 280 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V
0.42
0.53
fSAMPLE = 140 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V
0.24
SCLK on or off, VDD = 3.6 V
mW
0.3
1.08
µW
85
°C
TEMPERATURE RANGE
Specified performance
8
–40
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ADS7867
ADS7868
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SLAS465 – JUNE 2005
TIMING REQUIREMENTS
(1) (2)
At –40°C to 85°C, fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSCLK = 1.7 MHz if 1.2 V ≤ VDD < 1.6 V, 50-pF Load on SDO Pin,
unless otherwise noted
PARAMETER
tsample
TEST CONDITIONS
MIN
tconvert
TYP
Conversion time
ADS7866
13 × tC(SCLK)
ADS7867
11 × tC(SCLK)
UNIT
Cycle time
µs
µs
9 × tC(SCLK)
ADS7868
tC(SCLK)
MAX
tSU(CSF-FSCLKF) + 2 × tC(SCLK)
Sample time
1.2 V ≤ VDD < 1.6 V
See
(3)
100
1.6 V ≤ VDD < 1.8 V
See
(3)
100
1.8 V ≤ VDD < 2.5 V
See
(3)
50
2.5 V ≤ VDD ≤ 3.6 V
See
(3)
6.7
µs
tWH(SCLK)
Pulse duration
0.4 × tC(SCLK)
0.6 × tC(SCLK)
ns
tWL(SCLK)
Pulse duration
0.4 × tC(SCLK)
0.6 × tC(SCLK)
ns
tSU(CSF-FSCLKF)
Setup time
tD(CSF-SDOVALID)
tH(SCLKF-SDOVALID)
tD(SCLKF-SDOVALID)
tDIS(EOC-SDOZ)
Hold time
Delay time
Disable time
tWH(CS)
Pulse duration
tSU(LSBZ-CSF)
(1)
(2)
(3)
Delay time
Setup time
1.2 V ≤ VDD < 1.6 V
192
1.6 V ≤ VDD < 1.8 V
55
1.8 V ≤ VDD ≤ 3.6 V
55
ns
1.2 V ≤ VDD < 1.6 V
65
1.6 V ≤ VDD < 1.8 V
55
1.8 V ≤ VDD ≤ 3.6 V
55
1.2 V ≤ VDD < 1.6 V
20
1.6 V ≤ VDD < 1.8 V
10
1.8 V ≤ VDD ≤ 3.6 V
10
ns
ns
1.2 V ≤ VDD < 1.6 V
140
1.6 V ≤ VDD < 1.8 V
140
1.8 V ≤ VDD ≤ 3.6 V
140
1.2 V ≤ VDD < 1.6 V
10
80
1.6 V ≤ VDD < 1.8 V
7
60
1.8 V ≤ VDD ≤ 3.6 V
7
60
1.2 V ≤ VDD < 1.6 V
20
1.6 V ≤ VDD < 1.8 V
10
1.8 V ≤ VDD ≤ 3.6 V
10
1.2 V ≤ VDD < 1.6 V
20
1.6 V ≤ VDD < 1.8 V
10
1.8 V ≤ VDD ≤ 3.6 V
10
ns
ns
ns
ns
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See timing diagram in Figure 1.
Min tC(SCLK) is determined by the Min tSAMPLE of the specific resolution and supply voltage. See Acquisition Time, Conversion Time, and
Total Cycle Time section for further details.
HOLD
1
tC(SCLK)
3
2
4
EOC
5
tWH(SCLK)
6
7
8
9
10
16
14
12
Last SCLK= 16 for ADS 7866
14for ADS 7867
12for ADS 7868
1
tSU(CSF−FSCLKF)
2
SCLK
tWL(SCLK)
tWH(CS)
tSU(CSF−FSCLKF)
CS
tSAMPLE
tCONVERT
tDIS(EOC−SDOZ)
tH(SCLKF−SDOVALID)
tD(SCLKF−SDOVALID)
tD(CSF−SDOVALID)
SDO
tSU(LSBZ−CSF)
tD(CSF−SDOVALID)
Hi−Z
Hi−Z
MSB
“0” “0”
“0”
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5
LSB
“0”
Auto Power−Down
“0”
“0”
“0”
Auto Power− Down
tCYCLE
Figure 1. Timing Diagram
9
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ADS7867
ADS7868
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SLAS465 – JUNE 2005
PIN CONFIGURATION
ADS7866/67/68
DBV PACKAGE
(TOP VIEW)
REF/VDD
1
6
CS
GND
2
5
SDO
VIN
3
4
SCLK
TERMINAL FUNCTIONS
TERMINAL
NAME
DESCRIPTION
NO.
REF/VDD
1
External reference input and power supply
GND
2
Ground for signal and power supply. All analog and digital signals are referred with respect to this pin.
VIN
3
Analog signal input
SCLK
4
Serial clock input. This clock is used for clocking data out, and it is the source of conversion clock.
SDO
5
This is the serial data output of the conversion result. The serial stream comes with MSB first. The MSB is clocked out
(changed) on the falling edge one SCLK after the sampling period ends. This results in four leading zeros after CS
becomes active. SDO is 3-stated once all the valid bits are clocked out (12 for ADS7866, 10 for ADS7867, and 8 for
ADS7868).
CS
6
This is an active low input signal. It is used as a chip select to gate the SCLK input, to initiate a conversion, and to
frame output data.
10
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SLAS465 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7866
Normalized Amplitude − dB
FFT (8192 Points)
0
−10
VDD = 1.6 V,
fSAMPLE = 200 kSPS,
fi = 30 kHz,
SNR = 72.31 dB,
SINAD = 71.97 dB,
THD (9) = −83.18 dB,
SFDR = 86.83 dB
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
10
20
30
40
50
60
70
80
90
100
45
50
fi − Input Frquency − kHz
Figure 2.
Normalized Amplitude − dB
FFT (8192 Points)
0
−10
VDD = 1.2 V,
fSAMPLE = 100 kSPS,
fi = 30 kHz,
SNR = 71.42 dB,
SINAD = 67.62 dB,
THD (9) = −69.96 dB,
SFDR = 75.14 dB
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
5
10
15
20
25
30
35
40
fi − Input Frquency − kHz
Figure 3.
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE
AND DISTORTION
vs
INPUT FREQUENCY
VDD = 2.5 V, 200 KSPS
72
SINAD − Signal-to-Noise and Distortion − dB
SNR − Signal-to-Noise Ratio − dB
−56
73
VDD = 3.6 V,
200 KSPS
71.5
71
70.5
VDD = 1.2 V,
100 KSPS
70
VDD = 1.6 V,
200 KSPS
69.5
69
68.5
68
67.5
67
1
10
100
fi − Input Frequency − kHz
Figure 4.
1000
VDD = 3.6 V, 200 KSPS
VDD = 2.5 V,
200 KSPS
69
67
VDD = 1.2 V,
100 KSPS
65
THD Using 2nd − 10th harmonics,
−58
71
THD − Total Harmonic Distortion − dB
73
72.5
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
VDD = 1.6 V,
200 KSPS
63
61
59
TA = 25°C
−60
VDD = 1.2 V,
100 KSPS
−62
−64
VDD = 1.6 V, 200 KSPS
−66
VDD = 2.5 V,
200 KSPS
−68
−70
−72
−74
−76
−78
VDD = 3.6V,
200 KSPS
−80
57
−82
1
10
100
fi − Input Frequency − kHz
Figure 5.
1000
1
10
100
1000
fi − Input Frequency − kHz
Figure 6.
11
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SLAS465 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7866 (continued)
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
300
VDD = 2.5V,
200 KSPS
78
76
74
VDD = 1.6 V,
200 KSPS
72
70
68
VDD = 1.2 V, 100 KSPS
66
VDD = 1.8 V
250
200
175
150
62
1
100
1.6
1000
VDD = 1.6 V
225
125
100
fSAMPLE = 200 KSPS,
fSCLK = 3.4 MHz
TA = 85C
375
TA = 25C
350
TA = −40C
325
300
275
250
225
1.8
2
fi − Input Frequency − kHz
2.2 2.4 2.6 2.8
SCLK Frequency − MHz
Figure 7.
3
3.2
3.4
200
1.6 1.8
2
2.2 2.4 2.6 2.8 3
3.2 3.4 3.6
VDD − Supply Voltage − V
Figure 8.
POWER CONSUMPTION
vs
THROUGHPUT
Figure 9.
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
−58
1.4
TA = 25°C,
SCLK = 3.4 MHz
−60
THD − Total Harmonic Distortion − dB
VDD = 3.6 V
1.2
VDD = 3 V
Power Consumption − mW
400
VDD = 3 V
VDD = 2.5 V
275
64
10
425
TA = 25°C,
fSAMPLE = 100 KSPS
VDD = 3.6 V
ICC − Supply Current − µ A
80
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
325
VDD = 3.6V,
200 KSPS
82
ICC − Supply Current − µ A
SFDR − Spurious Free Dynamic Range − dB
84
SUPPLY CURRENT
vs
SCLK FREQUENCY
1
VDD = 2.5 V
VDD = 1.8 V
0.8
VDD = 1.6 V
0.6
0.4
0.2
−62
−64
VDD = 1.6 V,
TA = 25°C,
fSAMPLE = 200 KSPS,
fSCLK = 3.4 MHz
−66
−68
−70
RI = 100 −72
−74
−76
RI = 500 RI = 1000 −78
−80
RI = 0 −82
0
20
40
60
RI = 10 −84
1
80 100 120 140 160 180 200
Throughput − KSPS
10
100
1000
fi − Input Frequency − kHz
Figure 10.
Figure 11.
INL
INL − LSBs
1
VDD = 1.6 V,
TA = 25°C,
fSAMPLE = 200 KSPS,
fSCLK = 3.4 MHz
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
512
1024
1536
2048
2560
Code
(Straight Binary in Decimal)
Figure 12.
12
3072
3584
4096
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ADS7868
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SLAS465 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7866 (continued)
DNL
1
VDD = 1.6 V,
TA = 25°C,
fSAMPLE = 200 KSPS,
fSCLK = 3.4 MHz
0.8
DNL − LSBs
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
0
512
1024
1536
2048
2560
Code
(Straight Binary in Decimal)
Figure 13.
3072
3584
4096
3072
3584
4096
3072
3584
4096
INL
INL − LSBs
1
VDD = 1.2 V,
TA = 25°C,
fSAMPLE = 100 KSPS,
fSCLK = 1.7 MHz
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
512
1024
1536
2048
2560
Code
(Straight Binary in Decimal)
Figure 14.
DNL
1
VDD = 1.2 V,
TA = 25°C,
fSAMPLE = 100 KSPS,
fSCLK = 1.7 MHz
0.8
DNL − LSBs
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
0
512
1024
1536
2048
2560
Code
(Straight Binary in Decimal)
Figure 15.
13
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SLAS465 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7866 (continued)
MAX SUPPLY CURRENT
vs
SUPPLY VOLTAGE
fSCLK = 3.4 MHz
375
350
450
12-Bit NMC, TA = 25°C,
tSAMPLE = 2.375/fSCLK,
tDIS(EOC-SDOZ)+tSU(LSBZ-CSF) = 0.375/fSCLK,
275 Throughput Rate = 16 SCLK Cycles
fSCLK = 2.4 MHz
325
fSCLK = 1.7 MHz
300
275
425
Throughput Rate − KSPS
ICC − Supply Current − µ A
400
THROUGHPUT RATE
vs
SUPPLY VOLTAGE
300
TA = 25°C,
fSAMPLE = (fSCLK)/16
Throughput Rate − KSPS
425
THROUGHPUT RATE
vs
SUPPLY VOLTAGE
250
225
200
250
175
Figure 16.
14
150
3.2 3.4 3.6
375
350
325
300
12-Bit NMC, TA = 25°C,
tSAMPLE = 2.25/fSCLK,
tDIS(EOC-SDOZ)+tSU(LSBZ-CSF) = 0.25/fSCLK,
Throughput Rate = 16 SCLK Cycles
275
225
200
1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
VDD − Supply Voltage − V
400
1.2
1.4
1.6
VDD − Supply Voltage − V
Figure 17.
1.8
250
1.6
1.8
2
2.2 2.4 2.6 2.8
3 3.2
VDD − Supply Voltage − V
Figure 18.
3.4 3.6
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SLAS465 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7867
Normalized Amplitude − dB
FFT (8192 Points)
0
−10
−20
−30
−40
−50
VDD = 1.2 V,
fSAMPLE = 100 KSPS,
fi = 30 kHz,
SNR = 60.419 dB,
SINAD = 59.877 dB,
THD (9) = −69.181 dB,
SFDR = 73.682 dB
−60
−70
−80
−90
−100
0
5
10
15
20
25
30
35
40
45
50
70
80
90
100
fi − Input Frequency − kHz
Figure 19.
VDD = 1.6 V,
fSAMPLE = 200 KSPS,
fi = 30 kHz,
SNR = 61.173 dB,
SINAD = 61.128 dB,
THD (9) = −80.986 dB,
SFDR = 83.468 dB
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
10
20
30
40
50
60
fi − Input Frequency − kHz
Figure 20.
THROUGHPUT RATE
vs
SUPPLY VOLTAGE
THROUGHPUT RATE
vs
SUPPLY VOLTAGE
450
275
425
Throughput Rate − KSPS
250
Throughput Rate − KSPS
Normalized Amplitude − dB
FFT (8192 Points)
0
−10
225
200
175
150
1.2
10-Bit NMC, TA = 25°C,
tSAMPLE = 2.375/fSCLK,
tDIS(EOC-SDOZ)+tSU(LSBZ-CSF) = 0.375/fSCLK,
Throughput Rate = 14 SCLK Cycles
1.4
1.6
VDD − Supply Voltage − V
Figure 21.
400
375
350
325
300
10-Bit NMC, TA = 25°C,
tSAMPLE = 2.25/fSCLK,
tDIS(EOC-SDOZ)+tSU(LSBZ-CSF) = 0.25/fSCLK,
Throughput Rate = 14 SCLK Cycles
275
1.8
250
1.6
1.8
2
2.2 2.4
2.6 2.8
3
3.2
3.4 3.6
VDD − Supply Voltage − V
Figure 22.
15
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SLAS465 – JUNE 2005
TYPICAL CHARACTERISTICS ADS7868
FFT (8192 Points)
Normalized Amplitude − dB
0
VDD = 1.2 V,
fSAMPLE = 100 KSPS,
fi = 30 kHz,
SNR = 48.669 dB,
SINAD = 48.605 dB,
THD (9) = −66.910 dB,
SFDR = 67.041 dB
−10
−20
−30
−40
−50
−60
−70
−80
−90
0
5
10
15
20
25
30
35
40
45
50
70
80
90
100
fi − Input Frequency − kHz
Figure 23.
FFT (8192 Points)
Normalized Amplitude − dB
0
−10
−20
−30
−40
−50
VDD = 1.6 V,
fSAMPLE = 200 KSPS,
fi = 30 kHz,
SNR = 49.420 dB,
SINAD = 49.413 dB,
THD (9) = −77.085 dB,
SFDR = 67.893 dB
−60
−70
−80
−90
0
10
20
30
40
50
60
fi − Input Frequency − kHz
Figure 24.
THROUGHPUT RATE
vs
SUPPLY VOLTAGE
THROUGHPUT RATE
vs
SUPPLY VOLTAGE
300
575
550
525
Throughput Rate − KSPS
Throughput Rate − KSPS
275
250
225
200
175
150
1.2
8-Bit NMC, TA = 25°C,
tSAMPLE = 2.375/fSCLK,
tDIS(EOC-SDOZ)+tSU(LSBZ-CSF) = 0.375/fSCLK,
Throughput Rate = 12 SCLK Cycles
1.4
1.6
VDD − Supply Voltage − V
Figure 25.
16
500
475
450
425
400
375
350
325
1.8
300
1.6 1.8
8-Bit NMC, TA = 25°C,
tSAMPLE = 2.25/fSCLK,
tDIS(EOC-SDOZ)+tSU(LSBZ-CSF) = 0.25/fSCLK,
Throughput Rate = 12 SCLK Cycles
2
2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD − Supply Voltage − V
Figure 26.
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SLAS465 – JUNE 2005
THEORY OF OPERATION
The ADS7866/67/68 is a family of low supply voltage, low power, high-speed successive approximation register
(SAR) analog-to-digital converters (ADCs). The devices can be operated from a supply range from 1.2 V to 3.6
V. There is no need for an external reference. The reference is derived internally from the supply voltage, so the
analog input range can be from 0 V to VDD. These ADCs use a charge redistribution architecture, which
inherently includes a sample/hold function.
START OF A CONVERSION CYCLE
A conversion cycle is initiated by bringing the CS pin low and supplying the serial clock SCLK. The time between
the falling edge of CS and the third falling edge of SCLK after CS falls is used to acquire the input signal. This
must be greater than or equal to the minimum acquisition time (MIN tSAMPLE in Table 1) specified for the desired
resolution and supply voltage. On the third falling edge of SCLK after CS falls, the device goes into hold mode
and the process of digitizing the sampled input signal starts.
Acquisition Time, Conversion Time, and Total Cycle Time
The maximum SCLK frequency is determined by the minimum acquisition time (MIN tSAMPLE) specified for the
specific resolution and supply voltage of the device. The conversion time is determined by the frequency of SCLK
since this is a synchronous converter. The conversion time is 13 times the SCLK cycle time tC(SCLK) for the
ADS7866, 11 times for the ADS7867, and 9 times for the ADS7868. The acquisition time, which is also the
power up time, is the set-up time between the first falling edge of SCLK after CS falls (tSU(CSF-FSCLKF)) plus 2
times tC(SCLK).
The total cycle time, tCYCLE, which is the inverse of the maximum sample rate, can be calculated as follows:
tCYCLE = tSAMPLE + tCONVERT + 0.5 × tC(SCLK)
if tDIS(EOC-SDOZ) + tSU(LSBZ-CSF) ≤ 0.5 × tC(SCLK)
tCYCLE = tSAMPLE + tCONVERT + tDIS(EOC-SDOZ) + tSU(LSBZ-CSF)
if tDIS(EOC-SDOZ) + tSU(LSBZ-CSF) > 0.5 × tC(SCLK)
17
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465 – JUNE 2005
THEORY OF OPERATION (continued)
Table 1. Acquisition, Conversion, SCLK, and Potential Throughput Calculation
PARAMETER
MIN tSU(CSF-FSCLKF)
MAX tDIS(EOC-SDOZ)
MIN tSU(LSBZ-CSF)
MAX fSCLK
MIN tsample
MIN tconvert
MIN tCYCLE
fsample
SUPPLY VOLTAGE
Setup time
Disable time
Setup time
Frequency
Sample time
Conversion time
Cycle time
Theoretical sample frequency
ADS7866
ADS7867
ADS7868
UNIT
1.2 V ≤ VDD < 1.6 V
192
192
192
1.6 V ≤ VDD < 1.8 V
55
55
55
1.8 V ≤ VDD ≤ 3.6 V
55
55
55
1.2 V ≤ VDD < 1.6V
80
80
80
1.6 V ≤ VDD < 1.8 V
60
60
60
1.8 V ≤ VDD ≤ 3.6 V
60
60
60
1.2 V ≤ VDD < 1.6 V
20
20
20
1.6 V ≤ VDD < 1.8 V
10
10
10
1.8 V ≤ VDD ≤ 3.6 V
10
10
10
1.2 V ≤ VDD < 1.6 V
1.7
1.7
1.7
1.6 V ≤ VDD < 1.8 V
3.4
3.4
3.4
1.8 V ≤ VDD ≤ 3.6 V
3.4
3.4
3.4
1.2 V ≤ VDD < 1.6 V
1368
1368
1368
1.6 V ≤ VDD < 1.8 V
643
643
643
1.8 V ≤ VDD ≤ 3.6 V
643
643
643
1.2 V ≤ VDD < 1.6 V
7647
6471
5294
1.6 V ≤ VDD < 1.8 V
3824
3235
2647
1.8 V ≤ VDD ≤ 3.6 V
3824
3235
2647
1.2 V ≤ VDD < 1.6 V
9116
7939
6763
1.6 V ≤ VDD < 1.8 V
4537
3949
3360
1.8 V ≤ VDD ≤ 3.6 V
4537
3949
3360
1.2 V ≤ VDD < 1.6 V
110
126
148
1.6 V ≤ VDD < 1.8 V
220
253
298
1.8 V ≤ VDD ≤ 3.6 V
220
253
298
ns
ns
ns
MHz
ns
ns
ns
KSPS
TYPICAL CONNECTION
For a typical connection circuit for the ADS7866/67/68 see Figure 27. A REF3112 is used to supply 1.2 V to the
device. A 0.1-µF decoupling capacitor is required between the REF/VDD and GND pins of the converter. This
capacitor should be placed as close as possible to the pins of the device. Designers should strive to minimize the
routing length of the traces that connect the terminals of the capacitor to the pins of the converter.
Keep in mind the converter offers no inherent rejection of noise or voltage variation in regards to the reference
input. This is of particular concern because the reference input is tied to the power supply. Any noise and ripple
from the supply appears directly in the digital results. While high frequency noise can be filtered out as described
in the previous paragraph, voltage variation due to the line frequency (50 Hz or 60 Hz) can be difficult to remove.
1.8 V
REF3112
1.2 V
GND
0.1 F
Host
Processor
SS
REF/VDD
GND
CS
ADS7866/67/68
SCK
SCLK
MISO
SDO
VIN
Analog Input
Figure 27. Typical Circuit Configuration
18
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465 – JUNE 2005
ANALOG INPUT
Figure 28 shows the analog input equivalent circuit for the ADS7866/67/68. The analog input is provided
between the VIN and GND pins. When a conversion is initiated, the input signal is sampled on the internal
capacitor array. When the converter enters hold mode, the input signal is captured on the internal capacitor
array. The VIN input range is limited to 0 V to VDD because the reference is derived from the supply.
The current flowing into the analog input depends upon a number of factors, such as the sample rate, the input
voltage, and the input source impedance. The current from the input source charges the internal capacitor array
during the sample period. After this capacitance has been fully charged, there is no further input current. The
source of the analog input voltage must be able to charge the input capacitance CS (12 pF typical) within the
minimum acquisition time (MIN tSAMPLE) specified for the desired resolution and supply voltage. In the case of the
ADS7866, the MIN tSAMPLE for 12-bit resolution is 643 ns (VDD between 1.6 V and 3.6 V). When the converter
goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. In order to maintain the linearity of the
converter, the span (VIN – GND) should be within the limits specified. Outside of these limits, the converter’s
linearity may not meet specifications. Noise introduced into the converter from the input source may be
minimized by using low bandwidth input signals along with low-pass filters.
VDD
Device is in Hold Mode
60 VIN
12 pF
+
4 pF
2.105 k
_
VMID
GND
Figure 28. Analog Input Equivalent Circuit (Typical Impedance Values at VDD = 1.6 V, TA = 27°C)
Choice of Input Driving Amplifier
The analog input to the converter needs to be driven with a low noise, low voltage op amp like the OPA364 or
OPA333. An RC filter is recommended at the input pin to low-pass filter the noise from the source. The input to
the converter is a unipolar input voltage in the range 0 V to VDD.
DIGITAL INTERFACE
The ADS7866/67/68 interface with microprocessors or DSPs through a high-speed SPI compatible serial
interface with CPOL = 1 (inactive SCLK returns to logic high or SCLK leading edge is the rising edge), CPHA = 1
(output data changes on falling edge of SCLK and is available on the rising edge of SCLK). The sampling,
conversion, and activation of SDO are initiated on the falling edge of CS. The serial clock (SCLK) is used for
controlling the rate of conversion. It also provides a mechanism allowing synchronization with digital host
processors.
The digital inputs, CS and SCLK, can exceed the supply voltage VDD as long as they do not exceed the
maximum VIH of 3.6 V. This allows the ADS7866/67/68 family to interface with host processors which use a
different supply voltage than the converter without requiring external level-shifting circuitry. Furthermore, the
digital inputs can be applied to CS and SCLK before the supply voltage of the converter is activated without the
risk of creating a latch-up condition.
Conversion Result
The ADS7866/67/68 outputs 12/10/8-bit data after 4 leading zeros, respectively. These codes are in straight
binary format as shown in Table 2.
19
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465 – JUNE 2005
The serial output SDO is activated on the falling edge of CS. The first leading zero is available on SDO until the
first falling edge of SCLK after CS falls. The remaining 3 leading zeros are shifted out on SDO on the first,
second, and third falling edges of SCLK after CS falls. The MSB of the converted result follows 4 leading zeros
and is clocked out on the fourth falling edge of SCLK. The rising edge of CS or the falling edge of SCLK when
the EOC occurs puts SDO output into 3-state. Refer to Table 2 for ideal output codes versus input voltages.
Table 2. ADS7866/67/68 Ideal Output Codes Versus Input Voltages
DESCRIPTION
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT STRAIGHT BINARY
BINARY CODE
HEX CODE
ADS7866
Least Significant Bit (LSB)
VDD/4096
Full Scale
VDD – 1LSB
1111 1111 1111
FFF
Midscale
VDD/2
1000 0000 0000
800
VDD/2 – 1LSB
0111 1111 1111
7FF
0V
0000 0000 0000
000
Midscale – 1LSB
Zero
ADS7867
Least Significant Bit (LSB)
VDD/1024
Full Scale
VDD – 1LSB
11 1111 1111
3FF
Midscale
VDD/2
10 0000 0000
200
VDD/2 – 1LSB
01 1111 1111
1FF
0V
00 0000 0000
000
FF
Midscale – 1LSB
Zero
ADS7868
Least Significant Bit (LSB)
VDD/256
Full Scale
VDD – 1LSB
1111 1111
Midscale
VDD/2
1000 0000
80
VDD/2 – 1LSB
0111 1111
7F
0V
0000 0000
00
Midscale – 1LSB
Zero
POWER DISSIPATION
The ADS7866/67/68 family is capable of operating with very low supply voltages while drawing a fraction of a
milliamp. Furthermore, there is an auto power-down mode to reduce the power dissipation between conversion
cycles. Carefully selected system design can take advantage of these features to achieve optimum power
performance.
Auto Power-Down Mode
The ADS7866/67/68 family has an auto power-down feature. Besides powering down all circuitry, the converter
consumes only 8 nA typically in this mode. The device automatically wakes up when CS falls. However, not all of
the functional blocks are fully powered until sometime before the third falling edge of SCLK. The device powers
down once it reaches the end of conversion (EOC) which is the 16th falling edge of SCLK for the ADS7866 (the
14th and 12th for the ADS7867 and ADS7868, respectively). If CS is pulled high before the device reaches the
EOC, the converter goes into power-down mode and the ongoing conversion is aborted. Refer to the timing
diagram in Figure 1 for further information.
Power Saving: SCLK Frequency and Throughput
These converters achieve lower power dissipation for a fixed throughput rate fsample = 1/tcycle by using higher
SCLK frequencies. Higher SCLK frequencies reduce the acquisition time (tsample) and conversion time (tconvert).
This means the converters spend more time in auto power-down mode per conversion cycle. This can be
observed in Figure 8 which shows the ADS7866 supply current versus SCLK frequency for fsample = 100 KSPS.
For a particular SCLK frequency, the acquisition time and conversion time are fixed. Therefore, a lower
throughput increases the proportion of the time the converters are in power down. Figure 10 shows this case for
the ADS7866 power consumption versus throughput rate for fSCLK = 3.4 MHz.
20
www.ti.com
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
Power-On Initialization
There is no specific initialization requirement for these converters after power-on, but the first conversion might
not yield a valid result. In order to set the converter in a known state, CS should be toggled low then high after
VDD has stabilized during power-on. By doing this, the converter is placed in auto power-down mode, and the
serial data output (SDO) is 3-stated.
21
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS7866IDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
A66Y
ADS7866IDBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
A66Y
ADS7866IDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
A66Y
ADS7866IDBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
A66Y
ADS7867IDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
A67Y
ADS7867IDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-250C-1 YEAR
-40 to 85
A67Y
ADS7868IDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
A68Y
ADS7868IDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
A68Y
ADS7868IDBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
A68Y
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
24-Aug-2018
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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