Texas Instruments | 2nd-Order Delta-Sigma Modulator with Excitation for Hall Elements (Rev. A) | Datasheet | Texas Instruments 2nd-Order Delta-Sigma Modulator with Excitation for Hall Elements (Rev. A) Datasheet

Texas Instruments 2nd-Order Delta-Sigma Modulator with Excitation for Hall Elements (Rev. A) Datasheet
 ADS1208
SBAS348A – MARCH 2005 – REVISED MARCH 2005
2nd-Order Delta-Sigma Modulator
with Excitation for Hall Elements
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
The ADS1208 is a 2nd-order ∆Σ (delta-sigma) modulator operating at a 10MHz clock rate. The specified
input range is ±100mV, optimized for current
measurement with a Hall sensor, especially in motor
control applications. The ADS1208 contains a
programmable current source for sensor biasing and
has integrated input buffers for fast settling of the
sample capacitors; it also requires only a minimum of
external components. The differential analog input
offers low noise and excellent common-mode rejection.
±100mV Specified Input Range
±125mV Full-Scale Range
95dB typ. CMR, 82dB typ. SNR
Adjustable Current Output for Sensor Biasing
Digital Output Compatible to ADS1202/03
Differential Digital Outputs
Separate 2.7V to 5.5V Digital Supply Pin
APPLICATIONS
•
•
•
•
•
Motor Control
Current Measurement
Hall Sensors
Bridge Sensors
Instrumentation
AVDD
BVDD
AVDD
ADS1208
IADJ
IOUT
REFOUT
Internal 2.5V
Reference
Buffer
REFIN
Buffer
VIN+
Buffer
2nd−Order
∆Σ Modulator
VIN−
Interface
Circuit
Buffer
M0
RC Oscillator
20MHz
AGND
MDATA
MDATA
MCLK
MCLK
M1
BGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
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SBAS348A – MARCH 2005 – REVISED MARCH 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Package/Ordering Information
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
ADS1208I
UNIT
Supply voltage, AGND to AVDD
–0.3 to +6
V
Supply voltage, BGND to BVDD
–0.3 to +6
V
Analog input voltage with respect to AGND
AGND – 0.3 to AVDD + 0.3
V
Reference input voltage with respect to AGND
AGND – 0.3 to AVDD + 0.3
V
Digital input voltage with respect to BGND
BGND – 0.3 to BVDD + 0.3
V
Ground voltage difference AGND to BGND
±0.3
V
Input current to any pin except supply
±10
mA
Power dissipation
See Dissipation Ratings Table
Operating virtual junction temperature range, TJ
–40 to +150
°C
Operating free-air temperature range, TA
–40 to +85
°C
Storage temperature range, TSTG
–65 to +150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply voltage, AGND to AVDD
Supply voltage, BGND to BVDD
NOM
MAX
4.5
5.0
5.5
UNIT
V
Low-voltage levels
2.7
3.6
V
5V logic levels
4.5
5.0
5.5
V
0.5
2.5
3.0
V
+VREFIN /20
V
Reference input voltage
Analog inputs
MIN
VIN+– VIN-
–VREFIN /20
DISSIPATION RATINGS TABLE
BOARD
PACKAGE
Low-K (1)
High-K (2)
(1)
(2)
2
RθJC
RθJA
PW
35°C/W
147°C/W
PW
33.6°C/W
108.4°C
TA≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
6.8mW/°C
850mW
544mW
442mW
9.225W/°C
1150mW
738mW
600mW
DERATING FACTOR
ABOVE TA = 25°C
The JEDEC low-K (1s) board used to derive this data was a 3in x 3in, two-layer board with 2-ounce copper traces on top of the board.
The JEDEC high-K (2s2p) board used to derive this data was a 3in x 3in, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
ADS1208
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ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at –40°C to +85°C, AVDD = BVDD = +5V, VREF = internal +2.5V,
Mode 3, MCLK input = 20MHz, differential input voltage = 200mVPP, common-mode voltage = 1.4V, and 16-bit Sinc3 filter with
OSR = 256, unless otherwise noted.
ADS1208I
PARAMETER
TEST CONDITIONS
Resolution
MIN
TYP (1)
MAX
16
UNIT
Bits
DC Accuracy
Integral nonlinearity (2)
16-bit resolution
Integral nonlinearity
Differential nonlinearity (3)
16-bit resolution
Input offset (4)
–8
1.6
8
–0.012
0.0025
0.012
–1.0
Gain error (4)
Referenced to voltage at REFIN
Gain error drift
Referenced to voltage at REFIN
LSB
0
mV
–1.4
2.0
8.0
–1.25
–0.7
1.25
Power-supply rejection ratio
%
1.0
–2.0
Input offset drift
LSB
µV/°C
%
15
ppm/°C
66
dB
Analog Input
Full-scale range
VIN+– VIN–
Operating common-mode signal
–125
0.8
125
1.4
2.5
mV
V
Input capacitance
5.0
pF
Common-mode rejection
95
dB
Current Source (IOUT)
Output current (5)
IOUT
1.0
Voltage at IOUT pin
VOUT
0
Voltage between AVDD pin and IADJ
5.0
8.0
AVDD – 1.0
VADJ at IOUT = 1mA to 8mA
480
500
520
REFOUT
2.45
2.5
2.55
mA
V
mV
Internal Voltage Reference
Reference output voltage
Reference temperature drift
20
Output resistance
0.3
Output source current
V
ppm/°C
Ω
3.0
mA
Power-supply rejection ratio
60
dB
Startup time
0.1
ms
Voltage Reference Input
Reference voltage input
REFIN
0.5
Reference input capacitance
Reference input current
3.0
5
-50
V
pF
+50
nA
12.0
MHz
24.0
MHz
Internal Clock for Modes 0, 1 and 2
Clock frequency
8.0
10.1
External Clock for Mode 3
Clock frequency
(1)
(2)
(3)
(4)
(5)
1.0
All values are at TA = 25°C.
Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer
curve for VIN+– VIN– = –100mV to +100mV, expressed either as the number of LSBs or as a percent of the measured input range
(200mV).
Ensured by design.
Maximum values, including temperature drift, are ensured over the full specified temperature range.
It is possible to leave pin IOUT unconnected (IOUT = 0mA).
3
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating free-air temperature range at –40°C to +85°C, AVDD = BVDD = +5V, VREF = internal +2.5V,
Mode 3, MCLK input = 20MHz, differential input voltage = 200mVPP, common-mode voltage = 1.4V, and 16-bit Sinc3 filter with
OSR = 256, unless otherwise noted.
ADS1208I
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
AC Accuracy
SNR
VIN = 200mVPP at 1kHz
80
82
dB
SINAD
VIN = 200mVPP at 1kHz
77
81.5
dB
THD
VIN = 200mVPP at 1kHz
SFDR
VIN = 200mVPP at 1kHz
–91
80
–80
93
dB
dB
Digital Inputs (6)
Logic family
CMOS
VIH
High-level input voltage
0.7 x BVDD
BVDD + 0.3
V
VIL
Low-level input voltage
–0.3
0.3 x BVDD
V
IIN
Input current
50
nA
CI
Input capacitance
VIN = BVDD or GND
–50
5
pF
Digital Outputs (6)
Logic family
CMOS
VOH
High-level output voltage
BVDD = 4.5V, IOH = –100µA
VOL
Low-level output voltage
BVDD = 4.5V, IOL = +100µA
CL
Load capacitance
4.44
Data format
V
0.5
V
30
pF
V
Bit stream
Digital Inputs (7)
Logic family
LVCMOS
VIH
High-level input voltage
BVDD = 3.6V
2
BVDD + 0.3
VIL
Low-level input voltage
BVDD = 2.7V
–0.3
0.8
V
IIN
Input current
VIN = BVDD or GND
–50
50
nA
CI
Input capacitance
Digital
5
pF
Outputs (7)
Logic family
LVCMOS
VOH
High-level output voltage
BVDD = 2.7, IOH = –100µA
VOL
Low-level output voltage
BVDD = 2.7, IOL = +100µA
CL
Load capacitance
BVDD – 0.2
Data format
V
0.2
V
30
pF
V
Bit stream
Power Supply
Analog supply voltage, AVDD
4.5
5.0
5.5
Digital interface supply voltage, BVDD
2.7
5
5.5
V
Modes 0, 1 and 2
11.9
15.0
mA
Operating supply current, AIDD
Mode 3
11.5
14.5
mA
Operating supply current, BIDD
Modes 0, 1 and 2
2.3
3.0
mA
Operating supply current, BIDD
Mode 3
1.3
2.0
mA
Power dissipation
Modes 0, 1 and 2
71
90
mW
Power dissipation
Mode 3
64
82.5
mW
Operating supply current, AIDD
(6)
(7)
4
Applicable for 5.0V nominal supply; BVDD (min) = 4.5V and BVDD (max) = 5.5V.
Applicable for 3.0V nominal supply; BVDD (min) = 2.7V and BVDD (max) = 3.6V
ADS1208
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PARAMETER MEASUREMENT INFORMATION
tC1
MCLK
tW1
tD1
MDATA
Figure 1. Mode 0 Operation
TIMING CHARACTERISTICS: MODE 0
Over recommended operating free-air temperature range at –40°C to +85°C, and AVDD = +5V, BVDD = +2.7 to +5.5V, unless
otherwise noted.
PARAMETER
tC1
Clock period
tW1
Clock high time
tD1
Data delay after rising edge of clock
MIN
MAX
UNIT
83
125
ns
(tC1 /2) – 5
(tC1 /2) + 5
ns
–2
+2
ns
tC2
MCLK
tW2
tD2
tD3
MDATA
Figure 2. Mode 1 Operation
TIMING CHARACTERISTICS: MODE 1
Over recommended operating free-air temperature range at –40°C to +85°C, and AVDD = +5V, BVDD = +2.7 to +5.5V, unless
otherwise noted.
PARAMETER
MIN
MAX
UNIT
tC1
Clock period
166
250
ns
tW2
Clock high time
(tC2 /2) – 5
(tC2 /2) + 5
ns
tD2
Data delay after rising edge of clock
(tW2 /2) – 2
(tW2 /2) + 2
ns
tD3
Data delay after falling edge of clock
(tW2 /2) – 2
(tW2 /2) + 2
ns
5
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tC 1
Internal
MCLK
tW 1
Internal
MDATA
1
0
1
1
0
0
MDATA
Figure 3. Mode 2 Operation
TIMING CHARACTERISTICS: MODE 2
Over recommended operating free-air temperature range at –40°C to +85°C, and AVDD = +5V, BVDD = +2.7 to +5.5V, unless
otherwise noted.
PARAMETER
tC1
Clock period
tW1
Clock high time
MIN
MAX
UNIT
83
125
ns
(tC1 /2) – 5
(tC1 /2) + 5
ns
tC 4
M C LK
tW 4
tD 4
M C LK
M D AT
note:
MCLK is system clock input. MCLK is modulator clock output. Modulator clock frequency is half of system clock
frequency.
Figure 4. Mode 3 Operation
TIMING CHARACTERISTICS: MODE 3
Over recommended operating free-air temperature range at –40°C to +85°C, and AVDD = +5V, BVDD = +2.7 to +5.5V, unless
otherwise noted.
MIN
MAX
UNIT
tC4
Clock period
PARAMETER
41
1000
ns
tW4
Clock high time
10
tC4 – 10
ns
tD4
Data and output clock delay after falling edge of input clock
0
10
ns
tR
Rise time of clock (10% to 90% of BVDD)
0
10
ns
tF
Fall time of clock (90% to 10% of BVDD)
0
10
ns
6
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DEVICE INFORMATION
16-LEAD TSSOP PACKAGE
(TOP VIEW)
IOUT
1
16 BVDD
IADJ
2
15 BGND
AVDD
3
14 MCLK
VIN+
4
VIN−
5
12 MDATA
AGND
6
11 MDATA
REFIN
7
10 M0
REFOUT
8
9
13 MCLK
ADS1208
M1
Table 1. TERMINAL FUNCTIONS
PIN
DESCRIPTION
NO.
NAME
1
IOUT
Current output for sensor
2
IADJ
Output current adjustment
3
AVDD
Analog supply
4
VIN+
Positive input
5
VIN–
Negative input
6
AGND
Analog ground
7
REFIN
Reference input
8
REFOUT
9
M1
Mode selection input
10
M0
Mode selection input
11
MDATA
Inverted data output
12
MDATA
Noninverted data output
13
MCLK
Inverted clock output (Modes 0, 1); Clock input (Mode 3)
14
MCLK
Noninverted clock output
15
BGND
Digital interface ground
16
BVDD
Digital interface supply (2.7V to 5.5V)
Reference output
7
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FUNCTIONAL BLOCK DIAGRAM
+5V
IOUT
R2
RADJ
IADJ
BGND
AVDD
MCLK
VIN+
R3
R4
BVDD
+5V
100nF
Hall Element
R1
10µF
100nF
ADS1208
10µF
MCLK
VIN−
MDATA
AGND
MDATA
REFIN
M0
REFOUT
M1
1kΩ
100nF
A.
For Functional configuration (Mode 0), possible Hall elements include the Toshiba THS119 and the Philips KMZ10.
Figure 5. Functional Configuration (Mode 0)
8
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TYPICAL CHARACTERISTICS
At 25°C, AVDD = BVDD = +5V, VREF = internal +2.5V, Mode 3, MCLK input = 20MHz, differential input voltage = 200mVPP,
common-mode voltage = 1.4V, and 16-bit Sinc3 filter with OSR = 256, unless otherwise noted.
INTEGRAL NONLINEARITY vs
INPUT SIGNAL (Mode 0)
INTEGRAL NONLINEARITY vs
INPUT SIGNAL (Mode 3, MCLK = 20MHZ)
6
4
3
4
2
3
1
INL (LSB)
INL (LSB)
+25 C
5
2
+85 C
1
+85 C
−40C
0
+25 C
−1
−2
0
−40 C
−1
−2
−100 −80 −60 −40 −20
0
−3
20
40
60
80
−4
−100 −80 −60 −40 −20
100
Differential Input Signal (mV)
0
20
40
60
80
100
Differential Input Signal (mV)
Figure 6.
Figure 7.
INTEGRAL NONLINEARITY vs
TEMPERATURE
GAIN ERROR vs
TEMPERATURE
0
6
M0
−0.1
5
−0.2
Gain Error (%)
INL (LSB)
4
3
M3
2
−0.3
−0.4
−0.5
M0
−0.6
1
−0.7
0
−0.8
−40
M3
−40
−20
0
+20
+40
+60
+80
−20
0
Figure 9.
OFFSET vs
TEMPERATURE
OFFSET vs
POWER SUPPLY
0
0
−0.2
+60
+80
−0.4
−0.4
−0.6
Offset (mV)
Offset (mV)
+40
Figure 8.
−0.2
−0.8
−1.0
M0
−1.2
−0.6
−0.8
−1.0
M0
−1.2
−1.4
−1.4
−1.6
−40
+20
Temperature (C)
Temperature (C)
−20
M3
−1.6
M3
0
+20
+40
Temperature (C)
Figure 10.
+60
+80
−1.8
4.50
4.75
5.00
5.25
5.50
Power Supply (V)
Figure 11.
9
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TYPICAL CHARACTERISTICS (continued)
At 25°C, AVDD = BVDD = +5V, VREF = internal +2.5V, Mode 3, MCLK input = 20MHz, differential input voltage = 200mVPP,
common-mode voltage = 1.4V, and 16-bit Sinc3 filter with OSR = 256, unless otherwise noted.
SIGNAL-TO-NOISE RATIO vs
TEMPERATURE
85
85
84
84
83
83
M0
SINAD (dB)
SNR (dB)
SIGNAL-TO-NOISE AND DISTORTION vs
TEMPERATURE
82
M3
81
M3
82
81
80
80
79
79
M0
78
78
−40
−20
0
+20
+40
+60
−40
+80
−20
0
+40
+60
+80
Temperature (C)
Figure 12.
Figure 13.
SIGNAL-TO-NOISE RATIO vs
DECIMATION RATIO
EFFECTIVE NUMBER OF BITS vs
DECIMATION RATIO
100
16
90
14
80
12
Sincfast
70
Sinc3
60
Sinc2
ENOB (BIts)
SNR (dB)
+20
Temperature (C)
50
40
Sinc2
10
8
Sinc1
6
Sinc3
30
4
20
2
10
0
0
1
10
100
Decimation Ratio (OSR)
Figure 14.
10
1000
1
10
100
Decimation Ratio (OSR)
Figure 15.
1000
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TYPICAL CHARACTERISTICS (continued)
At 25°C, AVDD = BVDD = +5V, VREF = internal +2.5V, Mode 3, MCLK input = 20MHz, differential input voltage = 200mVPP,
common-mode voltage = 1.4V, and 16-bit Sinc3 filter with OSR = 256, unless otherwise noted.
−105
105
−105
100
−100
100
−100
95
−95
90
−90
SFDR
85
THD
80
−40
−20
0
+20
+40
+60
SFDR (dB)
105
−95
95
SFDR
THD
90
−90
−85
85
−85
−80
80
−80
−40
+80
THD (dB)
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs
TEMPERATURE (Mode 3)
THD (dB)
SFDR (dB)
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs
FREQUENCY (Mode 1)
−20
0
+20
+40
+60
+80
Temperature ( C)
Temperature (C)
Figure 16.
Figure 17.
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs
FREQUENCY (Mode 1)
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs
TEMPERATURE (Mode 3)
−105
105
−105
105
SFDR
−100
100
−100
100
−95
95
THD
90
−90
−85
85
−85
−80
80
THD (dB)
−90
90
SFDR (dB)
−95
95
THD (dB)
SFDR (dB)
SFDR
THD
85
80
0
5
10
fSIG (kHz)
Figure 18.
15
20
−80
0
5
10
15
20
fSIG (kHz)
Figure 19.
11
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TYPICAL CHARACTERISTICS (continued)
At 25°C, AVDD = BVDD = +5V, VREF = internal +2.5V, Mode 3, MCLK input = 20MHz, differential input voltage = 200mVPP,
common-mode voltage = 1.4V, and 16-bit Sinc3 filter with OSR = 256, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 POINT FFT, fIN = 5kHz)
0
0
−20
−20
−40
−40
Magnitude (dB)
Magnitude (dB)
FREQUENCY SPECTRUM
(4096 POINT FFT, fIN = 1kHz)
−60
−80
−100
−120
−80
−100
−120
−140
−140
0
5
10
15
20
0
5
10
15
Frequency (kHz)
Frequency (kHz)
Figure 20.
Figure 21.
COMMON-MODE REJECTION RATIO vs
FREQUENCY
POWER-SUPPLY REJECTION RATIO vs
FREQUENCY
110
20
90
105
85
M3
100
80
95
M0
90
PSRR (dB)
CMRR (dB)
−60
85
80
75
M0
70
65
M3
75
60
70
55
65
60
50
1
10
100
1000
0.1
1
10
100
Frequency (kHz)
Frequency (kHz)
Figure 22.
Figure 23.
CLOCK FREQUENCY vs
TEMPERATURE
CLOCK FREQUENCY vs
POWER SUPPLY
10.6
1000
10.20
10.5
10.4
10.15
MCLK (MHz)
MCLK (MHz)
10.3
10.2
10.1
10.0
10.10
10.05
9.9
9.8
10.00
9.7
9.6
−40
−20
0
+20
+40
Temperature (C)
Figure 24.
12
+60
+80
9.95
4.50
4.75
5.00
VDD (V)
Figure 25.
5.25
5.50
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TYPICAL CHARACTERISTICS (continued)
At 25°C, AVDD = BVDD = +5V, VREF = internal +2.5V, Mode 3, MCLK input = 20MHz, differential input voltage = 200mVPP,
common-mode voltage = 1.4V, and 16-bit Sinc3 filter with OSR = 256, unless otherwise noted.
ANALOG POWER SUPPLY CURRENT vs
TEMPERATURE
DIGITAL POWER SUPPLY CURRENT vs
TEMPERATURE
14
3.0
13
2.5
M0
M0
2.0
I DD (mA)
I DD (mA)
12
M3
11
10
1.0
9
0.5
8
M3
0
−40
−20
0
+20
+40
+60
−40
+80
0
+20
+60
+80
Figure 26.
Figure 27.
REFERENCE OUTPUT VOLTAGE vs
TEMPERATURE
REFERENCE OUTPUT VOLTAGE vs
POWER SUPPLY
2.5000
2.4998
2.4998
2.4996
2.4996
2.4994
2.4994
2.4992
2.4992
2.4990
2.4988
2.4990
2.4988
2.4986
2.4986
2.4984
2.4984
2.4982
2.4982
2.4980
−20
2.4980
0
+20
+40
+60
+80
3.0
3.5
4.0
Temperature ( C)
4.5
5.0
5.5
Figure 28.
Figure 29.
REFERENCE OUTPUT VOLTAGE vs
LOAD CURRENT
CURRENT SOURCE REFERENCE VOLTAGE vs
LOAD VOLTAGE (I = 8mA)
2.525
499.2
2.520
499.1
2.515
499.0
2.510
498.9
2.505
2.500
2.495
2.490
6.0
VDD (V)
VREF (mV)
VREF (V)
+40
Temperature (C)
2.5000
−40
−20
Temperature (C)
VREF (V)
VREF (V)
1.5
4.5V
VDD = 5.5V
VDD = 4.5V
498.8
498.7
498.6
VDD = 5.0V
498.5
5.5V
498.4
2.485
5.0V
2.480
498.3
498.2
2.475
−5
0
5
10
15
20
0
1
2
3
IOUT (mA)
VOUT (V)
Figure 30.
Figure 31.
4
5
6
13
ADS1208
www.ti.com
SBAS348A – MARCH 2005 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
At 25°C, AVDD = BVDD = +5V, VREF = internal +2.5V, Mode 3, MCLK input = 20MHz, differential input voltage = 200mVPP,
common-mode voltage = 1.4V, and 16-bit Sinc3 filter with OSR = 256, unless otherwise noted.
CURRENT SOURCE REFERENCE VOLTAGE vs
POWER SUPPLY (I = 8mA)
499.2
499.2
499.1
499.1
499.0
499.0
498.9
498.9
VADJ (mV)
VADJ (mV)
CURRENT SOURCE REFERENCE VOLTAGE vs
TEMPERATURE (I = 8mA)
498.8
498.7
498.6
498.8
498.7
498.6
498.5
498.5
498.4
498.4
498.3
498.3
498.2
−40
−20
0
+20
+40
+60
498.2
4.00
+80
4.25
4.50
Figure 32.
10
9
8
RMS Noise (µV)
5.00
Figure 33.
RMS NOISE vs
INPUT VOLTAGE LEVEL
7
6
5
4
3
2
1
0
−125 −100 −75 −50 −25
0
25
50
Differential Input Voltage (V)
Figure 34.
14
4.75
VDD (V)
Temperature ( C)
75
100
125
5.25
5.50
5.75
6.00
ADS1208
www.ti.com
SBAS348A – MARCH 2005 – REVISED MARCH 2005
APPLICATION INFORMATION
GENERAL DESCRIPTION
The ADS1208 is a 2nd-order delta-sigma modulator,
which is implemented with a switched capacitor
circuit. The analog input signal is continuously
sampled by the modulator and compared to an
internal voltage reference. A digital bit stream, which
accurately represents the analog input voltage over
time, appears at the output of the converter.
The ADS1208 is optimized for Hall sensors and
similar applications. As a result, the full-scale input
range is ±VREFIN/20, which is typically ±125mV. However, to achieve good noise and linearity, only 80% of
this range should be used (±100mV). The analog
input pins (VIN+ and VIN-) are internally buffered with
two low-noise, high bandwidth, low offset amplifiers.
A current source is also integrated into the ADS1208
that can be used for biasing a Hall element or bridge
sensor. This current can be programmed with a
resistor that must be placed between AVDD and
IADJ.
Additionally, the ADS1208 includes a reference voltage source with a buffered output. A reference input
pin is provided as well. The voltage at the REFIN pin
sets the analog input range.
The device digital interface is fully compatible with the
ADS1202 and ADS1203. The ADS1208 also provides
inverted outputs of MCLK and MDATA (MCLK and
MDATA, respectively) to increase noise immunity for
the digital data transmission.
The clock source can be internal as well as external.
Different clock frequencies in combination with an
optional digital filter enable a variety of solutions and
signal bandwidths.
Figure 5 (page 8) shows the functional block diagram
with external circuitry. The Hall element is biased
from the internal current source. The current is set by
resistor RADJ. An offset compensation of the Hall
element is enabled by the optional resistors R1 to R4.
The analog inputs VIN+ and VIN– are directly connected with the Hall element outputs. The reference input
REFIN is connected to the reference output REFOUT
with an optional RC low-pass filter, for additional
noise filtering. For both power-supply pairs, AVDD
and BVDD, decoupling capacitors of 100nF and 10µF
(respectively) are recommended.
ANALOG SECTION
Modulator
The 2nd-order modulator acts as a filter. The input
signal is low-passed while the quantization noise is
shifted to higher frequencies. A digital low-pass filter
should be used at the output of the delta-sigma
modulator. The primary purpose of the digital filter is
to remove high-frequency noise. The secondary purpose is to convert the 1-bit data stream at a high
sampling rate into a higher-bit data word at a lower
rate (that is, decimation). A digital signal processor
(DSP), microcontroller (µC), or field programmable
gate array (FPGA) could be used to implement the
digital filter.
Analog Inputs
The internal sampling capacitors present a very
significant load that needs to be recharged within
50ns. The ADS1208 provides two input buffers to
decouple the sampling capacitors from the pins (VIN+,
VIN–). These buffers provide a high bandwidth
(typically, 50MHz) at a low noise and low offset. This
configuration improves the system performance significantly, if the input source has a high impedance in
the kΩ range. A source impedance in this range
without buffers would decrease THD and linearity
significantly, and would also cause a gain error that
changes with supply or temperature.
The input buffers have an auto zero function to
reduce the input offset. The auto zero switches of the
input buffers may apply a glitch of 10fC to 50fC to the
signal source in each clock cycle. For this reason,
placing a 1nF capacitor between the inputs is recommended, if the source impedance is larger than
500Ω. See Figure 35 for the equivalent input circuit,
including the protection diodes.
AVDD
AZ
VIN+
AZ
Delta−Sigma
Modulator
VIN−
Figure 35. Equivalent Input Circuit
Internal Reference
The ADS1208 includes a 2.5V reference. The reference output is connected to the REFOUT pin via an
output buffer that can source 3mA. The sink current is
limited to 50µA. The output resistance of this buffer is
0.3Ω. The internal reference is also used to control
the current source at the IOUT pin.
The ADS1208 additionally provides a REFIN pin. The
applied voltage VREFIN sets the gain of the internal
15
ADS1208
www.ti.com
SBAS348A – MARCH 2005 – REVISED MARCH 2005
modulator. An external reference could vary from
0.5V to 3V. The modulator input range is defined to
±VREFIN/20. For a 2.5V reference, the full-scale range
is ±125mV. The REFIN pin is decoupled from the
modulator with a buffer.
Current Source for the Hall Element
also directly proportional to the reference voltage, the
drift of the reference is actually cancelled out. Be
aware that this is only the case if the application is
using IOUT to drive the Hall sensor and if REFIN is
connected to REFOUT.
Y OUT 1
RADJ
Internal circuitry (see Figure 36) forces the IADJ pin
to a potential of:
V
V IADJ AVDD REFOUT
5
This means that trimming the resistor can calibrate
the gain of the entire system. The resistor can be
chosen to be stable over temperature, or to compensate any temperature behavior of the Hall sensor.
DIGITAL OUTPUT
AVDD
VREF/5
VADJ = 0.5V
IADJ
RI = 0.3Ω
+5V
RADJ
e.g., 100Ω
for 5mA
IOUT
A differential analog input signal of 0V ideally produces a stream of 1s and 0s that are high 50% of the
time and low 50% of the time. A differential analog
input of +100mV produces a stream of 1s and 0s that
are high 80% of the time. A differential analog input
of –100mV produces a stream of 1s and 0s that are
high 20% of the time. The input voltage versus the
output modulator signal is shown in Figure 37.
ROUT
DIGITAL INTERFACE
Figure 36. Current Source
This means that the voltage drop of the resistor RADJ
is equal to the current source reference VADJ.
V
V ADJ REFOUT 0.5 V
5
With resistor RADJ placed between AVDD and IADJ, a
current of:
V REFOUT
I OUT 5 R ADJ0.3
is sourced out of the IOUT pin. The current should be
set between 1mA and 8mA. However, it is also
possible to leave the pin open. As the Hall voltage is
directly proportional to this current, the input voltage
to the modulator VIN is directly proportional to the
internal reference voltage VREFOUT. As the filtered
digital output data word YOUT from the modulator is
Introduction
The analog signal that is connected to the input of the
delta-sigma modulator is converted using the clock
signal that is applied to the modulator. The result of
the conversion, or modulation, is the output signal
MDATA from the delta-sigma modulator. In most
applications, the two standard signals (MCLK and
MDATA) are provided from the modulator to an ASIC,
FPGA, DSP, or µC (each with an implemented filter,
respectively). A single wire interface is provided in
Mode 2, where the data stream is Manchester
encoded. This configuration reduces the costs for
galvanic isolation.
The interface also provides the inverted outputs
MDATA and MCLK for the signals MDATA and
MCLK, respectively. These inverted outputs are useful for systems with high common-mode noise at the
digital data transmission. The digital interface is
specified for the voltage range of 2.7V to 5.5V.
Modulator Output
+FS (Analog Input)
−FS (Analog Input)
Analog Input
Figure 37. Analog Input vs Modulator Output of the ADS1208
16
ADS1208
www.ti.com
SBAS348A – MARCH 2005 – REVISED MARCH 2005
Different Modes of Operation
Mode 2
The typical system clock of the ADS1208 is 20MHz.
The system clock can be provided either from the
internal 20MHz RC oscillator or from an external
clock source. For this reason, the MCLK pin is
bidirectional and is controlled by the mode setting.
The system clock is divided by two for the modulator
clock. Therefore, the default clock frequency of the
modulator is 10MHz. With a possible external clock
range of 1MHz to 24MHz, the modulator operates
between 500kHz and 12MHz. The four modes of
operation for the digital data interface are shown in
Table 2.
In Mode 2, the internal RC oscillator is running. The
data is Manchester encoded and is provided at the
MDATA and MDATA pins. There is no clock output in
this mode. The MCLK and MCLK outputs are set to
low. The Manchester coding allows the data transfer
with only a single wire. See Figure 3 on page 6.
Mode 0
In Mode 0, the internal RC oscillator is running. The
data is provided at the MDATA and MDATA output
pins, and the modulator clock at the MCLK and
MCLK pins. The data changes at the falling edge of
MCLK. Therefore, it can safely be strobed with the
rising edge. See Figure 1 on page 5.
Mode 1
In Mode 1, the internal RC oscillator is running. The
data is provided at the MDATA and MDATA output
pins. The frequency at the MCLK and MCLK pins is
equivalent to the modulator clock frequency divided
by two. The data must be strobed at both the rising
and falling edges of MCLK. The data at MDATA
changes in the middle, between the rising and falling
edge. In this mode, the frequency of both MCLK and
MDATA is only 5MHz. See Figure 2 on page 5.
Mode 3
In Mode 3, the internal RC oscillator is disabled. The
system clock must be provided externally at the input
MCLK. The system clock must have twice the frequency of the chosen modulator clock. The data is
provided at the MDATA and MDATA output pins.
Since the modulator runs with half the frequency of
the system clock, the data changes at every other
falling edge of the external clock. The data can be
safely strobed at every rising edge of the MCLK
output, which provides half the frequency of the
system clock. This mode allows synchronous operation to any digital system or the use of modulator
clocks different from 10MHz. See Figure 4 on page 6.
Filter Usage
The modulator generates only a bitstream, which is
different from the digital word of an analog-to-digital
converter (ADC). In order to output a digital word
equivalent to the analog input voltage, the bitstream
must be processed by a digital filter. A very simple
filter built with minimal effort and hardware is the
Sinc3 filter, shown in Equation 1:
OSR
H(z) 1z 1
1z
3
(1)
Table 2. Operating Mode Definition and Description
MODE DEFINITION
M1
M0
Low
Low
Internal clock, synchronous data output, half output clock frequency
Low
High
Internal clock, Manchester encoded data output, no clock output
High
Low
External clock, synchronous data output
High
High
Mode 0
Internal clock, synchronous data output
Mode 1
Mode 2
Mode 3
17
ADS1208
www.ti.com
SBAS348A – MARCH 2005 – REVISED MARCH 2005
0
OSR = 32
fDATA = 10MHz/32 = 312.5kHz
−3dB: 81.9kHz
−10
Gain (dB)
−20
−30
−40
−50
−60
−70
−80
0
200
400
600
800 1000
Frequency (kHz)
1200
1400
1600
3
Figure 38. Frequency Response of Sinc Filter
16
14
12
ENOB (BIts)
This filter provides the best output performance at the
lowest hardware size (for example, a count of digital
gates). For oversampling ratios in the range of 16 to
256, the Sinc3 filter is a good choice. All
characterizations in this datasheet were obtained
using a Sinc3 filter with an oversampling ratio (OSR)
of 256 and an output word length of 16 bits. In a
Sinc3 filter response (shown in Figure 38 and Figure 39), the location of the first notch occurs at the
frequency of output data rate fDATA = fCLK/OSR. The
–3dB point is located at half the Nyquist frequency, or
fDATA/4. For some applications, it may be necessary
to use another filter type for better frequency response. Device performance can be improved, for
example, by using a cascaded filter structure. The
first decimation stage can be a Sinc3 filter with a low
OSR and a second stage, high-order filter.
Sincfast
8
Sinc1
6
Sinc3
4
2
0
1
10
In motor control applications, a very fast response
time for overcurrent detection is required. There is a
constraint between 1µs and 5µs with 3 bits to 7 bits
of resolution. The time for full settling depends on the
filter order. Therefore, the full settling of the Sinc3
filter needs three data clocks and the Sinc2 filter
needs two data clocks. The data clock is equal to the
modulator clock divided by the OSR. For overcurrent
protection, filter types other than Sinc3 might be a
better choice. A good example is a Sinc2 filter.
Figure 41 compares the settling time of different filter
types. The Sincfast is a modified Sinc2 filter, as
shown in Equation 2:
2
OSR
H(z) 1z 1 1z 2OSR
1z
(2)
Sinc3
9
OSR = 32
FSR = 32768
ENOB = 9.9 Bits
Settling Time =
3 × 1/fDATA = 9.6µs
8
Sincfast
7
ENOB (Bits)
Output Code
1000
Figure 40. Measured ENOB vs OSR
10
20k
100
Decimation Ratio (OSR)
30k
25k
Sinc2
10
15k
Sinc2
6
5
4
Sinc
3
10k
2
5k
1
0
0
0
0
5
10
15
20
25
30
Number of Output Clocks
35
40
Figure 39. Pulse Response of Sinc3 Filter
(fMOD = 10MHz)
The effective number of bits (ENOB) can be used to
compare the performance of ADCs and delta-sigma
modulators. Figure 40 shows the ENOB of the
ADS1208 with different filter types. In this datasheet,
the ENOB is calculated from the SNR:
SNR = 1.76dB + 6.02dB × ENOB
18
1
2
3
4
5
6
Settling Time (µs)
7
8
9
10
Figure 41. Measured ENOB vs Settling Time
For more information, see application note SBAA094,
Combining the ADS1202 with an FPGA Digital Filter
for Current Measurement in Motor Control Applications, available for download at www.ti.com.
ADS1208
www.ti.com
LAYOUT CONSIDERATIONS
Power Supplies
The ADS1208 has two power supplies, AVDD and
BVDD. If there are separate analog and digital power
supplies on the board, a good design approach is to
have AVDD connected to the analog and BVDD to
the digital power supply. Another possible approach
to control noise is the use of a resistor on the power
supply. The connection can be made between the
ADS1208 power supply pins via a 5Ω resistor. The
combination of this resistor and the decoupling capacitors between the power supply pins AVDD and
AGND provides some filtering. The analog supply
must be well-regulated and offer low noise. For
designs requiring higher resolution from the
ADS1208, power-supply rejection will be a concern.
The digital power supply has high-frequency noise
that can be coupled into the analog portion of the
ADS1208. This noise can originate from switching
power supplies,
microprocessors, or
DSPs.
High-frequency noise will generally be rejected by the
external digital filter at integer multiples of MCLK.
Just below and above these frequencies, noise will
alias back into the passband of the digital filter,
affecting the conversion result. Inputs to the
ADS1208, such as VIN+, VIN- and MCLK should not be
present before the power supply is turned on. Violating this condition could cause latch-up. If these
signals are present before the supply is turned on,
series resistors should be used to limit the input
current. Additional user testing may be necessary in
order to determine the appropriate connection between the ADS1208 and different power supplies.
SBAS348A – MARCH 2005 – REVISED MARCH 2005
Grounding
Analog and digital sections of the system design must
be carefully and cleanly partitioned. Each section
should have its own ground plane, with no overlap
between them. Do not join the ground planes. Instead, connect the two planes with a moderate signal
trace underneath the modulator. For multiple modulators, connect the two ground planes as close as
possible to one central location for all of the modulators. In some cases, experimentation may be required to find the best point to connect the two planes
together.
Decoupling
Good decoupling practices must be used for the
ADS1208 and for all components in the system
design. All decoupling capacitors, specifically the
0.1µF ceramic capacitors, must be placed as close as
possible to the respective pin being decoupled. A 1µF
and 10µF capacitor, in parallel with the 0.1µF ceramic
capacitor, can be used to decouple AVDD to AGND.
At least one 0.1µF ceramic capacitor must be used to
decouple BVDD to BGND, as well as for the digital
supply on each digital component
It is highly recommended to place the 100nF compensation capacitor, which is connected between
AVDD and AGND, directly at pins 3 and 6. Otherwise,
current glitches from the internal circuitry can cause
glitches in the supply, which again causes jitter on the
internal clock signal. This jitter degrades the noise
performance of the ADS1208. The input signals VIN+
and VIN– can be routed underneath this capacitor.
19
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
ADS1208IPW
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
PW
16
90
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
AZ1208I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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