Texas Instruments | 12-Bit, 10MHz Sampling Analog-To-Digital Converter (Rev. B) | Datasheet | Texas Instruments 12-Bit, 10MHz Sampling Analog-To-Digital Converter (Rev. B) Datasheet

Texas Instruments 12-Bit, 10MHz Sampling Analog-To-Digital Converter (Rev. B) Datasheet
ADS802
ADS
802
U
SBAS039B – MAY 1995 – REVISED FEBRUARY 2005
12-Bit, 10MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
●
●
●
●
●
The ADS802 is a low-power, monolithic 12-bit, 10MHz Analog-to-Digital (A/D) converter utilizing a small geometry CMOS
process. This complete converter includes a 12-bit quantizer,
wideband track-and-hold, reference, and three-state outputs.
It operates from a single +5V power supply and can be
configured to accept either differential or single-ended input
signals.
NO MISSING CODES
LOW POWER: 250mW
INTERNAL REFERENCE
WIDEBAND TRACK-AND-HOLD: 65MHz
SINGLE +5V SUPPLY
APPLICATIONS
The ADS802 employs digital error correction in order to
provide excellent Nyquist differential linearity performance
for demanding imaging applications. Its low distortion, high
SNR, and high oversampling capability give it the extra
margin needed for telecommunications, test instrumentation,
and video applications.
●
●
●
●
IF AND BASEBAND DIGITIZATION
DATA ACQUISITION CARDS
TEST INSTRUMENTATION
CCD IMAGING
Copiers
Scanners
Cameras
● VIDEO DIGITIZING
● GAMMA CAMERAS
This high-performance A/D converter is specified for AC and
DC performance at a 10MHz sampling rate. The ADS802 is
available in an SO-28 package.
CLK
MSBI
OE
Error
Correction
Logic
3-State
Outputs
Timing
Circuitry
IN
Pipeline
A/D
Converter
T/H
IN
12-Bit
Digital
Data
+3.25V
REFT
CM
REFB
+1.25V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 1995-2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
+VS ........................................................................................................ +6V
Analog Input .............................................................. 0V to (+VS + 300mV)
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Logic Input ................................................................. 0V to (+VS + 300mV)
Case Temperature .......................................................................... +100°C
Junction Temperature ..................................................................... +150°C
Storage Temperature ...................................................................... +125°C
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
External Top Reference Voltage (REFT) .................................. +3.4V Max
External Bottom Reference Voltage (REFB) .............................. +1.1V Min
NOTE: (1) Stresses above these ratings may permanently damage the device.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS802U
SO-28
DW
–40°C to +85°C
ADS802U
ADS802U
Rails, 28
ADS802U
"
"
"
ADS802U
ADS802U/1K
Tape and Reel, 1000
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, and Sampling Rate = 10MHz, and with a 50% duty cycle clock having 2ns rise-and-fall time, unless otherwise noted.
ADS802U
PARAMETER
RESOLUTION
Specified Temperature Range
ANALOG INPUT
Differential Full-Scale Input Range
Common-Mode Voltage
Analog Input Bandwidth (–3dB)
Small-Signal
Full-Power
Input Impedance
DIGITAL INPUT
Logic Family
Convert Command
ACCURACY(2)
Gain Error
Gain Tempco
Power-Supply Rejection of Gain
Input Offset Error
Power-Supply Rejection of Offset
CONDITIONS
TEMP
–40
Both Inputs
+1.25
–20dBFS(1) Input
0dBFS Input
+25°C
+25°C
MAX
UNITS
+85
Bits
°C
fS = 2.5MHz
∆ +VS = ±5%
+3.25
V
V
400
65
1.25 || 4
MHz
MHz
MΩ || pF
±0.6
±1.0
±85
0.03
±2.1
0.05
+25°C
Full
∆ +VS = ±5%
+2.25
TTL/HCT Compatible CMOS
Falling Edge
Start Conversion
+25°C
Full
+25°C
10k
±1.5
±2.5
0.1
±3.0
0.1
f = 5MHz
Best Fit
±0.3
±0.4
±0.4
±0.4
Tested
±1.7
+25°C
0°C to +85°C
+25°C
0°C to +85°C
0°C to +85°C
0°C to +85°C
+25°C
Full
+25°C
Full
67
66
63
62
77
75
67
66
%
%
ppm/°C
%FSR/%
%
%FSR/%
10M
Sample/s
Convert Cycle
±1.0
±1.0
±1.0
±1.0
LSB
LSB
LSB
LSB
LSB
LSB
6.5
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500kHz
f = 5MHz (–1dBFS input)
TYP
12
TAMBIENT
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
No Missing Codes
Integral Linearity Error at f = 500kHz
Spurious-Free Dynamic Range (SFDR)
f = 500kHz (–1dBFS input)
MIN
±2.75
dBFS
dBFS
dBFS
dBFS
NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) IMD is referred
to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (4) No “rollover” of bits.
2
ADS802
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SBAS039B
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, and Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
ADS802U
PARAMETER
CONDITIONS
TEMP
DYNAMIC CHARACTERISTICS (Cont.)
2-Tone Intermodulation Distortion (IMD)(3)
f = 4.4MHz and 4.5MHz (–7dBFS each tone)
+25°C
Full
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input)
f = 5MHz (–1dBFS input)
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
f = 5MHz (–1dBFS input)
Differential Gain Error
Differential Phase Error
Aperture Delay Time
Aperture Jitter
Over-Voltage Recovery Time(4)
OUTPUTS
Logic Family
Logic Coding
Logic Levels
NTSC or PAL
NTSC or PAL
1.5x Full-Scale Input
Logic Selectable
Logic LOW
Logic HIGH
3-State Enable Time
3-State Disable Time
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Power Consumption
MIN
Operating
Operating
Operating
Operating
Operating
TYP
MAX
UNITS
–65
–64
dBc
dBc
+25°C
Full
+25°C
Full
65
64
64
62
67
67
66
66
dB
dB
dB
dB
+25°C
Full
+25°C
Full
+25°C
+25°C
+25°C
+25°C
+25°C
63
61
61
60
66
65
63
62
0.5
0.1
2
7
2
dB
dB
dB
dB
%
Degrees
ns
ps rms
ns
TTL/HCT Compatible CMOS
SOB or BTC
Full
Full
Full
Full
0
2.0
Full
+25°C
Full
+25°C
Full
+4.75
Thermal Resistance, θJA
SO-28
20
2
0.4
+VS
40
10
V
V
ns
ns
+5.0
50
52
250
260
+5.25
62
62
310
310
V
mA
mA
mW
mW
75
°C/W
NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) IMD is referred
to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (4) No “rollover” of bits.
ADS802
SBAS039B
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3
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
SO
GND
1
28
GND
B1
2
27
IN
B2
3
26
IN
B3
4
25
GND
B4
5
24
+VS
B5
6
23
REFT
B6
7
22
CM
ADS802
PIN
DESIGNATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
GND
+VS
CLK
+VS
OE
19
MSBI
20
21
+VS
REFB
B7
8
21
REFB
B8
9
20
+VS
B9
10
19
MSBI
B10
11
18
OE
B11
12
17
+VS
B12
13
16
CLK
22
CM
GND
14
15
+VS
23
REFT
24
25
26
27
28
+VS
GND
IN
IN
GND
DESCRIPTION
Ground
Bit 1, Most Significant Bit (MSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12, Least Significant Bit (LSB)
Ground
+5V Power Supply
Convert Clock Input, 50% Duty Cycle
+5V Power Supply
HIGH: High-Impedance State. LOW or Floating:
Normal Operation. Internal pull-down resistors.
Most Significant Bit Inversion, HIGH: MSB inverted for complementary output. LOW or Floating: Straight output. Internal pull-down resistors.
+5V Power Supply
Bottom Reference Bypass. For external bypassing of internal +1.25V reference.
Common-Mode Voltage. It is derived by
(REFT + REFB)/2.
Top Reference Bypass. For external bypassing
of internal +3.25V reference.
+5V Power Supply
Ground
Input
Complementary Input
Ground
TIMING DIAGRAM
tCONV
Convert
Clock
tL
tD
tH
DATA LATENCY
(6.5 Clock Cycles)
Hold
Hold
Hold
Hold
Hold
Hold
Track “N + 1” Track “N + 2” Track “N + 3” Track “N + 4” Track “N + 5” Track “N + 6” Track
(1)
Internal
Track-and-Hold
Track
Hold
“N”
t2
Output
Data
Data Valid
N–8
Data Valid
N–7
Data Valid
N–6
N–5
N–4
N–3
N–2
N–1
N
t1
Data Invalid
SYMBOL
tCONV
tL
tH
tD
t1
t2
NOTE: (1) “
4
DESCRIPTION
MIN
Convert Clock Period
Clock Pulse LOW
Clock Pulse HIGH
Aperture Delay
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
100
48
48
TYP
MAX
UNITS
100µs
ns
ns
ns
ns
ns
ns
50
50
2
3.9
12.5
” indicates the portion of the waveform that will stretch out at slower sample rates.
ADS802
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SBAS039B
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fIN = 1MHz
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
fIN = 500kHz
–20
–60
–80
–100
–60
–80
–100
–120
–120
0
1.0
2.0
3.0
4.0
5.0
0
1.0
2.0
Frequency (MHz)
3.0
4.0
5.0
Frequency (MHz)
SPECTRAL PERFORMANCE
2-TONE INTERMODULATION
0
0
–20
–20
f1 = 4.5MHz
–60
Amplitude (dB)
Amplitude (dB)
–40
3fO
–80
2fO
–100
f2 = 4.4MHz
–40
–60
–80
–100
–120
–120
0
1.0
2.0
3.0
4.0
5.0
0.0
1.25
Frequency (MHz)
2.5
3.75
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
2.0
2.0
fIN = 5MHz
fIN = 500kHz
1.0
DLE (LSB)
1.0
DLE (LSB)
5.0
Frequency (MHz)
0
–1.0
0
–1.0
–2.0
–2.0
0
1.0
2.0
3.0
4.0
0
Code
2.0
3.0
4.0
Code
ADS802
SBAS039B
1.0
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5
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
OUTPUT NOISE HISTOGRAM (NO SIGNAL)
SWEPT POWER SFDR
800k
100
80
fIN = 10MHz
SFDR (dBFS)
Counts
600k
400k
60
40
200k
20
0.0
0
N–2
N–1
N
N+1
N+2
–50
–40
–30
Code
–20
SWEPT POWER SNR
0
10
INTEGRAL LINEARITY ERROR
80
4.0
fIN = 500kHz
fIN = 5MHz
60
2.0
ILE (LSB)
SNR (dB)
–10
Input Amplitude (dBm)
40
20
0
–2.0
0
–50
–40
–30
–20
–10
0
–4.0
10
0
1.0
2.0
3.0
4096
Input Amplitude (dBm)
Code
DYNAMIC PERFORMANCE vs
SINGLE-ENDED FULL-SCALE INPUT RANGE
DYNAMIC PERFORMANCE vs
DIFFERENTIAL FULL-SCALE INPUT RANGE
75
75
70
70
Dynamic Range (dB)
Dynamic Range (dB)
SFDR (fIN = 5MHz)
SNR (fIN = 5MHz)
65
SFDR (fIN = 5MHz)
60
55
SNR (fIN = 5MHz)
60
55
1
6
65
2
3
4
Single-Ended Full-Scale Range (Vp-p)
5
1
2
3
4
Differential Full-Scale Input Range (Vp-p)
5
ADS802
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SBAS039B
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR vs
TEMPERATURE
SPURIOUS-FREE DYNAMIC RANGE (SFDR) vs
TEMPERATURE
80
1.0
75
SFDR (dBFS)
DLE (LSBs)
0.8
0.6
fIN = 5MHz
0.4
fIN = 500kHz
70
65
0.2
fIN = 5MHz
fIN = 500kHz
60
0.1
0
–25
25
50
Temperature (°C)
75
–50
100
–25
0
25
50
75
100
Temperature (°C)
SIGNAL-TO-(NOISE + DISTORTION) vs
TEMPERATURE
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
70
68
fIN = 500kHz
fIN = 500kHz
66
SINAD (dB)
SNR (dB)
68
66
fIN = 5MHz
64
fIN = 5MHz
64
62
62
60
–50
–25
0
25
50
75
100
–50
–25
Temperature (°C)
0
25
50
75
100
Temperature (°C)
SUPPLY CURRENT vs TEMPERATURE
POWER DISSIPATION vs TEMPERATURE
265
52
260
IQ (mA)
PD (mW)
53
255
51
250
50
–50
–25
0
25
50
75
–50
100
Temperature (°C)
0
25
50
75
100
Temperature (°C)
ADS802
SBAS039B
–25
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7
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
OFFSET ERROR vs TEMPERATURE
–1.25
–0.55
–1.5
Offset (%FSR)
Gain (%FSR)
GAIN ERROR vs TEMPERATURE
–0.05
–1.05
–1.55
–2.0
–2.5
–50
–25
0
25
50
75
100
–50
Temperature (°C)
TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH
25
50
75
100
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
80
0
75
SFDR, SNR (dB)
Track-Mold Input Response (dB)
0
Temperature (°C)
1
–1
–2
–3
SFDR
70
65
SNR
60
–4
–5
10k
100k
1M
10M
100M
55
100k
1G
Frequency (Hz)
8
–25
1M
10M
Frequency (Hz)
ADS802
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SBAS039B
THEORY OF OPERATION
Op Amp
Bias
The ADS802 is a high-speed, sampling A/D converter with
pipelining. It uses a fully differential architecture and digital
error correction to ensure 12-bit resolution. The differential
track-and-hold circuit is shown in Figure 1. The switches are
controlled by an internal clock that has a non-overlapping 2phase signal, φ1 and φ2. At the sampling time, the input
signal is sampled on the bottom plates of the input capacitors. In the next clock phase, φ2, the bottom plates of the
input capacitors are connected together and the feedback
capacitors are switched to the op amp output. At this time,
the charge redistributes between CI and CH, completing one
track-and-hold cycle. The differential output is a held DC
representation of the analog input at the sample time. The
track-and-hold circuit can also convert a single-ended input
signal into a fully differential signal for the quantizer.
The pipelined quantizer architecture has 11 stages with each
stage containing a 2-bit quantizer and a 2-bit Digital-toAnalog Converter (DAC), as shown in Figure 2. Each 2-bit
quantizer stage converts on the edge of the sub-clock, which
is twice the frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to time-
IN
IN
φ1
φ1
CH
φ2
CI
IN
IN
φ1
φ2
OUT
φ1
OUT
φ1
CI
φ2
CH
φ1
φ1
Input Clock (50%)
Op Amp
Bias
VCM
Internal Non-Overlapping Clock
φ1
φ2
φ1
FIGURE 1. Input Track-and-Hold Configuration with Timing
Signals.
Digital Delay
Input
T/H
2-Bit
Flash
STAGE 1
VCM
2-Bit
DAC
+
Σ
–
x2
B1 (MSB)
Digital Delay
B2
STAGE 2
B3
2-Bit
DAC
Digital Error Correction
2-Bit
Flash
+
Σ
–
x2
B4
B5
B6
B7
B8
B9
B10
Digital Delay
B11
B12 (LSB)
2-Bit
Flash
STAGE 10
2-Bit
DAC
+
Σ
–
x2
STAGE 11
2-Bit
Flash
Digital Delay
FIGURE 2. Pipeline A/D Converter Architecture.
ADS802
SBAS039B
www.ti.com
9
align it with the data created from the following quantizer
stages. This aligned data is fed into a digital error correction
circuit that can adjust the output data based on the information found on the redundant bits. This technique gives the
ADS802 excellent differential linearity and ensures no missing codes at the 12-bit level.
Since there are two pipeline stages per external clock cycle,
there is a 6.5 clock cycle data latency from the start convert
signal to the valid output data. The output data is available in
Straight Offset Binary (SOB) or Binary Two’s Complement
(BTC) format.
THE ANALOG INPUT AND INTERNAL REFERENCE
The analog input of the ADS802 can be configured in various
ways and driven with different circuits, depending on the
nature of the signal and the level of performance desired.
The ADS802 has an internal reference that sets the full-scale
input range of the A/D converter. The differential input range
has each input centered around the common-mode of +2.25V,
with each of the two inputs having a full-scale range of
+1.25V to +3.25V. Since each input is 2Vp-p and 180° outof-phase with the other, a 4V differential input signal to the
quantizer results. As shown in Figure 3, the positive full-scale
reference (REFT) and the negative full-scale (REFB) are
brought out for external bypassing. In addition, the commonmode voltage (CM) may be used as a reference to provide
the appropriate offset for the driving circuitry. However, care
must be taken not to appreciably load this reference node.
For more information regarding external references, singleended input, and ADS802 drive circuits, refer to the applications section.
DIGITAL OUTPUT DATA
The 12-bit output data is provided at CMOS logic levels. The
standard output coding is Straight Offset Binary (SOB) where
a full-scale input signal corresponds to all “1s” at the output,
as shown in Table I. This condition is met with pin 19 “LO” or
Floating due to an internal pull-down resistor. By applying a
logic “HI” voltage to this pin, a Binary Two’s Complement
(BTC) output will be provided where the most significant bit
is inverted. The digital outputs of the ADS802 can be set to
a high-impedance state by driving OE (pin 18) with a logic
“HI”. Normal operation is achieved with pin 18 “LO” or floating
due to internal pull-down resistors. This function is provided
for testability purposes and is not meant to drive digital buses
directly, or be dynamically changed during the conversion
process.
OUTPUT CODE
DIFFERENTIAL INPUT(1)
SOB
PIN 19
FLOATING or LOW
BTC
PIN 19
HIGH
111111111111
111111111111
111111111110
111000000000
110000000000
101000000000
100000000001
100000000000
011111111111
011000000000
010000000000
001000000000
000000000001
000000000000
011111111111
011111111111
011111111110
011000000000
010000000000
001000000000
000000000001
000000000000
111111111111
111000000000
110000000000
101000000000
100000000001
100000000000
+FS (IN = +3.25V, IN = +1.25V)
+FS – 1LSB
+FS – 2LSB
+3/4 Full-Scale
+1/2 Full-Scale
+1/4 Full-Scale
+1LSB
Bipolar Zero (IN = IN = +2.25V)
–1LSB
–1/4 Full-Scale
–1/2 Full-Scale
–3/4 Full-Scale
–FS + 1LSB
–FS (IN = +1.25V, IN = +3.25V)
NOTE: (1) In the single-ended input mode, +FS = +4.25V and –FS = +0.25V.
TABLE I. Coding Table for the ADS802.
ADS802
APPLICATIONS
+3.25V
23
REFT
DRIVING THE ADS802
0.1µF
2kΩ
+2.25V
22
The ADS802 has a differential input with a common-mode of
+2.25V. For AC-coupled applications, the simplest way to
create this differential input is to drive the primary winding of
a transformer with a single-ended input. A differential output is
created on the secondary if the center tap is tied to the
common-mode voltage of +2.25V, as in Figure 4. This trans-
To
Internal
Comparators
CM
2kΩ
21
0.1µF
REFB
+1.25V
FIGURE 3. Internal Reference Structure.
22 CM
0.1µF
CLOCK REQUIREMENTS
The CLK pin accepts a CMOS level clock input. The rising
and falling edges of the externally applied convert command
clock controls the various interstage conversions in the
pipeline. Therefore, the duty cycle of the clock should be held
at 50% with low jitter and fast rise-and-fall times of 2ns or
less. This is particularly important when digitizing a highfrequency input and operating at the maximum sample rate.
Deviation from a 50% duty cycle will effectively shorten some
of the interstage settling times, thus degrading the SNR and
DNL performance.
10
26 IN
ac Input
Signal
ADS802
22pF
Mini-Circuits
TT1-6-KK81
or Equivalent
27 IN
22pF
FIGURE 4. AC-Coupled Single-Ended to Differential Drive
Circuit Using a Transformer.
ADS802
www.ti.com
SBAS039B
former-coupled input arrangement provides good high-frequency AC performance. It is important to select a transformer
that gives low distortion and does not exhibit core saturation at
full-scale voltage levels. Since the transformer does not appreciably load the ladder, there is no need to buffer the CommonMode (CM) output in this instance. In general, it is advisable
to keep the current draw from the CM output pin below 0.5µA
to avoid nonlinearity in the internal reference ladder. A FET
input operational amplifier, such as the OPA130, can provide
a buffered reference for driving external circuitry. The analog
IN and IN inputs should be bypassed with 22pF capacitors to
minimize track-and-hold glitches and to improve high input
frequency performance.
mined by fC = 1/(2pRSER • (CSH + CADC)), where RSER is the
resistor in series with the input, CSH is the external capacitor
from the input to ground, and CADC is the internal input
capacitance of the A/D converter (typically 4pF).
Figure 5 illustrates another possible low-cost interface circuit
that utilizes resistors and capacitors in place of a transformer. Depending on the signal bandwidth, the component
values should be carefully selected in order to maintain the
product performance. The input capacitors, CIN, and the input
resistors, RIN, create a high-pass filter with the lower corner
frequency at fC = 1/(2pRINCIN). The corner frequency can be
reduced by either increasing the value of RIN or CIN. If the
circuit operates with a 50Ω or 75Ω impedance level, the
resistors are fixed and only the value of the capacitor can be
increased. Usually AC-coupling capacitors are electrolytic or
tantalum capacitors with values of 1µF or higher. It should be
noted that these large capacitors become inductive with
increased input frequency, which could lead to signal amplitude errors or oscillation. To maintain a low AC-coupling
impedance throughout the signal band, a small value (e.g.
1µF) ceramic capacitor could be added in parallel with the
polarized capacitor.
If the signal needs to be DC-coupled to the input of the
ADS802, an operational amplifier input circuit is required. In
the differential input mode, any single-ended signal must be
modified to create a differential signal. This can be accomplished by using two operational amplifiers; one in the
noninverting mode for the input and the other amplifier in the
inverting mode for the complementary input. The low distortion circuit in Figure 6 will provide the necessary input shifting
required for signals centered around ground. It also employs
a diode for output level shifting to ensure a low distortion
+3.25V output swing. Other amplifiers can be used in place
of the OPA842s if the lowest distortion is not necessary. If
output level shifting circuits are not used, care must be taken
to select operational amplifiers that give the necessary performance when swinging to +3.25V with a ±5V supply operational amplifier.
Resistors R1 and R2 are used to derive the necessary
common-mode voltage from the buffered top and bottom
references. The total load of the resistor string should be
selected so that the current does not exceed 1mA. Although
the circuit in Figure 5 uses two resistors of equal value so
that the common-mode voltage is centered between the top
and bottom reference (+2.25V), it is not necessary to do so.
In all cases the center point, VCM, should be bypassed to
ground in order to provide a low-impedance AC ground.
The ADS802 can also be configured with a single-ended
input full-scale range of +0.25V to +4.25V by tying the
complementary input to the common-mode reference voltage (see Figure 7). This configuration will result in increased
even-order harmonics, especially at higher input frequencies. However, this tradeoff may be quite acceptable for timedomain applications. The driving amplifier must give adequate performance with a +0.25V to +4.25V output swing in
this case.
Capacitors CSH1 and CSH2 are used to minimize current
glitches resulting from the switching in the input track-andhold stage and to improve signal-to-noise performance. These
capacitors can also be used to establish a low-pass filter and
effectively reduce the noise bandwidth. In order to create a
real pole, resistors RSER1 and RSER2 were added in series
with each input. The cutoff frequency of the filter is deter-
C1
0.1µF
CIN
0.1µF
RSER1(1)
49.9Ω
R1
(6kΩ)
+3.25V
Top Reference
IN
RIN1
25Ω
CIN
0.1µF
RIN2
25Ω
CSH1
22pF
R3
1kΩ
RSER2(1)
49.9Ω
ADS8xx
VCM
C2
0.1µF
R2
(6kΩ)
IN
CSH2
22pF
+1.25V
Bottom Reference
C3
0.1µF
NOTE: (1) Indicates optional component.
FIGURE 5. AC-Coupled Differential Input Circuit.
ADS802
SBAS039B
www.ti.com
11
+5V
604Ω
+5V
301Ω
BAS16(1)
Optional
High Impedance
Input Amplifier
301Ω
27 IN
OPA842
301Ω
2.49kΩ
0.1µF
+5V(2)
22pF
0.1µF
–5V
604Ω
DC-Coupled
Input Signal
+5V
OPA842
604Ω
OPA130
+5V
–5V
24.9Ω
ADS802
49.9Ω
2.49kΩ +2.25V
22 CM
+5V
301Ω
BAS16(1)
301Ω
Input Level
Shift Buffer
26 IN
OPA842
0.1µF
–5V
22pF
604Ω
NOTES: (1) A Philips BAS16 diode or equivalent
may be used. (2) Supply bypassing not shown.
301Ω
FIGURE 6. A Low-Distortion, DC-Coupled, Single-Ended to Differential Input Driver Circuit.
For the differential configuration, the full-scale input
range will be set to the external reference values that are
selected. For the single-ended mode, the input range is
2 • (REFTEXT – REFBEXT), with the common-mode being
centered at (REFTEXT + REFBEXT)/2. Refer to the typical
characteristics for expected performance versus full-scale
input range.
22 CM
0.1µF
ADS802
Single-Ended
Input Signal
26 IN
27 IN
22pF
The circuit in Figure 8 works completely on a single +5V
supply. As a reference element, it uses micro-power reference REF1004-2.5 that is set to a quiescent current of
0.1mA. Amplifier A2 is configured as a follower to buffer the
+1.25V generated from the resistor divider. To provide the
necessary current drive, a pull-down resistor (RP) is added.
Full-Scale = +0.25V to +4.25V with internal references.
FIGURE 7. Single-Ended Input Connection.
EXTERNAL REFERENCES AND ADJUSTMENT
OF FULL-SCALE RANGE
The internal reference buffers are limited to approximately
1mA of output current. As a result, these internal +1.25V and
+3.25V references may be overridden by external references
that have at least 18mA (at room temperature) of output drive
capability. In this instance, the common-mode voltage will be
set halfway between the two references. This feature can be
used to adjust the gain error, improve gain drift, or to change
the full-scale input range of the ADS802. Changing the fullscale range to a lower value has the benefit of easing the
swing requirements of external input amplifiers. The external
references can vary as long as the value of the external top
reference (REFTEXT) is less than or equal to +3.4V, the value
of the external bottom reference (REFBEXT) is greater than or
equal to +1.1V, and the difference between the external
references are greater than or equal to 1.5V.
12
Amplifier A1 is configured as an adjustable-gain stage, with
a range of approximately 1 to 1.32. The pull-up resistor again
relieves the op amp from providing the full current drive. The
value of the pull-up, pull-down resistors is not critical and can
be varied to optimize power consumption. The need for pullup, pull-down resistors depends only on the drive capability
of the selected drive amplifiers, and thus can be omitted.
PC-BOARD LAYOUT AND BYPASSING
A well-designed, clean pc-board layout will assure proper
operation and clean spectral response. Proper grounding and
bypassing, short lead lengths, and the use of ground planes
are particularly important for high-frequency circuits. Multilayer
pc-boards are recommended for best performance, but if
carefully designed, a two-sided pc-board with large, heavy
ADS802
www.ti.com
SBAS039B
+5V
RP
220Ω
A1
1/2
OPA2234
+5V
Top
Reference
+2.5V to +3.25V
2kΩ
10kΩ
6.2kΩ
10kΩ
REF1004
+2.5V
10kΩ(1)
A2
0.1µF
+1.25V
1/2
OPA2234
10kΩ
Bottom
Reference
RP
220Ω
10kΩ(1)
NOTE: (1) Use parts alternatively for adjustment capability.
FIGURE 8. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp.
ground planes can give excellent results. It is recommended
that the analog and digital ground pins of the ADS802 be
connected directly to the analog ground plane. In our experience, this gives the most consistent results. The A/D converter
power-supply commons should be tied together at the analog
ground plane. Power supplies should be bypassed with 0.1µF
ceramic capacitors as close to the pin as possible.
DYNAMIC PERFORMANCE DEFINITIONS
1.
Signal-to-Noise-and-Distortion Ratio (SINAD):
10 log
2.
Sinewave Signal Power
Noise + Harmonic Power (first 15 harmonics)
Signal-to-Noise Ratio (SNR):
10 log
DYNAMIC PERFORMANCE TESTING
The ADS802 is a high-performance converter and careful
attention to test techniques is necessary to achieve accurate
results. Highly accurate phase-locked signal sources allow
high resolution FFT measurements to be made without using
data windowing functions. A low-jitter signal generator, such
as the HP8644A for the test signal, phase-locked with a lowjitter HP8022A pulse generator for the A/D converter clock,
gives excellent results. Low-pass filtering (or bandpass filtering) of test signals is absolutely necessary to test the low
distortion of the ADS802. Using a signal amplitude slightly
lower than full-scale will allow a small amount of “headroom”
so that noise or DC-offset voltage will not overrange the A/D
converter and cause clipping on signal peaks.
3.
Intermodulation Distortion (IMD):
10 log
Highest IMD Pr oduct Power ( to 5th − order )
Sinewave Signal Power
IMD is referenced to the larger of the test signals f1 or f2. Five
“bins” either side of peak are used for calculation of fundamental and harmonic power. The “0” frequency bin (DC) is
not included in these calculations, as it is of little importance
in dynamic signal processing applications.
ADS802
SBAS039B
Sinewave Signal Power
Noise Power
www.ti.com
13
FIGURE 9. ADS802 Interface Schematic with AC-Coupling and External Buffers.
14
www.ti.com
ADS802
SBAS039B
R2
50Ω
AC Input
Signal
Mini-circuits
T T1-6-KK81
or equivalent
0.1µF
R1
50Ω
22pF
0.1µF
Ext
Clk
(1)
22pF
0.1µF
GND
IN
IN
GND
+VS
REFT
CM
REFB
+VS
MSBI
OE
+VS
CLK
+VS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS802
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
MSB
LSB
GND
NOTE: (1) All capacitors should be located as close to the pins as the manufacturing
process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended.
0.1µF
0.1µF
0.1µF
0.1µF
+5V
Dir
–541
19
1
Dir
G+
2
3
17
18
4
6
5
14
15
16
7
8
12
13
9
2
11
19
1
18
G+
4
16
3
5
15
17
7
6
13
8
12
14
9
–541
11
PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
ADS802U
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
DW
28
20
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
ADS802U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2017
Addendum-Page 2
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