Texas Instruments | ADS7852: 12-Bit, 8-Channel, Parallel Output Analog-to-Digital Converter (Rev. C) | Datasheet | Texas Instruments ADS7852: 12-Bit, 8-Channel, Parallel Output Analog-to-Digital Converter (Rev. C) Datasheet

Texas Instruments ADS7852: 12-Bit, 8-Channel, Parallel Output Analog-to-Digital Converter (Rev. C) Datasheet
ADS7852
ADS
785
2
®
SBAS111C – JANUARY 1998 – REVISED JULY 2004
12-Bit, 8-Channel, Parallel Output
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
●
●
●
●
●
2.5V INTERNAL REFERENCE
8 INPUT CHANNELS
500kHz SAMPLING RATE
SINGLE 5V SUPPLY
●
●
●
●
NO MISSING CODES
70dB SINAD
LOW POWER: 13mW
TQFP-32 PACKAGE
The ADS7852 is an 8-channel, 12-bit Analog-to-Digital
(A/D) converter complete with sample-and-hold, internal 2.5V
reference and a full 12-bit parallel output interface. Typical
power dissipation is 13mW at 500kHz throughput rate. The
ADS7852 features both a nap mode and a sleep mode, further
reducing the power consumption to 2mW. The input range is
from 0V to twice the reference voltage. The reference voltage
can be overdriven by an external voltage.
The ADS7852 is ideal for multi-channel applications where
low power and small size are critical. Medical instrumentation, high-speed data acquisition and laboratory equipment
are just a few of the applications that would take advantage of
the special features offered by the ADS7852. The ADS7852
is available in an TQFP-32 package and is fully specified and
ensured over the –40°C to +85°C temperature range.
±1LSB: INL, DNL
APPLICATIONS
●
●
●
●
DATA ACQUISITION
TEST AND MEASUREMENT
INDUSTRIAL PROCESS CONTROL
MEDICAL INSTRUMENTS
A0
A1
A2
ADS7852
SAR
AIN0
AIN1
AIN2
AIN3
AIN4
3-State
Parallel
Data Bus
8-Channel
MUX
AIN5
CDAC
AIN6
AIN7
Comparator
Internal
+2.5V Ref
Buffer
Output
Latches
and
3-State
Drivers
CLK
BUSY
WR
CS
RD
10kΩ
VREF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 1998-2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
Analog Inputs to AGND, Any Channel Input .............. –0.3V to (VD + 0.3V)
REFIN ......................................................................... –0.3V to (VD + 0.3V)
Digital Inputs to DGND .............................................. –0.3V to (VD + 0.3V)
Ground Voltage Differences: AGND, DGND ..................................... ±0.3V
+VSS to AGND .......................................................................... –0.3V to 6V
Power Dissipation .......................................................................... 325mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
PACKAGE/ORDERING INFORMATION(1)
MAXIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
GAIN
ERROR
(LSB)
ADS7852Y
ADS7852Y
±2
"
ADS7852YB
ADS7852YB
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
±40
TQFP-32
PBS
–40°C to +85°C
A52Y
"
"
"
"
"
ADS7852Y/250
ADS7852Y/2K
Tape and Reel, 250
Tape and Reel, 2000
±1
±25
TQFP-32
PBS
–40°C to +85°C
A52YB
"
"
"
"
"
"
ADS7852YB/250
ADS7852YB/2K
Tape and Reel, 250
Tape and Reel, 2000
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
ADS7852 CHANNEL SELECTION
2
A2
A1
A0
CHANNEL SELECTED
0
0
0
Channel 0
0
0
1
Channel 1
0
1
0
Channel 2
0
1
1
Channel 3
1
0
0
Channel 4
1
0
1
Channel 5
1
1
0
Channel 6
1
1
1
Channel 7
ADS7852
SBAS111C
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, fS = 500kHz, fCLK = 16 • fS, and VSS = +5V, using internal reference, unless otherwise specified.
ADS7852Y
PARAMETER
CONDITIONS
MIN
ADS7852YB
TYP
MAX
RESOLUTION
0
REFERENCE OUTPUT
Internal Reference Voltage
Internal Reference Drift
Input Impedance
Source Current(4)
REFERENCE INPUT
Range
Resistance(5)
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
VIH
VIL
VOH
VOL
Data Format
POWER SUPPLY REQUIREMENT
+VSS
Quiescent Current
Normal Power
Nap Mode Current(6)
Sleep Mode Current(6)
TEMPERATURE RANGE
Specified Performance
Storage
5
✻
±2
±1
±2
±4
±0.5
±1
✻
±5
±1
±15
±40
Ext Ref = 2.5000V
Int Ref
±25
50kHz
50kHz
50kHz
50kHz
68
76
2.48
CS = GND
CS = VSS
Static Load
✻
✻
✻
✻
✻
72
–74
70
74
95
–72
71
78
2.50
30
5
5
2.52
2.0
IIH = +5µA
IIL = +5µA
IOH = 250µA
IOL = 250µA
✻
✻
–77
72
77
✻
✻
✻
✻
✻
2.55
✻
10
✻
CMOS
✻
3
–0.3
3.5
+VSS + 0.3
0.8
✻
✻
✻
0.4
4.75
2.6
13
600
10
–40
–65
–76
✻
✻
Bits
LSB(1)
LSB
LSB
ppm/°C
LSB
LSB
LSB
ppm/°C
LSB
µVrms
LSB
Clk Cycles
Clk Cycles
kHz
ns
ns
ps
dB
dB
dB
dB
dB
V
ppm/°C
GΩ
GΩ
µA
✻
V
kΩ
✻
✻
✻
V
V
V
V
✻
✻
✻
✻
✻
V
mA
mW
µA
µA
✻
✻
°C
°C
✻
Straight Binary
Specified Performance
±1
±1
✻
✻
50
to Internal Reference Voltage
V
Ω
pF
µA
✻
500
at
at
at
at
✻
✻
✻
150
1.2
500
5
30
5Vp-p
5Vp-p
5Vp-p
5Vp-p
Bits
✻
13.5
=
=
=
=
✻
✻
±10
±25
±1
1.5
VIN
VIN
VIN
VIN
UNITS
✻
12
Worst-Case ∆, +VSS = 5V ±5%
MAX
✻
✻
✻
5M
15
±1
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
Multiplexer Settling Time
Aperture Delay
Aperture Jitter
AC ACCURACY
Signal-to-Noise Ratio
Total Harmonic Distortion(3)
Signal-to-(Noise+Distortion)
Spurious Free Dynamic Range
Channel-to-Channel Isolation
TYP
12
ANALOG INPUT
Input Voltage Range
Input Impedance
Input Capacitance
Input Leakage Current
DC ACCURACY
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Drift
Offset Error Match
Gain Error(1)
Gain Error
Gain Error Drift
Gain Error Match
Noise
Power Supply Rejection Ratio
MIN
5.25
3.5
17.5
800
30
✻
+85
+150
✻
✻
✻
✻
✻
✻
✻ Specifications same as ADS7852Y.
NOTES: (1) LSB means Least Significant Bit, with VREF equal to +2.5V, one LSB is 1.22mV. (2) Measured relative to an ideal, full-scale input of 4.999V. Thus,
gain error includes the error of the internal voltage reference. (3) Calculated on the first nine harmonics of the input frequency. (4) If the internal reference is required
to source current to an external load, the reference voltage will change due to the internal 10kΩ resistor. (5) Can vary ±30%. (6) See Timing Characteristics for
further detail.
ADS7852
SBAS111C
3
PIN DESCRIPTIONS
PIN
NAME
1
AIN0
Analog Input Channel 0
2
AIN1
Analog Input Channel 1
3
AIN2
Analog Input Channel 2
4
AIN3
Analog Input Channel 3
DB1
5
AIN4
Analog Input Channel 4
6
AIN5
Analog Input Channel 5
25
PIN CONFIGURATION
7
AIN6
Analog Input Channel 6
8
AIN7
Analog Input Channel 7
9
AGND
10
VREF
11
DGND
12
A2
Channel Address. See Channel Selection
Table for details.
13
A1
Channel Address. See Channel Selection
Table for details.
14
A0
Channel Address. See Channel Selection
Table for details.
15
DB11
Data Bit 11 (MSB)
16
DB10
Data Bit 10
17
DB9
Data Bit 9
18
DB8
Data Bit 8
19
DB7
Data Bit 7
20
DB6
Data Bit 6
21
DB5
Data Bit 5
22
DB4
Data Bit 4
23
DB3
Data Bit 3
24
DB2
Data Bit 2
25
DB1
Data Bit 1
26
DB0
Data Bit 0 (LSB)
27
WR
Write Input. Active LOW. Use to start a
new conversion and to select an analog
channel via address inputs A0, A1 and A2
in combination with CS.
28
BUSY
29
CLK
External Clock Input. The clock speed
determines the conversion rate by the
equation: fCLK = 16 • fSAMPLE.
30
RD
Read Input. Active LOW. Use to read the
data outputs in combination with CS. Also
use (in conjunction with A0 or A1) to place
device in power-down mode.
31
CS
Chip Select Input. Active LOW. The
combination of CS taken LOW and WR
taken LOW initiates a new conversion and
places the outputs in tri-state mode.
32
VSS
Voltage Supply Input. Nominally +5V.
Decouple to ground with a 0.1µF ceramic
capacitor and a 10µF tantalum capacitor.
DB0 (LSB)
26
WR
27
BUSY
28
CLK
29
RD
30
31
32
AIN0
1
24
DB2
AIN1
2
23
DB3
AIN2
3
22
DB4
AIN3
4
21
DB5
ADS7852Y
AIN6
7
18
DB8
AIN7
8
17
DB9
DB10
DB11 (MSB)
A0
A1
A2
DGND
VREF
16
DB7
15
19
14
6
13
AIN5
12
DB6
11
20
10
5
9
AIN4
AGND
4
CS
TQFP
VSS
Top View
DESCRIPTION
Analog Ground, GND = 0V
Voltage Reference Input and Output. See
Electrical Characteristics table for ranges.
Decouple to ground with a 0.1µF ceramic
capacitor and a 2.2µF tantalum capacitor.
Digital Ground, GND = 0V
BUSY output goes LOW and stays LOW
during a conversion. BUSY rises when a
conversion is complete.
ADS7852
SBAS111C
TYPICAL CHARACTERISTICS
At TA = +25°C, VSS = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal reference, unless otherwise specified.
SPECTRAL PERFORMANCE
(4096 Point FFT, fIN = 100.7081kHz, –0.5dB)
0
0
–20
–20
Amplitude (dB)
Amplitude (dB)
SPECTRAL PERFORMANCE
(4096 Point FFT, fIN = 49.561kHz, –0.5dB)
–40
–60
–80
–100
–80
–120
0
50
100
150
200
250
0
50
100
150
200
Frequency (kHz)
Frequency (kHz)
SPECTRAL PERFORMANCE
(4096 Point FFT, fIN = 199.5851kHz, –0.5dB)
SPECTRAL PERFORMANCE
(4096 Point FFT, fIN = 247.1921kHz, –0.5dB)
0
0
–20
–20
Amplitude (dB)
Amplitude (dB)
–60
–100
–120
–40
–60
–80
–100
250
–40
–60
–80
–100
–120
–120
0
50
100
150
200
250
0
50
100
150
200
250
Frequency (kHz)
CHANGE IN SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs TEMPERATURE
CHANGE IN SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE
0.5
NOTE: (1) First nine harmonics
of the input frequency
–0.5
THD(1)
0.0
0.0
SFDR
–0.5
0.5
–1.0
1.0
–50
–25
0
25
Temperature (°C)
ADS7852
SBAS111C
50
75
100
THD Delta from +25°C (dB)
–1.0
fIN = 49.6kHz,–0.5dB
SNR and SINAD Delta from +25°C (dB)
Frequency (kHz)
1.0
SFDR Delta from +25°C (dB)
–40
0.4
fIN = 49.6kHz,–0.5dB
0.3
0.2
SNR
0.1
SINAD
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–50
–25
0
25
50
75
100
Temperature (°C)
5
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VSS = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal reference, unless otherwise specified.
SIGNAL-TO-NOISE and
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE and
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
76
90
–90
SNR
SFDR
72
SINAD
70
68
–85
THD*
80
–80
75
–75
*First nine harmonics
of the input frequency
66
70
1k
10k
100k
1M
–70
1k
10k
100k
1M
Input Frequency (Hz)
DIFFERENTIAL LINEARITY ERROR vs CODE
1.00
0.75
0.75
0.50
0.50
DLE (LSBs)
ILE (LSBs)
INTEGRAL LINEARITY ERROR vs CODE
1.00
0.25
0.00
–0.25
0.25
0.00
–0.25
–0.50
–0.50
–0.75
–0.75
–1.00
000H
400H
800H
C00H
FFFH
–1.00
000H
400H
800H
Output Code
CHANGE IN INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE
8
6
Delta from +25°C (LSB)
4.0
Delta from +25°C (mV)
FFFH
CHANGE IN GAIN ERROR vs TEMPERATURE
6.0
2.0
0.0
–2.0
–4.0
4
2
0
–2
–4
–6
–6.0
–8
–50
–25
0
25
Temperature (°C)
6
C00H
Output Code
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
ADS7852
SBAS111C
THD (dB)
85
SFDR (dB)
SNR and SINAD (dB)
74
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VSS = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal reference, unless otherwise specified.
CHANGE IN GAIN ERROR vs TEMPERATURE
(With External 2.5V Reference)
CHANGE IN OFFSET vs TEMPERATURE
0.5
1.0
0.8
0.3
Delta from +25°C (LSB)
Delta from +25°C (LSB)
0.4
0.2
0.1
0
–0.1
–0.2
–0.3
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.5
–0.4
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
Temperature (°C)
Temperature (°C)
CHANGE IN WORST-CASE CHANNEL-TO-CHANNEL
OFFSET MISMATCH vs TEMPERATURE
CHANGE IN WORST-CASE CHANNEL-TO-CHANNEL
GAIN MISMATCH vs TEMPERATURE
0.10
100
0.020
Delta from +25°C (LSB)
Delta from +25°C (LSB)
0.015
0.05
0.00
–0.05
0.010
0.005
0.000
–0.005
–0.010
–0.015
–0.10
–0.020
–25
0
25
50
75
100
–50
–25
0
25
50
75
Temperature (°C)
Temperature (°C)
CHANGE IN WORST-CASE INTEGRAL LINEARITY
AND DIFFERENTIAL LINEARITY vs SAMPLE RATE
CHANGE IN WORST-CASE INTEGRAL LINEARITY
AND DIFFERENTIAL LINEARITY vs TEMPERATURE
100
0.050
3.0
2.5
Delta from +25°C (LSB)
Delta Relative to fSAMPLE = 500kHz (LSB)
–50
2.0
1.5
1.0
Delta IL
0.5
0.0
Delta IL
0.025
0.000
–0.025
Delta DL
Delta DL
–0.5
–0.050
–1.0
100
200
300
400
500
Sample Rate (kHz)
ADS7852
SBAS111C
600
700
800
–50
–25
0
25
50
75
100
Temperature (°C)
7
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VSS = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal reference, unless otherwise specified.
SUPPLY CURRENT vs SAMPLE RATE
SUPPLY CURRENT vs TEMPERATURE
2.9
2.680
fSAMPLE = 500kHz
2.8
Supply Current (mA)
Supply Current (mA)
2.675
2.670
2.665
2.660
2.7
2.6
2.5
2.4
2.3
2.655
–50
–25
0
25
50
75
100
100
200
CHANGE IN NAP CURRENT AND SLEEP CURRENT
vs TEMPERATURE
400
500
600
CHANGE IN GAIN AND OFFSET vs SUPPLY VOLTAGE
25
0.25
Delta from VSS = 5.00V (LSB)
20
Delta from +25°C (µA)
300
Sample Rate (kHz)
Temperature (°C)
15
Nap
10
5
0
Sleep
–5
0.20
Gain
0.15
0.10
0.05
0.00
Offset
–0.05
–0.10
–0.15
–0.20
–10
–50
–25
0
25
50
75
–0.25
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15
100
Temperature (°C)
5.20 5.25
VSS (V)
POWER SUPPLY REJECTION
vs POWER SUPPLY RIPPLE FREQUENCY
Power Supply Rejection (mV/V)
30
25
20
15
10
5
0
10
8
100
1k
10k
100k
1M
ADS7852
SBAS111C
THEORY OF OPERATION
Read Input
Clock Input
Busy Output
CLK 29
BUSY 28
0V to 5V
DB1 25
DB0 (LSB) 26
0.1µF
WR 27
1
AIN0
2
AIN1
DB3 23
3
AIN2
DB4 22
4
AIN3
5
AIN4
DB6 20
6
AIN5
DB7 19
7
AIN6
DB8 18
8
AIN7
DB5 21
14 A0
A0 Select
DB9 17
16 DB10
13 A1
11 DGND
A1 Select
+
12 A2
2.2µF
A2 Select
+
10 VREF
AGND
9
0.1µF
DB2 24
ADS7852Y
15 DB11 (MSB)
+
RD 30
10µF
Chip Select
+
VSS 32
+5V
Analog Supply
CS 31
The ADS7852 is a high-speed successive approximation
register (SAR) Analog-to-Digital (A/D) converter with an
internal 2.5V bandgap reference. The architecture is based
on capacitive redistribution, which inherently includes a
sample/hold function. The converter is fabricated on a 0.6micron CMOS process. Figure 1 shows the basic operating
circuit for the ADS7852.
The ADS7852 requires an external clock to run the conversion process. This clock can vary between 200kHz (12.5Hz
throughput) and 8MHz (500kHz throughput). The duty cycle
of the clock is unimportant as long as the minimum HIGH
and LOW times are at least 50ns and the clock period is at
least 125ns. The minimum clock frequency is governed by
the parasitic leakage of the Capacitive Digital-to-Analog
(CDAC) capacitors internal to the ADS7852.
Write Input
The front-end input multiplexer of the ADS7852 features
eight single-ended analog inputs. Channel selection is performed using the address pins A0 (pin 14), A1 (pin 13), and
A2 (pin 12). When a conversion is initiated, the input
voltage is sampled on the internal capacitor array. While a
conversion is in progress, all channel inputs are disconnected from any internal function.
The range of the analog input is set by the voltage on the
VREF pin. With the internal 2.5V reference, the input range
is 0V to 5V. An external reference voltage can be placed on
VREF, overdriving the internal voltage. The range for the
external voltage is 2.0V to 2.55V, giving an input voltage
range of 4.0V to 5.1V.
FIGURE 1. Typical Circuit Configuration.
ADS7852
SBAS111C
9
ANALOG INPUTS
The ADS7852 features eight single-ended inputs. While the
static current into each analog input is basically zero, the
dynamic current depends on the input voltage and sample
rate. The current into the device must charge the internal
hold capacitor during the sample period. After this capacitor
has been fully charged, no further input current is required.
For optimum performance, the source driving the analog
inputs must be capable of charging the input capacitance to
a 12-bit settling level within the sample period. This can be
as little as 350ns in some operating modes. While the
converter is in the hold mode, or after the sampling capacitor
has been fully charged, the input impedance of the analog
input is greater than 1GΩ.
REFERENCE
The reference voltage on the VREF pin establishes the fullscale range of the analog input. The ADS7852 can operate
with a reference in the range of 2.0V to 2.55V corresponding
to a full-scale range of 4.0V to 5.1V.
The voltage at the VREF pin is internally buffered, and this
buffer drives the capacitor DAC portion of the converter.
This feature is important because the buffer greatly reduces
the dynamic load placed on the reference source. Since the
voltage at VREF will be unavoidably affected by noise and
glitches generated during the conversion process, it is highly
recommended that the VREF pin be bypassed to ground as
outlined in the sections that follow.
INTERNAL REFERENCE
The ADS7852 contains an onboard 2.5V reference, resulting
in a 0V to 5V input range on the analog input. The Specifications Table gives the various specifications for the internal
reference. This reference can be used to supply a small
amount of source current to an external load but the load
should be static. Due to the internal 10kΩ resistor, a dynamic load will cause variations in the reference voltage,
and will dramatically affect the conversion result. Note that
even a static load will reduce the internal reference voltage
seen at the buffer input. The amount of reduction depends on
the load and the actual value of the internal 10kΩ resistor.
The value of this resistor can vary by ±30%.
The VREF pin should be bypassed with a 0.1µF ceramic
capacitor placed as close to the ADS7852 as possible. In
addition, a 2.2µF tantalum capacitor should be used in
parallel with the ceramic capacitor.
EXTERNAL REFERENCE
The internal reference is connected to the VREF pin and to the
internal buffer via an on-chip 10kΩ series resistor. Because of
this configuration, the internal reference voltage can easily be
overridden by an external reference voltage. The voltage range
for the external voltage is 2.00V to 2.55V, corresponding to an
analog input range of 4.0V to 5.1V.
While the external reference will not have to provide significant
dynamic current to the VREF in, it does have to drive the series
10
10kΩ resistor that is connected to the 2.5V internal reference.
Accounting for the maximum difference between the external
reference voltage and the internal reference voltage, and the
processing variations for the on-chip 10kΩ resistor, this current
can be as high as 75µA. In addition, the VREF pin should still
be bypassed to ground with at least a 0.1µF ceramic capacitor
placed as close to the ADS7852 as possible. Depending on the
particular reference and A/D conversion speed, additional
bypass capacitance may be required, such as the 2.2µF tantalum capacitor shown in the Typical Circuit Configuration
(Figure 1). Close attention should be paid to the stability of any
external reference source that is driving the large bypass
capacitors present at the VREF pin.
BASIC OPERATION
Figure 1 shows the simple circuit required to operate the
ADS7852 with Channel 0 selected. A conversion can be
initiated by bringing the WR pin (pin 27) LOW for a
minimum of 35ns. BUSY (pin 28) will output a LOW during
the conversion process and rises only after the conversion is
complete. The 12 bits of output data will be valid on pins 15
through 26 following the rising edge of BUSY.
STARTING A CONVERSION
A conversion is initiated on the falling edge of the WR
input, with valid signals on A0, A1, A2, and CS. The
ADS7852 will enter the conversion mode on the first rising
edge of the external clock following the WR pin going
LOW. The conversion process takes 13.5 clock cycles (1.5
cycles for the DB0 decision, 2 clock cycles for the DB5
decision, and 1 clock cycle for each of the other bit decisions). This allows 2.5 clock cycles for sampling. Upon
initiating a conversion, the BUSY output will go LOW
approximately 20ns after the falling edge of the WR pin.
The BUSY output will return HIGH just after the ADS7852
has finished a conversion and the output data will be valid
on pins 15 through 26. The rising edge of BUSY can be used
to latch the output data into an external device. It is recommended that the data be read immediately after each conversion since the switching noise of the asynchronous data
transfer can cause digital feedthrough degrading the converter performance (see Figure 2).
CHANNEL ADDRESSING
The selection of the analog input channel to be converted is
controlled by address pins A0, A1, and A2. This channel
becomes active on the rising edge of WR with CS held LOW.
The data on the address pins should be stable for at least 10ns
prior to WR going HIGH.
The address pins are also used to control the power-down
functions of the ADS7852. Careful attention must be paid to
the status of the address pins following each conversion. If
the user does not want the ADS7852 to enter either of the
power-down modes following a conversion, the A0 and A1
pins must be LOW when RD and CS are returned HIGH after
reading the data at the end of a conversion (see the PowerDown Mode section of this data sheet for more details).
ADS7852
SBAS111C
HOLD
tCKH
CLK
1
2
3
4
5
6
tCKP
7
8
9
10
11
tCKL
t1
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
t4
t2
WR
t4
t3
CS
t5
BUSY
Conversion n
tCONV
Conversion n + 1
tACQ
t6
RD
t7
t8
Address
Bus
Address n + 1
Address n + 2
t9
t10
Data
Bus
Hi-Z
SYMBOL
tCONV
tACQ
tCKP
tCKL
tCKH
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Data
Valid
Data
Valid
Hi-Z
DESCRIPTION
MIN
Conversion Time
Acquisition Time
Clock Period
Clock LOW
Clock HIGH
WR LOW Prior to Rising Edge of CLK
WR LOW After Rising Edge of CLK
CS LOW After Rising Edge of CLK
CS and RD HIGH
BUSY Delay After CS LOW
RD LOW
Address Hold Time
Address Setup Time
Bus Access Time
Bus Relinquish Time
CS to RD Setup Time
RD to CS Hold Time
CLK LOW to BUSY HIGH
BUSY to RD Delay
RD HIGH to CLK LOW
125
40
40
35
20
20
25
20
25
5
5
30
5
0
0
10
0
50
TYP
MAX
UNITS
1.75
0.25
5000
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hi-Z
FIGURE 2. ADS7852 Write/Read Timing.
READING DATA
Data from the ADS7852 will appear at pins 15 through 26.
The MSB will output on pin 15 while the LSB will output
on pin 26. The outputs are coded in Straight Binary (with
0V = 000H and 5V = FFFH). Following a conversion, the
BUSY pin will go HIGH. After BUSY has been HIGH for
at least t14 seconds, the CS and RD pins may be brought
LOW to enable the 12-bit output bus. CS and RD must be
held LOW for at least 25ns following BUSY HIGH. Data
will be valid 30ns after the falling edge of both CS and RD.
The output data will remain valid for 20ns following the
rising edge of both CS and RD (see Figure 2 for the read
cycle timing diagram).
ADS7852
SBAS111C
DIGITAL OUTPUT
STRAIGHT BINARY
DESCRIPTION
ANALOG INPUT
BINARY CODE
HEX CODE
4.99878V
1111 1111 1111
FFF
2.5V
1000 0000 0000
800
Midscale –1LSB
2.49878V
0111 1111 1111
7FF
Zero Full Scale
0V
0000 0000 0000
000
Least Significant
Bit (LSB)
1.2207mV
Full Scale
Midscale
Table I. Ideal Input Voltages and Output Codes.
11
POWER-DOWN MODE
The ADS7852 has two different power-down modes: the
Nap mode and the Sleep mode. In Nap mode, all analog and
digital circuitry is powered off, with the exception of the
voltage reference. In Sleep mode, the device is completely
powered off.
While the Sleep mode affords the lowest power consumption, the time to come out of Sleep mode can be considerable
since it takes the internal reference voltage a finite amount of
time to power up and reach a stable value. This latency can
result in spurious output data for a minimum of ten conversion cycles at a 500kHz sampling rate. It should also be
noted that any external load connected to the VREF pin will
increase this effect since a discharge path for the VREF
bypass capacitor is provided during the Sleep cycle. Even the
parasitic leakage of the bypass capacitor itself should be
considered if the unit is left in the Sleep mode for an
extended period. After power-up, this capacitor must be
recharged by the internal reference voltage and the on-chip
10kΩ series resistor. Under worst-case conditions (for example, the bypass capacitor is completely discharged), the
output data can be invalid for several hundred milliseconds.
Since the Nap mode maintains the voltage on the VREF pin by
keeping the internal reference powered-up, valid conversions
are available immediately after the Nap mode is terminated.
The simplest way to use the power-down mode is following
a conversion. After a conversion has finished and BUSY has
returned HIGH, CS and RD must be brought LOW for a
minimum of 25ns. When RD and CS are returned HIGH, the
ADS7852 will enter the power-down mode on the rising
edge of RD. If CS is always kept LOW, the power-down
mode will be controlled exclusively by RD. Depending on
the status of the A0 and A1 address pins, the ADS7852 will
either enter the Nap mode, the Sleep mode, or be returned
to normal operation in the sampling mode. See Table II and
Figures 3 and 4 for further details.
RD
A2
A1
A0
POWER-DOWN MODE
X
0
0
None
X
1
0
Sleep
X
0
1
Nap
X
1
1
Sleep
= Signifies rising edge of RD pin. X = Don't care
TABLE II. ADS7852 Power-Down Mode.
CS
t11
t12
t6
RD
CLK
t13
t14
BUSY
t7
A1
t8
A0
NOTE: Rising edge of 1st RD while A0 = 1 initiates power-down immediately. A1 must be LOW to enter Nap mode.
FIGURE 3. Entering Nap Using RD and A0.
CS
t11
t12
t6
RD
t15
CLK
A1
t7
t8
A0
NOTE: Rising edge of 2nd RD while A0 = 0 places the ADS7852 in sample mode. A1 must be LOW to initiate wake-up.
FIGURE 4. Initiating Wake-Up Using RD and A0.
12
ADS7852
SBAS111C
LAYOUT
Test Point
VCC
DOUT
tdis Waveform 2, ten
3kΩ
tdis Waveform 1
100pF
CLOAD
Load Circuit for tdis and ten
VIH
CS/SHDN
DOUT
Waveform 1(1)
90%
tdis
DOUT
Waveform 2(2)
10%
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal
conditions such that the output is HIGH unless disabled
by the output control. (2) Waveform 2 is for an output
with internal conditions such that the output is LOW
unless disabled by the output control.
FIGURE 5. Timing Diagram and Test Circuits for Parameters in Figure 2.
In addition to using the address pins in conjunction with RD,
the power-down mode can also be terminated implicitly by
starting a new conversion (for example, taking WR LOW
while CS is LOW). If it is desired to keep the ADS7852 in
a power-down state for a period that is greater than dictated
by the sampling rate, the convert signal driving the WR pin
must be disabled.
The typical supply current of the ADS7852 is 2.6mA, with
a 5V supply and a 500kHz sampling rate. In the Nap mode,
the typical supply current is 600µA. In the Sleep mode, the
current is typically reduced to 10µA.
ADS7852
SBAS111C
For optimum performance, care should be taken with the
physical layout of the ADS7852 circuitry. This is particularly
true if the CLK input is approaching the maximum throughput
rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections,
and digital inputs that occur just prior to latching the output
of the analog comparator. Thus, driving any single conversion
for an n-bit SAR converter, there are n “windows” in which
large external transient voltages can affect the conversion
result. Such glitches might originate from switching power
supplies, nearby digital logic, or high power devices. The
degree of error in the digital output depends on the reference
voltage, layout, and the exact timing of the external event.
This error can change if the external event changes in times
with respect to the CLK input.
With this effect in mind, power to the ADS7852 should be
clean and well bypassed. A 0.1µF ceramic bypass capacitor
should be placed as close to the device as possible. In
addition, a 1µF to 10µF capacitor is recommended. If
needed, an even larger capacitor and a 5Ω or 10Ω series
resistor may be used to low pass filter a noisy supply. The
ADS7852 draws very little current from an external reference
on average as the reference voltage is internally buffered.
However, glitches from the conversion process appear at the
VREF input and the reference source must be able to handle
this. Whether the reference is internal or external, the VREF
pin should be bypassed with a 0.1µF capacitor. An additional
larger capacitor may also be used, if desired. If the reference
voltage is external and originates from an op amp, make sure
it can drive the bypass capacitor or capacitors without
oscillation.
The GND pin should be connected to a clean ground point. In
many cases, this will be the “analog” ground. Avoid connections
which are too near the grounding point of a microcontroller or
digital signal processor. If needed, run a ground trace directly
from the converter to the power supply entry point. The ideal
layout will include an analog ground plane dedicated to the
converter and associated analog circuitry.
13
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS7852Y/250
ACTIVE
TQFP
PBS
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
A52Y
ADS7852Y/250G4
ACTIVE
TQFP
PBS
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
A52Y
ADS7852Y/2K
ACTIVE
TQFP
PBS
32
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
A52Y
ADS7852YB/250
ACTIVE
TQFP
PBS
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
A52Y
B
ADS7852YB/2K
ACTIVE
TQFP
PBS
32
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
A52Y
B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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