Texas Instruments | 3.3-V 10-Bit A-to-D Converters With Serial Control And 11 Analog Inputs (Rev. E) | Datasheet | Texas Instruments 3.3-V 10-Bit A-to-D Converters With Serial Control And 11 Analog Inputs (Rev. E) Datasheet

Texas Instruments 3.3-V 10-Bit A-to-D Converters With Serial Control And 11 Analog Inputs (Rev. E) Datasheet
 SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
D
D
D
D
D
D
D
D
D
D
3.3-V Supply Operation
10-Bit-Resolution A/D Converter
11 Analog Input Channels
Three Built-In Self-Test Modes
Inherent Sample and Hold
Total Unadjusted Error . . . ± 1 LSB Max
On-Chip System Clock
End-of-Conversion (EOC) Output
Pin Compatible With TLC1543
CMOS Technology
DB, DW, FK, J, OR N PACKAGE
(TOP VIEW)
A0
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
EOC
I/O CLOCK
ADDRESS
DATA OUT
CS
REF +
REF −
A10
A9
description
FN PACKAGE
(TOP VIEW)
A2
A1
A0
VCC
EOC
The TLV1543C, TLV1543I, and TLV1543M are
CMOS 10-bit, switched-capacitor, successiveapproximation, analog-to-digital converters.
These devices have three inputs and a 3-state
output [chip select (CS), input-output clock (I/O
CLOCK), address input (ADDRESS), and data
output (DATA OUT)] that provide a direct 4-wire
interface to the serial port of a host processor. The
devices allow high-speed data transfers from the
host.
A3
A4
A5
A6
A7
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
I/O CLOCK
ADDRESS
DATA OUT
CS
REF +
A8
GND
A9
A10
REF −
In addition to a high-speed A /D converter and
versatile control capability, these devices have an
on-chip 14-channel multiplexer that can select
any one of 11 analog inputs or any one of three
internal self-test voltages. The sample-and-hold
function is automatic. At the end of A/D conversion, the end-of-conversion (EOC) output goes high to indicate
that conversion is complete. The converter incorporated in the devices features differential high-impedance
reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and
supply noise. A switched-capacitor design allows low-error conversion over the full operating free-air
temperature range.
The TLV1543C is characterized for operation from 0°C to 70°C. The TLV1543I is characterized for industrial
temperature range of − 40°C to 85°C. The TLV1543M is characterized for operation over the full military
temperature range of −55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL
OUTLINE
(DB)
SMALL
OUTLINE
(DW)
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
PLASTIC DIP
(N)
PLASTIC CHIP
CARRIER
(FN)
0°C to 70°C
TLV1543CDB
TLV1543CDW
—
—
TLV1543CN
TLV1543CFN
−40°C to 85°C
TLV1543IDB
—
—
—
—
—
−55°C to 125°C
—
—
TLV1543MFK
TLV1543MJ
—
—
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000 − 2004, Texas Instruments Incorporated
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1
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
functional block diagram
1
2
3
4
5
6
7
8
9
11
12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
REF +
REF −
14
13
10-Bit
Analog-to-Digital
Converter
(switched capacitors)
Sample and
Hold
10
14-Channel
Analog
Multiplexer
4
Output
Data
Register
Input Address
Register
10
10-to-1 Data
Selector and
Driver
16
DATA
OUT
4
3
System Clock,
Control Logic,
and I/O
Counters
Self-Test
Reference
ADDRESS
I/O CLOCK
CS
19
EOC
17
18
15
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 kΩ TYP
A0 −A10
A0 −A10
Ci = 60 pF MAX
(equivalent input
capacitance)
2
5 MΩ TYP
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
Terminal Functions
TERMINAL
I/O
DESCRIPTION
17
I
Serial address. A 4-bit serial address selects the desired analog input or test voltage that is to be converted
next. The address data is presented with the MSB first and is shifted in on the first four rising edges of I/O
CLOCK. After the four address bits have been read into the address register, ADDRESS is ignored for the
remainder of the current conversion period.
1−9, 11,
12
I
Analog signal. The 11 analog inputs are applied to A0 −A10 and are internally multiplexed. The driving source
impedance should be less than or equal to 1 kΩ.
CS
15
I
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT,
ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system
clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling edges
of the internal system clock.
DATA OUT
16
O
The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS
is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance
state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The
next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next most significant
bit, and the remaining bits are shifted out in order with the LSB appearing on the ninth falling edge of I/O
CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial
interface data transfers of more than ten clocks produce zeroes as the unused LSBs.
EOC
19
O
End of conversion. EOC goes from a high- to a low- logic level on the trailing edge of the tenth I/O CLOCK
and remains low until the conversion is complete and data are ready for transfer.
GND
10
I
The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are
with respect to GND.
I/O CLOCK
18
I
Input/output clock. I/O CLOCK receives the serial I/O CLOCK input and performs the following four functions:
1) It clocks the four input address bits into the address register on the first four rising edges of I/O
CLOCK with the multiplex address available after the fourth rising edge.
2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins
charging the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK.
3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.
4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.
REF +
14
I
The upper reference voltage value (nominally VCC) is applied to REF +. The maximum input voltage range
is determined by the difference between the voltage applied to REF + and the voltage applied to the REF −
terminal.
REF −
13
I
The lower reference voltage value (nominally ground) is applied to REF −.
VCC
20
I
Positive supply voltage
NAME
NO.
ADDRESS
A0 −A10
detailed description
With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT
is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins
with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state.
The host then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O CLOCK.
During this transfer, the host serial interface also receives the previous conversion result from DATA OUT. I/O
CLOCK receives an input sequence that is between 10 and 16 clocks long from the host. The first four I/O clocks
load the address register with the 4-bit address on ADDRESS selecting the desired analog channel and the next
six clocks providing the control timing for sampling the analog input.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
detailed description (continued)
There are six basic serial interface timing modes that can be used with the device. These modes are determined
by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with
a 10-clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer
and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between
conversion cycles, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with
an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and (6) a slow mode with a
16-clock transfer and CS active (low) continuously.
The MSB of the previous conversion appears on DATA OUT on the falling edge of CS in mode 1, mode 3, and
mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the 16th clock falling edge in mode 6.
The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data are
transmitted to the host through DATA OUT. The number of serial clock pulses used also depends on the mode
of operation, but a minimum of ten clock pulses is required for conversion to begin. On the 10th clock falling
edge, the EOC output goes low and returns to the high logic level when conversion is complete and the result
can be read by the host. On the 10th clock falling edge, the internal logic takes DATA OUT low to ensure that
the remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long.
Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that
can be used, and the timing edge on which the MSB of the previous conversion appears at the output.
Table 1. Mode Operation
MODES
Fast Modes
Slow Modes
NO. OF
I/O CLOCKS
CS
MSB AT DATA OUT†
TIMING
DIAGRAM
Mode 1
High between conversion cycles
10
CS falling edge
Figure 9
Mode 2
Low continuously
10
EOC rising edge
Figure 10
Mode 3
High between conversion cycles
CS falling edge
Figure 11
Mode 4
Low continuously
11 to 16‡
16‡
EOC rising edge
Figure 12
Mode 5
High between conversion cycles
CS falling edge
Figure 13
Mode 6
Low continuously
11 to 16‡
16‡
16th clock falling edge
Figure 14
† These edges also initiate serial-interface communication.
‡ No more than 16 clocks should be used.
fast modes
The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is
completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not
begin until the falling edge of the 10th I/O CLOCK.
mode 1: fast mode, CS inactive (high) between conversion cycles, 10-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The
falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge
of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.
Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling
edges of the internal system clock.
mode 2: fast mode, CS active (low) continuously, 10-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then
begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous
conversion to appear immediately on this output.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 4: fast mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of
EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the
previous conversion to appear immediately on this output.
slow modes
In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow
mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must
occur before the conversion period is complete; otherwise, the device loses synchronization with the host serial
interface, and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must
occur within 9.5 µs after the tenth I/O clock falling edge.
mode 5: slow mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 6: slow mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of
the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next
16-clock transfer initiated by the serial interface.
address bits
The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal
(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address
selects one of 14 inputs (11 analog inputs or 3 internal test inputs).
analog inputs and test modes
The 11 analog inputs and the 3 internal test inputs are selected by the 14-channel multiplexer according to the
input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce
input-to-input noise injection resulting from channel switching.
Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six
I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are
applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
Table 2. Analog-Channel-Select Address
ANALOG INPUT
SELECTED
VALUE SHIFTED INTO
ADDRESS INPUT
BINARY
HEX
A0
0000
0
A1
0001
1
A2
0010
2
A3
0011
3
A4
0100
4
A5
0101
5
A6
0110
6
A7
0111
7
A8
1000
8
A9
1001
9
A10
1010
A
Table 3. Test-Mode-Select Address
INTERNAL SELF-TEST
VOLTAGE SELECTED†
V
ref)
–V
ref–
VALUE SHIFTED INTO
ADDRESS INPUT
BINARY
HEX
1011
B
OUTPUT RESULT (HEX)‡
200
2
Vref −
1100
C
000
Vref +
1101
D
3FF
† Vref + is the voltage applied to the REF + input, and Vref − is the voltage applied to the REF −
input.
‡ The output results shown are the ideal values and vary with the reference stability and with
internal offsets.
converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF −)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks
at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF−. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half the VCC voltage), a bit 0 is
placed in the output register and the 512-weight capacitor is switched to REF−. If the voltage at the summing
node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the 512-weight
capacitor remains connected to REF + through the remainder of the successive-approximation process. The
process is repeated for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all
bits are counted.
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
converter and analog input (continued)
SC
Threshold
Detector
512
Node 512
REF −
256
128
REF+
REF+
REF −
REF −
ST
ST
16
8
REF+
REF −
ST
4
REF+
REF −
ST
REF+
REF −
ST
2
1
REF+
REF+
REF −
ST
REF −
ST
To Output
Latches
1
REF −
ST
ST
VI
Figure 1. Simplified Model of the Successive-Approximation System
chip-select operation
The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.
A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS from being taken low close to completion of conversion because the output data
can be corrupted.
reference voltage inputs
There are two reference inputs used with these devices: REF+ and REF−. These voltage values establish the
upper and lower limits of the analog input to produce a full-scale and zero-scale reading respectively. The values
of REF+, REF−, and the analog input should not exceed the positive supply or be lower than GND consistent
with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal
to or higher than REF + and at zero when the input signal is equal to or lower than REF −.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1): TLV1543C/TLV1543I . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
TLV1543M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Positive reference voltage, Vref + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.1 V
Negative reference voltage, Vref − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.1 V
Peak input current (any input), I(p-p) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Peak total input current (all inputs), Ip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Operating free-air temperature range, TA: TLV1543C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLV1543I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
TLV1543M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF − and GND wired together (unless otherwise noted).
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
TLV1543C/TLV1543I
3
3.3
5.5
V
TLV1543M
3
3.3
3.6
V
Positive reference voltage, Vref + (see Note 2)
VCC
0
Negative reference voltage, Vref − (see Note 2)
Differential reference voltage, Vref + − Vref − (see Note 2)
2.5
Analog input voltage (see Note 2)
0
TLV1543C/TLV1543I
High-level control input voltage, VIH
TLV1543M
TLV1543C/TLV1543I
Low-level control input voltage, VIL
TLV1543M
VCC = 3 V to 5.5 V
VCC = 3 V to 3.6 V
V
V
VCC + 0.2
VCC
V
V
2
V
2
V
VCC = 3 V to 5.5 V
VCC = 3 V to 3.6 V
Setup time, address bits at data input before I/O CLOCK↑, tsu(A) (see Figure 4)
VCC
UNIT
0.6
0.8
V
V
100
ns
Hold time, address bits after I/O CLOCK↑, th(A) (see Figure 4)
0
ns
Hold time, CS low after last I/O CLOCK↓, th(CS)
0
ns
1.425
µs
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3)
Clock frequency at I/O CLOCK (see Note 4)
TLV1543C/TLV1543I
0
1.1
TLV1543M
0
2.1
Pulse duration, I/O CLOCK high, tw(H_I/O)
190
Pulse duration, I/O CLOCK low, tw(L_I/O)
190
Transition time, I/O CLOCK, tt(I/O) (see Note 5)
Transition time, ADDRESS and CS, tt(CS)
TLV1543C
Operating free-air temperature, TA
MHz
ns
ns
1
µs
10
µs
0
70
TLV1543I
−40
85
TLV1543M
−55
125
°C
°C
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF− convert as all zeros (0000000000).
3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS
setup time has elapsed.
4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V), at least one I/O clock rising edge (≥ 2 V) must occur within
9.5 µs.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
electrical characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C, and TLV1543I
VCC = Vref+ = 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz for the TLV1543M (unless otherwise
noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
MIN
TYP†
UNIT
TLV1543C/TLV1543I
VCC = 3 V,
VCC = 3 V to 5.5 V,
IOH = − 1.6 mA
IOH = 20 µA
TLV1543M
VCC = 3 V,
VCC = 3 V to 3.6 V,
IOH = − 1.6 mA
IOH = 20 µA
IOL = 1.6 mA
IOL = 20 µA
0.4
V
TLV1543C/TLV1543I
VCC = 3 V,
VCC = 3 V to 5.5 V,
0.1
V
IOL = 1.6 mA
IOL = 20 µA
0.4
V
TLV1543M
VCC = 3 V,
VCC = 3 V to 3.6 V,
0.1
V
VO = VCC,
VO = 0,
VI = VCC
CS at VCC
10
CS at VCC
−10
High-level output voltage
Low-level output voltage
IOZ
Off-state (high-impedance-state) output current
IIH
IIL
High-level input current
ICC
Operating supply current
Low-level input current
VI = 0
CS at 0 V
2.4
V
VCC −0.1
2.4
V
V
VCC −0.1
V
Selected channel leakage current
Maximum static analog reference current into REF +
µA
2.5
−0.005
−2.5
µA
0.8
2.5
mA
1
A
µA
Selected channel at 0 V,
Unselected channel at VCC
Vref + = VCC,
µA
A
0.005
Selected channel at VCC,
Unselected channel at 0 V
Ci
MAX
−1
Vref − = GND
10
Input capacitance, Analog
inputs
TLV1543C/TLV1543I
7
60
TLV1543M
7
60
Input capacitance, Control
inputs
TLV1543C/TLV1543I
5
60
TLV1543M
5
60
µA
pF
pF
† All typical values are at VCC = 5 V, TA = 25°C.
WWW.TI.COM
9
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C, and TLV1543I
VCC = Vref+ = 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz for the TLV1543M
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Linearity error (see Note 6)
±1
LSB
Zero error (see Note 7)
±1
LSB
Full-scale error (see Note 7)
±1
LSB
Total unadjusted error (see Note 8)
±1
LSB
21
µs
ADDRESS = 1011
Self-test output code (see Table 3 and Note 9)
tc(1)
512
ADDRESS = 1100
0
ADDRESS = 1101
1023
Conversion time
See Figures 9 −14
tc(2)
Total cycle time (access, sample, and conversion)
See Figures 9 −14
and Note 10
t(acq)
Channel acquisition time (sample)
See Figures 9 −14
and Note 10
tv
td(I/O-DATA)
Valid time, DATA OUT remains valid after I/O CLOCK↓
See Figure 6
Delay time, I/O CLOCK↓ to DATA OUT valid
See Figure 6
td(I/O-EOC)
td(EOC-DATA)
Delay time, tenth I/O CLOCK↓ to EOC↓
See Figure 7
Delay time, EOC↑ to DATA OUT (MSB)
See Figure 8
tPZH, tPZL
tPHZ, tPLZ
Enable time, CS↓ to DATA OUT (MSB driven)
Disable time, CS↑ to DATA OUT (high impedance)
tr(EOC)
tf(EOC)
tr(bus)
tf(bus)
td(I/O-CS)
TYP†
21
+10 I/O
CLOCK
periods
6
10
µs
I/O
CLOCK
periods
ns
240
ns
240
ns
100
ns
See Figure 3
1.3
µs
See Figure 3
150
ns
Rise time, EOC
See Figure 8
300
ns
Fall time, EOC
See Figure 7
300
ns
Rise time, data bus
See Figure 6
300
ns
Fall time, data bus
See Figure 6
300
ns
9
µs
Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion
(see Note 11)
70
† All typical values are at TA = 25°C.
NOTES: 6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6).
11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425 µs) after the transition.
10
WWW.TI.COM
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
Test Point
VCC
Test Point
VCC
RL = 2.18 kΩ
RL = 2.18 kΩ
EOC
DATA OUT
12 kΩ
CL = 50 pF
12 kΩ
CL = 100 pF
Figure 2. Load Circuits
Address
Valid
2V
CS
tPZH, tPZL
DATA
OUT
2V
VIL
ADDRESS
VIL
tPHZ, tPLZ
2.4 V
90%
0.4 V
10%
th(A)
tsu(A)
I/O CLOCK
VIL
Figure 3. DATA OUT to Hi-Z Voltage Waveforms
Figure 4. ADDRESS Setup Voltage Waveforms
2V
CS
VIL
tsu(CS)
th(CS)
I/O CLOCK
VIL
First
Clock
Last
Clock
VIL
Figure 5. CS and I/O CLOCK Voltage Waveforms
WWW.TI.COM
11
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
tt(I/O)
tt(I/O)
I/O CLOCK
2V
2V
VIL
VIL
VIL
I/O CLOCK Period
td(I/O-DATA)
tv
DATA OUT
2.4 V
0.4 V
2.4 V
0.4 V
tr(bus), tf(bus)
Figure 6. DATA OUT and I/O CLOCK Voltage Waveforms
I/O CLOCK
10th
Clock
VIL
td(I/O-EOC)
2.4 V
EOC
0.4 V
tf(EOC)
Figure 7. I/O CLOCK and EOC Voltage Waveforms
tr(EOC)
2.4 V
EOC
0.4 V
td(EOC-DATA)
2.4 V
0.4 V
DATA OUT
Valid MSB
Figure 8. EOC and DATA OUT Voltage Waveforms
12
WWW.TI.COM
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
7
8
9
10
Sample Cycle B
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
1
Hi-Z State
DATA
OUT
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Previous Conversion Data
MSB
B9
ÎÎÎÎ
ÎÎÎÎ
LSB
ADDRESS
B3
B2
B1
B0
MSB
C3
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup
time has elapsed.
Figure 9. Timing for 10-Clock Transfer Using CS
Must be High on Power Up
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
A9
A8
A7
7
9
10
1
Sample Cycle B
A6
A5
A4
A3
Previous Conversion Data
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
MSB
8
A2
A1
A0
Low Level
ÎÎÎÎ
ÎÎÎÎ
LSB
ADDRESS
B3
MSB
B2
B1
B9
B0
C3
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Initialize
A/D Conversion
Interval
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup
time has elapsed.
Figure 10. Timing for 10-Clock Transfer Not Using CS
WWW.TI.COM
13
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
ÏÏÏ
ÏÏÏ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
See Note B
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
A9
A8
7
8
9
10
Sample Cycle B
A7
A6
A5
A4
A3
A2
A1
A0
Previous Conversion Data
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
MSB
11
Low
Level
LSB
ADDRESS
B3
B2
B1
B0
MSB
1
16
Hi-Z
B9
C3
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
Initialize
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS
setup time has elapsed.
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock.
Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion)
Must be High on Power Up
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
A9
A8
A7
7
9
10
14
15
16
Sample Cycle B
A6
A5
A4
A3
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Previous Conversion Data
MSB
8
A2
See Note B
A1
A0
Low Level
B3
B2
B1
B9
ÎÎÎÎÎ
ÎÎÎÎÎ
LSB
ADDRESS
MSB
1
B0
C3
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Initialize
A/D Conversion
Interval
Initialize
NOTES: A. The first I/O CLOCK must occur after the rising edge of EOC.
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock.
Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion)
14
WWW.TI.COM
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
A9
A8
A7
7
8
9
10
Sample Cycle B
A6
A5
A4
A3
A2
A1
A0
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Hi-Z State
Low
Level
LSB
ADDRESS
B3
B2
B1
B0
MSB
1
16
See Note B
Previous Conversion Data
MSB
11
ÏÏÏ
ÏÏÏ
ÎÎÎ
ÎÎÎ
B9
ÎÎÎÎÎ
ÎÎÎÎÎ
C3
ÏÏÏ
ÏÏÏ
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
Initialize
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum
chip CS setup time has elapsed.
B. The eleventh rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial
interface synchronization.
Figure 13. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Longer Than Conversion)
Must be High on Power Up
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
A9
A8
A7
A6
A5
A4
A3
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
B3
MSB
B2
B1
8
9
10
Sample Cycle B
Previous Conversion Data
MSB
ADDRESS
7
A2
14
15
See Note A
A1
Low Level
A0
LSB
B0
16
1
See Note B
B9
ÎÎÎÎÎ
ÎÎÎÎÎ
C3
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Initialize
A/D Conversion
Interval
NOTES: A. The eleventh rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial
interface synchronization.
B. The I/O CLOCK sequence is exactly 16 clock pulses long.
Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion)
WWW.TI.COM
15
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
APPLICATION INFORMATION
1023
1111111111
See Notes A and B
1022
1111111110
1021
1111111101
VF T = VFS − 1/2 LSB
513
1000000001
512
1000000000
VZ T = VZS + 1/2 LSB
Step
Digital Output Code
VFS
511
0111111111
VZS
0000000001
1
0000000000
0
0.0048
0.0096
2.4528
2.4576
4.9056
2.4624
4.9080
2
0.0024
0000000010
4.9104
0
4.9152
VI − Analog Input Voltage − V
NOTES: A. This curve is based on the assumption that Vref + and Vref − have been adjusted so that the voltage at the transition from digital
0 to 1 (VZ T) is 0.0024 V and the transition to full scale (VF T) is 4.908 V. 1 LSB = 4.8 mV.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS)
is the step whose nominal midstep value equals zero.
Figure 15. Ideal Conversion Characteristics
TLV1543
1
2
3
4
5
Analog
Inputs
6
7
8
9
11
12
15
A0
CS
A1
I/O CLOCK
A2
ADDRESS
18
17
Processor
A3
A4
DATA OUT
A5
EOC
16
19
A6
A7
A8
A10
14
REF +
A9
REF −
3-V DC Regulated
13
GND
10
To Source
Ground
Figure 16. Serial Interface
16
WWW.TI.COM
Control
Circuit
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
APPLICATION INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 17, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
(
VC = VS 1−e
−t c /RtCi
)
(1)
Where:
Rt = Rs + ri
The final voltage to 1/2 LSB is given by
VC (1/2 LSB) = VS − (VS /2048)
(2)
Equating equation 1 to equation 2 and solving for time tc gives
(
VS −(VS/2048) = VS 1−e
−t c /RtCi
)
(3)
and
tc (1/2 LSB) = Rt × Ci × ln(2048)
(4)
Therefore, with the values given the time for the analog input signal to settle is
tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(2048)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Source†
TLV1543
Rs
VS
ri
VI
VC
1 kΩ MAX
Ci
60 pF MAX
VI = Input Voltage at A0 −A10
VS = External Driving Source Voltage
Rs = Source Resistance
ri = Input Resistance
Ci = Input Capacitance
† Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.
Figure 17. Equivalent Input Circuit Including the Driving Source
WWW.TI.COM
17
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV1543CDB
ACTIVE
SSOP
DB
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TV1543
TLV1543CDBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TV1543
TLV1543CDW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV1543C
TLV1543CDWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV1543C
TLV1543CDWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV1543C
TLV1543CFN
ACTIVE
PLCC
FN
20
46
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
TLV1543C
TLV1543CN
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLV1543IDB
ACTIVE
SSOP
DB
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TY1543
TLV1543IDBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TY1543
TLV1543CN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
24-Aug-2018
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLV1543CDBR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
TLV1543CDWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
TLV1543IDBR
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV1543CDBR
SSOP
DB
20
2000
350.0
350.0
43.0
TLV1543CDWR
SOIC
DW
20
2000
350.0
350.0
43.0
TLV1543IDBR
SSOP
DB
20
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
NOTE 3
5.85
10
11
20X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.1
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
11
10
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
FN0020A
PLCC - 4.57 mm max height
SCALE 1.300
PLASTIC CHIP CARRIER
B
.180 MAX
[4.57]
.350-.356
[8.89-9.04]
NOTE 3
A
3
1
(.008)
[0.2]
20
4
.020 MIN
[0.51]
18
PIN 1 ID
(OPTIONAL)
.350-.356
[8.89-9.04]
NOTE 3
.283-.339
[7.19-8.61]
14
8
9
13
.090-.120 TYP
[2.29-3.04]
20X .026-.032
[0.66-0.81]
C
SEATING PLANE
20X .013-.021
[0.33-0.53]
.007 [0.18]
C A B
.004 [0.1] C
16X .050
[1.27]
.385-.395
[9.78-10.03]
TYP
4215152/B 04/2017
NOTES:
1. All linear dimensions are in inches. Any dimensions in brackets are in millimeters. Any dimensions in parenthesis are for reference only.
Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension does not include mold protrusion. Maximum allowable mold protrusion .01 in [0.25 mm] per side.
4. Reference JEDEC registration MS-018.
www.ti.com
EXAMPLE BOARD LAYOUT
FN0020A
PLCC - 4.57 mm max height
PLASTIC CHIP CARRIER
SYMM
3
20X (.096 )
[2.45]
20X (.025 )
[0.64]
1
(R.002 ) TYP
[0.05]
20
4
18
SYMM
(.327)
[8.3]
16X (.050 )
[1.27]
14
8
9
13
(.327)
[8.3]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
EXPOSED METAL
.002 MAX
[0.05]
ALL AROUND
METAL
.002 MIN
[0.05]
ALL AROUND
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4215152/B 04/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
FN0020A
PLCC - 4.57 mm max height
PLASTIC CHIP CARRIER
SYMM
20X (.096 )
[2.45]
20X (.025 )
[0.64]
3
1
(R.002 ) TYP
[0.05]
20
4
18
SYMM
(.327)
[8.3]
16X (.050 )
[1.27]
14
8
9
13
(.327)
[8.3]
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4215152/B 04/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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