Texas Instruments | ADS822, ADS825: 10-Bit, 40MHz Sampling Analog-To-Digital Converter (Rev. B) | Datasheet | Texas Instruments ADS822, ADS825: 10-Bit, 40MHz Sampling Analog-To-Digital Converter (Rev. B) Datasheet

Texas Instruments ADS822, ADS825: 10-Bit, 40MHz Sampling Analog-To-Digital Converter (Rev. B) Datasheet
ADS
A DS
ADS822
ADS825
825
82 2
SBAS069B – MARCH 2001 – REVISED AUGUST 2002
10-Bit, 40MHz Sampling
ANALOG-TO-DIGITAL CONVERTERS
● +3V OR +5V LOGIC I/O COMPATIBLE (ADS825)
● POWER DOWN: 20mW
● SSOP-28 PACKAGE
FEATURES
●
●
●
●
●
HIGH SNR: 60dB
HIGH SFDR: 72dBFS
LOW POWER: 190mW
INTERNAL/EXTERNAL REFERENCE OPTION
SINGLE-ENDED OR
FULLY DIFFERENTIAL ANALOG INPUT
● PROGRAMMABLE INPUT RANGE
● LOW DNL: 0.5LSB
● SINGLE +5V SUPPLY OPERATION
APPLICATIONS
● MEDICAL IMAGING
● TEST EQUIPMENT
● COMPUTER SCANNERS
● COMMUNICATIONS
● VIDEO DIGITIZING
DESCRIPTION
The ADS822 and ADS825 are pipeline, CMOS Analog-to-Digital
Converters (ADC) that operate from a single +5V power supply.
These converters provide excellent performance with a single-ended
input and can be operated with a differential input for added spurious
performance. These high-performance converters include a 10-bit
quantizer, high-bandwidth track-and-hold, and a high-accuracy internal reference. They also allow for the user to disable the internal
reference and utilize external references. This external reference
option provides excellent gain and offset matching when used in
multichannel applications, or in applications where full-scale range
adjustment is required.
The ADS822 and ADS825 employ digital error correction techniques
to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed
for medical imaging, communications, video, and test instrumentation.
The ADS822 and ADS825 offer power dissipation of 190mW and also
provide a power-down mode, thus reducing power dissipation to only
20mW. The ADS825 is +3V or +5V logic I/O compatible.
The ADS822 and ADS825 are specified at a maximum sampling
frequency of 40MSPS and a single-ended input range of 1.5V to 3.5V.
The ADS822 and ADS825 are available in an SSOP-28 package and
are pin-for-pin compatible with the 10-bit, 60MSPS ADS823 and
ADS826, and the 10-bit, 75MSPS ADS828, providing an upgrade
path to higher sampling frequencies.
CLK
+VS
ADS822
ADS825
VIN
IN
IN
T/H
VDRV
Timing
Circuitry
10-Bit
Pipelined
A/D Core
Error
Correction
Logic
3-State
Outputs
D0
•
•
•
D9
Internal
Reference
CM
Optional External
Reference
Int/Ext
PD
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
+VS ....................................................................................................... +6V
Analog Input ............................................................. –0.3V to (+VS + 0.3V)
Logic Input ............................................................... –0.3V to (+VS + 0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
DEMO BOARD ORDERING INFORMATION
PRODUCT
DEMO BOARD
ADS822E
DEM-ADS822E
PACKAGE/ORDERING INFORMATION
PRODUCT
ADS822
"
ADS825
"
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
SSOP-28
DB
–40°C to +85°C
ADS822E
"
"
"
"
ADS822E
ADS822E/1K
Rails,
Tape and Reel, 1000
SSOP-28
DB
–40°C to +85°C
ADS825E
"
"
"
"
ADS825E
ADS825E/1K
Rails,
Tape and Reel, 1000
NOTES: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, sampling rate = 40MHz and, external reference, unless otherwise noted.
ADS825E(1)
ADS822E
PARAMETER
CONDITIONS
MIN
RESOLUTION
SPECIFIED TEMPERATURE RANGE
ANALOG INPUT
Standard Single-Ended Input Range
Optional Single-Ended Input Range
Common-Mode Range
Optional Differential Input Range
Analog Input Bias Current
Input Impedance
Track-Mode Input Bandwidth
Ambient Air
2Vp-p
1Vp-p
1.5
2
2Vp-p
2
2
MAX
MIN
MAX
UNITS
10
10
Bits
–40 to +85
°C
3.5
3
✻
✻
3
✻
10k
✻
✻
✻
✻
40M
✻
±1.0
✻
✻
Tested
✻
±2.0
V
V
V
V
µA
MΩ || pF
MHz
✻
Samples/s
Clk Cyc
✻
LSB
LSB
✻
LSBs
✻
5
±0.25
±0.5
Tested
±0.5
✻
✻
✻
1
1.25 || 5
300
–3dBFS Input
TYP
–40 to +85
2.5
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 1MHz
f = 10MHz
No Missing Codes
Integral Nonlinearity Error, f = 1MHz
Spurious-Free Dynamic Range(2)
f = 1MHz
f = 10MHz
2-Tone Intermodulation Distortion(4)
f = 9.5MHz and 9.9MHz (–7dB each tone)
Signal-to-Noise Ratio (SNR)
f = 1MHz
f = 10MHz
Signal-to-(Noise + Distortion) (SINAD)
f = 1MHz
f = 10MHz
Effective Number of Bits(5), f = 1MHz
Output Noise
Aperture Delay Time
Aperture Jitter
Overvoltage Recovery Time
Full-Scale Step Acquisition Time
TYP
Referred to Full-Scale
63
72
66
60
–67
71
65
dBFS(3)
dBFS
✻
dBc
✻
✻
dB
dB
✻
✻
✻
✻
✻
✻
✻
✻
dB
dB
Bits
LSBs rms
ns
ps rms
ns
ns
Referred to Full-Scale
57
60
60
✻
Referred to Full-Scale
56
Input Tied to Common-Mode
59
58
9.5
0.2
3
1.2
2
5
✻
ADS822, ADS825
SBAS069B
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
ADS825E(1)
ADS822E
PARAMETER
CONDITIONS
DIGITAL INPUTS
Logic Family
Convert Command
High-Level Input Current(6) (VIN = 5VDD)
Low-Level Input Current (VIN = 0V)
High-Level Input Voltage
Low-Level Input Voltage
Input Capacitance
Start Conversion
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (IOL = 50µA to 1.6mA)
High Output Voltage, (IOH = 50µA to 0.5mA)
Low Output Voltage, (IOL = 50µA to 1.6mA)
High Output Voltage, (IOH = 50µA to 0.5mA)
3-State Enable Time
3-State Disable Time
Output Capacitance
ACCURACY (Internal Reference, 2Vp-p,
Unless Otherwise Noted)
Zero Error (referred to –FS)
Zero Error Drift (referred to –FS)
Midscale Offset Error
Gain Error(7)
Gain Error Drift(7)
Gain Error(8)
Gain Error Drift(8)
Power-Supply Rejection of Gain
REFT Tolerance
REFB Tolerance(9)
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Power Dissipation: VDRV = 5V
VDRV = 3V
VDRV = 5V
VDRV = 3V
Power Down
Thermal Resistance, θJA
SSOP-28
VDRV = 5V
VDRV = 3V
OE = H to L
OE = L to H
MIN
MAX
MIN
TYP
MAX
CMOS-Compatible
Rising Edge of Convert Clock
100
10
+3.5
+1.0
5
TTL, +3V/+5V CMOS-Compatible
Rising Edge of Convert Clock
✻
✻
+2.0
+0.8
✻
CMOS-Compatible
Straight Offset Binary
+0.1
+4.9
+0.1
+2.8
2
40
2
10
5
CMOS-Compatible
Straight Offset Binary
fS = 2.5MHz
at 25°C
at 25°C
at 25°C
at 25°C
∆ VS = ±5%
Deviation From Ideal 3.5V
Deviation From Ideal 1.5V
REFB + 0.8
1.25
REFT to REFB
Operating
Operating (External Reference)
External Reference
External Reference
Internal Reference
Internal Reference
Operating
TYP
+4.75
±1.0
5
±3.0
±1.5
38
±0.75
25
70
±10
±10
3.5
1.5
1.6
±3.5
+5.0
40
200
190
250
240
20
89
✻
✻
✻
✻
±2.5
±25
±25
VS – 1.25
REFT – 0.8
✻
✻
+5.25
✻
230
✻
✻
✻
✻
✻
✻
✻
±0.29
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
UNITS
µA
µA
V
V
pF
V
V
V
V
ns
ns
pF
% FS
ppm/°C
% FS
% FS
ppm/°C
% FS
ppm/°C
dB
mV
mV
V
V
kΩ
V
mA
mW
mW
mW
mW
mW
°C/W
✻ Indicates the same specifications as the ADS822E.
NOTES: (1) ADS825E accepts a +3V clock input. (2) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (3) dBFS means dB relative to Full
Scale. (4) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone
fundamental envelope. (5) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (6) A 50kΩ pull-down resistor is inserted internally on OE pin. (7) Includes
internal reference. (8) Excludes internal reference. (9) Assured by design.
ADS822, ADS825
SBAS069B
3
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
SSOP
GND
1
28
VDRV
Bit 1 (MSB)
2
27
+VS
Bit 2
3
26
GND
Bit 3
4
25
IN
Bit 4
5
24
IN
Bit 5
6
23
CM
Bit 6
7
22
REFT
Bit 7
8
21
ByT
Bit 8
9
20
ByB
Bit 9 10
19
REFB
Bit 10 (LSB) 11
18
INT/EXT
OE 12
17
RSEL
PD 13
16
GND
CLK 14
15
+VS
ADS822
ADS825
PIN
DESIGNATOR
1
2
3
4
5
6
7
8
9
10
11
12
GND
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
OE
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PD
CLK
+VS
GND
RSEL
INT/EXT
REFB
ByB
ByT
REFT
CM
IN
IN
GND
+VS
VDRV
DESCRIPTION
Ground
Data Bit 1 (D9) (MSB)
Data Bit 2 (D8)
Data Bit 3 (D7)
Data Bit 4 (D6)
Data Bit 5 (D5)
Data Bit 6 (D4)
Data Bit 7 (D3)
Data Bit 8 (D2)
Data Bit 9 (D1)
Data Bit 10 (D0) (LSB)
Output Enable. HI = high impedance state
LO = normal operation (internal pull-down
resistor)
Power Down. HI = enable; LO = disable
Convert Clock Input
+5V Supply
Ground
Input Range Select. HI = 2V; LO = 1V
Reference Select. HI = external, LO = internal
Bottom Reference
Bottom Ladder Bypass
Top Ladder Bypass
Top Reference
Common-Mode Voltage Output
Complementary Input (–)
Analog Input (+)
Analog Ground
+5V Supply
Output Logic Driver Supply Voltage
TIMING DIAGRAM
N+2
N+1
Analog In
N+4
N+3
N
tD
N+5
tL
tCONV
N+7
N+6
tH
Clock
5 Clock Cycles
t2
Data Out
N–5
N–4
N–3
N–2
N–1
N
Data Invalid
SYMBOL
tCONV
tL
tH
tD
t1
t2
4
N+1
N+2
t1
DESCRIPTION
MIN
Convert Clock Period
Clock Pulse Low
Clock Pulse High
Aperture Delay
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
25
11.5
11.5
TYP
MAX
UNITS
100µs
ns
ns
ns
ns
ns
ns
12.5
12.5
3
3.9
12
ADS822, ADS825
SBAS069B
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, sampling rate = 40MHz, and external reference, unless otherwise noted.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fIN = 10MHz
fIN = 1MHz
–20
Magnitude (dB)
Magnitude (dB)
–20
–40
–60
–100
–100
0
5
10
15
0
20
5
10
15
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE
(Differential Input, 1Vp-p)
SPECTRAL PERFORMANCE
(Single-Ended, 1Vp-p)
0
20
0
fIN = 10MHz
SNR = 58dBFS
SFDR = 74dBFS
fIN = 10MHz
SNR = 57dBFS
SFDR = 71dBFS
–20
Magnitude (dB)
–20
Magnitude (dB)
–60
–80
–80
–40
–60
–80
–40
–60
–80
–100
–100
0
5
10
15
20
0
5
10
15
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE
(Single-Ended, 1Vp-p)
UNDERSAMPLING
(Differential Input, 2Vp-p)
0
20
0
fIN = 20MHz
SNR = 57dBFS
SFDR = 70dBFS
fS = 40MHz
fIN = 45MHz
SNR = 60dBFS
SFDR = 74dBFS
–20
Magnitude (dB)
–20
Magnitude (dB)
–40
–40
–60
–80
–40
–60
–80
–100
–100
0
5
10
Frequency (MHz)
ADS822, ADS825
SBAS069B
15
20
0
5
10
15
20
Frequency (MHz)
5
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, sampling rate = 40MHz, and external reference, unless otherwise noted.
UNDERSAMPLING
(Differential Input, 2Vp-p)
2-TONE INTERMODULATION DISTORTION
0
0
fS = 40MHz
fIN = 75MHz
SNR = 59dBFS
SFDR = 66dBFS
–20
Magnitude (dB)
Magnitude (dB)
–20
f1 = 9.5MHz at –7dBFS
f2 = 9.9MHz at –7dBFS
IMD (3) = –67dB
–40
–60
–40
–60
–80
–80
–100
–100
0
5
10
15
0
20
5
10
1.0
fIN = 10MHz
fIN = 1MHz
0.5
DLE (LSB)
0.5
DLE (LSB)
20
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
1.0
0
0
–0.5
–0.5
–1.0
–1.0
0
128
256
512
768
0
1024
128
256
512
768
1024
Output Code
Output Code
INTEGRAL LINEARITY ERROR
SWEPT POWER SFDR
2.0
100
80
SFDR (dBFS, dBc)
1.0
ILE (LSB)
15
Frequency (MHz)
Frequency (MHz)
0
–1.0
dBFS
60
40
dBc
20
–2.0
0
0
256
512
Output Code
6
768
1024
–60
–50
–40
–30
–20
–10
0
Input Amplitude (dBFS)
ADS822, ADS825
SBAS069B
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, sampling rate = 40MHz, and external reference, unless otherwise noted.
DYNAMIC PERFORMANCE vs TEMPERATURE
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
75
75
SFDR
SFDR, SNR (dBFS)
SFDR, SNR (dBFS)
70
65
60
SNR
55
70
SFDR (fIN = 10MHz)
65
SFDR (fIN = 20MHz)
SNR (fIN = 10MHz)
60
SNR (fIN = 20MHz)
55
50
0.1
1
10
–50
100
–25
0
25
50
75
Frequency (MHz)
Temperature (°C)
SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
60
100
.60
fIN = 1MHz
fIN = 10MHz
DLE (LSB)
Sinad (dBFS)
fIN = 20MHz
59
.50
fIN = 10MHz
.40
58
fIN = 20MHz
.30
57
–50
–25
0
25
50
75
–50
100
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
POWER DISSIPATION vs TEMPERATURE
OUTPUT NOISE (DC Input)
205
800k
Counts
Power (mW)
600k
200
400k
195
200k
190
0
–50
–25
0
25
50
Temperature (°C)
ADS822, ADS825
SBAS069B
75
100
N-2
N-1
N
N+1
N+2
Code
7
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS822 and ADS825 are high-speed CMOS ADCs
which employ a pipelined converter architecture consisting of
nine internal stages. Each stage feeds its data into the digital
error correction logic ensuring excellent differential linearity
and no missing codes at the 10-bit level. The output data
becomes valid on the rising clock edge (see Timing Diagram). The pipeline architecture results in a data latency of
5 clock cycles.
The analog inputs of the ADS822 and ADS825 are differential track-and-hold, as shown in Figure 1. The differential
topology, along with tightly matched capacitors, produce a
high level of AC performance while sampling at very high rates.
Op Amp
Bias
φ1
IN
φ1
φ2
φ1
CH
φ2
OUT
φ1
OUT
φ1
CI
φ2
CH
φ1
φ1
Input Clock (50%)
Op Amp
Bias
VCM
Internal Non-overlapping Clock
φ1
φ2
φ1
FIGURE 1. Simplified Circuit of Input Track-and-Hold with
Timing Diagram.
The ADS822 and ADS825 allow their analog inputs to be
driven either single-ended or differentially. The typical configuration for the ADS822 and ADS825 is the single-ended
mode in which the input track-and-hold performs a singleended-to-differential conversion of the analog input signal.
Both inputs (IN, IN) require external biasing using a common-mode voltage that is typically at the mid-supply level
(+VS/2).
The following application discussion focuses on the singleended configuration. Typically, its implementation is easier to
achieve and the rated specifications for the ADS822 and
ADS825 are characterized using the single-ended mode of
operation.
DRIVING THE ANALOG INPUT
The ADS822 and ADS825 achieve excellent AC performance
either in the single-ended or differential mode of operation.
8
INPUT CONFIGURATIONS
AC-Coupled, Single-Supply Interface
See Figure 2 for the typical circuit for an AC-coupled analog
input configuration of the ADS822 and ADS825 while all
components are powered from a single +5V supply.
VCM
CI
IN
The selection for the optimum interface configuration will
depend on the individual application requirements and system structure. For example, communications applications
often process a band of frequencies that do not include DC,
whereas in imaging applications, the previously restored DC
level must be maintained correctly up to the ADC. Features
on the ADS822 and ADS825, such as the input range select
(RSEL pin) or the option for an external reference, provide
the needed flexibility to accommodate a wide range of
applications. In any case, the ADS822 and ADS825 should
be configured such that the application objectives are met
while observing the headroom requirements of the driving
amplifier in order to yield the best overall performance.
With the RSEL pin connected HI, the full-scale input range is
set to 2Vp-p. In this configuration, the top and bottom
references (REFT, REFB) provide an output voltage of +3.5V
and +1.5V, respectively. Two resistors ( 2x 1.62kΩ) are used
to create a common-mode voltage (VCM) of approximately
+2.5V to bias the inputs of the driving amplifier A1. Using the
OPA680 on a single +5V supply, its ideal common-mode
point is at +2.5V which coincides with the recommended
common-mode input level for the ADS822 and ADS825. This
obviates the need of a coupling capacitor between the
amplifier and the converter. Even though the OPA680 has an
AC gain of +2, the DC gain is only +1 due to the blocking
capacitor at resistor RG.
The addition of a small series resistor (RS) between the
output of the op amp and the input of the ADS822 and
ADS825 will be beneficial in almost all interface configurations. This will decouple the op amp’s output from the
capacitive load and avoid gain peaking, which can result in
increased noise. For best spurious and distortion performance, the resistor value should be kept below 100Ω.
Furthermore, the series resistor in combination with the 10pF
capacitor establishes a passive low-pass filter limiting the
bandwidth for the wideband noise, thus helping improve the
SNR performance.
AC-Coupled, Dual Supply Interface
The circuit provided in Figure 3 illustrates typical connections
for the analog input in case the selected amplifier operates
on dual supplies. This might be necessary to take full
advantage of very low distortion operational amplifiers, like
the OPA642. The advantage is that the driving amplifier can
be operated with a ground-referenced bipolar signal swing.
This will keep the distortion performance at its lowest, since
the signal range stays within the linear region of the op amp
and sufficient headroom to the supply rails can be maintained. By capacitively coupling the single-ended signal to
the input of the ADS822 and ADS825, its common-mode
requirements can easily be satisfied with two resistors connected between the top and bottom references.
ADS822, ADS825
SBAS069B
1.62kΩ
+5V
VCM +2.5V
1.62kΩ
+5V
0.1µF
50Ω
REFB
+1.5V
RS
50Ω
VIN
REFT
+3.5V
RSEL
+VS
IN
OPA690
10pF
+VIN
0V
ADS822
ADS825
RF
402Ω
–VIN
CM
IN
RG
402Ω
0.1µF
INT/EXT
0.1µF
GND
FIGURE 2. AC-Coupled Input Configuration for a 2Vp-p Full-Scale Range and a Common-Mode Voltage, VCM, at +2.5V Derived
From the Internal Top (REFT) and Bottom References (REFB).
+5V
1.62kΩ
+5V
RS
24.9Ω
VIN
REFT
+3.5V
0.1µF
RSEL
+VS
IN
OPA642
100pF
ADS822
ADS825
–5V
RF
402Ω
1.62kΩ
CM
IN
RG
402Ω
0.1µF
REFB
+1.5V
INT/EXT
GND
FIGURE 3. AC-Coupling the Dual Supply Amplifier, OPA642, to the ADS822 for a 2Vp-p Full-Scale Input Range.
For applications requiring the driving amplifier to provide a
signal amplification, with a gain ≥ 5, consider using decompensated voltage-feedback op amps, like the OPA686, or
current-feedback op amps like the OPA691.
DC-coupled with Level Shift
Several applications may require that the bandwidth of the
signal path include DC, in which case, the signal has to be
DC-coupled to the ADC. In order to accomplish this, the
interface circuit has to provide a DC level shift to the analog
input signal. See Figure 4 for a circuit that employs a dual op
amp, A1, to drive the input of the ADS822 and ADS825, and
level shifts the signal to be compatible with the selected input
range. With the RSEL pin tied to the supply and the INT/EXT
pin to ground, the ADS822 and ADS825 are configured for a
2Vp-p input range and use the internal references. The
complementary input (IN) may be appropriately biased using
ADS822, ADS825
SBAS069B
the +2.5V common-mode voltage available at the CM pin.
One half of amplifier A1 buffers the REFB pin and drives the
voltage dividers R1, R2. Due to the op amp’s noise gain of
+2V/V, assuming RF = RIN , the common-mode voltage (VCM)
has to be re-scaled to +1.25V. This results in the correct DC
level of +2.5V for the signal input (IN). Any DC voltage
differences between the IN and IN inputs of the ADS822 and
ADS825 effectively produces an offset, which can be corrected for by adjusting the resistor values of the divider, R1
and R2. The selection criteria for a suitable op amp should
include the supply voltage, input bias current, output voltage
swing, distortion, and noise specification. Note that in this
example, the overall signal phase is inverted. To re-establish
the original signal polarity, it is always possible to interchange the IN and IN connections.
9
+5V
RF
499Ω
RIN
499Ω
A1
VIN
1/2
OPA2691
+VS
RSEL
RS
50Ω
IN
2Vp-p
10pF
ADS822
ADS825
NOTE: RF = RIN, G = –1
CM (+2.5)
IN
+5V
R2
200Ω
VCM = +1.25V
A2
0.1µF
REFB
(+1.5V)
REFT
(+3.5V)
INT/EXT
50Ω
0.1µF
1/2
OPA2691
0.1µF
R1
1kΩ
RF
1kΩ
FIGURE 4. DC-Coupled Interface Circuit with Dual Current-Feedback Amplifier OPA2681.
SINGLE-ENDED-TO-DIFFERENTIAL CONFIGURATION
(Transformer Coupled)
If the application requires a signal conversion from a singleended source to feed the ADS822 and ADS825 differentially,
a RF transformer might be a good solution. The selected
transformer must have a center tap in order to apply the
common-mode DC voltage necessary to bias the converter
inputs. AC-grounding the center tap will generate the differential signal swing across the secondary winding. Consider
a step-up transformer to take advantage of a signal amplification without the introduction of another noise source.
Furthermore, the reduced signal swing from the source may
lead to an improved distortion performance.
The differential input configuration may provide a noticeable
advantage of achieving good SFDR performance over a wide
range of input frequencies. In this mode, both inputs of the
ADS822 and ADS825 see matched impedances, and the
differential signal swing can be reduced to half of the swing
required for single-ended drive. Figure 5 shows the schematic for the suggested transformer-coupled interface circuit.
RG
The component values of the R-C low-pass may be optimized depending on the desired roll-off frequency. The
resistor across the secondary side (RT) should be calculated
using the equation RT = n2 • RG to match the source impedance
(RG) for good power transfer and Voltage Standing Wave Ratio
(VSWR).
REFERENCE OPERATION
Figure 6 depicts the simplified model of the internal reference
circuit. The internal blocks are the bandgap voltage reference, the drivers for the top and bottom references, and the
RSEL
ADS822
50kΩ
+VS
INT/EXT
50kΩ
Bandgap Reference and Logic
VREF
+1
0.1µF 1:n
+1
22Ω
VIN
IN
47pF
ADS822
ADS825
RT
400Ω
400Ω
400Ω
400Ω
22Ω
IN
CM
RSEL INT/EXT
REFT
ByT
CM
ByB
REFB
47pF
+5V
+
10µF
FIGURE 5. Transformer Coupled Input.
10
0.1µF
Bypass Capacitors: 0.1µF || 2.2µF each (optionally, 2.2µF tantalum
capacitors maybe added to ByT and ByB pins for the best results).
FIGURE 6. Equivalent Reference Circuit with Recommended
Reference Bypassing.
ADS822, ADS825
SBAS069B
resistive reference ladder. The bandgap reference circuit
includes logic functions that allows setting the analog input
swing of the ADS822 and ADS825 to either a 1Vp-p or
2Vp-p full-scale range simply by tying the RSEL pin to a Low
or High potential, respectively. While operating the ADS822
in the external reference mode, the buffer amplifiers for the
REFT and REFB are disconnected from the reference ladder.
As shown, the ADS822 and ADS825 have internal 50kΩ pullup resistors at the range select pin (RSEL) and reference
select pin (INT/EXT). Leaving these pins open configures the
ADS822 and ADS825 for a 2Vp-p input range and external
reference operation. Setting the ADS822 and ADS825 up for
internal reference mode requires bringing the INT/EXT pin
Low.
The reference buffers can be utilized to supply up to 1mA
(sink and source) to external circuitry. The resistor ladders of
the ADS822 and ADS825 are divided into several segments
and have two additional nodes, ByT and ByB, which are
brought out for external bypassing only (see Figure 6). To
ensure proper operation with any reference configurations, it
is necessary to provide solid bypassing at all reference pins
in order to keep the clock feedthrough to a minimum. All
bypassing capacitors should be located as close to their
respective pins as possible.
The common-mode voltage available at the CM pin may be
used as a bias voltage to provide the appropriate offset for
the driving circuitry. However, care must be taken not to
appreciably load this node, which is not buffered and has a
high impedance. An alternative way of generating a common-mode voltage is given in Figure 7. Here, two external
precision resistors (tolerance 1% or better) are located
between the top and bottom reference pins. The commonmode voltage, CMV, will appear at the midpoint.
EXTERNAL REFERENCE OPERATION
For even more design flexibility, the internal reference can be
disabled and an external reference voltage be used. The
utilization of an external reference may be considered for
applications requiring higher accuracy, improved temperature performance, or a wide adjustment range of the
converter’s full-scale range. Especially in multichannel
applications, the use of a common external reference has the
benefit of obtaining better matching of the full-scale range
between converters.
The external references can vary as long as the value of the
external top reference REFTEXT stays within the range of
(VS – 1.25V) and (REFB + 0.8V), and the external bottom
reference REFBEXT stays within 1.25V and (REFT – 0.8V)
(See Figure 8).
DIGITAL INPUTS AND OUTPUTS
ADS822
ADS825
REFT
+3.5V
R1
1.6kΩ
Clock Input Requirements
REFB
+1.5V
Clock jitter is critical to the SNR performance of high-speed,
high-resolution ADCs. Clock jitter leads to aperture jitter (tA),
which adds noise to the signal being converted. The ADS822
and ADS825 samples the input signal on the rising edge of the
CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total SNR is given by
R2
1.6kΩ
0.1µF
0.1µF
CMV
+2.5V
FIGURE 7. Alternative Circuit to Generate CM Voltage.
+5V
B
A - Short for 1Vp-p Input Range
B - Short for 2Vp-p Input Range (Default)
+VS
A
RSEL
INT/EXT
GND
IN
VIN
ADS822
ADS825
CMV
+2.5VDC
IN
REFT
External Top Reference
REFT = REFB +0.8V to +3.75V
ByT
GND
4 x 0.1µF
ByB
REFB
External Bottom Reference
REFB = REFT –0.8V to +1.25V
FIGURE 8. Configuration Example for External Reference Operation.
ADS822, ADS825
SBAS069B
11
the following equation. If this value is near your system
requirements, input clock jitter must be reduced.
Jitter SNR = 20 log
1
rms signal to rms noise
2π ƒIN t A
where: ƒIN is input signal frequency
tA is rms clock jitter
Particularly in undersampling applications, special consideration should be given to clock jitter. The clock input should be
treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should have
50% duty cycle (tH = tL), along with fast rise and fall times of
2ns or less. The clock input of the ADS825 can be driven with
either 3V or 5V logic levels. Using low-voltage logic (3V) may
lead to improved AC performance of the converter.
Digital Outputs
The output data format of the ADS822 and ADS825 are in
positive Straight Offset Binary code, as shown in Tables I
and II. This format can easily be converted into the Binary
Two’s Complement code by inverting the MSB.
It is recommended to keep the capacitive loading on the data
lines as low as possible (≤ 15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS822 and ADS825 and affect the
performance. If necessary, external buffers or latches close
to the converter’s output pins may be used to minimize the
capacitive loading. They also provide the added benefit of
isolating the ADS822 and ADS825 from any digital noise
activities on the bus coupling back high frequency noise.
SINGLE-ENDED INPUT
(IN = CMV)
+FS –1LSB (IN = REFT)
+1/2 Full Scale
Bipolar Zero (IN = CMV)
–1/2 Full Scale
–FS (IN = REFB)
STRAIGHT OFFSET BINARY
(SOB)
11
11
10
01
00
1111
0000
0000
0000
0000
1111
0000
0000
0000
0000
TABLE I. Coding Table for Single-Ended Input Configuration
with IN Tied to the Common-Mode Voltage (CMV).
DIFFERENTIAL INPUT
+FS –1LSB (IN = +3V, IN = +2V)
+1/2 Full Scale
Bipolar Zero (IN = IN = CMV)
–1/2 Full Scale
–FS (IN = +2V, IN = +3V)
STRAIGHT OFFSET BINARY
(SOB)
11
11
10
01
00
1111
0000
0000
0000
0000
1111
0000
0000
0000
0000
TABLE II. Coding Table for Differential Input Configuration and
2Vp-p Full-Scale Range.
Digital Output Driver (VDRV)
The ADS822 features a dedicated supply pin for the output
logic drivers, VDRV, which are not internally connected to
the other supply pins. Setting the voltage at VDRV to +5V or
+3V, the ADS822 and ADS825 produce corresponding logic
levels and can directly interface to the selected logic family.
The output stages are designed to supply sufficient current
to drive a variety of logic families. However, it is recommended to use the ADS822 and ADS825 with +3V logic
supply. This will lower the power dissipation in the output
stages due to the lower output swing and reduce current
glitches on the supply line which may affect the AC-performance of the converter. In some applications, it might be
advantageous to decouple the VDRV pin with additional
capacitors or a pi filter.
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for highfrequency designs. Multilayer PC boards are recommended
for best performance since they offer distinct advantages like
minimizing ground impedance, separation of signal layers by
ground layers, etc. The ADS822 and ADS825 should be
treated as analog components. Whenever possible, the
supply pins should be powered by the analog supply. This
will ensure the most consistent results, since digital supply
lines often carry high levels of noise which otherwise would
be coupled into the converter and degrade the achievable
performance. All ground connections on the ADS822 and
ADS825 are internally joined together obviating the design of
split ground planes. The ground pins (1, 16, 26) should
directly connect to an analog ground plane which covers the
PC board area around the converter. While designing the
layout, it is important to keep the analog signal traces
separated from any digital lines to prevent noise coupling
onto the analog signal path. Due to their high sampling rates,
the ADS822 and ADS825 generate high frequency current
transients, and noise (clock feedthrough) that are fed back
into the supply and reference lines. This requires that all
supply and reference pins are sufficiently bypassed.
Figure 9 shows the recommended decoupling scheme for
the ADS822 and ADS825. In most cases, 0.1µF ceramic
chip capacitors at each pin are adequate to keep the impedance low over a wide frequency range. Their effectiveness
largely depends on the proximity to the individual supply pin.
Therefore, they should be located as close to the supply pins
as possible. In addition, a larger bipolar capacitor (1µF to
22µF) should be placed on the PC board in proximity of the
converter circuit.
+VS
27
GND
26
ADS822
ADS825
+VS
15
0.1µF
GND
16
0.1µF
VDRV
28
0.1µF
10µF
+
+5V
+3/+5V
FIGURE 9. Recommended Bypassing for the Supply Pins.
12
ADS822, ADS825
SBAS069B
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS822E
ACTIVE
SSOP
DB
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS822E
ADS822E/1K
ACTIVE
SSOP
DB
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS822E
ADS825E
ACTIVE
SSOP
DB
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS825E
ADS825E/1K
ACTIVE
SSOP
DB
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS825E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS822E/1K
SSOP
DB
28
1000
330.0
16.4
8.1
10.4
2.5
12.0
16.0
Q1
ADS825E/1K
SSOP
DB
28
1000
330.0
16.4
8.1
10.4
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS822E/1K
SSOP
DB
28
1000
350.0
350.0
43.0
ADS825E/1K
SSOP
DB
28
1000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0028A
SSOP - 2 mm max height
SCALE 1.500
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
26X 0.65
28
1
2X
10.5
9.9
NOTE 3
8.45
14
15
28X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.15
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
28X (1.85)
(R0.05) TYP
1
28X (0.45)
28
26X (0.65)
SYMM
15
14
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
28X (1.85)
SYMM
(R0.05) TYP
1
28X (0.45)
28
26X (0.65)
SYMM
14
15
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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