Texas Instruments | ADS804: 12-Bit, 10MHz Sampling Analog-To-Digital Converter (Rev. B) | Datasheet | Texas Instruments ADS804: 12-Bit, 10MHz Sampling Analog-To-Digital Converter (Rev. B) Datasheet

Texas Instruments ADS804: 12-Bit, 10MHz Sampling Analog-To-Digital Converter (Rev. B) Datasheet
ADS804
ADS
804
E
SBAS068B – JANUARY 1997 – REVISED AUGUST 2002
12-Bit, 10MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
APPLICATIONS
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HIGH SFDR: 80dB at NYQUIST
HIGH SNR: 69dB
LOW POWER: 180mW
LOW DLE: ±0.3LSB
FLEXIBLE INPUT RANGE
OVERRANGE INDICATOR
DESCRIPTION
The ADS804 is a high-speed, high dynamic range, 12-bit,
pipelined Analog-to-Digital (A/D) converter. This converter
includes a high-bandwidth track-and-hold that gives excellent spurious performance up to and beyond the Nyquist
rate. This high-bandwidth, linear track-and-hold minimizes
harmonics and has low jitter, leading to excellent SNR
performance. The ADS804 is also pin-compatible with the
5MHz ADS803 and the 20MHz ADS805.
The ADS804 provides an internal reference and can be
programmed for a 2Vp-p input range for the best spurious
performance and ease of driving. Alternatively, the 5Vp-p
input range can be used for the lowest input referred noise
IF AND BASEBAND DIGITIZATION
CCD IMAGING
SCANNERS
TEST INSTRUMENTATION
of 0.09LSBs rms giving superior imaging performance. There
is also a capability to set the input range in between the 2Vpp and 5Vp-p input ranges or to use external reference. The
ADS804 also provides an over-range indicator flag to indicate an input range that exceeds the full-scale input range of
the converter. This flag can be used to reduce the gain of the
front end gain-ranging circuitry.
The ADS804 employs digital error correction techniques to
provide excellent differential linearity for demanding imaging
applications. Its low distortion and high SNR give the extra
margin needed for communications, medical imaging, video,
and test instrumentation applications. The ADS804 is available in a SSOP-28 package.
+VS
CLK
VDRV
ADS804
Timing Circuitry
VIN
IN
12-Bit
Pipelined
A/D Converter Core
T&H
IN
(Opt.)
Error
Correction
Logic
3-State
Outputs
D0
•
•
•
D11
CM
OVR
Reference Ladder
and Driver
Reference and
Mode Select
REFT
VREF
SEL
REFB
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
+VS, VDRV ........................................................................................... +6V
Analog Input .......................................................... (–0.3V) to (+VS + 0.3V)
Logic Input ............................................................ (–0.3V) to (+VS + 0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
ADS804
"
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
SSOP-28
DB
–40°C to +85°C
ADS804E
"
"
"
"
ADS804E
ADS804E/1K
Rails, 48
Tape and Reel, 1000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input, and sampling rate = 5MHz, unless otherwise specified.
ADS804E
PARAMETER
CONDITIONS
MIN
RESOLUTION
SPECIFIED TEMPERATURE RANGE
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
ANALOG INPUT
Single-Ended Input Range
Single-Ended Input Range (Optional)
Common-Mode Voltage
Input Impedance
Track-Mode Input Bandwidth
DYNAMIC CHARACTERISTICS
Differential Linearity Error (Largest Code Error)
f = 500kHz
No Missing Codes
Spurious-Free Dynamic Range(1)
f = 4.8MHz
2-Tone Intermodulation Distortion(3)
f = 3.5MHz and 4.0MHz (–7dBFS each tone)
Signal-to-Noise Ratio (SNR)
f = 4.8MHz
Signal-to-(Noise + Distortion) (SINAD)
f = 4.8MHz
Effective Number of Bits at 4.8MHz(4)
Input Referred Noise
Integral Nonlinearity Error
f = 500kHz
Aperture Delay Time
Aperture Jitter
Over-Voltage Recovery Time
Full-Scale Step Acquisition Time
2
TYP
MAX
12
Bits
–40 to +85
°C
10k
10M
Samples/s
Clk Cycles
3.5
5
V
V
V
MΩ || pF
MHz
±0.75
LSB
6
1.5
0
+2.5
1.25 || 16
270
–3dBFS Input
±0.3
Tested
73
0V to 5V Input
1.5V to 3.5V Input
1.5 • FS Input
UNITS
80
dBFS
76
dBc
66.5
69
dBFS
65
68
11
0.09
0.23
dBFS
Bits
LSBs rms
LSBs rms
±1
1
4
2
30
±2
LSB
ns
ps rms
ns
ns
ADS804
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SBAS068B
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 10MHz, unless otherwise specified.
ADS804E
PARAMETER
DIGITAL INPUTS
Logic Family
Convert Command
High Level Input Current (VIN = 5V)(5)
Low Level Input Current (VIN = 0V)
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
DIGITAL OUTPUTS
Logic Family
Convert Command
Output Voltages, VDRV = +5V
Low Level
High Level
Low Level
High Level
Output Voltages, VDRV = +3V
Low Level
High Level
3-State Enable Time
3-State Disable Time
Output Capacitance
ACCURACY (5Vp-p Input Range)
Zero Error (Referred to –FS)
Zero Error Drift
Gain Error(6)
Gain Error Drift(6)
Gain Error(7)
Gain Error Drift(7)
Power-Supply Rejection of Gain
Reference Input Resistance
Internal Voltage Reference Tolerance (VREF = 2.5V)
Internal Voltage Reference Tolerance (VREF = 1.0V)
CONDITIONS
MIN
TYP
MAX
UNITS
100
10
µA
µA
V
V
pF
CMOS Compatible
Rising Edge of Convert Clock
Start Conversion
+3.5
+1.0
5
CMOS/TTL Compatible
Straight Offset Binary
IOL = 50µA
IOH = 50µA
IOL = 1.6mA
IOH = 0.5mA
IOL = 50µA
IOH = 50µA
OE = L
OE = H
+0.1
±4.6
+0.4
±2.4
+0.1
+2.5
fS = 2.5MHz
At 25°C
20
2
5
40
10
0.2
±5
±1.5
At 25°C
±15
At 25°C
∆VS = ±5%
60
±15
82
1.6
At 25°C
At 25°C
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Power Dissipation
Thermal Resistance, θJA
SSOP-28
+4.7
+5.0
36
180
50
V
V
V
V
V
V
ns
ns
pF
±35
±14
%FS
ppm/°C
%FS
ppm/°C
%FS
ppm/°C
dB
kΩ
mV
mV
+5.3
40
200
V
mA
mW
±2.0
±1.5
°C/W
NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full-scale. (3) 2-tone intermodulation
distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope.
(4) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (5) Internal 50kΩ pull-down resistor. (6) Includes internal reference. (7) Excludes internal
reference.
ADS804
SBAS068B
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3
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
SSOP
OVR
1
28
VDRV
B1
2
27
+VS
B2
3
26
GND
B3
4
25
IN
B4
5
24
GND
B5
6
23
IN
B6
7
22
REFT
B7
8
21
CM
B8
9
20
REFB
B9 10
19
VREF
B10 11
18
SEL
B11 12
17
GND
B12 13
16
+VS
CLK 14
15
OE
ADS804
PIN
DESIGNATOR
1
OVR
2
3
4
5
6
7
8
9
10
11
12
13
14
15
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
CLK
OE
16
17
18
+VS
GND
SEL
19
20
21
22
23
24
25
26
27
28
VREF
REFB
CM
REFT
IN
GND
IN
GND
+VS
VDRV
DESCRIPTION
Over-Range Indicator (See Application
Section)
Data Bit 1(D11) (MSB)
Data Bit 2 (D10)
Data Bit 3 (D9)
Data Bit 4 (D8)
Data Bit 5 (D7)
Data Bit 6 (D6)
Data Bit 7 (D5)
Data Bit 8 (D4)
Data Bit 9 (D3)
Data Bit 10 (D2)
Data Bit 11 (D1)
Data Bit 12 (D0) (LSB)
Convert Clock Input
Output Enable. H = High Impedance State.
L = Low or floating, normal operation
(Internal pull-down resistor).
+5V Supply
Ground
Input Range Select (See Application
Section)
Reference Voltage Select (I/O)
Bottom Reference
Common-Mode Voltage
Top Reference
Analog Input (–)
Ground
Analog Input (+)
Ground
+5V Supply
Output Driver Voltage (See Application
Section)
TIMING DIAGRAM
N+2
N+1
Analog In
N+4
N+3
N
tD
N+5
tL
tCONV
N+7
N+6
tH
Clock
6 Clock Cycles
t2
Data Out
N–6
N–5
N–4
N–3
N–2
N–1
N
Data Invalid
SYMBOL
tCONV
tL
tH
tD
t1
t2
4
N+1
t1
DESCRIPTION
MIN
Convert Clock Period
Clock Pulse LOW
Clock Pulse HIGH
Aperture Delay
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
100
48
48
TYP
MAX
UNITS
100µs
ns
ns
ns
ns
ns
ns
49
49
2
3.9
12
ADS804
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SBAS068B
TYPICAL CHARACTERISTICS
At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 10MHz, unless otherwise specified.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fIN = 4.8MHz
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
fIN = 500kHz
–20
–60
–80
–100
–60
–80
–100
–120
–120
0
1.0
2.0
3.0
4.0
5.0
0
1.0
2.0
Frequency (MHz)
2-TONE INTERMODULATION
4.0
5.0
DIFFERENTIAL LINEARITY ERROR
0
1.0
fIN = 4.8MHz
f1 = 3.5MHz at –7dB
f2 = 4MHz at –7dB
IMD (3) = –76dBc
–20
0.5
–40
DLE (LSB)
Magnitude (dBFSR)
3.0
Frequency (MHz)
–60
0
–80
–0.5
–100
–120
–1.0
0
1.25
2.5
3.75
5.0
0
1024
2048
Frequency (MHz)
3072
INTEGRAL LINEARITY ERROR
SWEPT POWER SFDR
4.0
100
fIN = 500kHz
fIN = 4.8MHz
80
SFDR (dBFS, dBc)
2.0
ILE (LSB)
4096
Output Code
0
–2.0
dBFS
60
dBc
40
20
–4.0
0
0
1024
2048
3072
4096
Output Code
–50
–40
–30
–20
–10
0
Input Amplitude (dBFS)
ADS804
SBAS068B
–60
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5
TYPICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 10MHz, unless otherwise specified.
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
(Differential Input, VIN = 5Vp-p)
85
85
80
80
SFDR, SNR (dBFS)
SFDR, SNR (dBFS)
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
SFDR
75
70
SNR
65
SFDR
75
70
SNR
65
60
60
0.1
1
0.1
10
1
10
Frequency (MHz)
Frequency (MHz)
DIFFERENTIAL LINEARITY vs TEMPERATURE
SPURIOUS-FREE DYNAMIC RANGE
vs TEMPERATURE
0.40
84
fIN = 4.8MHz
SFDR (dBFS)
DLE (LSB)
82
0.35
fIN = 500kHz
0.30
fIN = 500kHz
80
fIN = 4.8MHz
78
0.25
–50
–25
0
25
50
75
76
100
–50
–25
0
25
50
75
Temperature (°C)
Temperature (°C)
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
100
70
72
fIN = 500kHz
SINAD (dBFS)
SNR (dBFS)
70
68
fIN = 4.8MHz
69
fIN = 500kHz
68
66
fIN = 4.8MHz
67
64
–50
–25
0
25
50
75
–50
100
6
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
ADS804
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SBAS068B
TYPICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 10MHz, unless otherwise specified.
POWER DISSIPATION vs TEMPERATURE
OUTPUT NOISE HISTOGRAM (DC INPUT)
185
800
Counts (k)
Power (mW)
600
180
400
175
200
170
–50
–25
0
25
50
75
0
N–2
100
N–1
N
N+1
N+2
Code
Temperature (°C)
OUTPUT NOISE HISTOGRAM
(DC Input, VIN = 5Vp-p Range)
800
Counts (k)
600
400
200
0
N–2
N–1
N
N+1
N+2
Code
ADS804
SBAS068B
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7
APPLICATION INFORMATION
configurations. This will decouple the op amp’s output from
the capacitive load and avoid gain peaking, which can result
in increased noise. For best spurious and distortion performance, the resistor value should be kept below 100Ω.
Furthermore, the series resistor together with the 100pF
capacitor establish a passive low-pass filter, limiting the
bandwidth for the wideband noise thus, help improving the
SNR performance.
DRIVING THE ANALOG INPUT
The ADS804 allows its analog inputs to be driven either
single-ended or differentially. The focus of the following
discussion is on the single-ended configuration. Typically, its
implementation is easier to achieve, and the rated specifications for the ADS804 are characterized using the singleended mode of operation.
DC-COUPLED WITHOUT LEVEL SHIFT
AC-COUPLED INPUT CONFIGURATION
In some applications the analog input signal may already be
biased at a level which complies with the selected input
range and reference level of the ADS804. In this case, it is
only necessary to provide an adequately low source impedance to the selected input, IN or IN. Always consider wideband
op amps since their output impedance will stay low over a
wide range of frequencies. For those applications requiring
the driving amplifier to provide a signal amplification, with a
gain ≥ 3, consider using the decompensated voltage feedback op amp OPA643.
Given in Figure 1 is the circuit example of the most common
interface configuration for the ADS804. With the VREF pin
connected to the SEL pin, the full-scale input range is defined
to be 2Vp-p. This signal is ac-coupled in single-ended form
to the ADS804 using the low distortion voltage- feedback
amplifier OPA642. As is generally necessary for singlesupply components, operating the ADS804 with a full-scale
input signal swing requires a level-shift of the amplifier’s
zero-centered analog signal to comply with the A/D converters input range requirements. Using a DC blocking capacitor
between the output of the driving amplifier and the converter’s
input, a simple level-shifting scheme can be implemented. In
this configuration, the top and bottom references (REFT,
REFB) provide an output voltage of +3V and +2V, respectively. Here, two resistor pairs (2 • 2kΩ) are used to create a
common-mode voltage of approximately +2.5V to bias the
inputs of the ADS804 (IN, IN) to the required DC voltage.
DC-COUPLED WITH LEVEL SHIFT
Several applications may require that the bandwidth of the
signal path include DC, in which case the signal has to be
DC-coupled to the A/D converter. In order to accomplish this,
the interface circuit has to provide a DC-level shift. See the
circuit of Figure 2 which employs an op amp, to sum the
ground-centered input signal with a required DC offset. The
ADS804 typically operates with a +2.5V common-mode voltage, which is established at the center tap of the ladder and
connected to the IN input of the converter. Amplifier A1
operates in inverting configuration. Here resistors R1 and
R2 set the DC-bias level for A1. Because of the op amp’s
noise gain of +2V/V, assuming RF = RIN, the DC offset
voltage applied to its noninverting input has to be divided
down to +1.25V, resulting in a DC output voltage of +2.5V.
An advantage of ac-coupling is that the driving amplifier still
operates with a ground-based signal swing. This will keep
the distortion performance at its optimum since the signal
swing stays within the linear region of the op amp and
sufficient headroom to the supply rails can be maintained.
Consider using the inverting gain configuration to eliminate
CMR induced errors of the amplifier. The addition of a small
series resistor (RS) between the output of the op amp and the
input of the ADS804 will be beneficial in almost all interface
+5V –5V
+VIN
2Vp-p
VIN
0.1µF
RS
24.9Ω
2kΩ
IN
OPA642
0V
–VIN
REFT
(+3V)
2kΩ
100pF
RF
402Ω
ADS804
2kΩ
RG
402Ω
+2.5VDC
IN
0.1µF
2kΩ
(+2V)
REFB
(+1V)
VREF
SEL
FIGURE 1. AC-Coupled Input Configuration for 2Vp-p Input Swing and Common-Mode Voltage at +2.5V Derived from Internal
Top and Bottom Reference.
8
ADS804
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SBAS068B
RF
RIN
+1V
0
+VS
VIN
REFT
2kΩ
RS
24.9Ω
IN
OPA691
–1V
2Vp-p
100pF
R1
ADS804
R2
+VS
+2.5V
+
0.1µF
IN
0.1µF
10µF
REFB
(+1V)
VREF
SEL
2kΩ
NOTE: RF = RIN, G = –1
FIGURE 2. DC-Coupled, Single-Ended Input Configuration with DC-Level Shift.
DC voltage differences between the IN and IN inputs of the
ADS804 effectively will produce an offset, which can be
corrected for by adjusting the values of resistors R1 and R2.
The bias current of the op amp may also result in an
undesired offset. The selection criteria of the appropriate op
amp should include the input bias current, output voltage
swing, distortion, and noise specification. Note that in this
example the overall signal phase is inverted. To re-establish
the original signal polarity it is always possible to interchange
the IN and IN connections.
RG
0.1µF
22Ω
1:n
VIN
IN
100pF
RT
ADS804
22Ω
IN
CM
100pF
SINGLE-ENDED-TO-DIFFERENTIAL
CONFIGURATION (TRANSFORMER COUPLED)
+
In order to select the best suited interface circuit for the
ADS804, the performance requirements must be known. If
an ac-coupled input is needed for a particular application, the
next step is to determine the method of applying the signal;
either single-ended or differentially. The differential input
configuration may provide a noticeable advantage of achieving good SFDR performance based on the fact that in the
differential mode, the signal swing can be reduced to half of
the swing required for single-ended drive. Secondly, by
driving the ADS804 differentially, the even-order harmonics
will be reduced. Figure 3 shows the schematic for the
suggested transformer-coupled interface circuit. The resistor
across the secondary side (RT) should be set to get an input
impedance match (e.g., RT = n2 • RG).
0.1µF
4.7µF
FIGURE 3. Transformer-Coupled Input.
gain for the internal reference buffer. For more design flexibility, the internal reference can be shut off and an external
reference voltage used. Table I provides an overview of the
possible reference options and pin configurations.
MODE
INPUT
FULL-SCALE
RANGE
REQUIRED
VREF
CONNECT
TO
Internal
2Vp-p
+1V
SEL
VREF
REFERENCE OPERATION
Internal
5Vp-p
+2.5V
SEL
GND
Integrated into the ADS804 is a bandgap reference circuit
including logic that provides either a +1V or +2.5V reference
output, by simply selecting the corresponding pin-strap configuration. Different reference voltages can be generated by
the use of two external resistors, which will set a different
Internal
External
1V < VREF < 2.5V
R1
VREF and SEL
VREF = 1 + (R1/R2)
R2
SEL and Gnd
1V < FSR < 5V
0.5V < VREF < 2.5V
SEL
+VS
VREF
Ext. VREF
TABLE I. Selected Reference Configuration Examples.
ADS804
SBAS068B
2V ≤ FSR < 5V
FSR = 2 • VREF
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9
A simple model of the internal reference circuit is shown in
Figure 4. The internal blocks are a 1V-bandgap voltage
reference, buffer, the resistive reference ladder, and the
drivers for the top and bottom reference which supply the
necessary current to the internal nodes. As shown, the
output of the buffer appears at the VREF pin. The full-scale
input span of the ADS804 is determined by the voltage at
VREF, according to equation (1):
Full-Scale Input Span = 2 • VREF
ADS804
REFT
0.1µF
+
0.1µF
0.1µF
10µF
0.1µF
FIGURE 5. Recommended Reference Bypassing Scheme.
The top reference (REFT) and the bottom reference (REFB)
are brought out mainly for external bypassing. For proper
operation with all reference configurations, it is necessary to
provide solid bypassing to the reference pins in order to keep
the clock feedthrough to a minimum. Figure 5 shows the
recommended decoupling network.
In addition, the common-mode voltage (CMV) may be used
as a reference level to provide the appropriate offset for the
driving circuitry. However, care must be taken not to appreciably load this node, which is not buffered and has a high
impedance. An alternate method of generating a commonmode voltage is given in Figure 6. Here, two external precision resistors (tolerance 1% or better) are located between
the top and bottom reference pins. The common-mode level
will appear at the midpoint. The output buffers of the top and
bottom reference are designed to supply approximately 2mA
of output current.
VREF
CM
10µF
+
(1)
Note that the current drive capability of this amplifier is limited
to about 1mA and should not be used to drive low loads. The
programmable reference circuit is controlled by the voltage
applied to the select pin (SEL). Refer to Table I for an
overview.
REFB
0.1µF
IN
REFT
0.1µF
R1
ADS804
CMV
R2
IN
REFB
0.1µF
FIGURE 6. Alternative Circuit to Generate Common-Mode
Voltage.
Disable
Switch
SEL
VREF
1VDC
to A/D
Converter
REFT
Resistor Network
and Switches
800Ω
Bandgap
and Logic
Reference
Driver
CM
800Ω
REFB
to A/D
Converter
ADS804
FIGURE 4. Equivalent Reference Circuit.
10
ADS804
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SBAS068B
EXTERNAL REFERENCE OPERATION
SELECTING THE INPUT RANGE AND
REFERENCE
Figures 7 through 9 show a selection of circuits for the most
common input ranges when using the internal reference of
the ADS804. All examples are for single-ended input and
operate with a nominal common-mode voltage of +2.5V.
5V
VIN
IN
0V
as described for the internal reference operation.
ADS804
IN
VREF
Depending on the application requirements, it might be
advantageous to operate the ADS804 with an external reference. This may improve the DC accuracy if the external
reference circuitry is superior in its drift and accuracy. To use
the ADS804 with an external reference, the user must
disable the internal reference (as shown in Figure 10). By
connecting the SEL pin to +VS, the internal logic will shut
down the internal reference. At the same time, the output of
the internal reference buffer is disconnected from the VREF
pin, which now must be driven with the external reference.
Note that a similar bypassing scheme should be maintained
SEL
4.5V
+2.5V
VIN
IN
0.5V
ADS804
FIGURE 7. Internal Reference with 0V to 5V Input Range.
REF1004
+2.5V
+2.5V ext.
IN
+
0.1µF
10µF
VREF
SEL
1.24kΩ
+2VDC
+5V
3.5V
VIN
IN
4.99kΩ
1.5V
ADS804
+2.5V Ext.
IN
VREF
FIGURE 10. External Reference, Input Range 0.5V to 4.5V
(4Vp-p), with +2.5V Common-Mode Voltage.
SEL
+1V
FIGURE 8. Internal Reference with 1.5V to 3.5V Input Range.
4V
VIN
IN
1V
ADS804
+2.5V Ext.
IN
VREF
SEL
R1
5kΩ
VREF = 1V 1 +
R1
R2
+1.5V
R2
10kΩ
FSR = 2 • VREF
DIGITAL INPUTS AND OUTPUTS
Over-Range (OVR)
One feature of the ADS804 is its ‘Over-Range’ digital output
(OVR). This pin can be used to monitor any out-of-range
condition, which occurs every time the applied analog input
voltage exceeds the input range (set by VREF). The OVR
output is LO when the input voltage is within the defined input
range. It becomes HI when the input voltage is beyond the
input range. This is the case when the input voltage is either
below the bottom reference voltage or above the top reference voltage. OVR will remain active until the analog input
returns to its normal signal range and another conversion is
completed. Using the MSB and its complement in conjunction with OVR a simple clue logic can be built that detects the
over-range and under-range conditions, (see Figure 11). It
should be noted that OVR is a digital output which is updated
along with the bit information corresponding to the particular
sampling incidence of the analog signal. Therefore, the OVR
data is subject to the same pipeline delay (latency) as the
digital data.
FIGURE 9. Internal Reference with 1V to 4V Input Range.
ADS804
SBAS068B
www.ti.com
11
MSB
Over = HI
OVR
Under = HI
provide the added benefit of isolating the ADS804 from any
digital noise activities on the bus coupling back high frequency noise. In addition, resistors in series with each data
line may help maintain the ac performance of the ADS804.
Their use depends on the capacitive loading seen by the
converter. Values in the range of 100Ω to 200Ω will limit the
instantaneous current the output stage has to provide for
recharging the parasitic capacitances, as the output levels
change from LO-to-HI or HI-to-LO.
GROUNDING AND DECOUPLING
FIGURE 11. External Logic for Decoding Under- and Overrange Conditions.
CLOCK INPUT REQUIREMENTS
Clock jitter is critical to the SNR performance of high speed,
high resolution A/D converters. It leads to aperture jitter (tA)
which adds noise to the signal being converted. The ADS804
samples the input signal on the rising edge of the CLK input.
Therefore, this edge should have the lowest possible jitter.
The jitter noise contribution to total SNR is given by the
following equation. If this value is near your system requirements, input clock jitter must be reduced.
1
JitterSNR = 20 log
rms signal to rms noise
2π ƒIN t A
Where: ƒIN is Input Signal Frequency
tA is rms Clock Jitter
Particularly in undersampling applications, special consideration should be given to clock jitter. The clock input should be
treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should have
a 50% duty cycle (tH = tL), along with fast rise and fall times
of 2ns or less.
DIGITAL OUTPUTS
The digital outputs of the ADS804 are designed to be
compatible with both high-speed TTL and CMOS logic families. The driver stage for the digital outputs is supplied
through a separate supply pin, VDRV, which is not connected to the analog supply pins. By adjusting the voltage on
VDRV, the digital output levels will vary respectively. Therefore, it is possible to operate the ADS804 on a +5V analog
supply while interfacing the digital outputs to 3V logic.
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for highfrequency designs. Multi-layer PC boards are recommended
for best performance since they offer distinct advantages like
minimizing ground impedance, separation of signal layers by
ground layers, etc. It is recommended that the analog and
digital ground pins of the ADS804 be joined together at the
IC and be connected only to the analog ground of the
system.
The ADS804 has analog and digital supply pins, however,
the converter should be treated as an analog component and
all supply pins should be powered by the analog supply. This
will ensure the most consistent results, since digital supply
lines often carry high levels of noise that would otherwise be
coupled into the converter and degrade the achievable performance.
Because of the pipeline architecture, the converter also
generates high-frequency current transients and noise that
are fed back into the supply and reference lines. This
requires that the supply and reference pins be sufficiently
bypassed. Figure 12 shows the recommended decoupling
scheme for the analog supplies. In most cases, 0.1µF ceramic chip capacitors are adequate to keep the impedance
low over a wide frequency range. Their effectiveness largely
depends on the proximity to the individual supply pin. Therefore, they should be located as close to the supply pins as
possible. In addition, a larger size bipolar capacitor (1µF to
22µF) should be placed on the PC board in close proximity
to the converter circuit.
ADS804
+VS
27
GND
26
+VS
16
0.1µF
It is recommended to keep the capacitive loading on the data
lines as low as possible (≤ 15pF). Larger capacitive loads
demand higher charging currents as the outputs are changing. Those high current surges can feed back to the analog
portion of the ADS804 and influence the performance. If
necessary, external buffers or latches may be used which
GND
17
0.1µF
VDRV
28
0.1µF
2.2µF
+
+5V
+5V/+3V
FIGURE 12. Recommended Bypassing for Analog Supply
Pins.
12
ADS804
www.ti.com
SBAS068B
PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS804E
ACTIVE
SSOP
DB
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS804E
ADS804E/1K
ACTIVE
SSOP
DB
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS804E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS804E/1K
Package Package Pins
Type Drawing
SSOP
DB
28
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
8.1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.4
2.5
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS804E/1K
SSOP
DB
28
1000
350.0
350.0
43.0
Pack Materials-Page 2
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