Texas Instruments | DAC7616: Quad, Serial Input, 12-Bit, Voltage Output Digital-to-Analog Converter | Datasheet | Texas Instruments DAC7616: Quad, Serial Input, 12-Bit, Voltage Output Digital-to-Analog Converter Datasheet

Texas Instruments DAC7616: Quad, Serial Input, 12-Bit, Voltage Output Digital-to-Analog Converter Datasheet
DAC
DAC7616
761
6
DAC
®
761
6
www.ti.com
Quad, Serial Input, 12-Bit, Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
● LOW POWER: 3mW
● SETTLING TIME: 10µs to 0.012%
●
●
●
●
●
●
● 12-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
● USER SELECTABLE RESET TO MIDSCALE OR ZERO-SCALE
ATE PIN ELECTRONICS
PROCESS CONTROL
CLOSED-LOOP SERVO-CONTROL
MOTOR CONTROL
DATA ACQUISITION SYSTEMS
DAC-PER-PIN PROGRAMMERS
● SECOND-SOURCE for DAC8420
● SO-16 or SSOP-20 PACKAGES
● SINGLE SUPPLY +3V OPERATION
DESCRIPTION
The DAC7616 is a quad, serial input, 12-bit, voltage
output Digital-to-Analog Converter (DAC) with guaranteed 12-bit monotonic performance over the –40°C
to +85°C temperature range. An asynchronous reset
clears all registers to either mid-scale (800H) or zeroscale (000H), selectable via the RESETSEL pin. The
device is powered from a single +3V supply.
for process control, data acquisition systems, and
closed-loop servo-control. The device is available in
SO-16 or SSOP-20 packages, and is guaranteed over
the –40°C to +85°C temperature range.
Low power and small size makes the DAC7616 ideal
VDD
GND
VREFH
DAC
Register A
DAC A
DAC
Register B
DAC B
DAC
Register C
DAC C
DAC
Register D
DAC D
VOUTA
SDI
Serial-toParallel
Shift
Register
CLK
CS
DAC
Select
LDAC
Copyright © 2001, Texas Instruments Incorporated
VOUTB
12
RESET
RESETSEL
SBAS186
VOUTC
VOUTD
VREFL AGND
Printed in U.S.A. February, 2001
SPECIFICATIONS
At TA = –40°C to +85°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, unless otherwise noted.
DAC7616E, U
PARAMETER
ACCURACY
Linearity Error(1)
Linearity Matching(3)
Differential Linearity Error
Monotonicity
Zero-Scale Error
Zero-Scale Drift
Zero-Scale Matching(3)
Full-Scale Error
Full-Scale Matching(3)
Power Supply Rejection
ANALOG OUTPUT
Voltage Output(4)
Output Current
Load Capacitance
Short-Circuit Current
Short-Circuit Duration
CONDITIONS
Output Noise Voltage
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
Data Format
POWER SUPPLY REQUIREMENTS
VDD
IDD
Power Dissipation
TEMPERATURE RANGE
Specified Performance
TYP
DAC7616EB, UB
MAX
MIN
TYP
±2
±2
±1
5
±1
Code = FFFH
±1
30
VREFL
–625
No Oscillation
VREFH
+625
0
0
| IIH | ≤ 10µA
| IIL | ≤ 10µA
±2.4
10
±2
±2.4
±2
✻
✻
✻
✻
✻
✻
+1.25
5
0.1
–40
✻
✻
✻
✻
10
65
✻
CMOS
✻
VDD • 0.7
VDD
–0.3
VDD • 0.3
Straight Binary
3.0
UNITS
±1
±1
±1
LSB(2)
LSB
LSB
Bits
mV
ppm/°C
mV
mV
mV
ppm/V
3.3
0.8
2.4
✻
✻
±1.2
✻
±1.2
✻
✻
V
µA
pF
mA
✻
V
V
✻
µs
LSB
✻
✻
✻
100
+8, –2
Indefinite
To ±0.012%
Full-Scale Step
On Any Other DAC
Bandwidth: 0Hz to 1MHz
MAX
✻
12
Code = 00AH
REFERENCE INPUT
VREFH Input Range
VREFL Input Range
DYNAMIC PERFORMANCE
Settling Time
Channel-to-Channel Crosstalk
MIN
✻
✻
nV/√Hz
✻
✻
V
V
✻
✻
✻
V
mA
mW
✻
°C
✻
3.6
1
3
✻
+85
✻
✻
✻
✻
✻ Specification same as DAC7616E, U.
NOTES: (1) Specification applies at code 00AH and above. (2) LSB means Least Significant Bit, with VREFH equal to +1.25V and VREFL equal to 0V, one LSB
is 0.305mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage does not take into account zero or full-scale error.
2
DAC7616
SBAS186
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
VDD to GND ........................................................................ –0.3V to +5.5V
VREFL to GND ........................................................... –0.3V to (VDD + 0.3V)
VDD to VREFH .......................................................................... –0.3V to VDD
VREFH to VREFL ........................................................................ –0.3V to VDD
Digital Input Voltage to GND ...................................... –0.3V to VDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
MAXIMUM
LINEARITY
ERROR
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
DAC7616U
PACKAGE
PACKAGE
DRAWING
NUMBER
SPECIFICATION
TEMPERATURE
RANGE
±2
±1
SO-16
211
–40°C to +85°C
"
"
"
"
"
"
DAC7616UB
±1
±1
SO-16
211
–40°C to +85°C
"
"
"
"
"
"
±2
±1
SSOP-20
334
–40°C to +85°C
"
"
"
"
"
"
DAC7616EB
±1
±1
SSOP-20
334
–40°C to +85°C
"
"
"
"
"
"
DAC7616E
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
DAC7616U
DAC7616U/1K
DAC7616UB
DAC7616UB/1K
Rails
Tape and Reel
Rails
Tape and Reel
DAC7616E
DAC7616E/1K
DAC7616EB
DAC7616EB/1K
Rails
Tape and Reel
Rails
Tape and Reel
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC7616EB/1K” will get a single 1000-piece Tape and Reel.
DAC7616
SBAS186
3
PIN CONFIGURATION—U Package
PIN CONFIGURATION—E Package
Top View
SO
VDD
1
16
RESETSEL
VOUTD
2
15
VOUTC
3
VREFL
4
DAC7616U
1
20
RESETSEL
RESET
VOUTD
2
19
RESET
14
LDAC
VOUTC
3
18
LDAC
13
NIC
VREFL
4
17
NIC
12
CS
NIC
5
16
NIC
VREFH
5
VOUTB
6
11
CLK
NIC
6
15
NIC
VOUTA
7
10
SDI
VREFH
7
14
CS
AGND
8
9
GND
VOUTB
8
13
CLK
VOUTA
9
12
SDI
AGND 10
11
GND
DAC7616E
LABEL
PIN DESCRIPTIONS—E Package
DESCRIPTION
PIN
LABEL
DESCRIPTION
1
VDD
Positive Analog Supply Voltage, +3V nominal.
1
VDD
2
VOUTD
DAC D Voltage Output
2
VOUTD
DAC D Voltage Output
3
VOUTC
DAC C Voltage Output
3
VOUTC
DAC C Voltage Output
4
VREFL
Reference Input Voltage Low. Sets minimum
output voltage for all DACs.
4
VREFL
Reference Input Voltage Low. Sets minimum
output voltage for all DACs.
5
VREFH
Reference Input Voltage High. Sets maximum
output voltage for all DACs.
5
NIC
Not Internally Connected.
6
NIC
Not Internally Connected.
7
VREFH
Reference Input Voltage High. Sets maximum
output voltage for all DACs.
Positive Analog Supply Voltage, +3V nominal.
6
VOUTB
DAC B Voltage Output
7
VOUTA
DAC A Voltage Output
8
AGND
Analog Ground
8
VOUTB
DAC B Voltage Output.
9
GND
Ground
9
VOUTA
DAC A Voltage Output.
10
SDI
Serial Data Input
10
AGND
11
CLK
Serial Data Clock
11
GND
Ground
Analog Ground
12
CS
Chip Select Input
12
SDI
Serial Data Input
13
NIC
Not Internally Connected.
13
CLK
Serial Data Clock
14
LDAC
The selected DAC register becomes transparent
when LDAC is LOW. It is in the latched state
when LDAC is HIGH.
14
CS
Chip Select Input
15
NIC
Not Internally Connected.
16
NIC
Not Internally Connected.
17
NIC
Not Internally Connected.
18
LDAC
The selected DAC register becomes transparent
when LDAC is LOW. It is in the latched state
when LDAC is HIGH.
19
RESET
Asynchronous Reset Input. Sets all DAC
registers to either zero-scale (000H) or midscale (800H) when LOW. RESETSEL determines
which code is active.
20
RESETSEL
When LOW, a LOW on RESET will cause all
DAC registers to be set to code 000H. When
RESETSEL is HIGH, a LOW on RESET will set
the registers to code 800H.
15
16
4
SSOP
VDD
PIN DESCRIPTIONS—U Package
PIN
Top View
RESET
RESETSEL
Asynchronous Reset Input. Sets all DAC
registers to either zero-scale (000H) or midscale (800H) when LOW. RESETSEL determines
which code is active.
When LOW, a LOW on RESET will cause all
DAC registers to be set to code 000H. When
RESETSEL is HIGH, a LOW on RESET will set
the registers to code 800H.
DAC7616
SBAS186
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified.
0.50
0.25
0.25
0
–0.25
0.50
0.25
0.25
DLE (LSB)
–0.50
0.50
0
–0.25
200H
400H
600H
800H
A00H
C00H
E00H
0
–0.25
–0.50
000H
FFFH
800H
A00H
C00H
E00H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
0.25
LE (LSB)
0.50
0
–0.25
0
0.50
0.25
0.25
DLE (LSB)
–0.50
0.50
0
–0.25
200H
400H
600H
800H
A00H
C00H
E00H
0
–0.25
–0.50
000H
FFFH
200H
400H
600H
800H
A00H
C00H
E00H
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
0.50
0.50
0.25
0.25
0
–0.25
0
–0.50
0.50
0.50
0.25
0.25
–0.25
200H
400H
600H
800H
A00H
Digital Input Code
C00H
E00H
FFFH
FFFH
–0.25
–0.50
0
FFFH
–0.25
–0.50
SBAS186
600H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, –40°C)
0.25
DAC7616
400H
Digital Input Code
0.50
–0.50
000H
200H
Digital Input Code
LE (LSB)
LE (LSB)
DLE (LSB)
0
–0.25
–0.50
–0.50
000H
LE (LSB)
LE (LSB)
0.50
–0.50
000H
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85°C)
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
0
–0.25
–0.50
000H
200H
400H
600H
800H
A00H
C00H
E00H
FFFH
Digital Input Code
5
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified.
0.50
0.25
0.25
0
–0.25
0.50
0.25
0.25
DLE (LSB)
–0.50
0.50
0
–0.25
200H
400H
600H
800H
A00H
C00H
E00H
0
–0.25
–0.50
000H
FFFH
400H
600H
800H
A00H
C00H
E00H
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, –40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
0.50
0.25
0.25
LE (LSB)
0.50
0
–0.25
0
0.50
0.50
0.25
0.25
DLE (LSB)
–0.50
0
–0.25
200H
400H
600H
800H
A00H
C00H
E00H
0
–0.25
–0.50
000H
FFFH
200H
400H
600H
800H
A00H
C00H
E00H
Digital Input Code
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, –40°C)
0.50
0.50
0.25
0.25
0
–0.25
–0.50
–0.50
0.50
0.50
0.25
0.25
–0.25
200H
400H
600H
800H
A00H
Digital Input Code
C00H
E00H
FFFH
FFFH
0
–0.25
0
FFFH
–0.25
–0.50
–0.50
000H
200H
Digital Input Code
LE (LSB)
LE (LSB)
DLE (LSB)
LE (LSB)
0
–0.25
–0.50
–0.50
000H
DLE (LSB)
LE (LSB)
0.50
–0.50
000H
6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85°C)
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
0
–0.25
–0.50
000H
200H
400H
600H
800H
A00H
C00H
E00H
FFFH
Digital Input Code
DAC7616
SBAS186
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified.
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
2.0
Code
Code(0040
(000HH))
1.5
1.0
DAC D
DAC C
DAC B
0.5
0
DAC A
–0.5
1.5
Positive Full-Scale Error (mV)
Negative Full-Scale Error (mV)
2.0
–1.0
–1.5
Code
Code (0040
(FFFHH))
1.0
0
DAC A
–0.5
DAC B
–1.0
–1.5
–2.0
–2.0
–40 –30 –20 –10
0
10
20
30 40
50
60 70
80
90
–40 –30 –20 –10
0
Temperature (°C)
10
20
30 40
50
60 70
80
90
Temperature (°C)
VREFL CURRENT vs CODE
VREFH CURRENT vs CODE
0.000
0.200
0.050
0.150
VREF Current (mA)
VREF Current (mA)
DAC D
DAC C
0.5
–0.100
–0.150
0.100
0.050
–0.200
000H
200H
400H
600H
800H
A00H
C00H
E00H
FFFH
0.000
000H
200H
400H
Digital Input Code
600H
800H
A00H
C00H
E00H
FFFH
Digital Input Code
SUPPLY CURRENT LIMIT vs INPUT CODE
SUPPLY CURRENT vs DIGITAL INPUT CODE
0.8
10
No Load
0.7
8
Short to VDD
6
0.5
IOUT (mA)
IDD (mA)
0.6
0.4
0.3
4
2
0
0.2
0.1
–2
0.0
000H
–4
000H
200H
400H
600H
800H
A00H
Digital Input Code
DAC7616
SBAS186
C00H
E00H
FFFH
Short to Ground
200H
400H
600H
800H
A00H
C00H
E00H
FFFH
Input Code
7
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified.
POWER SUPPLY CURRENT vs TEMPERATURE
OUTPUT VOLTAGE vs RLOAD
1000
3.0
2.5
800
700
2.0
600
VOUT (V)
Quiescent Current (uA)
900
500
400
1.5
Source
1.0
300
200
0.5
100
Sink
0
–40
–20
0
20
40
60
80
100
0.0
0.01
0.1
1
10
100
Temperature (°C)
RLOAD (kΩ)
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +1.25V)
OUTPUT VOLTAGE vs SETTLING TIME
(+1.25V to 0V)
Large-Signal Output (0.5V/div)
Large-Signal Output (0.5V/div)
Small-Signal Error (1mV/div)
Small-Signal Error (1mV/div)
LDAC (5.0V/div)
Time (2µs/div)
Time (2µs/div)
MID-SCALE GLITCH PERFORMANCE
(CODE 7FFH to 800H)
MID-SCALE GLITCH PERFORMANCE
(CODE 800H to 7FFH)
Glitch Waveform (20mV/div)
LDAC (5.0V/div)
Time (1µs/div)
8
LDAC (5.0V/div)
Glitch Waveform (20mV/div)
LDAC (5.0V/div)
Time (1µs/div)
DAC7616
SBAS186
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified.
WIDEBAND NOISE
(Bandwidth = 10kHz)
OUTPUT NOISE VOLTAGE vs FREQUENCY
120
Code FFFH
Noise (nV/√Hz)
Noise Voltage (20µV/div)
100
80
60
40
20
0
Time (100µs/div)
100
1k
10k
100k
1M
Frequency (Hz)
DAC7616
SBAS186
9
THEORY OF OPERATION
measuring the zero-scale error. If the output amplifier has
a negative offset, the output voltage may not change for the
first few digital input codes (000H, 001H, 002H, etc.) since
the output voltage cannot swing below ground.
The DAC7616 is a quad, serial input, 12-bit, voltage output
DAC. The architecture is a classic R-2R ladder configuration
followed by an operational amplifier that serves as a buffer.
Each DAC has its own R-2R ladder network and output op
amp, but all share the reference voltage inputs. The minimum
voltage output (“zero-scale”) and maximum voltage output
(“full-scale”) are set by external voltage references (VREFL
and VREFH, respectively). The digital input is a 16-bit serial
word that contains the 12-bit DAC code and a 2-bit address
code that selects one of the four DACs (the two remaining
bits are unused). The converter can be powered from a single
+3V supply. Each device offers a reset function which immediately sets all DAC output voltages and internal registers to
either zero-scale (code 000H) or mid-scale (code 800H). The
reset code is selected by the state of the RESETSEL pin
(LOW = 000H, HIGH = 800H). See Figure 1 for the basic
operation of the DAC7616.
The behavior of the output amplifier can be critical in some
applications. Under short-circuit conditions (DAC output
shorted to VDD), the output amplifier can sink more current
than it can source. See the Specifications table for more
details concerning short-circuit current.
REFERENCE INPUTS
The minimum output of each DAC is equal to VREFL
plus a small offset voltage (essentially, the offset of
the output op amp). The maximum output is equal to
VREFH – 1LSB plus a similar offset voltage.
The current into the reference inputs depends on the DAC
output voltages and can vary from a few microamps to
approximately 0.4 milliamp. Bypassing the reference voltage or voltages with a 0.1µF capacitor placed as close as
possible to the DAC7616 package is strongly recommended.
ANALOG OUTPUTS
The output of the DAC7616 can swing to ground. Note that
the settling time of the output op amp will be longer with
voltages very near ground. Also, care must be taken when
+3V
+
DAC7616(1)
1µF to 10µF
0.1µF
0V to +1.25V
0V to +1.25V
1
VDD
2
RESETSEL
16
VOUTD
RESET
15
Reset DACs(2)
3
VOUTC
LDAC
14
Update Selected Register
4
VREFL
NIC
13
5
VREFH
CS
12
Chip Select
6
VOUTB
CLK
11
Clock
7
VOUTA
SDI
10
Serial Data In
8
AGND
GND
9
+1.25V
0.1µF
0V to +1.25V
0V to +1.25V
NOTES: (1) U package pin configuration shown. (2) As configured, RESET LOW sets all internal registers
to code 000H (0V). If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800H (1.25V).
FIGURE 1. Basic Single-Supply Operation of the DAC7616.
10
DAC7616
SBAS186
DIGITAL INTERFACE
The DAC code and address are provided via a 16-bit serial
interface as shown in Figure 2. The first two bits select the
DAC register that will be updated when LDAC goes LOW
(see Table II). The next two bits are not used. The last 12 bits
is the DAC code which is provided, most significant bit first.
Figure 2 and Table I provide the basic timing for the
DAC7616. The interface consists of a serial clock (CLK),
serial data (SDI), and a load DAC signal (LDAC). In
addition, a chip select (CS) input is available to enable serial
communication when there are multiple serial devices. An
asynchronous reset input (RESET) is provided to simplify
start-up conditions, periodic resets, or emergency resets to a
known state.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tDS
Data Valid to CLK Rising
25
ns
tDH
Data Held Valid after CLK Rises
20
ns
tCH
CLK HIGH
30
ns
tCL
CLK LOW
50
ns
tCSS
CS LOW to CLK Rising
55
ns
tCSH
CLK HIGH to CS Rising
15
ns
tLD1
LDAC HIGH to CLK Rising
40
ns
tLD2
CLK Rising to LDAC LOW
15
ns
tLDDW
LDAC LOW Time
45
ns
tRSSH
RESETSEL Valid to RESET LOW
25
tRSTW
RESET LOW Time
Settling Time
tS
Note that CS and CLK are combined with an OR gate,
whose output controls the serial-to-parallel shift register
internal to the DAC7616 (see the block diagram on the front
of this data sheet). These two inputs are completely interchangeable. In addition, care must be taken with the state of
CLK when CS rises at the end of a serial transfer. If CLK is
LOW when CS rises, the OR gate will provide a rising edge
to the shift register, shifting the internal data one additional
bit. The result will be incorrect data and possible selection of
the wrong DAC.
STATE OF
SELECTED
DAC
REGISTER
A1
A0
LDAC
RESET
SELECTED
DAC
REGISTER
L(1)
L
L
H
A
Transparent
L
H
L
H
B
Transparent
ns
H
L
L
H
C
Transparent
70
ns
H
H
L
H
D
Transparent
10
µs
X(2)
X
H
H
NONE
(All Latched)
X
X
X
L
ALL
Reset(3)
TABLE I. Timing Specifications (TA = –40°C to +85°C).
NOTES: (1) L = Logic LOW. (2) X = Don’t Care. (3) Resets to either 000H or
800H, per the RESETSEL state (LOW = 000H, HIGH = 800H). When RESET
rises, all registers that are in their latched state retain the reset value.
TABLE II. Control Logic Truth Table.
(MSB)
SDI
A1
A0
X
X
D11
(LSB)
D10
D9
D3
D2
D1
D0
CLK
tcss
tCSH
tLD1
tLD2
CS
LDAC
tLDDW
tDS
tDH
SDI
tCL
tCH
CLK
tLDDW
LDAC
tS
VOUT
tS
1 LSB
ERROR BAND
1 LSB
ERROR BAND
tRSTW
RESET
tRSSH
RESETSEL
FIGURE 2. DAC7616 Timing.
DAC7616
SBAS186
11
LAYOUT
If both CS and CLK are used, then CS should rise only when
CLK is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table III for more information.
CS(1)
CLK(1)
LDAC
RESET
H(2)
X(3)
H
H
No Change
L(4)
L
H
H
No Change
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies.
As the DAC7616 offers single-supply operation, it will
often be used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the
higher the switching speed, the more difficult it will be to
keep digital noise from appearing at the converter output.
SERIAL SHIFT REGISTER
L
↑(5)
H
H
Advanced One Bit
↑
L
H
H
Advanced One Bit
H(6)
X
L(7)
H
No Change
H(6)
X
H
L(8)
No Change
Because the DAC7616 has a single ground pin, all return
currents, including digital and analog return currents, must
flow through the GND pin. Ideally, GND should be connected directly to an analog ground plane. This plane should
be separate from the ground connection for the digital
components until they were connected at the power entry
point of the system (see Figure 3).
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X =
Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH
value is suggested in order to avoid a “false clock” from advancing the shift
register and changing the shift register. (7) If data is clocked into the serial
register while LDAC is LOW, the selected DAC register will change as the shift
register bits “flow” through A1 and A0. This will corrupt the data in each DAC
register that has been erroneously selected. (8) RESET LOW causes no
change in the contents of the serial shift register.
The power applied to VDD should be well regulated and low
noise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high-frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between the power connections and analog output.
TABLE III. Serial Shift Register Truth Table.
Digital Input Coding
The DAC7616 input data is in Straight Binary format. The
output voltage is given by the following equation:
VOUT = VREFL +
(VREFH – VREFL ) • N
As with the GND connection, VDD should be connected to
a +3V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the
power entry point. In addition, the 1µF to 10µF and 0.1µF
capacitors shown in Figure 4 are strongly recommended. In
some situations, additional bypassing may be required, such
as a 100µF electrolytic capacitor or even a “Pi” filter made
up of inductors and capacitors—all designed to essentially
lowpass filter the +3V supply, removing the high frequency
noise (see Figure 3).
4096
where N is the digital input code (in decimal). This equation
does not include the effects of offset (zero-scale) or gain
(full-scale) errors.
Digital Circuits
+3V
+3V
Power Supply
Ground
+3V
DAC7616
Ground
VDD
100µF +
+
1µF to
10µF
0.1µF
AGND
Optional
Other
Analog
Components
FIGURE 3. Suggested Power and Ground Connections for a DAC7616 Sharing a +3V Supply with a Digital System.
12
DAC7616
SBAS186
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC7616EB
ACTIVE
SSOP
DB
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7616E
B
DAC7616U
LIFEBUY
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7616U
DAC7616UB
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7616U
B
DAC7616UB/1K
ACTIVE
SOIC
DW
16
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7616U
B
DAC7616UBG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7616U
B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2019
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DAC7616UB/1K
Package Package Pins
Type Drawing
SOIC
DW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.7
2.7
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC7616UB/1K
SOIC
DW
16
1000
350.0
350.0
43.0
Pack Materials-Page 2
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