Texas Instruments | 12-Bit High Speed Micro Power Sampling Analog-To-Digital Converter | Datasheet | Texas Instruments 12-Bit High Speed Micro Power Sampling Analog-To-Digital Converter Datasheet

Texas Instruments 12-Bit High Speed Micro Power Sampling Analog-To-Digital Converter Datasheet
ADS7816
®
AD
ADS
781
6
OPSA7816
658
12-Bit High Speed Micro Power Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 200kHz SAMPLING RATE
● MICRO POWER:
1.9mW at 200kHz
150µW at 12.5kHz
● POWER DOWN: 3µA Max
● 8-PIN MINI-DIP, SOIC, AND MSOP
● DIFFERENTIAL INPUT
● SERIAL INTERFACE
The ADS7816 is a 12-bit, 200kHz sampling analogto-digital converter. It features low power operation
with automatic power down, a synchronous serial
interface, and a differential input. The reference voltage can be varied from 100mV to 5V, with a corresponding resolution from 24µV to 1.22mV.
Low power, automatic power down, and small size
make the ADS7816 ideal for battery operated systems
or for systems where a large number of signals must be
acquired simultaneously. It is also ideal for remote
and/or isolated data acquisition. The ADS7816 is
available in an 8-pin plastic mini-DIP, an 8-lead SOIC,
or an 8-lead MSOP package.
APPLICATIONS
● BATTERY OPERATED SYSTEMS
● REMOTE DATA ACQUISITION
● ISOLATED DATA ACQUISITION
Control
SAR
VREF
DOUT
+In
CDAC
Serial
Interface
–In
S/H Amp
Comparator
DCLOCK
CS/SHDN
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
SBAS061
1996 Burr-Brown Corporation
PDS-1355B
Printed in U.S.A., March, 1997
SPECIFICATIONS
At –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
ADS7816
PARAMETER
CONDITIONS
MIN
+In – (–In)
+In
–In
0
–0.2
–0.2
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
Capacitance
Leakage Current
ADS7816B
TYP
MAX
MIN
VREF
VCC +0.2
+0.2
✻
✻
✻
Current Drain
±0.5
±0.5
1kHz
5kHz
1kHz
1kHz
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
VIH
VIL
VOH
VOL
Data Format
POWER SUPPLY REQUIREMENTS
VCC
Specified Performance
Quiescent Current
fSAMPLE = 12.5kHz(2, 3)
fSAMPLE = 12.5kHz(3)
Power Down
CS = VCC, fSAMPLE = 0Hz
TEMPERATURE RANGE
Specified Performance
±0.5
±0.25
5
5
5
38
2.4
0.001
3
–0.3
3.5
✻
✻
✻
✻
✻
✻
✻
400
3
–40
+85
✻
✻
✻
✻
✻
✻
V
GΩ
GΩ
µA
µA
µA
✻
✻
✻
V
V
V
V
✻
✻
✻
✻
✻
✻
✻
✻
✻
Clk Cycles
Clk Cycles
kHz
✻
✻
✻
Bits
Bits
LSB(1)
LSB
LSB
LSB
µVrms
dB
dB
dB
dB
dB
✻
✻
✻
✻
✻
✻
✻
5.25
700
380
30
280
✻
✻
✻
✻
✻
✻
0.4
4.50
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
Straight Binary
±1
±0.75
✻
✻
✻
✻
+VCC +0.3
0.8
V
V
V
pF
µA
✻
✻
100
20
3
✻
✻
✻
✻
✻
✻
CMOS
IIH = +5µA
IIL = +5µA
IOH = –250µA
IOL = 250µA
±2
±1
✻
✻
✻
✻
✻
✻
0.1
CS = GND, fSAMPLE = 0Hz
CS = VCC
At Code 710h
fSAMPLE = 12.5kHz
CS = VCC
UNITS
✻
✻
–84
–82
72
86
MAX
✻
✻
✻
200
at
at
at
at
TYP
✻
12
5.0Vp-p
5.0Vp-p
5.0Vp-p
5.0Vp-p
✻
✻
✻
✻
✻
1.5
SINAD
Spurious Free Dynamic Range
REFERENCE INPUT
Voltage Range
Resistance
±2
±2
±4
±4
33
82
VIN =
VIN =
VIN =
VIN =
✻
✻
✻
12
±0.5
±0.5
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
MIN
✻
12
11
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
ADS7816C
MAX
✻
✻
25
±1
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Noise
Power Supply Rejection
TYP
✻
✻
✻
✻
✻
V
µA
µA
µA
µA
✻
°C
✻ Specifications same as grade to the left.
NOTE: (1) LSB means Least Significant Bit, with VREF equal to +5V, one LSB is 1.22mV. (2) fCLK = 3.2MHz, CS = VCC for 251 clock cycles out of every 256. (3) See
the Power Dissipation section for more information regarding lower sample rates.
®
ADS7816
2
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
+VCC ..................................................................................................... +6V
Analog Input ........................................................... –0.3V to (+VCC + 0.3V)
Logic Input ............................................................. –0.3V to (+VCC + 0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +125°C
External Reference Voltage .............................................................. +5.5V
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
NOTE: (1) Stresses above these ratings may permanently damage the device.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
PIN CONFIGURATION
VREF
1
+In
2
–In
3
GND
4
8
+VCC
7
DCLOCK
6
DOUT
5
CS/SHDN
ADS7816
8-Pin PDIP,
8-Lead SOIC,
8-Lead MSOP
PIN ASSIGNMENTS
PIN
NAME
1
VREF
2
+In
Non Inverting Input.
3
–In
Inverting Input. Connect to ground or to remote ground sense point.
4
GND
5
CS/SHDN
6
DOUT
7
DCLOCK
8
+VCC
DESCRIPTION
Reference Input.
Ground.
Chip Select when LOW, Shutdown Mode when HIGH.
The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The
second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.
Data Clock synchronizes the serial data transfer and determines conversion speed.
Power Supply.
PACKAGE/ORDERING INFORMATION
PRODUCT
ADS7816P
ADS7816U
ADS7816E
ADS7816PB
ADS7816UB
ADS7816EB
ADS7816PC
ADS7816UC
ADS7816EC
MAXIMUM
INTEGRAL
LINEARITY ERROR
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY ERROR
(LSB)
TEMPERATURE
RANGE
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
±2
±2
±2
±2
±2
±2
±1
±1
±1
±2
±2
±2
±1
±1
±1
±0.75
±0.75
±0.75
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Plastic DIP
SOIC
MSOP
Plastic DIP
SOIC
MSOP
Plastic DIP
SOIC
MSOP
006
182
337
006
182
337
006
182
337
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3
ADS7816
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.
CHANGE IN OFFSET vs TEMPERATURE
CHANGE IN OFFSET vs REFERENCE VOLTAGE
0.6
5
0.4
4
Delta from 25°C (LSB)
Change in Offset (LSB)
4.5
3.5
3
2.5
2
1.5
1
0.2
0
–0.2
–0.4
0.5
–0.6
0
1
2
3
Reference Voltage (V)
4
–55
5
CHANGE IN GAIN vs REFERENCE VOLTAGE
70
85
0.15
3.5
0.1
Delta from 25°C (LSB)
Change in Gain (LSB)
–25
0
25
Temperature (°C)
CHANGE IN GAIN vs TEMPERATURE
4
3
2.5
2
1.5
1
0.05
0
–0.05
–0.1
0.5
–0.15
0
1
2
3
Reference Voltage (V)
4
–55
5
–40
–25
0
25
70
85
Temperature (°C)
EFFECTIVE NUMBER OF BITS
vs REFERENCE VOLTAGE
PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE
12
10
11.75
9
Peak-to-Peak Noise (LSB)
Effective Number of Bits (rms)
–40
11.5
11.25
11
10.75
10.5
10.25
8
7
6
5
4
3
2
1
10
0
0.1
1
Reference Voltage (V)
10
0.1
®
ADS7816
4
1
Reference Voltage (V)
10
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.
FREQUENCY SPECTRUM
(2048 Point FFT; fIN = 9.9kHz, –0.5dB)
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
0
0
–10
–20
–20
–30
Amplitude (dB)
Power Supply Rejection (dB)
–10
–40
–50
–60
–30
–40
–50
–60
–70
–80
–90
–70
–100
–80
–110
–120
–90
1
10
100
1000
10000
0
25
Ripple Frequency (kHz)
SPURIOUS FREE DYNAMIC RANGE and
SIGNAL-TO-NOISE RATIO vs FREQUENCY
100
0
Spurious Free Dynamic Range
90
80
70
60
–10
Total Harmonic Distortion (dB)
Spurious Free Dynamic Range
and Signal-to-Noise Ratio (dB)
75
TOTAL HARMONIC DISTORTION vs FREQUENCY
100
Signal-to-Noise Ratio
50
40
30
20
–20
–30
–40
–50
–60
–70
–80
10
–90
0
–100
1
10
Frequency (kHz)
100
1
90
80
70
60
50
40
30
20
10
0
1
10
Frequency (kHz)
10
Frequency (kHz)
100
SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL
Signal-to-(Noise Ratio Plus Distortion) (dB)
SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY
100
Signal-to-(Noise + Distortion) (dB)
50
Frequency (kHz)
100
80
70
60
50
40
30
20
10
0
–40
–35
–30
–25
–20
–15
Input Level (dB)
–10
–5
0
®
5
ADS7816
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.
DIFFERENTIAL LINEARITY ERROR vs CODE
1.00
0.75
0.75
Differential Linearity Error (LSB)
Integral Linearity Error (LSB)
INTEGRAL LINEARITY ERROR vs CODE
1.00
0.50
0.25
0.00
–0.25
–0.50
–0.75
0.50
0.25
0.00
–0.25
–0.50
–0.75
–1.00
–1.00
0
2048
Code
0
4095
CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL
LINEARITY vs REFERENCE VOLTAGE
4095
INPUT LEAKAGE CURRENT vs TEMPERATURE
0.10
10
0.05
Leakage Current (nA)
Delta from +5V Reference (LSB)
2048
Code
Change in Differential
Linearity (LSB)
0.00
–0.05
–0.10
Change in Integral
Linearity (LSB)
–0.15
–0.20
1
0.1
0.01
1
2
3
Reference Voltage (V)
4
5
–55
–25
0
25
70
85
70
85
Temperature (°C)
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
3
450
400
2.5
fSAMPLE = 200kHz
Supply Current (µA)
Supply Current (µA)
–40
350
300
fSAMPLE = 12.5kHz
250
2
1.5
1
0.5
200
0
150
–55
–40
–25
0
25
70
–55
85
®
ADS7816
–40
–25
0
25
Temperature (°C)
Temperature (°C)
6
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.
REFERENCE CURRENT vs SAMPLE RATE
(Code = 710h)
REFERENCE CURRENT vs TEMPERATURE
(Code = 710h)
40
55
Reference Current (µA)
50
30
25
20
15
10
45
40
35
30
5
25
0
0
40
80
120
160
–55
200
–40
–25
0
25
70
85
Temperature (°C)
Sample Rate (kHz)
CHANGE IN INTEGRAL LINEARITY and DIFFERENTIAL
LINEARITY vs SAMPLE RATE
1.5
Delta from fSAMPLE = 200kHz (LSB)
Reference Current (µA)
35
Change in Integral
Linearity (LSB)
1.0
0.5
0
Change in Differential
Linearity (LSB)
–0.5
0
100
200
300
400
500
Sample Rate (kHz)
®
7
ADS7816
THEORY OF OPERATION
to a 12-bit settling level within 1.5 clock cycles. When the
converter goes into the hold mode or while it is in the power
down mode, the input impedance is greater than 1GΩ.
The ADS7816 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a 0.6µ
CMOS process. The architecture and process allow the
ADS7816 to acquire and convert an analog signal at up to
200,000 conversions per second while consuming very little
power.
Care must be taken regarding the absolute analog input
voltage. To maintain the linearity of the converter, the –In
input should not exceed GND ±200mV. The +In input
should always remain within the range of GND –200mV to
VCC +200mV. Outside of these ranges, the converter’s linearity may not meet specifications.
The ADS7816 requires an external reference, an external
clock, and a single +5V power source. The external reference can be any voltage between 100mV and VCC. The value
of the reference voltage directly sets the range of the analog
input. The reference input current depends on the conversion
rate of the ADS7816.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS7816 will operate with a reference in the range of 100mV
to VCC. There are several important implications of this.
As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the LSB (least significant bit) size and is equal
to the reference voltage divided by 4096. This means that
any offset or gain error inherent in the A/D converter will
appear to increase, in terms of LSB size, as the reference
voltage is reduced. The typical performance curves of
“Change in Offset vs Reference Voltage” and “Change in
Gain vs Reference Voltage” provide more information.
The external clock can vary between 10kHz (625Hz throughput) and 3.2MHz (200kHz throughput). The duty cycle of
the clock is essentially unimportant as long as the minimum
high and low times are at least 150ns. The minimum clock
frequency is set by the leakage on the capacitors internal to
the ADS7816.
The analog input is provided to two input pins: +In and –In.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from
any internal function.
The noise inherent in the converter will also appear to
increase with lower LSB size. With a 5V reference, the
internal noise of the converter typically contributes only
0.16 LSB peak-to-peak of potential error to the output code.
When the external reference is 100mV, the potential error
contribution from the internal noise will be 50 times larger—
8 LSBs. The errors due to the internal noise are gaussian in
nature and can be reduced by averaging consecutive conversion results.
The digital result of the conversion is clocked out by the
DCLOCK input and is provided serially, most significant bit
first, on the DOUT pin. The digital data that is provided on the
DOUT pin is for the conversion currently in progress—there
is no pipeline delay. It is possible to continue to clock the
ADS7816 after the conversion is complete and to obtain the
serial data least significant bit first. See the Digital Interface
section for more information.
For more information regarding noise, consult the typical
performance curves “Effective Number of Bits vs Reference
Voltage” and “Peak-to-Peak Noise vs Reference Voltage.”
The effective number of bits (ENOB) figure is calculated
based on the converter’s signal-to-(noise + distortion) ratio
with a 1kHz, 0dB input signal. SINAD is related to ENOB
as follows: SINAD = 6.02 • ENOB +1.76.
ANALOG INPUT
The +In and –In input pins allow for a differential input signal.
Unlike some converters of this type, the –In input is not resampled later in the conversion cycle. When the converter
goes into the hold mode, the voltage difference between +In
and –In is captured on the internal capacitor array.
With lower reference voltages, extra care should be taken to
provide a clean layout including adequate bypassing, a clean
power supply, a low-noise reference, and a low-noise input
signal. Because the LSB size is lower, the converter will also
be more sensitive to external sources of error such as nearby
digital signals and electromagnetic interference.
The range of the –In input is limited to ±200mV. Because of
this, the differential input can be used to reject only small
signals that are common to both inputs. Thus, the –In input
is best used to sense a remote signal ground that may move
slightly with respect to the local ground potential.
The current that must be provided by the external reference
will depend on the conversion result. The current is lowest
at full-scale (FFFh) and is typically 25µA at a 200kHz
conversion rate (25°C). For the same conditions, the current
will increase as the input approaches zero, reaching 50µA at
an output result of 000h. The current does not increase
linearly, but depends, to some degree, on the bit pattern of
the digital output.
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, source impedance, and
power down mode. Essentially, the current into the ADS7816
charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is
no further input current. The source of the analog input
voltage must be able to charge the input capacitance (25pF)
®
ADS7816
8
The reference current diminishes directly with both conversion rate and reference voltage. As the current from the
reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will
not reduce the overall current drain from the reference. The
reference current changes only slightly with temperature.
See the curves, “Reference Current vs Sample Rate” and
“Reference Current vs Temperature” in the Typical Performance Curves section for more information.
value for one clock period. For the next 12 DCLOCK
periods, DOUT will output the conversion result, most significant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in
a least significant bit first format.
After the most significant bit (B11) has been repeated, DOUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
DIGITAL INTERFACE
SYMBOL
DESCRIPTION
MIN
1.5
TYP
MAX
UNITS
2.0
Clk Cycles
SERIAL INTERFACE
tSMPL
Analog Input Sample TIme
The ADS7816 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface as
shown in Figure 1 and Table I. The DCLOCK signal
synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems
will capture the bitstream on the rising edge of DCLOCK.
However, if the minimum hold time for DOUT is acceptable,
the system can use the falling edge of DCLOCK to capture
each bit.
tCONV
Conversion Time
tCYC
Throughput Rate
200
kHz
tCSD
CS Falling to
DCLOCK LOW
0
ns
tSUCS
CS Falling to
DCLOCK Rising
30
ns
thDO
DCLOCK Falling to
Current DOUT Not Valid
15
ns
tdDO
DCLOCK Falling to Next
DOUT Valid
85
tdis
CS Rising to DOUT Tri-State
ten
DCLOCK Falling to DOUT
Enabled
A falling CS signal initiates the conversion and data transfer.
The first 1.5 to 2.0 clock periods of the conversion cycle are
used to sample the input signal. After the second falling
DCLOCK edge, DOUT is enabled and will output a LOW
12
Clk Cycles
150
ns
25
50
ns
50
100
ns
tf
DOUT Fall Time
70
100
ns
tr
DOUT Rise Time
60
100
ns
TABLE I. Timing Specifications –40°C to +85°C.
tCYC
CS/SHDN
POWER
DOWN
tSUCS
DCLOCK
tCSD
DOUT
HI-Z
NULL
BIT
B11 B10 B9
(MSB)
tSMPL
NULL
BIT
HI-Z
B8
B7
B6
B5
B4
B3
B2
B1 B0(1)
tCONV
B11 B10
B9
B8
tDATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.
tCYC
CS/SHDN
tSUCS
POWER DOWN
DCLOCK
tCSD
DOUT
HI-Z
tSMPL
NULL
BIT
B11 B10 B9
(MSB)
HI-Z
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9 B10 B11
(2)
tCONV
tDATA
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output zeroes indefinitely.
tDATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
FIGURE 1. ADS7816 Basic Timing Diagrams.
®
9
ADS7816
1.4V
3kΩ
VOH
DOUT
DOUT
VOL
Test Point
tr
100pF
CLOAD
tf
Voltage Waveforms for DOUT Rise and Fall TImes tr, and tf
Load Circuit for tdDO, tr, and tf
Test Point
DCLOCK
VIL
VCC
tdDO
DOUT
VOH
DOUT
tdis Waveform 2, ten
3kΩ
tdis Waveform 1
100pF
CLOAD
VOL
thDO
Load Circuit for tdis and tden
Voltage Waveforms for DOUT Delay Times, tdDO
VIH
CS/SHDN
DOUT
Waveform 1(1)
CS/SHDN
90%
DCLOCK
10%
DOUT
1
2
tdis
DOUT
Waveform 2(2)
VOL
B11
ten
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal conditions such that
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.
Voltage Waveforms for ten
FIGURE 2. Timing Diagrams and Test Circuits for the Parameters in Table I.
POWER DISSIPATION
DATA FORMAT
The output data from the ADS7816 is in Straight Binary
format as shown in Table II. This table represents the ideal
output code for the given input voltage and does not include
the effects of offset, gain error, or noise.
DESCRIPTION
The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS7816 to
convert at up to a 200kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
The power dissipation of the ADS7816 scales directly with
conversion rate. The first step to achieving the lowest power
dissipation is to find the lowest conversion rate that will
satisfy the requirements of the system.
ANALOG VALUE
Full Scale Range
VREF
Least Significant
Bit (LSB)
VREF/4096
BINARY CODE
VREF –1 LSB
Full Scale
Midscale
Midscale – 1 LSB
Zero
DIGITAL OUTPUT:
STRAIGHT BINARY
HEX CODE
1111 1111 1111
In addition, the ADS7816 is in power down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 1). Ideally, each conversion should
occur as quickly as possible, preferably, at a 3.2MHz clock
rate. This way, the converter spends the longest possible
time in the power down mode. This is very important as the
FFF
VREF/2
1000 0000 0000
800
VREF/2 – 1 LSB
0111 1111 1111
7FF
0V
0000 0000 0000
000
Table II. Ideal Input Voltages and Output Codes.
®
ADS7816
10
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously, until
the power down mode is entered.
Supply Current (µA)
1000
Figure 3 shows the current consumption of the ADS7816
versus sample rate. For this graph, the converter is clocked
at 3.2MHz regardless of the sample rate—CS is HIGH for
the remaining sample period. Figure 4 also shows current
consumption versus sample rate. However, in this case, the
DCLOCK period is 1/16th of the sample period—CS is
HIGH for one DCLOCK cycle out of every 16.
100
10
TA = 25°C
VCC = VREF = +5V
fCLK = 3.2MHz
1
1
There is an important distinction between the power down
mode that is entered after a conversion is complete and the
full power down mode which is enabled when CS is HIGH.
While both power down the analog section, the digital section
is powered down only when CS is HIGH. Thus, if CS is left
LOW at the end of a conversion and the converter is continually clocked, the power consumption will not be as low as
when CS is HIGH. See Figure 5 for more information.
10
100
1000
Sample Rate (kHz)
FIGURE 3. Maintaining fCLK at the Highest Possible Rate
Allows Supply Current to Drop Directly with
Sample Rate.
1000
Supply Current (µA)
By lowering the reference voltage, the ADS7816 requires
less current to completely charge its internal capacitors on
both the analog input and the reference input. This reduction
in power dissipation should be weighed carefully against the
resulting increase in noise, offset, and gain error as outlined
in the Reference section. The power dissipation of the
ADS7816 is reduced roughly 10% when the reference voltage and input range are changed from 5V to 100mV.
100
10
TA = 25°C
VCC = VREF = +5V
fCLK = 16 • fSAMPLE
SHORT CYCLING
1
Another way of saving power is to utilize the CS signal to
short cycle the conversion. Because the ADS7816 places the
latest data bit on the DOUT line as it is generated, the
converter can easily be short cycled. This term means that
the conversion can be terminated at any time. For example,
if only 8-bits of the conversion result are needed, then the
conversion can be terminated (by pulling CS HIGH) after
the 8th bit has been clocked out.
1
10
100
1000
Sample Rate (kHz)
FIGURE 4. Scaling fCLK Reduces Supply Current Only
Slightly with Sample Rate.
60
This technique can be used to lower the power dissipation
(or to increase the conversion rate) in those applications
where an analog signal is being monitored until some condition becomes true. For example, if the signal is outside a
predetermined range, the full 12-bit conversion result may
not be needed. If so, the conversion can be terminated after
the first n-bits, where n might be as low as 3 or 4. This
results in lower power dissipation in both the converter and
the rest of the system, as they spend more time in the power
down mode.
TA = 25°C
VCC = VREF = +5V
fCLK = 16 • fSAMPLE
Supply Current (µA)
50
CS LOW
(GND)
40
30
20
10
CS = HIGH (VCC)
0
1
LAYOUT
10
100
1000
Sample Rate (kHz)
For optimum performance, care should be taken with the
physical layout of the ADS7816 circuitry. This is particularly
true if the reference voltage is low and/or the conversion rate
is high. At 200kHz conversion rate, the ADS7816 makes a bit
decision every 312ns. That is, for each subsequent bit deci-
FIGURE 5. Shutdown Current is Considerably Lower with
CS HIGH than when CS is LOW.
®
11
ADS7816
sion, the digital output must be updated with the results of the
last bit decision, the capacitor array appropriately switched
and charged, and the input to the comparator settled to a
12-bit level all within one clock cycle.
described in the previous paragraph, voltage variation due to
the line frequency (50Hz or 60Hz), can be difficult to
remove.
The GND pin on the ADS7816 should be placed on a clean
ground point. In many cases, this will be the “analog”
ground. Avoid connecting the GND pin too close to the
grounding point for a microprocessor, microcontroller, or
digital signal processor. If needed, run a ground trace directly from the converter to the power supply connection
point. The ideal layout will include an analog ground plane
for the converter and associated analog circuitry.
The basic SAR architecture is sensitive to spikes on the
power supply, reference, and ground connections that occur
just prior to latching the comparator output. Thus, during
any single conversion for an n-bit SAR converter, there are
n “windows” in which large external transient voltages can
easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high
power devices, to name a few. This particular source of error
can be very difficult to track down if the glitch is almost
synchronous to the converter’s DCLOCK signal—as the
phase difference between the two changes with time and
temperature, causing sporadic misoperation.
The –In input pin should be connected directly to ground. In
those cases where the ADS7816 is a large distance from the
signal source and/or the circuit environment contains large
EMI or RFI sources, the –In input should be connected to the
ground nearest the signal source. This should be done with
a signal trace that is adjacent to the +In input trace. If
appropriate, coax cable or twisted-pair wire can be used.
With this in mind, power to the ADS7816 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the ADS7816 package as possible. In
addition, a 1 to 10µF capacitor and a 10Ω series resistor may
be used to lowpass filter a noisy supply.
APPLICATION CIRCUITS
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to lowpass filter the reference voltage. If the reference
voltage originates from an op amp, be careful that the opamp can drive the bypass capacitor without oscillation (the
series resistor can help in this case). Keep in mind that while
the ADS7816 draws very little current from the reference on
average, there are higher instantaneous current demands
placed on the external reference circuitry.
Figures 6, 7, and 8 show some typical application circuits for
the ADS7816. Figure 6 uses an ADS7816 and a multiplexer
to provide for a flexible data acquisition circuit. A resistor
string provides for various voltages at the multiplexer input.
The selected voltage is buffered and driven into VREF. As
shown in Figure 6, the input range of the ADS7816 is
programmable to 100mV, 200mV, 300mV, or 400mV. The
100mV range would be useful for sensors such as the
thermocouple shown.
Also, keep in mind that the ADS7816 offers no inherent
rejection of noise or voltage variation in regards to the
reference input. This is of particular concern when the
reference input is tied to the power supply. Any noise and
ripple from the supply will appear directly in the digital
results. While high frequency noise can be filtered out as
Figure 7 is more complex variation of Figure 6 with increased flexibility. In this circuit, a digital signal processor
designed for audio applications is put to use in running three
ADS7816s and a DAC56. The DAC56 provides a variable
voltage for VREF —enabling the input range of the ADS7816s
to be programmed from 100mV to 3V.
+5V
+5V
+5V
R8
46kΩ
D1
R1
150kΩ
TC1
R9
1kΩ
OPA237
C2
0.1µF
R3
500kΩ
R2
59kΩ
0.4V
R7
10Ω
R6
1MΩ
C1
10µF
VREF
MUX
0.2V
ADS7816
DOUT
A0
CS/SHDN
A1
Thermocouple
TC3
ISO Thermal Block
R4
1kΩ
C4
10µF
U1
R5
500Ω
U3
C5
0.1µF
µP
3-Wire
Interface
U4
FIGURE 6. Thermocouple Application Using a MUX to Scale the Input Range of the ADS7816.
®
ADS7816
R10
1kΩ
DCLOCK
C3
0.1µF
TC2
0.3V
U2
12
R11
1kΩ
0.1V
R12
1kΩ
DSP56004
ADS7816
+
VREF
10µF
0.1µF
WST
CS
SDO0
+In
DOUT
SDO1
–In
DCLOCK
SDO2
SCKT
ADS7816
+
CS
SDI0
+In
DOUT
SDI1
–In
DCLOCK
WSR
VREF
10µF
0.1µF
SCKR
ADS7816
+
10µF
0.1µF
SCK/SCL
CS
MISO/SDA
+In
DOUT
MOSI/HA0
–In
DCLOCK
VREF
Serial Audio
Interface
Serial Host
Interface
HREQ
SS/HA2
10Ω
10Ω
10Ω
DAC56
VOUT
LE
CLK
DATA
FIGURE 7. Flexible Data Acquisition System.
+5V
5Ω to 10Ω
+ 1µF to
10µF
ADS7816
VREF
VCC
0.1µF
+In
CS
–In
DOUT
GND
+ 1µF to
10µF
Microcontroller
DCLOCK
FIGURE 8. Basic Data Acquisition System.
The ADS7816s and the DSP56004 can all be placed into a
power down mode. Or, the DSP56004 can run the ADS7816s
at a full 3.2MHz clock rate while on-board software enables
the ADS7816s as needed. With additional glue logic, the
DSP56004 could be used to run multiple DAC56s or provide
CS controls for each of the three ADS7816s.
Figure 8 shows a basic data acquisition system. The ADS7816
input range is 0V to 5V, as the reference input is connected
directly to the +5V supply. The 5Ω to 10Ω resistor and 1µF
to 10µF capacitor filter the microcontroller “noise” on the
supply, as well as any high-frequency noise from the supply
itself. The exact values should be picked such that the filter
provides adequate rejection of the noise.
®
13
ADS7816
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS7816E/250
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
A16
ADS7816E/250G4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
A16
ADS7816E/2K5
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
A16
ADS7816E/2K5G4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
A16
ADS7816EB/250
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
A16
ADS7816EB/2K5
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
A16
ADS7816EB/2K5G4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
A16
ADS7816EC/250
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
A16
ADS7816EC/2K5
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
A16
ADS7816U
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7816U
ADS7816U/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7816U
ADS7816U/2K5G4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7816U
ADS7816UB
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7816U
B
ADS7816UB/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7816U
B
ADS7816UBG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7816U
B
ADS7816UC
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7816U
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
C
ADS7816UC/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7816U
C
ADS7816UC/2K5G4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7816U
C
ADS7816UG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
7816U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS7816E/250
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS7816E/2K5
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS7816EB/250
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS7816EB/2K5
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS7816EC/250
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS7816EC/2K5
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS7816U/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ADS7816UB/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ADS7816UC/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7816E/250
VSSOP
DGK
8
250
210.0
185.0
35.0
ADS7816E/2K5
VSSOP
DGK
8
2500
350.0
350.0
43.0
ADS7816EB/250
VSSOP
DGK
8
250
210.0
185.0
35.0
ADS7816EB/2K5
VSSOP
DGK
8
2500
350.0
350.0
43.0
ADS7816EC/250
VSSOP
DGK
8
250
210.0
185.0
35.0
ADS7816EC/2K5
VSSOP
DGK
8
2500
350.0
350.0
43.0
ADS7816U/2K5
SOIC
D
8
2500
367.0
367.0
35.0
ADS7816UB/2K5
SOIC
D
8
2500
367.0
367.0
35.0
ADS7816UC/2K5
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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