Texas Instruments | 20-Bit Analog-to-Digital Converter | Datasheet | Texas Instruments 20-Bit Analog-to-Digital Converter Datasheet

Texas Instruments 20-Bit Analog-to-Digital Converter Datasheet
®
DDC101
101
DDC
20-BIT ANALOG-TO-DIGITAL CONVERTER
FEATURES
APPLICATIONS
● MONOLITHIC CHARGE INPUT ADC
● DIRECT PHOTOSENSOR DIGITIZATION
● DIGITAL FILTER NOISE REDUCTION:
0.9ppm, rms
● PRECISION INSTRUMENTATION
● INFRARED PYROMETRY
● DIGITAL ERROR CORRECTION: CDS
● PRECISION PROCESS CONTROL
● CT SCANNER DAS
● CHEMICAL ANALYZERS
● CONVERSION RATE: Up to 15kHz
● USER FRIENDLY EVALUATION FIXTURE
DESCRIPTION
The DDC101 is a precision, wide dynamic range, charge
digitizing A/D converter with 20-bit resolution. Low
level current output devices, such as photosensors, can be
directly connected to its input. The most stringent accuracy requirements of many unipolar output sensor applications occur at low signal levels. To meet this requirement, Burr-Brown developed the adaptive delta modulation architecture of the DDC101 to provide linearly
improving noise and linearity errors as the input signal
level decreases. The DDC101 combines the functions of
current-to-voltage conversion, integration, input programmable gain amplification, A/D conversion, and digital
filtering to produce precision, wide dynamic range results. The input signal can be a low level current connected directly into the unit or a voltage connected
through a user selected resistor. Although the DDC101 is
optimized for unipolar signals, it can also accurately
digitize bipolar input signals. The patented delta modula-
tion topology combines charge integration and digitization functions. Oversampling and digital filtering reduce
system noise dramatically. Correlated Double Sampling
(CDS) captures and eliminates steady state and conversion cycle dependent offset and switching errors that are
not eliminated with conventional analog circuits.
The DDC101 block diagram is shown below. During
conversion, the input signal is collected on the internal
integration capacitance for a user determined integration
period. A high precision, autozeroed comparator samples
the analog input node. Tracking logic updates the internal
high resolution D/A converter at a 2MHz rate to maintain
the analog input at virtual ground. A user programmable
digital filter oversamples the tracking logic’s output. The
digital filter passes a low noise, high resolution digital
output to the serial I/O register. The serial outputs of
multiple DDC101 units can be easily connected together
in series or parallel if desired to minimize interconnections.
+VS
Test In
DDC101 Integrated Circuit
Test Current
Reset
CDAC
CINT
18 Bits
DAC
Analog
Input
Digital Integration,
Tracking and
Control Logic
Ground
Comparator
VREF
Digital Filter and
Error Correction
20 Bits
Serial I/O
Register
Serial In
Serial Out
Oversampled
Digital Out
Setup
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
SBAS029
1993 Burr-Brown Corporation
PDS-1211E
Printed in U.S.A. March, 1998
TABLE OF CONTENTS
The second block diagram, Figure 2, shows the DDC101
circuit architecture which implements these functions
monolithically. During each conversion, the input signal
current is collected on the internal integration capacitance,
CINT, as charge for a user determined integration period, TINT.
As the integration capacitor collects input charge, the tracking logic updates the internal high resolution D/A converter
at a 2MHz rate to maintain the analog input node at virtual
ground.
The digital filter oversamples the tracking logic’s output at
the beginning and end of each integration period to produce
two oversampled data points. The DDC101 measures the
charge accumulated in the integration and performs correlated double sampling (CDS) by subtracting these two data
points. CDS eliminates integration cycle dependent errors
such as charge injection, offset voltage, and reset noise since
these errors are measured with the signal at each of the two
data points. The number of oversamples, and thus the frequency response of the digital filter, is user programmable.
The digital filter passes a low noise, high resolution digital
output to the serial I/O register. Since the timing control of
the serial I/O register is independent of the DDC101 conversion process, the outputs of multiple DDC101 units can be
connected together in series or parallel to minimize interconnections.
Section 1 ............. Basic Theory of Operation
2 ............. Specifications
3 ............. Pin Descriptions
4 ............. Timing Diagrams
5 ............. Discussion of Specifications
6 ............. Detailed Theory of Operation
7 ............. Applications Information
8 ............. Mechanical
SECTION 1
BASIC THEORY OF OPERATION
The basic function of the DDC101 is illustrated in the
Simplified Equivalent Circuit shown in Figure 1. The operation is equivalent to the functions performed by a very high
quality, low bias current switched integrator followed by a
precision floating point programmable gain amplifier and
ending with a high resolution A/D converter.
Reset
i Signal
CINT
A/D Converter
and Control Logic
Sensor
Switched Integrator
Data Out
Programmable Gain
Amplifier
FIGURE 1. Simplified Equivalent Circuit of DDC101 to Illustrate Function.
+VS
Test In
DDC101 Integrated Circuit
Test Current
Reset
CDAC
CINT
18 Bits
DAC
Analog
Input
Digital Integration,
Tracking and
Control Logic
Ground
Comparator
VREF
Digital Filter and
Error Correction
Oversampled
Digital Out
Setup
FIGURE 2. DDC101 Block Diagram.
®
DDC101
2
20 Bits
Serial I/O
Register
Serial In
Serial Out
An internal test current source is provided for basic functionality testing and diagnostics. This approximately 100nA
current source is pin activated and sums with the external
input current.
Capacitor Digital-to-Analog Converter (CDAC). By switching between ground and VREF the binary weighted capacitor
array of the CDAC accumulates the input signal’s charge to
keep the comparator input at virtual ground.
Figure 3 shows a more detailed circuit configuration of the
DDC101. The single integration capacitor, CINT, and the
D/A converter have been replaced with a high resolution
+VS
DDC101
Test Current
Reset
CDAC
CINT
Buffer
ANALOG
In
High
Resolution
Digital Out
3rd Order Digital
Integration,
Tracking and
Control Logic
Sensor
ANALOG
COMMON
Digital
Filter
20 Bits
Serial I/O
Register
DATA
INPUT
DATA
OUTPUT
Oversampled
Digital Out
Comparator
TEST
In
18 Bits
VREF
SYSTEM System Control
CLOCK
DATA
DATA
TRANSMIT CLOCK
FIGURE 3. DDC101 Detailed Circuit Diagram.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3
DDC101
SECTION 2
SPECIFICATIONS
ELECTRICAL
All specifications with unipolar current input range, TINT = 1ms, correlated double sampling enabled, System Clock = 2MHz, VREF = –2.5V, TA = +25°C and VS = ±5VDC,
unless otherwise noted.
DDC101
PARAMETER
INPUTS
Charge Input(6)
Unipolar Input Range
Bipolar Input Range
Input Current
Current Input Range Examples(10)
Unipolar Input Range
Unipolar Input Range
Bipolar Input Range
Bipolar Input Range
Voltage Input Examples(10)
Unipolar Input Range(2)
Bipolar Input Range(2)
CONDITIONS
MIN
BTC Output Code
BTC Output Code
Unipolar or Bipolar Range
MAX
UNITS
–1.95
–251.95
500
250
7.8
pC/Integration
pC/Integration
µA
TINT = 100µs
TINT = 1ms
TINT = 100µs
TINT = 1ms
–0.0195
–1.95
–2.5195
–251.95
5
500
2.5
250
µA
nA
µA
nA
RIN = 10MΩ, TINT = 1ms
RIN = 10MΩ, TINT = 1ms
–0.0195
–2.5195
5
2.5
V
V
64
64
0.5
256 x 106
106
2
µs
µs
MHz
3
ppm of FSR, rms(3)
ppm of FSR, rms
ppm of FSR, rms
ppm of FSR, rms
ppm of FSR, rms
DYNAMIC CHARACTERISTICS
Conversion Time
Integration Time
System Clock Input
ACCURACY
Unipolar Mode Noise
Noise, Low Level Current Input(1)
Noise, Low Level Current Input(1)
Noise, Low Level Current Input(1)
Noise, Low Level Current Input(1)
Noise, Voltage Input(1, 2)
Differential Linearity Error
Unipolar Input Range
Unipolar or Bipolar Input Range
Integral Linearity Error
Unipolar Input Range(11)
Unipolar or Bipolar Input Range(11)
No Missing Codes
Unipolar Input Range
Bipolar Input Range
Input Bias Current
DC Gain Error
Output Offset Error(8)
Input Offset Voltage(8)
External Voltage Reference, VREF
Internal Test Signal
Internal Test Signal Accuracy
Gain Sensitivity to VREF
PSRR
CSENSOR = 0pF, L = 8
CSENSOR = 0pF, L = 1
CSENSOR = 100pF, L = 1
CSENSOR = 500pF, L = 1
RIN ≥ 20MΩ
0.9
1.6
2.1
4.2
1.9
Entire Range
0.1% FSR Input
1% FSR Input
10% FSR Input
±0.005% Reading ±0.5ppm FSR, max
±0.00006
% of FSR
±0.00010
% of FSR
±0.00055
% of FSR
±0.0015
% of FSR
0 to 500 pc/Integration
–1.95 to 0 pc/Integration
0.1% FSR Input
1% FSR Input
10% FSR Input
±0.0244% Reading ±2.5ppm FSR, max
±0.0244% Reading ±3.0ppm FSR, max
±0.00028
% of FSR
±0.00050
% of FSR
±0.0027
% of FSR
±0.003
% of FSR
TA = +25°C
VREF = 2.5V ±0.1V
80
PERFORMANCE OVER TEMPERATURE
Output Offset Drift(8)
not including bias current drift
Input Offset Voltage Drift(8)
Input Bias Current Drift
+25°C to +45°C
Input Bias Current
TA = +85°C
Gain Drift(4)
DIGITAL INPUT/OUTPUT
Logic Family
Logic Level: VIH
VIL
VOH
VOL
Data Clock
Data I/O
SETUP Code I/O(9)
Data Format
Straight Binary
Two’s Complement
18
16
3
±0.5
±0.5
±0.5
–2.5
100
±20
1:1
90
0
1
0.1
8
±15
10
±2
±2
Bits
Bits
pA
% of FSR
ppm of FSR
mV
VDC
nA
nA
dB
0.5
40
µV/°C
µV/°C
pA/°C
pA
ppm/°C
TTL Compatible CMOS
IIH = +5µA
IIL = +5µA
IOH = 2 TTL Loads
IOL = 2 TTL Loads
+2.0
–0.3
+2.4
0.0
Unipolar or Bipolar Range
Unipolar or Bipolar Range
20
21
®
DDC101
TYP
4
+VCC
+0.8
+VCC
0.4
V
V
V
V
8
4
MHz
MHz
Bits
Bits
SPECIFICATIONS (CONT)
ELECTRICAL
All specifications with unipolar current input range, TINT = 1ms, correlated double sampling enabled, System Clock = 2MHz, VREF = –2.5V, TA = +25°C and VS = ±5VDC,
unless otherwise noted.
DDC101
PARAMETER
CONDITIONS
POWER SUPPLY REQUIREMENTS
Operation(5)
Quiescent Current, Positive Supply
Analog, VS+
Digital, VDD+
Quiescent Current, Negative Supply
Operating Power
MIN
TYP
MAX
UNITS
±4.75
±5
15.6
8.9
6.7
18.0
170
±5.25
19.5
VDC
mA
mA
mA
mA
mW
VS+ = +5VDC, VDD+ = +5VDC
VS– = –5VDC
TEMPERATURE RANGE
Operating
Storage
–40
–60
22.5
+85
+100
°C
°C
NOTES: (1) Input = low level (less than 1% of Full Scale); Full Scale IIN = 500nA; TINT = 1ms; Unipolar Input Range; Acquisition Time = 16 clock cycles, Oversampling = 128. (2) Voltage input is converted through user
provided input resistor, RIN. (3) FSR is Full Scale Range. (4) Gain Drift does not include the drift of the external reference. (5) VDD+ must be less than or equal to VS+. See Section 7 for recommended connections. (6)
Straight Binary output code has slightly different Charge Range. See Section 6. (8) Input offset voltage is nulled by autozero circuitry and causes no output error. See Section 6 (Internal Error Correction). (9) This is
the maximum clock frequency at which SETUP codes can be written to and read from the DDC101. (10) For other input current and voltage configurations, see Discussion of Specifications and Detailed Theory of Operation
sections. (11) A best-fit straight line method is used to determine linearity. Two different best-fit straight lines are used for the two unipolar integral linearity specifications. Acquisition Time = 16 clock cycles, Oversampling
= 128.
ELECTROSTATIC
DISCHARGE SENSITIVITY
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
DDC101U
24-Lead SOIC
239
THERMAL
RESISTANCE (θJA)
100
(°C/W)
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ABSOLUTE MAXIMUM RATINGS
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published
specifications.
Analog Inputs
Input Current ............................................................ 100mA, momentary
Input Current .............................................................. 10mA, continuous
Input Voltage ................................................... VS+ +0.5V to VS– –0.5V
Power Supply
VS+ .................................................................................................. + 7V
VS– .................................................................................................... –7V
VDD+ ................................................................................. must be ≤ VS+
Maximum Junction Temperature ................................................... +165°C
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
5
DDC101
PIN CONFIGURATION
Top View
24-Lead SOIC
VS–, ANALOG
1
24
REFERENCE BUFFER BYPASS
ANALOG COMMON
2
23
VREF
ANALOG In
3
22
TEST In
ANALOG COMMON
4
21
RESET SETUP In
VS+, ANALOG
5
20
SETUP
VS+, ANALOG
6
19
READ DATA/SETUP
RESET SYSTEM In
7
18
DATA TRANSMIT In
FDS (Final Data Point Start) In
8
17
OVERFLOW + Out
SYSTEM CLOCK
9
16
OVERFLOW – Out
DATA CLOCK
10
15
DATA VALID Out
DATA INPUT
11
14
DATA OUTPUT
VDD+, DIGITAL
12
13
DIGITAL GROUND
SECTION 3
PIN DESCRIPTIONS
PIN
NUMBER
NAME
1
VS–, ANALOG
2
ANALOG COMMON
3
ANALOG INPUT
4
ANALOG COMMON
5
VS+, ANALOG
Positive analog power supply voltage, +5VDC. Hardwire to pin 6.
6
VS+, ANALOG
Positive analog power supply voltage, +5VDC. Hardwire to pin 5.
7
RESET SYSTEM In
This input resets DDC101, but does not reset the SETUP register. The DDC101 system is reset when this pin
is active; reset action is removed when the pin is inactive.
8
FDS In
This is Final Data point Start input. This input is the basic user control of the integration and conversion timing.
When it becomes active, the DDC101 starts collection of the M, final data point samples. The beginning of the
next integration time is exactly M system clock periods after the Final Data point Start command when operating
in the continuous mode.
9
SYSTEM CLOCK
This clock input sets the basic sampling rate of the DDC101. The DDC101 is specified with a clock speed of
2MHz. The clock speed can be 0.5MHz to 2.0MHz.
10
DATA CLOCK
This clock input controls the data transfer rate for the serial DATA INPUT and DATA OUTPUT ports. The DATA
CLOCK is independent of the SYSTEM CLOCK. This allows the DATA CLOCK to be operated at higher or lower
speeds than the SYSTEM CLOCK. For best noise performance, data should not be transmitted and the DATA
CLOCK should not be active during the initial and final data point collection. If data is being transmitted during
the initial and final data point collection periods, the DATA CLOCK should be synchronized to the SYSTEM
CLOCK, to minimize added noise. DATA CLOCK can be connected to SYSTEM CLOCK, so that the same clock
is used for both; however, for best noise performance, the DATA CLOCK input should be active only when data
is transmitted.
11
DATA INPUT
This input can be used to “daisy chain” the output of several DDC101s together to minimize wiring. The output
register of the DDC101 acts as a shift register to pass through the output of previously connected DDC101 units.
In this way, multiple DDC101 units can convert simultaneously then sequence the data out serially on the same
data line with one common control line and one common data line for all DDC101 units.
DESCRIPTION
Negative analog power supply voltage, –5VDC.
Analog ground point.
Input for low level current signal. Photosensor can be directly connected to this input. With a resistor in series,
DDC101 will convert a voltage input.
Analog ground point.
12
VDD+, DIGITAL
13
DIGITAL GROUND
14
DATA OUTPUT
This output provides serial digital data clocked out at user controlled DATA CLOCK rate. Output data format
is a 21-bit Binary Two's Complement word or a 20-bit Straight Binary word. The data word is transmitted MSB
first. When DATA TRANSMIT is not active DATA OUTPUT tri-states.
15
DATA VALID
This output is activated when conversion is complete and remains active until the DATA TRANSMIT input is
activated.
16
OVERFLOW–
The OVERFLOW output signals each provide an open collector output so that the overflow outputs from several
17
OVERFLOW+
DDC101s can easily be connected (wire ORed) together to a common pull-up resistor. They are activated when
the input is beyond the acceptable range during conversion. Specifically, they are activated when the internal
D/A converter input or digital filter exceeds full scale. They are Cleared at the end of conversion 1/2 clock cycle
after DATA VALID high. DATA VALID can be used to capture OVERFLOW data into an external register.
Digital power supply, +5VDC. VDD+ must be less than or equal to VS+.
Digital ground point.
®
DDC101
6
PIN DESCRIPTIONS (CONT)
PIN
NUMBER
NAME
18
DATA TRANSMIT In
This input controls the transmission of data from the serial I/O register of the DDC101. It can be activated
anytime after DATA VALID out becomes active. It must remain active until all data has been collected from the
serial I/O register(s) of all DDC101s in the data path.
19
READ DATA/
SETUP In
This input can be used to read back the current SETUP data. When this input is held high, the output from DATA
OUTPUT is the data collected by the DDC101. When this input is pulled low, an internal shift register is loaded
with the current SETUP data on the rising edge of DATA CLOCK. This SETUP data shift register is logically
connected between DATA INPUT and DATA OUTPUT pins and can be read in the same way that the data
output is read. SETUP data read back does not invalidate data already stored in the DDC101's serial I/O register
or data being
collected by the DDC101, although digital noise concerns should be considered as
discussed in DATA CLOCK.
20
SETUP In
This input pin controls the DDC101 SETUP. A 12-bit digital word transmitted into this pin controls Acquisition
Time, K, Oversampling, M, Multiple Integrations, L, Input Range and Output Data Format. The DDC101 reads
the SETUP code at this pin after the RESET SETUP input transitions from active to inactive. The SETUP code
is read into the SETUP register on the 12 positive data clock transitions following that transition.
21
RESET SETUP
Resets SETUP register only, does not reset balance of DDC101. The DDC101 reads SETUP input data after
this input transitions from active (reset) to inactive.
22
TEST In
This is a digital input that controls the connection of an internal DC current source to the DDC101's input. TEST
In exercises the DDC101 and is intended to test for functionality only. The typical test input current is 100nA
±20nA. The quiescent current of the DDC101 increases by approximately 1mA when TEST In is active. When
TEST is HIGH, the internal current source is ON and current is flowing into the DDC101 input. When TEST is
LOW, the current source is disconnected from the input.
23
VREF
An external –2.5V reference must be connected to the REFERENCE In pin. Use of an external reference allows
multiple DDC101s to use the same system reference for optimum channel matching. The external reference
should be filtered to minimize noise contribution (see Figure 24).
24
REFERENCE
An external capacitor of 10µF should be connected to this node to provide proper operation of the internal
BUFFER BYPASS D/A converter. The REFERENCE In pin is connected to an internal reference buffer
amplifier. The internal reference buffer drives the internal CDAC. This buffer output is not intended for external
use.
DESCRIPTION
SECTION 4
TIMING CHARACTERISTICS
All specifications with Unipolar input range, TINT = 1ms, Current Input, Correlated Double Sampling enabled, Sys Clock = 2MHz, VREF = –2.5V, TA = +25°C and
VS = ±5VDC, unless otherwise noted.
SYMBOL
DESCRIPTION
MIN
t1
FDS Setup
30
t2
FDS width, Continuous Conversion
50
t3
FDS width, Asynchronous Conversion
TYP
MAX
UNITS
ns
(M–1) Clocks+t1+100ns
M Clocks+t1
ns
ns
t4
FDS HIGH to start of next integration, Asynchronous Conversion
t5
Setup time for RESET SETUP HIGH to DATA CLOCK HIGH
60
ns
t6
Setup time for Setup Codes data valid before rising edge of DATA Clock
30
ns
t7
Hold time for Setup Codes data valid after rising edge of DATA Clock
30
t8
Propagation delay from rising edge of SYSTEM CLOCK to DATA VALID LOW
t9
Propagation delay from DATA TRANSMIT LOW to DATA VALID HIGH
t10
Setup time for DATA CLOCK LOW to DATA TRANSMIT LOW
t11
Propagation delay from DATA TRANSMIT LOW to valid data out
t12
Hold time that Data output is valid after falling edge of DATA CLOCK
t13
Propagation delay from DATA TRANSMIT HIGH to Data Output tri-stated
t14
Propagation delay from falling edge of SYSTEM CLOCK to OVERFLOW+ and
50
ns
ns
50
ns
35
ns
30
ns
30
ns
10
ns
40
ns
25
ns
ns
OVERFLOW–cleared
t15
SYSTEM CLOCK pulse width HIGH
240
t16
SYSTEM CLOCK pulse width LOW
240
t17
DATA VALID LOW to DATA TRANSMIT LOW, Single DDC101
30
ns
(LxN–21) Clocks
ns
®
7
DDC101
Continuous Integration Timing
TINT'
TINT
SYSTEM
CLOCK
t1
FDS In should be coincident with negative clock.
t2
FDS In
Internal
Oversampling
Interval
FDS initiates oversampling period.
End of oversample period
initiates reset for next integration.
M Clock Periods
Internal
Reset
M Clock Periods
Next integration begins when 1 clock
period wide Internal Reset ends.
DATA VALID
Out
Non-Continuous Integration Timing
SYSTEM
CLOCK
FDS In should be coincident with negative clock.
t3
FDS In
Internal
Oversampling
Interval
End of FDS In
initiates end of Internal Reset.
FDS initiates oversampling period.
End of oversample
period initiates
reset.
Internal
Reset
t4
DATA VALID Out
When Internal Reset period ends,
next integration begins.
FIGURE 4. Conversion Timing Diagrams.
RESET SETUP In
t5
DATA CLOCK
(4MHz, max for setup)
Read
t7
t6
ACQMSB
SETUP In
Read
ACQLSB
Read
Input
Range
Read
Output
Format
FIGURE 5. Input/Output Timing Diagram—SETUP Timing Diagram.
SYSTEM
CLOCK
t8
DATA VALID
Out
DATA TRANSMIT
In
t9
DATA TRANSMIT In resets DATA VALID Out.
t17
t10
Data can be read on rising or falling edge of Data Clock
DATA CLOCK
(8MHz, max for data)
t11
DATA OUTPUT
Output Disabled
t12
DDC(1)
Bit 1, MSB
t13
DDC(n)
Bit 21, LSB
DDC
(n+1)
Bit 1
Output Enabled
Last DDC
Bit 21
FIGURE 6. DATA TRANSMIT Timing Diagram.
®
DDC101
8
Output Disabled
TIMING DIAGRAMS (CONT)
SYSTEM CLOCK In
t8
t14
DATA VALID Out
Read
Clear
Read
Clear
OVERFLOW + Out
OVERFLOW – Out
DATA VALID Out can be used to latch data from the overflow status outputs.
FIGURE 7. OVERFLOW Out Monitoring Timing Diagram.
SYSTEM CLOCK In
t15
t16
SYSTEM CLOCK
FIGURE 8. System Clock Timing.
®
9
DDC101
TYPICAL PERFORMANCE CURVES
ELECTRICAL
System Clock = 2MHz, VS = ±5VDC, VREF = –2.5V, L = 1 Integration/Conversion, and TA = +25°C, unless otherwise noted.
SINAD AT 10kHz CONVERSION, UNIPOLAR INPUT
SINAD AT 1kHz CONVERSION, UNIPOLAR INPUT
0
0
100µs Integration Time
K = 16 Acquisition Clocks
M = 32 Oversamples
40
–60dB
60
80
1ms Integration Time
K = 16 Acquisition Clocks
M = 128 Oversamples
20
THD + N (dB)
THD + N (dB)
20
40
–60dB
60
80
0dB
0dB
100
100
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
50
100 150 200 250 300 350 400 450 500
Input Frequency (Hz)
Input Frequency (Hz)
NOISE vs INPUT LEVEL (UNIPOLAR) WITH CDS
NOISE vs INPUT LEVEL (UNIPOLAR) WITHOUT CDS
18
18
1ms Integration Time
K = 16 Acquisition Clocks
M = 128 Oversamples
16
14
Noise (ppm, rms)
Noise (ppm, rms)
14
12
10
8
CIN = 500pF
16
CIN = 500pF
6
4
CIN = 100pF
12
10
8
CIN = 0pF
6
1ms Integration Time
M = 128 Oversamples
4
CIN = 100pF
2
2
CIN = 0pF
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.1
0.2
0.3
Input Level of FS
0.5
0.6
0.7
0.8
0.9
1.0
CHARGE INJECTION vs INPUT CAPACITANCE
NOISE vs RESISTOR VALUE
350
1000
Low Level, Unipolar Input
K = 16 Acquisition Clocks
300
Charge Injection (ppm)
Noise (ppm, rms)
0.4
Input Level of FS
1ms Int., M = 128 O/S
100
10
100µs Int., M = 16 O/S
250
200
150
No CDS
100
50
CDS On, K = 16
0
1
0.01
–50
0.1
1
10
100
0
1G
RIN (MΩ)
200
CIN (pF)
®
DDC101
100
10
500
1000
TYPICAL PERFORMANCE CURVES (CONT)
ELECTRICAL
System Clock = 2MHz, VS = ±5VDC, VREF = –2.5V, L = 1 Integration/Conversion, and TA = +25°C, unless otherwise noted.
NOISE vs INPUT CAPACITANCE, UNIPOLAR INPUT
NOISE vs OVERSAMPLING, UNIPOLAR INPUT
50
40
1ms Integration Time
K = 16 Acquisition Clocks
CIN = 0pF
1ms Integration Time
M = 128 Oversamples
35
Noise (ppm, rms)
Noise (ppm, rms)
30
25
No CDS
20
15
10
L = 1 Integration/Conversion
10
L = 128
1.0
5
L = 64
L=2
L = 32 L = 16
L = 256
CDS On, K = 16
0.5
0
0
100
200
500
1000
1
2000
2
4
8
CIN (pF)
16
32
64
128
256
M Oversamples
CHANGE IN IB vs TEMPERATURE
NOISE vs TEMPERATURE, UNIPOLAR INPUT
2.0
5
0
1ms Integration Time
K = 16 Acquisition Clocks
M = 128 Oversamples
Noise (ppm, rms)
4
–2.0
–4.0
–6.0
3
2
1
–8.0
–40
–20
0
20
40
60
80
0
–40
100
Temperature (°C)
K = 16 Acquisition Clocks
CIN = 0pF
–20
0
25
45
65
85
Temperature (°C)
INPUT OFFSET VOLTAGE vs INPUT CAPACITANCE
NOISE vs INTEGRATION TIME, UNIPOLAR INPUT
5
0.050
M = 16 O/S
0.000
4
–0.050
VBIAS (mV)
Noise (ppm, rms)
∆ IB (pA)
L=4
L=8
3
M = 64 O/S
2
M = 256 O/S
0.100
–0.150
–0.200
1
–0.250
–0.300
0
0.1
1
10
0
100
100
500
CIN (pF)
Integration Time (ms)
®
11
DDC101
TYPICAL PERFORMANCE CURVES (CONT)
ELECTRICAL
System Clock = 2MHz, VS = ±5VDC, VREF = –2.5V, L = 1 Integration/Conversion, and TA = +25°C, unless otherwise noted.
POSITIVE PSRR vs FREQUENCY
100
90
90
80
80
70
70
PSRR (dB)
PSRR (dB)
NEGATIVE PSRR vs FREQUENCY
100
60
50
40
30
60
50
40
30
1ms Integration Time
K = 16 Acquisition Clocks
M = 128 Oversamples
20
10
1ms Integration Time
K = 16 Acquisition Clocks
M = 128 Oversamples
20
10
0
0
0
20
40
60
80
100 120 140 160 180 200
0
20
40
60
Frequency (kHz)
NEGATIVE PSRR vs FREQUENCY
100 120 140 160 180 200
POSITIVE PSRR vs FREQUENCY
100
100
90
90
80
80
70
70
PSRR (dB)
PSRR (dB)
80
Frequency (kHz)
60
50
40
30
60
50
40
30
100µs Integration Time
K = 16 Acquisition Clocks
M = 32 Oversamples
20
10
100µs Integration Time
K = 16 Acquisition Clocks
M = 32 Oversamples
20
10
0
0
0
20
40
60
80
100 120 140 160 180 200
0
®
DDC101
20
40
60
80
100 120 140 160 180 200
Frequency (kHz)
Frequency (kHz)
12
SECTION 5
DISCUSSION OF
SPECIFICATIONS
input range, an input current of 0.5µA integrated for 1ms
will result in the full scale charge of 500pC. For voltage
inputs, the input resistor is chosen to achieve the proper full
scale input current. As an example, for a 5V full scale input,
a 10MΩ input resistor is selected to achieve a full scale input
current of 0.5µA (1ms integration time).
INPUT
The DDC101 is a charge digitizing A/D converter. Low
level current output sources, such as a photosensors, can be
directly connected to its input. The input signal can also be
a voltage connected through a user selected resistor.
Noise of 1.6ppm of FSR is equal to 1.6ppm x 500pC = 0.8fC
or 1.6ppm x 0.5µA = 0.8pA or 1.6ppm x 5V = 8µV. Thus,
in this instance, noise is 1.6pA or 8µV.
For the unipolar input range, the following table shows the
full scale input current required for different integration
times to collect 500pC of charge and the equivalent current
values for 2 and 5ppm of FSR.
CHARGE INPUT
The maximum charge that can be captured in one integration
by the DDC101 is 500pC. In the unipolar input range mode,
the maximum positive charge that can be collected in one
integration is 500pC. The DDC101 has a small negative
range in the unipolar mode of –1.95pC. This small negative
underrange is included to allow for a small amount of
leakage current from the user’s PC board and sensor. In the
bipolar input range, the maximum positive charge that can
be collected is +250pC. The maximum negative charge that
can be collected is –251.95pC.
TINT
IFS
2ppm
5ppm
50ms
5ms
1ms
500µs
100µs
10nA
100nA
500nA
1µA
5µA
0.02pA
0.2pA
1pA
2pA
10pA
0.5pA
1pA
2.5pA
5pA
25pA
TABLE I. Integration Time (TINT) and Full Scale Current (IFS)
for Full Scale 500pC Integration.
CURRENT INPUT
The maximum average input current that can be captured by
the DDC101 is ±7.8µA. This current will result in an
integration time of 64µs for unipolar input range and 32µs
for bipolar input range. For longer integration times, the
average input current must be less.
The maximum input current is limited by the slew and
update rate of the internal tracking logic and CDAC. The
largest input current that the DDC101 can accurately track is
7.8µA. Input currents larger than 7.8µA and high speed
current input pulses can be accurately captured and digitized
by the DDC101 with an external input or sensor capacitance
on the DDC101 input. The average current during a complete integration cycle cannot exceed 7.8µA. Likewise, the
total charge input must not exceed 500pC unipolar, 250pC
bipolar during the integration time.
An external user provided input capacitance, CS, as shown in
Figure 9a, will capture the input signal charge if the input
current limit is temporarily exceeded during the integration
cycle. The DDC101 will then transfer the charge completely
to CINT based upon conservation of charge. An additional
In addition to the normal mode of one integration per
conversion, DDC101 can be configured by the user for 1 to
256 integrations per conversion. When the multiple integrations per conversion mode is chosen, the DDC101 DSP
circuitry internally averages multiple integration cycles to
provide one conversion result. This result has lower noise
because it is the average of multiple integrations. In this
mode, the maximum total charge that can be captured by the
DDC101 in 256 integrations is 128,000pC.
TEST CURRENT INPUT
An internal DC test current can be connected under user
control to the DDC101’s input. The test current is nominally
100nA and will be summed with any applied external input
signal. It is derived by a resistive network from the positive
power supply. The test current is intended to test for functionality only. The TEST In pin of the DDC101 controls the
current. When TEST is HIGH, the internal current source is
ON and current is flowing into the DDC101 input. When
TEST is LOW, the current source is disconnected from the
input. With TEST active, positive power supply current
increases by approximately 1mA.
FULL SCALE RANGE
The full scale range (FSR), which is referenced in the
specification table, is the difference between the positive full
scale charge and the negative full scale charge for the
DDC101 in one integration cycle. Specifications such as
noise and linearity, which are specified in percent or ppm of
FSR, are referring to a value of 500pC for both unipolar and
bipolar input ranges.
The full scale input current for a given integration time will
result in a full scale input charge. As an example for unipolar
Voltage across input must not exceed ±2.5V.
Analog Input, pin 3
i
CS
V
DDC101
Analog Common
External user provided capacitance, CSOURCE, to store current pulses.
FIGURE 9a. Current Pulse Input Capture.
®
13
DDC101
maximum input voltage based upon several selections of
input current and input resistor for unipolar input range. The
accuracy of the input resistor will add directly to the DC
Gain Error of the DDC101; the drift of the input resistor will
add directly to the Gain Drift of the DDC101.
Note that the DDC101 output noise decreases as RIN increases. This is because the DDC101 noise gain decreases
and the input resistance current noise decreases as RIN
increases. This effect is shown in the “Noise vs Resistor
Value” typical performance curve.
constraint is, the voltage that appears at the DDC101 input,
must not exceed 2.5V. If this voltage is exceeded, charge
may be lost and the integration result may be invalid. The
input voltage can be calculated:
i(t) = C S
dv
dt
or
1
V=
∫ i(t)dt
CS
therefore,
V=i
t
.
CS
INPUT RESISTOR, RIN
INTEGRATION TIME
As an example, with a user supplied input capacitance of
100pF, a current pulse of 100µA for 2µs could be stored
without exceeding 2.5V applied to the input:
V = (100µA ) •
2µs
100pF
Full Scale Input Current
Full Scale Voltage
50mV
500mV
5V
50V
= 2V.
The DDC101 is a charge digitizing device. With a user
provided input resistor, the DDC101 can digitize voltage
inputs. All of the general charge/current input specifications
apply to the voltage input situation. The specification table
shows the typical noise of the DDC101 including the effects
of a 20MΩ input resistor, RIN.
Current Input Configuration
i
100kΩ
1MΩ
10MΩ
100MΩ
50kΩ
500kΩ
5MΩ
50MΩ
10kΩ
100kΩ
1MΩ
10MΩ
0.1
Analog Input, pin 3
Linearity Error (% of FSR)
Data Out
Analog Common
Voltage Input Configuration
V
5µA
To illustrate the improvement in unipolar mode linearity
error, Figure 10 shows the maximum unipolar integral linearity error (ILE) of the DDC101 as a function of the input
signal level. The maximum integral linearity error is
±0.0244% of reading ±2.5ppm of FSR (ILE max for unipolar input of –1.95 to 0 pc is ±0.0244% of reading ±3.0ppm
of FSR). Thus, the maximum ILE for an input level of 1%
of FSR is 0.0005%FSR.
The input of the DDC101 is a virtual ground. A voltage input
causes a current, i, to flow into the input through RIN as
shown in Figure 9b. The maximum input current is determined by the integration time selected. Table II shows the
i
100µs
1µA
UNIPOLAR LINEARITY ERRORS
Due to innovative design techniques, the absolute level of
linearity error of the DDC101 improves as the input signal
level decreases when used in the unipolar input mode.
Therefore, in unipolar input mode, the integral linearity of
the DDC101 is specified as a small base error plus a
percentage of reading error or as a percentage of full scale
range. A best-fit straight line method is used to determine
integral linearity. Two different best-fit straight lines are
used for the two unipolar integral linearity specifications.
For bipolar input mode, linearity is specified only as a
percentage of full scale range.
VOLTAGE INPUT SPECIFICATIONS
Input
Resistor
500µs
TABLE II. Example of Input Resistor Values Unipolar Input
Range.
The current pulse must occur completely during part of one
DDC101 integration time, and the DDC101 must still have
time to discharge the input capacitance to ground at a
maximum rate of 7.8µA before the DDC101 is triggered
(through the FDS input) to end the integration. In addition,
the total charge integrated must be 500pC or less for the
unipolar range. A current pulse of 100µA for 2µs creates
200pC of charge.
DDC101
1ms
0.5µA
0.01
0.001
Analog Input, pin 3
RIN
DDC101
0.0001
0.001
Data Out
0.1
1
10
100
Unipolar Input Level (% of FSR)
Analog Common
FIGURE 10. Maximum Unipolar Integral Linearity Error
Relative to Full-Scale, Converted From % of
Reading Specification.
FIGURE 9b. DDC101 Input Configurations.
®
DDC101
0.01
14
NOISE
The noise of the DDC101 improves as the input signal level
decreases, thus very low level signals can be resolved. Noise
is shown in the specification table for low level inputs. For
unipolar input range, the DDC101 noise at low level inputs
is dominated by comparator noise gained to the output; at
full scale inputs, the noise is dominated by D/A converter
noise. The noise at low low level inputs is a function of input
capacitance; the noise at full scale is relatively independent
of input capacitance. For bipolar input operation, the noise
is dominated by D/A converter noise and is higher than the
full scale unipolar noise.
2. Oversampling
This is the low pass filter characteristic of the digital
filter’s oversampling. This response reduces the broadband noise in the input signal and the DDC101. Broadband noise decreases as the number of oversamples
increases.
3. Multiple Integrations
This is the low pass filter characteristic that results when
the digital filter is used to average multiple integrations.
This will determine the primary response of the DDC101
if two or more integrations are internally averaged.
See Section 6 for more details.
BIPOLAR INPUT ACCURACY
Linearity—As a bipolar input device, the linearity of the
DDC101 is specified as a percentage of full scale range that
does not improve with lower input signal levels. Performance is generally limited by the linearity of the unit when
operated in the bipolar input mode.
SECTION 6
DETAILED THEORY
OF OPERATION
INTEGRATION CYCLE
Noise—In general, noise is not as important as linearity
when determining total error. The output noise of the DDC101
in the bipolar mode peaks at midscale (zero input signal
level). Output noise is lower for inputs above and below
zero.
An integration cycle, as illustrated in Figure 11, includes the
Acquisition Time, Initial Data Point Sampling, Tracking
Interval, and Final Data Point Sampling. The Acquisition
Time is K clock periods. The first clock cycle of the
Acquisition Time is used to reset the integrating capacitor,
CINT, to zero from the previous integration. The balance of
the Acquisition Time insures that the DDC101 system is
accurately tracking the input signal prior to initial data point
acquisition. Close-ups of the Reset and Acquisition time are
shown in Figures 12 and 13.
The Initial Data Point is then sampled M times. The Integration cycle time consists primarily of the Tracking Interval
during which time the DDC101 “tracks” the integration of
the input signal. The Tracking Interval is followed by the
measurement of the Final Data Point with the same user
selected number of samples, M. M and K are user selectable.
The entire integration cycle consists of N clock periods as
controlled by the user.
The DDC101 operates in continuous and non-continuous
integration modes. In the continuous mode, one integration
follows another with no delay from the end of one integration to the beginning of the next conversion. In the noncontinuous mode, each new integration is started separately
under user control.
The Final Data point Start (FDS) input is the primary user
control of the integration cycle. The FDS input controls the
end of one integration cycle and the start of the next
integration cycle in both the continuous and non-continuous
integration modes. Measurement of the M final data point
samples begins when the FDS input is activated.
RESET CHARGE ERROR
The reset charge error (typically less than 250fC) is an offset
error that could result from offset voltage, charge injection
and kT/C errors. The DDC101 eliminates the effects of reset
charge errors with correlated double sampling.
DC BIAS VOLTAGE
The DDC101 generates a small bias voltage (typically 500µV)
at the input. This voltage is impressed on any sensor that is
connected to the input. The DC bias voltage is the actual
virtual ground voltage of the DDC101. The DDC101 input
comparator circuitry includes an autozero circuit which
eliminates this offset internally so that it does not produce an
output error.
GAIN SENSITIVITY TO VREF
The DDC101 gain is dependent upon the external reference
voltage, VREF. A change in the value of VREF will be seen as
a directly proportional change in the gain of the DDC101.
FREQUENCY RESPONSE
The DDC101 is a sampling system whose transfer function
has three separate frequency components. These components are multiplied together to make the total frequency
characteristic of the DDC101. The three components are:
1. Basic Integration
This is the characteristic sin(x)/x response of the basic
integration function. This response is controlled by the
integration time of the DDC101.
CONTINUOUS INTEGRATION MODE
In the continuous integration mode, the “Final Data Point
Start” command (using the FDS pin) initiates the measurement of the M final data point samples. The next integration
cycle begins immediately after the final data point sampling
®
15
DDC101
N
Aquisition
Time, K
X
Time,
Clock
Cycles
Oversampled
Initial Data Point
M
Tracking Interval
Final Data
Point Start
M
X
Oversampled
Final Data Point
Measurement Time
Digital
Output
DDC101 digital output is precise integration of input during measurement time.
FIGURE 11. Equivalent Integrator Output for Single Integration.
Aquisition
Time
K
M
Time,
Clock
Cycles
X
Oversampled
Initial Data Point
Reset of
Previous Integration
Tracking
Interval
Digital
Output
FIGURE 12. Close-up of Initial Oversampled Data Point for DDC101.
has been completed; this occurs M clock periods after the
FDS transition to “ON”. Acquisition, Initial Data Point and
Tracking for the next integration follow automatically. The
DDC101 continues in the Tracking mode until the next FDS
command initiates the measurement of the M final data point
samples. An FDS command is needed for each integration
cycle. In the continuous integration mode, the FDS pulse
width must be less than M clock periods. If the FDS pulse
is held low past this time of M clock periods, the DDC101
will reset as for non-continuous mode (see also Figure 4).
In the continuous mode of operation, the tracking logic of
the DDC101 “remembers” the integration rate of the previous integration and begins the next integration at the rate of
the previous integration. This allows faster acquisition of the
signal for the next integration.
®
DDC101
16
Correlated Double Sampling is implemented in the DDC101
by subtracting the Initial Data Point from the Final Data
Point. Thus, the error correction is updated automatically for
each integration. When operating in the unipolar input range,
CDS functions with either output data format—straight
binary or binary two’s complement. When operating in the
bipolar input range, CDS functions with binary two’s complement output data format only.
Acquisition Time, K
Actual Integration
Ideal Integration
Reset of
Previous Integration
Signal Acquired
The errors that CDS removes are charge injection, kT/C and
DDC101 input voltage offset. These errors are very difficult
to eliminate in equivalent analog circuits. Charge injection
errors result from charge that is transferred through the reset
switch into the integration capacitor. kT/C errors are switching errors due to the noise of the resistance of the reset
switch. DDC101 voltage offset errors are due to input offset
of the input comparator. Both initial offset and offset drift
with time and temperature are corrected since the correction
is performed each integration cycle.
FIGURE 13. Close-up of Reset and Acquisition Time for
DDC101.
Integration n + 1
Integration n
Final
Oversampled
Data
Initial
Oversampled
Data
Acquisition
SINGLE CYCLE INTEGRATION
The DDC101 acquires charge (q) by integrating input current (i) for a specific time (T). That is,
Tracking Interval
Reset
T
q = ∫ i dt
O
Final Data Point Start
The DDC101 acquires up to 500pC of full scale charge per
integration cycle in the unipolar input range, and approximately ±250pC of full scale charge in the bipolar input
range. Therefore, for the DDC101, maximum values can be
calculated.
FIGURE 14. Close-up of End of One Integration Cycle and
Beginning of Next.
NON-CONTINUOUS INTEGRATION MODE
For the non-continuous integration mode, FDS controls the
start of the M final data point samples and the end of
integration as discussed above. In this mode, however, FDS
is also used to control the start of a new integration cycle
asynchronously with the end of the previous integration.
When FDS transitions to “ON”, the collection of the M final
data point samples begins. At the end of each integration, the
DDC101 automatically resets the integration capacitance. If
FDS remains “ON” past the end of integration, the DDC101
will stay in the integration reset state until FDS transitions to
“OFF”. Holding FDS “ON” past the end of integration will
also reset the DDC101’s tracking logic to zero integration
rate.
In non-continuous integration mode, the initial data point
measurement may be less accurate since the DDC101’s
internal tracking logic is reset at the beginning of the
integration and tracking may not be accurate for the initial
data point measurement. In this situation, Correlated Double
Sampling (CDS) operation may not be advantageous.
Unipolar Input Range
Bipolar Input Range
500pC = IFS x TINT
±250pC = ±IFS x TINT
Where IFS is the full scale input current and TINT is the
integration time of the DDC101. Examples of IFS and TINT
that equal 500pC and ±250pC are shown in the following
tables.
The maximum average input current that the DDC101 can
integrate is 7.8µA. This results in a minimum integration
time of 64µs for unipolar inputs and 32µs for bipolar inputs.
Further flexibility is possible with multiple integration cycles
per conversion as described in the following text.
INPUT RANGE
Unipolar Input Range
For the unipolar input range, the range of charge for each
integration cycle is from positive full scale of +500pC to a
slightly negative charge of –1/256 (approximately –0.4%) of
the positive full scale charge. This is +500pC to –1.95pC.
The negative charge measurement capability allows for low
level PC board parasitic leakages.
INTERNAL ERROR CORRECTION
The DDC101 uses CDS techniques to gain optimum performance. CDS removes internal DDC101 errors which occur
for a given integration cycle such as, charge injection, kT/C,
and DDC101 offset errors. Correlated Double Sampling is
user selectable. It is recommended for most continuous
measurement applications.
Bipolar Input Range
For the bipolar input range, the range of charge for each
integration cycle is from positive full scale of +250pC to
negative full scale of –251.95pC.
®
17
DDC101
IFS
TINT
1nA
10nA
100nA
1µA
5µA
7.8µA
500ms
50ms
5ms
500µs
100µs
64µs
Conversion Cycle
Integration 1
Integration 2
Time
TABLE III. Input Current vs Integration Time Examples
for Maximum Charge. Unipolar input range
maximum charge = 500pC.
±IFS
TINT
1nA
10nA
100nA
1µA
2.5µA
7.8µA
250ms
25ms
2.5ms
250µs
100µs
32µs
FIGURE 15. Conversion Cycle with Two Integrations.
TABLE IV. Input Current vs Integration Time Examples
for Maximum Charge. Bipolar input range
maximum charge = ±250pC.
MULTIPLE INTEGRATIONS
PER CONVERSION CYCLE
If more than 500pC, unipolar (or ±250pC, bipolar) of charge
must be integrated in one conversion cycle, the DDC101 can
be user programmed for multiple integrations per conversion
cycle. This feature can be used to provide for longer conversion periods for a specific input current other than shown in
the previous table. The integration cycles forming a conversion cycle may be continuous or non-continuous. The number of integrations per conversion cycle, L, can be 1, 2, 4, 8,
16, 32, 64, 128, or 256. The multiple integrations are
automatically averaged in the DDC101 so that one conversion result is output per total conversion cycle. Note that
each integration requires individual control by the FDS
signal. For example, if L = 4, then four FDS signals per
conversion are required.
INTEGRATIONS
PER CONVERSION
IFS
CONVERSION
TIME
MAX CHARGE/
CONVERSION
L=1
L=2
L=4
L=8
L = 16
L = 32
L = 64
L = 128
L = 256
10nA
10nA
10nA
10nA
10nA
10nA
10nA
10nA
10nA
50ms
100ms
200ms
400ms
800ms
1.6s
3.2s
6.4s
12.8s
500pC
1000pC
2000pC
4000pC
8000pC
16000pC
32000pC
64000pC
128000pC
TABLE V. Integrations/Conversion vs Conversion Time.
Example for multiple integrations with unipolar
input range.
individual component has a sinc (sinx/x) frequency response
function.
1. Basic Integration
This is the characteristic sin(x)/x response of the basic
integration function. This response is controlled by the
measurement time of the DDC101, TMEAS; see Figure 16.
2. Oversampling
This is the low pass filter characteristic of the digital
filter’s oversampling. This response reduces the broadband noise in the input signal of the DDC101. Broadband
noise decreases as the number of oversamples increases.
This response is controlled by the number of oversamples,
M; see Figure 17.
FINAL DATA POINT CONFIGURATION LIMITS
In each conversion cycle, the maximum number of final data
points which can be collected is 256. This means that at the
extremes, the DDC101 can be setup to perform one integration cycle with 256 oversamples, or the DDC101 can be
setup to perform 256 integration cycles with one sample per
integration cycle. The total number of integrations, L, multiplied by the number of samples per final data point, must
be 256 or less. As an example, if 16 integration cycles, L, are
used, the number of samples per final data point must be 16
or less.
3. Multiple Integrations
This is the low pass filter characteristic that results when
the digital filter is used to average multiple integrations.
This will determine the primary response of the DDC101
if two or more integrations are internally averaged. This
response is controlled by the total conversion time of the
DDC101; see Figure 18.
Input frequencies are multiplied by the DDC101 frequency
response. The Nyquist frequency is fCONV/2, where fCONV is
the DDC101 conversion rate. The highest frequency that can
be reconstructed from the output data is fCONV/2. Input
frequencies above Nyquist are multiplied by the DDC101
frequency response and are then aliased into DC to fCONV/2.
NOTE: When CDS is used, the initial data points impose no
additional conversion sampling limitations.
FREQUENCY RESPONSE
The DDC101 charge digitizing A/D Converter is a sampled
system whose frequency response has three separate components. These components are multiplied together to make the
total frequency characteristic of the DDC101. The three
frequency response components are shown below. Each
®
DDC101
One data output per
conversion cycle with
two integrations/conversion
CDAC
Charge
18
Basic Integration Frequency Response
The sin(x)/x basic integration characteristic is controlled by
the digital filter’s measurement time (TMEAS). The measurement frequency, fMEAS is l/TMEAS. The input frequency response of the DDC101 is down –3dB at fMEAS/2.26 with a
null at fMEAS. Subsequent nulls are at harmonics 2fMEAS,
3fMEAS, 4fMEAS, etc. as shown in the frequency response curve
below. This characteristic is often used to eliminate known
interference by setting fMEAS or a harmonic to exactly the
frequency of the interference. Table VI illustrates the frequency characteristics of the DDC101 integration function
for various measurement times. As an example, for N =
2272, K = 16, and M = 256: TMEAS = (N-M-K)/fCLK = (2272256-16)/2MHz = 1ms and fMEAS = 1kHz. TINT = 2272/2MHz
= 1.14ms; fCONV = l/TINT = 880Hz.
MEASUREMENT TIME
–3dB FREQUENCY
fMEAS
100µs
1ms
10ms
16.66ms
20ms
4.42kHz
442Hz
44.2Hz
26.5Hz
22.1Hz
10kHz
1kHz
100Hz
60Hz
50Hz
0
–10
Gain (dB)
Nyquist
(fCONV/2)
–20dB/decade
Slope
–20
–30
–40
fCONV
–50
0.1fMEAS
fMEAS
10fMEAS
Frequency
FIGURE 16. Basic Integration Frequency Response.
at fOS = 1/TOS. The oversample time, TOS, is M/fCLK. For M =
256 and fCLK = 2MHz, fOS is approximately 7.8kHz. Subsequent nulls are at harmonics 2fOS, 3fOS, 4fOS, etc. The –3dB
point is at fOS/2.26. Table VII illustrates the DDC101
oversampling frequency characteristics with approximate
values for fOS and the –3dB frequency. An oversampling
frequency response graph is shown below in Figure 17. This
figure shows the frequency response for M = 256 oversamples
with an fCLK of 2MHz . The slope of the attenuation curve
decreases at approximately 20dB/decade.
TABLE VI. Basic Integration Frequency Response Examples.
Oversampling Frequency Response
The M oversamples of the initial and the final data points
create an oversampling sin(x)/x type of low pass filter
response. The oversampling function reduces broadband
noise of the input signal and the DDC101. Broadband noise
is reduced approximately in proportion to the square root of
the number of oversamples, M. As an example, a conversion
with 128 oversamples will have approximately 1/2 the noise
of a conversion with 32 oversamples (√32/128 = √1/4 =
1/2) The oversampling low pass filter response creates a null
OVERSAMPLES (M)
–3dB FREQUENCY
fOS
256
128
64
16
3.5kHz
6.9kHz
13.9kHz
55kHz
7.8kHz
15.6kHz
31.2kHz
125kHz
TABLE VII. Oversample Frequency Response Examples.
Normalized DDC101 Frequency Response
The normalized frequency response, H(f), of the DDC101 that is applied to the input signal consists of the product of the three
frequency response components:
H( f ) =
( (
sin πf N − M − K ) / f CLK
πf ( N − M − K ) / f CLK
Basic Integration
) • sin(πfM/ f ) • sin(πfLN/ f ) • e
CLK
(
Msin πf / f CLK
Oversampling
)
(
CLK
Lsin πfN/ f CLK
Multiple Integrations
)
− jπf ( LN − K −1) / f CLK
Linear Phase
Where:
f
fCLK
is the signal frequency
is the system clock frequency, typically 2MHz
N
is the total number of clock periods in each integration time, TINT = N/fCLK, TINT is the DDC101 CDAC's
integration time
M
K
(N-M-K)/fCLK
is the number of oversamples in one oversampled data point
is the number of clocks used in the acquisition time
is the digital filters measurement time, TMEAS, (TMEAS = TINT –(M+K)/fCLK)
is the oversample time, TOS
M/fCLK
LN/fCLK
is the total conversion time for multiple integrations, TCONV
The DDC101's transfer response has a linear phase characteristic as indicated by the exponential term.
®
19
DDC101
Gain (dB)
0
0
–5
–5
–10
–10
–15
–15
–20
–20
–25
–25
–30
–30
–35
–35
–40
N = 1000
L = 64
fCONV = 31Hz
–40
fOS 10k
1k
100k
1M
1
10
Frequency (Hz)
FIGURE 17. Oversampling Frequency Response for M = 256
(fCLK = 2MHz).
1ms
1ms
1ms
1ms
1ms
10ms
10ms
10ms
10ms
10ms
2
8
16
64
256
2
8
16
64
256
CONVERSION
–3dB
TIME
FREQUENCY
2ms
8ms
16ms
64ms
256ms
20ms
80ms
160ms
640ms
2560ms
1k
221Hz
55Hz
27.5Hz
6.9Hz
1.73Hz
22.1Hz
5.5Hz
2.75Hz
0.69Hz
0.173Hz
Signal Noise—The noise of the input signal is filtered and
reduced in a manner similar to the DDC101 noise reduction
through the integrating and oversampling functions of the
DDC101.
Figures 19 and 20 show the frequency response of the
DDC101 for the product of the basic integration and
oversampling frequency response for two different values of
M. In both examples, the integration time is 1ms, the only
difference is in the number of oversamples, M; for Figure
19, M = 256 oversamples was used; for Figure 20, M = 32
oversamples was used. The first null frequency is fMEAS and
subsequent nulls are at multiples of fMEAS. The first example
with the larger number of oversamples (M = 256) clearly
reduces high frequency noise more than the second example
with M = 32.
For M = 256, fOS is 7.8kHz, fMEAS is 1.16kHz, and the –3dB
frequency is 507Hz. For M = 32, fOS is 62.4kHz, fMEAS is
1.02kHz and the –3dB frequency is 453Hz.
fCONV
500Hz
125Hz
62.5Hz
15.6Hz
3.91Hz
50.0Hz
12.5Hz
6.25Hz
1.56Hz
0.39Hz
0
N = 2000
M = 256
K = 16
–5
–10
–15
Gain
L
100
FIGURE 18. A Multiple Integration Frequency Response
Example.
Multiple Integration Frequency Response
If the DDC101 is operated in the multiple integrations per
conversion mode of operation, an additional sin(x)/x type
low pass filter is created. The filter creates an initial null
frequency at the conversion frequency, fCONV of the DDC101
and at multiples of fCONV. The –3dB point for this filter is also
at fCONV/2.26. The conversion time, TCONV, is the sum of the
integration times for multiple integrations that are averaged
together by the DDC101. TCONV = LN/fCLK. fCONV = l/TCONV.
If multiple integrations per conversion are used, this filter
will be the dominant low frequency filter of the DDC101.
Table VIII shows examples of the conversion time and
frequency for different parameter selections. Figure 18 shows
an example of the frequency response due to Multiple
Integrations. In the case of Figure 18, the integration time is
500µs (N = 1000 clock periods) and L = 64 integrations per
conversion.
INTEGRATION
TIME
fCONV
Frequency (Hz)
TABLE VIII. Multiple Integration Time Examples.
–20
–25
System Noise implications
The noise at the digital output of the DDC101 consists of
system noise that is included in the analog input signal and
noise from the DDC101.
DDC101 Noise—The noise of the DDC101 includes low
frequency and broadband noise. The low frequency noise is
reduced by the integrating function and the CDS function of
the DDC101. This is reflected in the basic integration
frequency response and in the multiple integration frequency
response. The broadband electronic noise is reduced primarily by the oversampling function of the DDC101
–30
–35
–40
100
10k
100k
Frequency (Hz)
FIGURE 19. Product of Frequency Response of Basic Integration and Oversampling: 1ms Integration
Time, 256 Oversamples.
®
DDC101
1k
20
0
SYSTEM SETUP
After power up, the Reset System and FDS signal inputs
should be held low (active), while the SETUP register is
loaded by the user. After the SETUP register is loaded, the
Reset System input should transition to inactive while the
FDS input remains active. The FDS should transition to
inactive at the start of operation. Thereafter, Reset System
should stay inactive and the FDS should be used to control
each integration cycle.
N = 2000
M = 32
K = 16
–5
–10
Gain
–15
–20
–25
–30
SETUP INPUT
Software Control
Many of the options of the DDC101 are set through a serial
bit stream transmitted by the user into the SETUP Input pin.
The 12-bit word transmitted into the SETUP Input is used to
set the following four options, in sequence:
1. Acquisition Time Control, K
2 bits
–35
–40
100
1k
10k
100k
Frequency (Hz)
FIGURE 20. Product of Frequency Response of Basic Integration and Oversampling; 1ms Integration
Time, 32 Oversamples.
2. Oversampling Control
Samples/Integration, M
3. Multiple Integration Control
Integrations/Conversion, L
4. Unipolar or Bipolar Input Range
Figure 21 shows the frequency response of the DDC101 and
an ideal integrator with the same integration time. In this
comparison, the DDC101 has greater bandwidth to the first
null, but it also has greater out of band attenuation which
reduces broadband noise significantly. If desired, the frequency response of the ideal integrator can be produced by
passing the DDC101 output through an external digital
filtering function which has the frequency response from DC
to Nyquist of
4 bits
4 bits
1 bit
5. Output Format
1 bit
Total for SETUP
12 bits
See Figure 5: SETUP Timing Diagram.
Acquisition Time Control, K
This signal sets the acquisition time (K clock periods) and
controls the use of Correlated Double Sampling. The acquisition time occurs at the start of each new integration. The
acquisition time control can be set to four options: “no
CDS”, 1, 16 or 32 clock periods. For typical continuous
integration applications, K = 16 is recommended. The acquisition time always begins with one clock period for reset.
This reset clock period is followed by 0, 15 or 31 clock
periods for signal acquisition. Correlated Double Sampling
is activated if the initial acquisition time is set to 1, 16 or 32
clock periods. Correlated Double Sampling is disabled and
the Initial Data Point is not acquired if “no CDS” is selected.
πf T MEAS
M sin(πf / f CLK )
sin(πf T INT )
•
•
.
πf T INT
sin(πf T MEAS ) sin(πf M / f CLK )
This has the effect of further attenuating undesired signals
(noise) outside the “passband”, further increasing the signalto-noise ratio of the DDC101 and closely emulating the ideal
integrator’s signal accumulation characteristics.
Comparison of DDC101 with Ideal Integrator
0
DDC101 with N = 2000;
L = 1; M = 256; K = 16;
TCONV = TINT = 2MHz/N = 1ms
fMEAS = 2MHz/(N-M-K) = 1.16kHz
–5
Gain (dB)
–10
–15
Nyquist
(fCONV/2)
Ideal Integrator
with TINT = 1ms
–20
K
RESET
CLOCKS
ACQUISITION
CLOCKS
CDS
“No CDS”
1
16
32
1
1
1
1
0
0
15
31
Disabled
Enabled
Enabled
Enabled
TABLE IX. Acquisition Time Control, K.
–25
When Correlated Double Sampling is activated, the DDC101
acquires the initial data point for error correction as part of
each conversion. At the end of the conversion cycle, the
initial data point is subtracted from the final data point. The
errors that are corrected with CDS are charge injection,
kT/C noise, and DDC101 voltage offset. When Correlated
Double Sampling is deactivated, the initial data point is not
taken.
–30
fCONV
–35
–40
100
1k
fMEAS
10k
100k
Frequency (Hz)
FIGURE 21. Comparison of DDC101 with Ideal Integrator.
®
21
DDC101
BIPOLAR INPUT RANGE
For Binary Two’s Complement, output data format, the
output word is a 21-bit Two’s Complement word. The first
bit is the sign bit followed by the Most Significant Bit
(MSB), etc. The output range is +100%FS to –100.8%FS,
where FS is 250pC. For the bipolar input range, the output
code table changes with the use of Correlated Double Sampling (CDS). (There is no difference with or without CDS in
the output code table when using the unipolar input range.)
When operating in the unipolar input range, CDS functions
with either output data format—straight binary or binary
two’s complement. When operating in the bipolar input
range, CDS functions correctly only with binary two’s
complement output data format.
Oversampling Control
Samples/Integration, M
This control sets the number of samples, M, used by the
DDC101 to oversample the initial and final data points. M
can be set for these values: 1, 2, 4, 8, 16, 32, 64, 128, 256.
Broadband noise in the conversion is reduced roughly in
proportion to the square root of M. Therefore, a conversion
with 128 oversamples will have 1/2 the broadband noise of
a conversion with 32 oversamples. See the previous frequency response discussion.
CODE
Multiple Integration Control, L
This control sets the number of integrations per conversion
cycle, L. It is used to reduce the data rate, increase the
magnitude of the input signal range, and/or reduce the noise.
The product of L and M must be 256 or less.
CODE
+500pC
CODE
–1.95pC
0pC
–250pC
–251.95pC
+100%FS
+100%FS – 1LSB
+1LSB
Zero
–1LSB
–100%FS
+250pC
0pC
–250pC
TABLE XIV. Straight Binary Code Table — Bipolar Input
Range without CDS.
SETUP INPUT CODE
Acquisition Time Control—K - 2 bits
INPUT SIGNAL
498.05pC
CODE
RESULT
00
1 Reset clock period, 0 clock period Acquisition Time,
CDS disabled, no initial data point,
1 Reset clock period, 0 clock period Acquisition Time
1 Reset clock period, 15 clock period Acquisition Time
1 Reset clock period, 31 clock period Acquisition Time
01
10(1)
11
–1.95pC
TABLE XI. Straight Binary Code Table — Unipolar Input
Range.
NOTE: (1) Recommended for continuous integration mode.
®
DDC101
+250pC
INPUT SIGNAL
1111 1111 1111 1111 1111
1111 1111 1111 1111 1110
1000 0000 0000 0000 0001
1000 0000 0000 0000 0000
0111 1111 1111 1111 1111
0000 0000 0000 0000 0000
For Straight Binary output data format, the output is a 20-bit
straight binary word. The first bit is the Most Significant Bit
(MSB), etc. The output range is +99.6%FS to –0.4%FS in
which +99.6%FS represents positive full scale and –0.4%FS
represents the minimum input.
+99.6%FS
+99.6%FS –1LSB
+1LSB
Zero
–0.4%FS
+100%FS
+100%FS – 1LSB
+1LSB
Zero
–1LSB
–100%FS + 1LSB
–100%FS
–100.8%FS
0pC
TABLE X. BTC Code Table—Unipolar Input Range.
1111 1111 1111 1111 1111
1111 1111 1111 1111 1110
0000 0001 0000 0000 0001
0000 0001 0000 0000 0000
0000 0000 0000 0000 0000
–250pC
–251.95pC
For Straight Binary output data format with the bipolar input
range, the output is a 20-bit straight binary word. The first
bit is the Most Significant Bit (MSB), etc. The output range
is +100%FS to –100%FS in which +100%FS represents
positive full scale and –100%FS represents the negative full
scale. When using the straight binary output data format in
bipolar input range, do not use CDS. This will cause a
negative overflow to occur.
INPUT SIGNAL
CODE
0pC
TABLE XIII. BTC Code Table — Bipolar Input Range with
CDS.
UNIPOLAR INPUT RANGE
For Binary Two’s Complement, output data format, the
output word is a 21-bit Two’s Complement word. The first
bit is the sign bit followed by the Most Significant Bit
(MSB), etc. The output range is +100%FS to –0.4%FS,
where FS is 500pC.
+100%FS
+100%FS –1LSB
+1SLB
Zero
–1LSB
–0.4%FS
+250pC
INPUT SIGNAL
0 0111 1111 1111 1111 1111
0 0111 1111 1111 1111 1110
0 0000 0000 0000 0000 0001
0 0000 0000 0000 0000 0000
1 1111 1111 1111 1111 1111
1 1000 0000 0000 0000 0001
1 1000 0000 0000 0000 0000
1 0111 1111 0000 0000 0000
Binary Two’s Complement (BTC) and Straight Binary.
0 1111 1111 1111 1111 1111
0 1111 1111 1111 1111 1110
0 0000 0000 0000 0000 0001
0 0000 0000 0000 0000 0000
1 1111 1111 1111 1111 1111
1 1111 1111 0000 0000 0000
+100%FS
+100%FS –1LSB
+1LSB
Zero
–1LSB
–100%FS + 1SLB
–100%FS
–100.8%FS
TABLE XII. BTC Code Table — Bipolar Input Range without CDS.
Output Format
Two output formats are available for either the unipolar or
bipolar input ranges:
CODE
INPUT SIGNAL
0 1111 1111 1111 1111 1111
0 1111 1111 1111 1111 1110
0 1000 0000 0000 0000 0001
0 1000 0000 0000 0000 0000
0 0111 1111 1111 1111 1111
0 0000 0000 0000 0000 0001
0 0000 0000 0000 0000 0000
1 1111 1111 0000 0000 0000
22
Oversampling Control
Samples/Integration—M - 4 bits
CODE
SAMPLES PER INTEGRATION
0000
0001
0010
0011
0100
0101
0110
0111
1XXX
1
2
4
8
16
32
64
128
256
Guard
Pattern
INTEGRATIONS PER CONVERSION
0000
0001
0010
0011
0100
0101
0110
0111
1XXX
1
2
4
8
16
32
64
128
256
INPUT RANGE
0
1
Unipolar
Bipolar
FIGURE 22. PC Board Layout Showing “Guard” Traces
Surrounding Analog Input Pin and Traces.
Power Supplies
The ±5VDC supplies of the DDC101 should be bypassed
with 10µF solid tantalum capacitors and 0.1µF ceramic
capacitors. The supplies should each have a 10µF solid
tantalum capacitor at a central point on the PC board. Each
of the DDC101 power supply lines (VS+, VS–, VDD+) should
have a separate 0.1µF ceramic capacitor placed as close to
the DDC101 package as possible.
The digital power supply voltage, VDD+ must be equal to or
less than the analog power supply voltage, VS+. The analog
power supply, VS+, is connected to pins 5 and 6, these pins
should be hardwired together on the printed circuit board at
the pins for best performance.
VDD+ should be as quiet as possible with minimal noise
coupling. It is particularly important to eliminate noise from
VDD+ that is non-synchronous with DDC101 operation.
Figure 23 illustrates two acceptable ways to supply VDD+
power to the DDC101. The first case shows two separate
+5VDC supplies for VDD+ and VS+. The second case shows
the VDD+ power supply derived from the VS+ supply as used
on the DDC101 Evaluation Fixture Device Under Test
(DUT) board.
Output Format - 1 bit
CODE
OUTPUT FORMAT
1
0
Binary Two's Complement
Straight Binary
Analog Common
Analog Common
Input Range - 1 bit
CODE
VS–
Analog Input
Multiple Integration Control
Integrations/Conversion—L - 4 bits
CODE
DDC101
Pin 1
VS+
SECTION 7
APPLICATIONS INFORMATION
5
10µF
6
DDC101
0.1µF
BASIC PRINTED CIRCUIT BOARD LAYOUT
VDD+
As with any precision circuit, careful printed circuit layout
will ensure best performance. Make short, direct interconnections and avoid stray wiring capacitance—particularly at
the analog input pin. Digital signals should be kept as far
from the analog input signals as possible on the PC board.
Leakage currents between PC board traces can exceed the
input bias current of the DDC101 if care is not taken. A
circuit board “guard” pattern for the analog input pin and for
the PC board trace that connects to the analog input pin is
recommended. The guard pattern reduces leakage effects by
surrounding the analog input pin and trace with a low
impedance analog ground. Leakage currents from other
portions of the circuit will flow harmlessly to the low
impedance analog ground rather than into the analog input
of the DDC101. Analog ground pins are placed on either
side of the analog input pin in the DDC101 package to allow
convenient layout of guard patterns. Figure 22 illustrates the
use of guard patterns to protect the analog input.
12
10µF
0.1µF
Separate +5VDC Supplies
VS+
5
10µF
10Ω
6
DDC101
0.1µF
12
0.1µF
One +5VDC Supply
FIGURE 23. Positive Supply Connection Options.
®
23
DDC101
–5VDC
10µF
Reference Buffer Bypass
0.1µF
Analog Input
+5VDC
Guard
10µF
0.1µF
10Ω
0.1µF
1
VS– , ANALOG
24
2
ANALOG COMMON
23
3
ANALOG INPUT
22
4
ANALOG COMMON
21
5
VS+, ANALOG
20
6
VS+, ANALOG
19
7
18
8
17
9
16
10
15
11
14
12 VDD+, DIGITAL
13
REF1004 –2.5
10µF
1kΩ
VREF
–2.5V
10µF
Reference
Noise Filter
Reference
Bias
Resistor
25kΩ
VS–
DIGITAL GROUND
24-Lead SOIC
Top view
Analog Common
Digital Common
FIGURE 24. Example of Basic DDC101 Circuit Connections.
Reading Data Output
Data from the previous conversion can be read any time after
the DATA VALID output is activated and before the end of
the next conversion. Data is held in an internal serial shift
register until the end of the next conversion. The data must
be completely read before the end of the next conversion or
it will be overwritten with new data.
The time between “Final Data point Start” commands is the
Integration Time, TINT. The Measurement Time, TMEAS, is the
Integration time reduced by the Acquisition Time and by the
Oversampling Time, TOS.
TMEAS = TINT - TACQ - TOS.
When CDS is used; TOS, the oversampling time, is the time
required to collect a data point (M clock periods). Each
group of samples is averaged with the result at the midpoint
of each sample group. Therefore, with CDS, TOS = M clock
periods. This is shown in Figure 25.
Recommended Setup
The following Setup parameters are recommended, in general, for use with the DDC101 with integration times of 1ms
or longer. Multiple integrations per conversion, where practical, will provide lowest noise as illustrated in the typical
performance curves.
Measurement Time Calculation
FUNCTION
Two calculations of the Measurement Time are shown
FUNCTION
Acquisition Time, K
RECOMMENDED
CLOCK CYCLES
USER
CONTROLLED
1, 16, 32
Yes
Acquisition Clocks, K
16
Initial Data Point
Samples, M(1)
1, 2, 4, 8, 16, 32,64, 128, 256
Yes
Oversamples, M
128
Tracking Interval
Variable
Yes
Enabled
Final Data Point
Samples, M(1)
1, 2, 4, 8, 16, 32, 64, 128, 256
Yes
CDS
A Continuous Integration Cycle consists of the Acquisition
Time, Initial Data Point Collection, Tracking Interval, and
Final Data Point Collection. The user can select these
functions as illustrated in Table XV.
NOTE: (1) Will be the same in CDS mode, initial Data Point Samples = 0 in nonCDS mode.
TABLE XV. Components of Integration Cycle.
®
DDC101
24
N
Aquisition
Time, K
Time
Clock
Cycles
Oversampled
Initial Data Point
X
M
Tracking Interval
Final Data
Point Start
M
Oversampled
Final Data Point
X
Measurement Time
Digital
Output
DDC101 digital output is precise integration of input during measurement time.
FIGURE 25. DDC101 Equivalent Integrator Output for Single Integration with CDS.
FUNCTION
USER SETTING
(Clock Cycles)
Integration Time (TINT)
Acquisition Time K
(TACQ)
Initial Data Point
Samples, M
16
128
TIME
Integration Time (TINT)
8µs
Acquisition Time, K
(TACQ) “No CDS”
64µs
Initial Data Point
Samples
928µs
128
USER SETTING
(Clock Cycles)
FUNCTION
1ms
Measurement Time
Final Data Point
Samples, M
MEASUREMENT
(Calculated)
TIME
MEASUREMENT
(Calculated)
1ms
1
0.5µs
None
0µs
Measurement Time
967.5µs
Final Data Point
Samples, M
64µs
128
64µs
TABLE XVI. Measurement Time with CDS.
TABLE XVII. Measurement Time without CDS.
below: one with Correlated Double Sampling (CDS) and the
other without CDS. Each example assumes that the recommended system clock frequency of 2MHz is used and that
the time between “Final Data point Start” commands, (the
integration time, TINT) is 1ms.
Input Current Calculation
The following formula calculates the input current from the
actual DDC output:
Example with CDS. The Measurement Time with CDS is
calculated as the Integration Time (TINT) of 1ms less TACQ
and TOS. TOS, the oversampling time, is 1/2 of the Initial Data
Point time plus 1/2 the Final Data Point time since each
group of samples is averaged with the result at the midpoint
of each sample group.
Therefore, the Measurement Time = 1ms –(8 + 32 + 32)µs
= 928µs.
Example without CDS. The Measurement Time without
CDS is calculated as the Total Integration Time (TINT) of
1ms less TACQ and TOS. TOS, the oversampling time, is 1/2 of
the Final Data Point time since this group of samples is
averaged with the result at the midpoint of the sample group.
Therefore, the Measurement Time = 1ms –(0.5 + 32)µs
= 967.5µs.
With CDS:
DDC output 
500pC • 

2 20

i=
T MEAS
i=
T INT
Without CDS:
i=
T INT
DDC output 
500pC • 

2 20

– K clock periods – M clock periods
DDC output 
500pC • 

2 20

i=
T MEAS
DDC output 
500pC • 

2 20

– K clock periods – M / 2 clock periods
®
25
DDC101
DATA
INPUT
DDC101
DATA
OUTPUT
DATA
TRANSMIT
In
DATA
INPUT
DDC101
DATA
TRANSMIT
In
DATA
OUTPUT
DATA
INPUT
DDC101
DATA
OUTPUT
DATA
TRANSMIT
In
FIGURE 26. Daisy Chained DDC101s.
DDC101
DATA
INPUT
DATA OUTPUT
DATA TRANSMIT In
DDC101
DATA
INPUT
Data Output
DATA OUTPUT
DATA TRANSMIT In
DDC101
DATA
INPUT
DATA OUTPUT
DATA TRANSMIT In
Enable
FIGURE 27. DDC101 Parallel Operation.
MULTIPLE DDC101 OPERATION
Multiple DDC101 units can be connected in serial or parallel
configuration as illustrated in Figures 26 and 27.
a complete evaluation of the performance of the DDC101 is
an IBM compatible PC with EGA or VGA graphics, a
parallel interface port, a laser printer (optional), a ±5VDC
power supply, and a signal source.
The DEM-DDC101P-C software is mouse compatible and
retrieves data from up to 32 DDC101s in an easy to read,
graphical format on the screen. The DEM-DDC101P-C
Evaluation Fixture includes a PC Interface Board (with
necessary parts), a DDC101 Board, a 25-pin ribbon connector and a 34-pin ribbon connector. The PC Interface Board
makes timing commands and access to and from the DDC101
test board possible through the provided PC software. Data
sheet, LI-439, provides complete information describing the
evaluation fixture.
DATA OUTPUT can be used with DATA INPUT to “daisy
chain” the output of several DDC101 units together to
minimize wiring; in this mode of operation, the serial data
output is shifted through multiple DDC101s (Figure 26).
DATA OUTPUT is in a high impedance state until DATA
TRANSMIT In is active. In this way, several DDC101 units
can be connected in parallel to be enabled by the DATA
TRANSMIT In line (Figure 27).
DDC101 EVALUATION FIXTURE
The DEM-DDC101P-C Evaluation Fixture is highly recommended for initial evaluation of the DDC101. It is designed
for ease of use. The only additional equipment required to do
®
DDC101
26
FIGURE 28. Photo of DEM-DDC101P-C Evaluation Fixture.
25 Pin Cable
PC Interface Board
Your PC
Analog Input
DUT Board Assembly
34 Pin Cable
±5VDC
+5VDC
Power Supply
FIGURE 29. DEM-DDC101P-C Evaluation Fixture Connection Diagram.
®
27
DDC101
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jan-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DDC101U
NRND
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DDC101UG4
NRND
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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