Texas Instruments | Power-supply margining circuit for SMPS using a precision DAC (Rev. A) | Application notes | Texas Instruments Power-supply margining circuit for SMPS using a precision DAC (Rev. A) Application notes

Texas Instruments Power-supply margining circuit for SMPS using a precision DAC (Rev. A) Application notes
Analog Engineer's Circuit: Data
Converters
SBAA342A – January 2019 – Revised September 2019
Power-supply margining circuit for SMPS using
a precision DAC
Uttama Kumar Sahu
Design Goals
Power Supply (DAC
VDD)
Nominal Output
Margin High
Margin Low
5V
5V
5V + 10%
5V – 10%
Design Description
A power-supply margining circuit is used for tuning the output of a power converter. This is done either to
adjust the offset and drift of the power-supply output or to program a desired value at the output.
Adjustable power supplies like LDOs and DC/DC converters provide a feedback or adjust input that is
used to set the desired output. A precision voltage output DAC is suitable for controlling the power-supply
output linearly. An example power-supply margining circuit is shown in the following figure. Typical
applications of power-supply margining is in Test and Measurement, Communications Equipment, and
General Purpose Power Supply Modules.
L
VIN
IN
PH
SMPS
VOUT
BOO T
CB
SENSE
CL
R1
R3
DAC
VFB
GND
R2
RPUL L-DOWN
GND
Design Notes
1. Choose a DAC with required resolution, pulldown resistor value, and output range
2. Derive the relationship of the DAC output to VOUT
3. Choose R1 based on typical current through the feedback circuit
4. Calculate the start-up or nominal value of VDAC, considering the power-down and power-up conditions
of the DAC
5. Select R2, and R3 such that the desired start-up output voltage is met along with the DAC output
voltage range for the desired tuning range
6. Calculate the margin low and margin high DAC outputs
7. Choose a compensation capacitor to get the desired step response
SBAA342A – January 2019 – Revised September 2019
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Design Steps
1. Select the switching DC/DC converter TPS5450 for the calculations. The DAC53608 device is an ultralow cost, 10-bit, 8-channel unipolar output DAC suitable for such applications
2. The output voltage of the power supply is given by
(
)
V O UT = V RE F + I 1 R 1 = V RE F + I 2 + I 3 R 1
where
•
•
•
I1 is the current flowing through R1
I2 is the current flowing through R2
I3 is the current flowing through R3
DACs in this application typically include power-down mode, which includes an internal pulldown
resistor at the voltage output. Hence, replacing the values of the currents in the previous equation
yields:
• When DAC is in power-down mode:
æ æ V REF
V OUT = V REF + ç ç
çç R 2
èè
•
ö æ
V REF
÷+ç
÷ ç R 3 + R PULL -DOW N
ø è
öö
÷÷ R1
÷÷
øø
When DAC output is powered-up:
æ æ V REF
V OUT = V REF + ç ç
çç R 2
èè
ö æ V REF - V DAC
÷+ç
÷ ç
R3
ø è
öö
÷÷ R1
÷÷
øø
For DAC53608, RPULLDOWN is 10kΩ. For the LDO device TPS5450, the value of VREF is 1.221V.
3. R1 can be calculated with the following method:
The current through the FB pin of the TPS5450 device is negligible. Select I1 to be 50µA. So, R1 is
calculated as follows:
R1 =
V OUT - V REF
= 75.6 k W
I1
The nominal value of I1 is given by:
• When DAC is in power-down mode:
æ V REF ö æ
ö
V REF
I 1-Nom = ç
÷+ç
÷
ç R 2 ÷ ç R 3 + 10 k W ÷
è
ø è
ø
•
When DAC output is powered-up:
æ V REF
I 1-Nom = ç
ç R2
è
ö æ V REF - V DAC
÷+ç
÷ ç
R3
ø è
ö
÷
÷
ø
The values of I1 at margin high and margin low outputs are given by:
I 1-HIGH =
I 1-LOW =
I 1-LOW =
VOUT -HIGH - V REF
R1
VOUT -LOW - V REF
R1
VOUT -LOW - V REF
R1
= 56.6μA
= 43.4
= 43.4
4. The nominal, or startup value of VDAC is calculated by the following method:
To make sure the 10-kΩ resistor does not impact when the DAC is transitioning from power-down to
power-up, the power-up value for the DAC voltage is calculated with:
V REF
R 3 + 10 k W
2
=
V REF - V DAC
R3
Power-supply margining circuit for SMPS using a precision DAC
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The previous equation is further simplified to:
æ 10 k W
ö
V DAC = V REF ç
÷
ç R 3 + 10 k W ÷
è
ø
5. The values of R2 and R3 are calculated as follows:
If the power-up or nominal value of VDAC is kept at 1/3 of VREF, that is, 407mV, then R3 is 2 × 10kΩ =
20kΩ. And, R2 can be calculated as:
V REF
R2
+
V REF
R 3 + 10 k W
= 50μA
Replacing the value of R3, calculate R2 = 131.3kΩ.
6. Subtracting the margin high and nominal values of I1 and the corresponding equations yields:
V REF - V DAC
R3
-
V REF
R 3 + 10 k W
= 6.6μA
The margin high value of VDAC is 275mV and similarly, the margin low value is calculated as 539mV
using the following equation:
V REF
R 3 + 10 k W
-
V REF - V DAC
R3
- = 6.6μA
7. The step response of this circuit without a compensation capacitor causes the inductor current to reach
its limit as shown in the following figure. This kind of surge can take the inductor into saturation. To
minimize the surge, a compensation capacitor C1 is used as the circuit diagram shows. The value of
this capacitance is usually obtained through simulation. A comparative output shows the waveforms
with a compensation capacitor of 10nF.
Output With DAC in Power Down Mode
SBAA342A – January 2019 – Revised September 2019
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Small-Signal Step Response Without Compensation
Small-Signal Step Response With C1 = 10nF
4
Power-supply margining circuit for SMPS using a precision DAC
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Design Featured Devices and Alternative Parts
Device
Key Features
DAC53608
8-channel 10-bit, I2C interface, buffered-voltage-output digital-to-analog converter (DAC) http://www.ti.com/product/DAC53608
Link
DAC60508
8-channel, true 12-bit, SPI, voltage-output DAC With precision internal reference
http://www.ti.com/product/DAC60508
DAC60501
12-bit, 1-LSB INL, digital-to-analog converter (DAC) with precision internal reference
http://www.ti.com/product/DAC60501
DAC8831
16-bit, ultra-low power, voltage output digital to analog converter
http://www.ti.com/product/DAC8831
TPS5450
5.5-V to 36-V input, 5-A, 500-kHz step-down converter
http://www.ti.com/product/TPS5450
Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
TINA source files – http://www.ti.com/lit/zip/sbam416.
For direct support from TI Engineers use the E2E community
e2e.ti.com
Revision History
Revision
Date
A
September 2019
Change
Updated the circuit image on the first page.
SBAA342A – January 2019 – Revised September 2019
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