Texas Instruments | Power-supply margining circuit for LDOs using a precision DAC (Rev. A) | Application notes | Texas Instruments Power-supply margining circuit for LDOs using a precision DAC (Rev. A) Application notes

Texas Instruments Power-supply margining circuit for LDOs using a precision DAC (Rev. A) Application notes
Analog Engineer's Circuit: Data
Converters
SBAA341A – January 2019 – Revised September 2019
Power-supply margining circuit for LDOs using a
precision DAC
Uttama Kumar Sahu
Design Goals
Power Supply (VDD)
Nominal Output
Margin High
Margin Low
5V
3.3V
3.3V + 10%
3.3V – 10%
Design Description
A power-supply margining circuit is used for tuning the output of a power converter. This is done either to
adjust the offset and drift of the power supply output or to program a desired value at the output.
Adjustable power supplies like Low-Dropout Regulators (LDOs) and DC/DC converters provide a feedback
or adjust input that is used to set the desired output. A precision voltage output digital-to-analog converter
(DAC) is suitable for controlling the power-supply output linearly. The following image shows an example
power-supply margining circuit. Typical applications of power-supply margining is in Test and
Measurement, Communications Equipment, and Power Delivery.
VIN
OUT
IN
VOUT
R1
LDO
ADJ
C1
R3
VFB
DAC
GND
R2
RPUL L-DOWN
GND
GND
GND
Design Notes
1. Choose a DAC with the required resolution, pulldown resistor value, and output range.
2. Derive the relationship of the DAC output to VOUT.
3. Choose R1 based on typical current through the feedback circuit.
4. Calculate the start-up or nominal value of VDAC considering the power-down and power-up conditions of
the DAC.
5. Select R2, and R3 such that the desired start-up output voltage is met along with the DAC output
voltage range for the desired tuning range.
6. Calculate the margin low and margin high DAC outputs.
7. Choose a compensation capacitor to achieve the desired step response.
SBAA341A – January 2019 – Revised September 2019
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Design Steps
1. Select the LDO TPS79501 device for the calculations. The DAC53608 device is an ultra-low cost, 10bit, 8-channel, unipolar output DAC suitable for such applications
2. The output voltage of the power supply is given by:
VOUT VREF I1R1 VREF I2 I3 R1
where
•
•
•
I1 is the current flowing through R1
I2 is the current flowing through R2
I3 is the current flowing through R3
DACs in this application typically include power-down mode, which includes an internal pulldown
resistor at the voltage output. Hence, replacing the values of the currents in the previous equation
yields:
• When the DAC is in Power Down mode:
ææ V
VOUT = VREF + ç ç REF
ç R
2
èè
•
ö æ
VREF
÷+ç
+
R
R
ø è 3
PULL-DOW N
öö
÷ ÷÷ R1
øø
When the DAC output is powered-up:
ææ V
ö æV
- VDAC ö ö
VOUT = VREF + ç ç REF ÷ + ç REF
÷ ÷÷ R1
ç R
R3
øø
èè 2 ø è
For DAC53608, RPULL-DOWN is 10kΩ. For the LDO part number TPS79501, the value of VREF is 1.225V.
3. R1 can be calculated by the following method.
The current through the FB pin of TPS79501 is 1µA. To make this current negligible, I1 should be >>
IFB. Choose I1 to be 50µA. Calculate R1 as follows:
R1 =
VOUT - VREF
= 41.5 k W
I1
The nominal value of I1 can be given by:
• When the DAC is in Power Down mode
ö
æV
ö æ
VREF
I1-Nom = ç REF ÷ + ç
÷
+
W
R
R
10
k
è
2 ø è 3
ø
•
When the DAC output is powered-up
æV
I1-Nom = ç REF
è R2
ö æ VREF - VDAC ö
÷
÷+ç
R3
ø è
ø
The values of I1 at Margin High and Margin Low outputs are given by:
I1-HIGH =
VOUT -HIGH - VREF
= 57.95 mA
R1
I1-LOW =
VOUT -LOW - VREF
= 42.05 mA
R1
I1-H IG H - I1-N om = I1-N om - I1-LO W = 7.65 m A
4. The nominal or startup value of VDAC can be calculated using the following method:
To make sure the 10-kΩ resistor does not impact when the DAC is transitioning from power-down to
power-up, the power-up value for the DAC voltage can be calculated with:
V
- VDAC
VREF
= REF
R 3 + 10 k W
R3
The previous equation can be further simplified to:
æ 10 k W ö
VDAC = VREF ç
÷
è R3 + 10 k W ø
2
Power-supply margining circuit for LDOs using a precision DAC
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5. The values of R2 and R3 can be calculated as follows:
If the power-up or nominal value of VDAC is kept at one-third of VREF, that is, 408.3mV, then R3 will be 2
× 10kΩ = 20kΩ. R2 can be calculated as:
VREF
VREF
+
= 50 mA
R2
R 3 + 10 k W
Replacing the value of R3, R2 can be calculated to equal 133kΩ.
6. Subtracting the Margin High and Nominal values of I1 and the corresponding equations, we get
VREF - VDAC
VREF
= 7.95 mA
R3
R 3 + 10 k W
So, the Margin High value of VDAC will be 249mV and similarly, the Margin Low value can be calculated
as 567mV from the following equation:
- VDAC
V
VREF
- REF
= 7.95 mA
R 3 + 10 k W
R3
7. The step response of this circuit without a compensation capacitor has some overshoot and ringing as
shown in the following curves. This kind of transient response can cause errors at the load circuits. To
minimize this, use a compensation capacitor C1. The value of this capacitance is usually obtained
through simulation. A comparative output shows the waveforms with a compensation capacitor of
22pF.
SBAA341A – January 2019 – Revised September 2019
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DC Transfer Characteristics
T
5.00
VDAC: 249mV
VOUT: 3.63V
VOUT (V)
VDAC: 567mV
VOUT: 2.97V
VDAC: 408.3mV
VOUT: 3.3V
2.00
0.00
500.00m
VDAC (V)
1.00
Small Signal Step Response Without Compensation
Small-Signal Step Response With C1= 22pF
4
Power-supply margining circuit for LDOs using a precision DAC
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Design Featured Devices and Alternative Parts
Device
Key Features
Link
DAC53608
8-channel 10-bit, I2C interface, buffered-voltage-output DAC
http://www.ti.com/product/DAC53608
DAC60508
8-channel, true 12-bit, SPI, voltage-output DAC with precision internal reference
http://www.ti.com/product/DAC60508
DAC60501
12-bit, 1-LSB INL, DAC with precision internal reference
http://www.ti.com/product/DAC60501
DAC8831
16-bit, ultra-low power, voltage output DAC
http://www.ti.com/product/DAC8831
TPS79501-Q1
Automotive catalog single output LDO, 500mA, adj.(1.2 to 5.5V), low-noise, high PSRR
http://www.ti.com/product/TPS79501-Q1
Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
TINA source files – http://www.ti.com/lit/zip/sbam415.
For direct support from TI Engineers use the E2E community
e2e.ti.com
Revision History
Revision
Date
A
September 2019
Change
Updated circuit image on first page.
Fixed typographical error in the first equation on the third page.
SBAA341A – January 2019 – Revised September 2019
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Power-supply margining circuit for LDOs using a precision DAC
Copyright © 2019, Texas Instruments Incorporated
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