Texas Instruments | Designing a Cost-Optimized DAQ Solution (Rev. B) | Application notes | Texas Instruments Designing a Cost-Optimized DAQ Solution (Rev. B) Application notes

Texas Instruments Designing a Cost-Optimized DAQ Solution (Rev. B) Application notes
Designing a Small-Size and Cost-Optimized Multi-Channel
Data Acquisition System
Rahul Kulkarni, Data Converter Products
In applications like patient monitoring, optical line
cards, and test and measurement, there are several
signals that need to be measured. This application
note presents a cost optimized, low-power, and smallsize solution for a multichannel data acquisition
system. The ADS8168 features a high-precision, 16
bit, 1 MSPS, SAR ADC with an eight channel
multiplexer, low thermal drift voltage reference,
precision reference buffer, and refby2 buffer for signal
biasing.
Challenges in Signal Chain Design with
Multichannel ADC
Multichannel ADC
R
AIN0
Signal input
+
AIN1
Amplifier
C
AIN2
ADC
R
AIN7
Signal input
To achieve a full sampling rate, the charge-kickback
created by the ADC must be settled to be within 0.5
LSB of the ADC resolution. An ADC driver amplifier
with more than 20-MHz bandwidth and low-output
impedance is required to settle the charge-kickback.
Every MUX input must be driven by an ADC driver
amplifier to settle the charge-kickback.
The conventional circuit, shown in Figure 1, needs
eight ADC driver amplifiers which increase system
size, power, and cost. There is increased channel-tochannel performance mismatch as the amplifiers
exhibit independent thermal drifts and offset errors.
Refer to the TI Precision Labs – ADCs for more details
on driving SAR ADC inputs.
Simplified Design with ADS8168
+
Amplifier
When the sample-and-hold circuit connects to AIN0, a
charge-kickback is created by the ADC sampling
capacitor, CADC, and the MUX parasitic capacitor, CMUX.
The sampling capacitor of the ADC (typically 60 pF) is
much larger than the MUX parasitic capacitance
(typically 10 pF), hence ADC dominates the chargekickback created at the MUX inputs.
MUXOUT-P
C
ADC-INP
Low output
impedance buffers
ADS8168
AIN0
Figure 1. DAQ System Using Conventional
Multichannel ADC
AIN1
AIN2
AIN3
Figure 1 shows a typical multichannel data acquisition.
Figure 2 shows the equivalent model for the MUX
input channel AIN0 and ADC.
AIN4
MUX
ADC
Enhanced-SPI
AIN5
AIN6
4.096 V
AIN7
SWMUX
SWADC
RMUX
÷2
RADC
Channel
Sequencer
AIN0
REFIO
CMUX
REFby2
CADC
Figure 3. ADS8168 Block Diagram
Figure 2. Equivalent Model of Channel AIN0
Connected to ADC
RADC is the resistance of sample-and-hold switch,
SWADC, and CADC is the ADC sampling capacitor. RMUX
is the ON resistance of the MUX switch, SWMUX, and
CMUX is the equivalent parasitic capacitance of the
MUX.
SBAA308B – June 2019 – Revised June 2019
Submit Documentation Feedback
The ADS8168 is a 16 bit, eight channel, SAR ADC
with integrated reference and refby2 buffer and an
Enhanced-SPI digital interface. For a complete list of
devices in the ADS8168 device family, see Table 1. In
ADS8168, the output of the multiplexer and ADC
inputs are available to be used externally as shown in
Figure 3. An ADC driver amplifier, common to all
multiplexer channels, can be used as shown in
Figure 4.
Designing a Small-Size and Cost-Optimized Multi-Channel Data Acquisition
System Rahul Kulkarni, Data Converter Products
Copyright © 2019, Texas Instruments Incorporated
1
www.ti.com
R
Buffer
C
The ADS8168EVM-PDK is designed with the common
buffer amplifier topology shown in Figure 4. Figure 6
shows the FET plot for a 2-kHz sine way input signal.
+
0
-36
ADS8168
AIN0
Amplitude (dB)
Signal input
ADC
AIN1
AIN2
4.096V
-72
-108
Signal input
÷2
AIN7
REFIO
REFby2
-144
-180
REFby2 voltage for mid-scale biasing
0
Figure 4. Low-Cost, Small-Size, Precision DAQ
System Using ADS8168
Figure 5 shows an equivalent model of AIN0 and ADC.
Charge-kickback from the ADC is settled by the ADC
driver between the multiplexer output and the ADC
input. Hence, there is no charge-kickback at the
multiplexer inputs due to the ADC sampling capacitor.
ADC driver
Multiplexer
output
SWMUX
ADC
input
SWADC
100
200
300
fIN, Input Frequency (kHz)
400
500
D001
fIN = 2 kHz, SNR = 92 dB, THD = –109 dB
Figure 6. FFT Plot: AC Performance on
ADS8168EVM-PDK
Conclusion
The ADS8168 enables design of a small-size and
cost-optimized multichannel data acquisition system
because:
• MUX breakout allows single ADC driver
• Extended settling time for high-impedance sources
• Integration of reference and refby2 buffer enables
smaller system size
RADC
RMUX
Table 1. ADS8168 Device Family
AIN0
CMUX
CADC
Device
Sampling
Rate
ADS8168
1000 kSPS
ADS8167
500 kSPS
ADS8166
250 kSPS
Description
ADS8168
Figure 5. Equivalent Model of ADS8168 Analog
Input
16-bit, 8-channel, high-precision, SAR
ADC with integrated reference and
refby2 buffer
Table 2. Related Documentation
The ADS8168 supports extended settling time for
analog signal inputs, which allows tCYCLE – 100 ns
settling time at the multiplexer inputs. See the section
on Early Switching for Direct Sensor Interface in the
ADS8168 datasheet for more details. The extended
settling time and small charge-kickback at the
multiplexer input enables connecting high-impedance
sources without amplifiers.
2
Type
Title
Application Note
Optimizing Data Transfer on High-Resolution,
High-Throughput Data Converters (SBAA249)
Application Note
Optimizing Data Transfer on High-Resolution,
High-Throughput Data Converters (SBAA249)
Application Note
Improving Input Settling for Precision Data
Converters (SBAA250)
Product List
List of ADCs with Enhanced-SPI Interface
Designing a Small-Size and Cost-Optimized Multi-Channel Data Acquisition
System Rahul Kulkarni, Data Converter Products
Copyright © 2019, Texas Instruments Incorporated
SBAA308B – June 2019 – Revised June 2019
Submit Documentation Feedback
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