Texas Instruments | Low-power sensor measurements: 3.3-V, 1-ksps, 12-bit, single-ended, dual-supply (Rev. A) | Application notes | Texas Instruments Low-power sensor measurements: 3.3-V, 1-ksps, 12-bit, single-ended, dual-supply (Rev. A) Application notes

Texas Instruments Low-power sensor measurements: 3.3-V, 1-ksps, 12-bit, single-ended, dual-supply (Rev. A) Application notes
Analog Engineer's Circuit: Data
Converters
SBAA251A – November 2017 – Revised March 2019
Low-power sensor measurements: 3.3-V, 1-ksps, 12-bit,
single-ended, dual-supply circuit
Reed Kaczmarek
Input
ADC Input
Digital Output ADS7042
VinMin = 0V
AIN_P = 0V, AIN_M = 0V
000H or 010
VinMax = 3.3V
AIN_P = 3.3V, AIN_M = 0V
FFFH or 409610
Power Supplies
AVDD
Vee
Vdd
3.3V
–0.3V
4.5V
Design Description
This design shows an low-power amplifier being used to drive a SAR ADC that consumes only nW of
power during operation. This design is intended for systems collecting sensor data and require a lowpower signal chain which only burns single-digit µW of power. PIR sensors, gas sensors, and glucose
monitors are a few examples of power-sensitive systems that benefit from this SAR ADC design. The
values in the component selection section can be adjusted to allow for different data throughput rates and
different bandwidth amplifiers. Low-Power Sensor Measurements: 3.3 V, 1 ksps, 12-bit Single-Ended,
Single Supply shows a simplified version of this circuit where the negative supply is grounded. The –0.3-V
negative supply in this example is used to achieve the best possible linear input signal range. See SAR
ADC Power Scaling for a detailed description of trade-offs in low-power SAR design.
AVDD 3.3V
Vdd 4.5V
0.1 F
0.1 F
Rfilt
200kŸ
-+
LPV811
+
+
VSENSOR
AVDD
AinP
Cfilt
510pF
Vee -0.3V
AinM
ADS7042
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Specifications
Specification
Calculated
Simulated
< 0.5 × LSB = 402µV
41.6µV
N/A
AVDD Supply Current (1ksps)
230nA
N/A
214.8nA
AVDD Supply Power (1ksps)
759nW
N/A
709nW
VDD OPAMP Supply Current
450nA
N/A
431.6nA
VDD OPAMP Supply Power
2.025µW
N/A
1.942µW
AVDD + VDD System Power (1ksps)
2.784µW
N/A
2.651µW
Transient ADC Input Settling (1ksps)
Measured
Design Notes
1. Determine the linear range of the op amp based on common mode, output swing, and linear open loop
gain specification. This is covered in the component selection section.
2. Select a COG (NPO) capacitor for Cfilt to minimize distortion.
3. The TI Precision Labs – ADCs training video series covers methods for selecting the charge bucket
circuit Rfilt and Cfilt (see Introduction to SAR ADC Front-End Component Selection). These component
values are dependent on the amplifier bandwidth, data converter sampling rate, and data converter
design. The values shown here will give good settling and AC performance for the amplifier and data
converter in this example. If you modify the design you will need to select a different RC filter.
2
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Component Selection
1. Select a low-power op amp:
• Supply current < 0.5µA
• Gain bandwidth product > 5kHz (5 times the sampling rate)
• Unity gain stable
• LPV811 – 450-nA supply current, 8-kHz gain bandwidth product, unity gain stable
2. Find op amp maximum and minimum output for linear operation:
3. Typical power calculations (at 1ksps) with expected values. See SAR ADC Power Scaling for a
detailed description of trade-offs in low-power SAR design:
4. Typical power calculations (at 1ksps) with measured values:
5. Find Rfilt and Cfilt to allow for settling at 1ksps. Refer to Refine the Rfilt and Cfilt Values (a Precision
Labs video) for the algorithm to select Rfilt and Cfilt. The final value of 200kΩ and 510pF proved to
settle to well below ½ of a least significant bit (LSB).
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DC Transfer Characteristics
The following graph shows a linear output response for inputs from 0 to 3.3V. The full-scale range (FSR)
of the ADC falls within the linear range of the op amp. Refer to Determining a SAR ADC’s Linear Range
when using Operational Amplifiers for detailed theory on this subject.
Op Amp Output (V)
5.0
4.0
3.0
2.0
Vin=3.3V
Vout=3.3V
Vin=0V
Vout=55uV
1.0
0.0
-1.0
-1.0
0.0
1.0
2.0
3.0
Op Amp Input VSENSOR (V)
4.0
5.0
AC Transfer Characteristics
The bandwidth simulation includes the effects of the amplifier output impedance and the RC charge
bucket circuit (Rfilt and Cfilt).The bandwidth of the RC circuit is shown in the following equation to be
1.56kHz. The simulated bandwidth of 2kHz includes effects from the output impedance interacting with the
impedance of the load. See TI Precision Labs - Op Amps: Bandwidth 1 for more details on this subject.
Gain (dB)
T
0.00
fc = 2kHz
-24.60
Phase [deg]
-49.21
0.00
-207.14
-413.84
10
4
100
1k
Frequency (Hz)
Low-power sensor measurements: 3.3-V, 1-ksps, 12-bit, single-ended, dualsupply circuit
10k
100k
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Transient ADC Input Settling Simulation
The following simulation shows settling to a 3-V DC input signal. This type of simulation shows that the
sample and hold kickback circuit is properly selected to within ½ of an LSB (402µV). Refer to Introduction
to SAR ADC Front-End Component Selection for detailed theory on this subject.
1.00
T
Vacq
0.00
0.00
Verror
41.6µV
Verror
-10.00m
2.55m
Time (s)
2.00m
3.10m
Noise Simulation
This section walks through a simplified noise calculation for a rough estimate. We neglect resistor noise in
this calculation as it is attenuated for frequencies greater than 10kHz.
Note that the calculated and simulated values match well. Refer to Calculating the Total Noise for ADC
Systems for detailed theory on this subject.
T
16.84u
Total noise (V)
Vn = 16.84uV rms
8.42u
0.00
1
10
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100
1k
10k
100k
Frequency (Hz)
1MEG 10MEG
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Measure FFT
This performance was measured on a modified version of the ADS7042EVM with a 10-Hz input sine
wave. The AC performance indicates SNR = 71.0dB, THD = –82.4dB, and ENOB (effective number of
bits) = 11.51, which matches well with the specified performance of the ADC, SNR = 70dB and THD =
–80dB. This test was performed at room temperature. See Introduction to Frequency Domain for more
details on this subject.
Measured FFT and AC Performance for ADS7042 and LPV811 Dual Supply
SNR = 71.0 dB
THD = -82.4 dB
ENOB = 11.51
Signal Power = -0.05 dBFS
Fundamental at 2kHz
Design Featured Devices
Device
Key Features
Link
Similar Devices
ADS7042 (1)
12-bit resolution, SPI, 1-Msps sample rate, single-ended input,
AVDD reference input range 1.6 V to 3.6 V.
www.ti.com/product/ADS7042
www.ti.com/adcs
LPV811 (2)
8-kHz bandwidth, rail-to-rail output, 450-nA supply current, unity
gain stable
www.ti.com/product/LPV811
www.ti.com/opamp
(1)
(2)
The ADS7042 uses the AVDD as the reference input. A high-PSRR LDO, such as the TPS7A47, should be used as the power
supply.
The LPV811 is also commonly used in low-speed applications for sensors. Furthermore, the rail-to-rail output allows for linear
swing across the entire ADC input range.
Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files (TINA)
Design files for this circuit – http://www.ti.com/lit/zip/sbam342.
Revision History
6
Revision
Date
A
March 2019
Change
Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.
Low-power sensor measurements: 3.3-V, 1-ksps, 12-bit, single-ended, dualsupply circuit
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