Texas Instruments | ADS856x Design Challenges and Improvement Techniques for SAR Driver Circuit (Rev. A) | Application notes | Texas Instruments ADS856x Design Challenges and Improvement Techniques for SAR Driver Circuit (Rev. A) Application notes

Texas Instruments ADS856x Design Challenges and Improvement Techniques for SAR Driver Circuit (Rev. A) Application notes
Application Report
SLAA571A – November 2012 – Revised May 2015
Design Challenges and Improvement Techniques for SAR
ADC Driver Circuit
Dale Li................................................................................... High Performance Analog/Field Application
ABSTRACT
Driver circuit design of switched-capacitor successive approximation register (SAR) analog-to-digital
converters (ADC) is critical. The ADS8568 is a typical device using this kind of architecture. The
ADS8568’s 8-channel, 16-bit, simultaneous sampling ADC with true bipolar input, supports up to 510KSPS sampling rate per channel. The ADS8568’s structure is perfectly suitable for relay measurement
and protection systems of industrial power automation applications. This application report presents the
solution with the system performance improvement techniques to resolve the challenges of designing the
driver circuit for the ADS8568 with comparison tests that also demonstrate these performance
improvements.
used for break, so List of Tables title will go to next page
1
2
3
4
5
6
7
8
Contents
Introduction ................................................................................................................... 2
Design Challenge for a Driver Circuit Without An Amplifier ............................................................ 3
2.1
Driver Circuit Without an Amplifier................................................................................ 3
2.2
Sampling Rate and Acquisition Time............................................................................. 3
2.3
Design Challenge for the Driver Circuit .......................................................................... 4
2.4
Improvement Techniques .......................................................................................... 6
Performance Test ............................................................................................................ 6
3.1
Test System ......................................................................................................... 6
3.2
Performance Comparison Test ................................................................................... 7
Conclusion .................................................................................................................... 8
References ................................................................................................................... 8
Appendix A. FFT for Second-Order Filter (RFLT = 10 kΩ, CFLT = 22 nF) .............................................. 9
Appendix B. FFT for First-Order Filter (RFLT = 10 kΩ, CFLT = 22 nF) ................................................. 11
Appendix C. FFT for First-Order Filter (RFLT = 10 kΩ, CFLT = 820 pF) ............................................... 13
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
....................................................................................... 2
ADS8568’s Driver Circuit Without a Front-End Amplifier ............................................................... 3
ADS8568’s Acquisition Time and Conversion Time..................................................................... 4
Simplified Model for First-Order RC Filter ................................................................................ 4
Performance Test System for the ADS8568 Circuit ..................................................................... 6
FFT for 10-KSPS Sampling Rate (VS = –0.5 dBFS) .................................................................... 9
FFT for 4-KSPS Sampling Rate (VS = –0.5 dBFS) ...................................................................... 9
FFT for 1-KSPS Sampling Rate (VS = –0.5 dBFS) .................................................................... 10
FFT for 10-KSPS Sampling Rate (VS = –0.5 dBFS) ................................................................... 11
FFT for 4-KSPS Sampling Rate (VS = –0.5 dBFS) .................................................................... 11
FFT for 1-KSPS Sampling Rate (VS = –0.5 dBFS) .................................................................... 12
FFT for 10-KSPS Sampling Rate (VS = –0.5 dBFS) ................................................................... 13
Typical Driver Circuit for SAR ADC
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Introduction
13
14
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....................................................................
FFT for 1-KSPS Sampling Rate (VS = –0.5 dBFS) ....................................................................
FFT for 4-KSPS Sampling Rate (VS = –0.5 dBFS)
13
14
List of Tables
Test Result for Second-Order Filter – RFLT = 10 kΩ, CFLT = 22 nF (unit: dBc)
7
2
Test Result for First-Order Filter – RFLT = 10 kΩ, CFLT = 22 nF (unit: dBc)
7
3
1
.......................................
...........................................
Test Result for First-Order Filter – RFLT = 10 kΩ, CFLT = 820 pF (unit: dBc) ..........................................
1
7
Introduction
In power line measurement and protection systems, it is often required to simultaneously sample large
numbers of voltage and current channels in multi-phase power distribution and transmission networks and
critical to have the simultaneous sampling capability to maintain the phase information between the
voltage and current channels. The ADS8568 is the 8-channel, 16-bit simultaneous sampling SAR ADC
with true bipolar input up to ±12 V; these features make it ideal for capturing voltage and current signals
from PT(Voltage Transformer) and CT(Current Transformer) with an operational amplifier or directly in this
kind of system application.
SAR ADC
Signal Source
V CSH
R
-
S1
FLT
R
RS
S2
+
+
VS
S1
C
OP AMP
C SH
FLT
V
SH0
Figure 1. Typical Driver Circuit for SAR ADC
For optimum SAR-ADC performance, the recommended driver circuit is an operational amplifier used in
combination with an RC (resistor-capacitor) filter as shown in Figure 1. This driver circuit’s major functions
include:
• Signal conditioning for input signal from the source
• Filter function
• Isolation between the signal source and ADC
• Providing enough charges to the internal sampling capacitor of SAR ADC which uses the switched
capacitor array architecture
The driver circuit must have the ability to charge the ADC’s internal input sampling capacitor to the proper
value and maintain stability during the ADC’s acquisition period. The CFLT provides a nearly perfect input
source to the SAR ADC. RFLT keeps the amplifier stable by isolating the amplifier’s output stage from the
capacitive load. The selection of components for the driver circuit is important and the proper selections
make it possible to get the optimal system performance, including the value selections of RFLT and CFLT.
2
Design Challenges and Improvement Techniques for SAR ADC Driver Circuit
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2
Design Challenge for a Driver Circuit Without An Amplifier
To simplify the circuit design and save cost, it is popular to design the driver circuit of SAR ADCs without
any amplifier in power line measurement and protection systems. Engineers only use one first-order
passive RC filter and sometimes a second-order RC filter is used to get faster roll-off and stop-band
attenuation.
But if proper care is not taken with system architecture or if the correct value of components RFLT and CFLT
are not selected, the circuit could produce system errors and the system performance suffers in the area
of DC and AC performance, THD (total harmonic distortion), for example. THD is a very important system
parameter for industrial replay protection and an important measurement system in power automation
applications.
2.1
Driver Circuit Without an Amplifier
The circuit in Figure 2 is a typical circuit without a front-end amplifier used widely in industrial replay
protection and measurement systems. The second-order RC filter or much larger value RFLT and CFLT are
often used in this kind of application too, thus providing poor system performance. The operating
frequency for CT and PT isolation and measurement transformers is 50 Hz (or 60 Hz). The input signal is
usually ±10 V or ±5-V bipolar, 50-Hz sine wave from PT or CT (signal source, VS). To filter the noise and
get the optimal filter result, the larger value resistor (RFLT) and capacitor (CFLT) are usually used. This also
provides a lower cut-off frequency of the filter. The reason for using this big resistor is the demand of
isolation between the SAR ADC and signal resource because there is not any front-end amplifier. In
general, 20, 80 or 200 sample points per cycle is often used and depends on system demand, so the
sampling rate of the ADC is 1 KSPS, 4 KSPS, or 10 KSPS for a 50-Hz sine-wave input signal.
ADS8568
Signal Source
(PT/CT)
V CSH
RS
R
FLT
= 10 kΩ
R
FLT
= 10 kΩ
S1
R
S2
S1
+
C
VS
FLT
= 22 nF
C
FLT
= 22 nF
C SH
V
SH0
Figure 2. ADS8568’s Driver Circuit Without a Front-End Amplifier
After tests, the system performances are bad for this circuit configuration, including THD, SINAD (Signalto-Noise and Distortion ratio) and SFDR (Spurious Free Dynamic Range) performances. If the filter order
is increased, from first order to second order, the performances are worse. If the sampling rate is
increased, the performances for the same circuit are much worse.
2.2
Sampling Rate and Acquisition Time
SAR ADC’s sampling rate and acquisition times are important parameters in the design challenges. SAR
ADC’s sampling rate usually correlates to ADC’s acquisition time (tACQ) and conversion time (tCONV).
1
T=
= t ACQ + t CONV
tS
(1)
fS is the sampling rate.
For ADS8568,
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Figure 3. ADS8568’s Acquisition Time and Conversion Time
The conversion time (tCONV, 1.7 µs) in ADS8568’s data sheet is the maximum time the ADS8568 needs for
one conversion. The acquisition time (tACQ, 280 ns) in ADS8568’s data sheet is the minimum time to
specify excellent performance at the highest sampling rate. The real and operating acquisition time to
ADC depends on the real sampling rate because the conversion time is approximately fixed and the ADC
enters into the acquisition status automatically after the conversion is finished and when the BUSY signal
is going down.
2.3
Design Challenge for the Driver Circuit
When designing the driver circuit of switched-capacitor input structure SAR ADCs, the time constant (τFLT)
of the RC filter in front of the ADC or the equivalent time constant (τTOT) must be considered. This τFLT
determines the settling time of the filter. This time constant also depends on the acquisition time (tACQ) and
must be properly set so that k (the time constant multiplier) time constants are allowed during the
converter’s operating acquisition time.
Figure 4 shows a simplified model for the capacitive input stage of the circuit in Figure 2, if just
considering the first-order RC filter (see reference 2).
Figure 4. Simplified Model for First-Order RC Filter
Use the following equations according to the charge redistribution between CFLT and CSH:
t ACQ ³ k 3 ´ t
æ 1
ö
k 3 = ln ç
´ 2N+1 ÷ ,
1
a
+
è
ø
a=
CFLT
CSH
(2)
Where tACQ is acquisition time
k3 is new time-constant multiplier
τ is the time-constant
4
Design Challenges and Improvement Techniques for SAR ADC Driver Circuit
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N is data converter’s resolution
For the first-order RC filter system in Figure 2,
C
22 nF
a = FLT =
= 1100
CSH
20 pF
(3)
So,
1
æ 1
ö
æ
ö
´ 2N+1 ÷ = ln ç
´ 216 +1 ÷ = 4.78
k 3 = ln ç
è a +1
ø
è 1100 + 1
ø
(4)
When ADS8568’s sampling rate (fS) is 10 KSPS, the operating acquisition time is,
1
1
t ACQ =
- t CONV =
´ 106 - 1.7ms = 98.3ms
fS
10k
(5)
Calculate the required time constant of ADC,
t
09.3ms
t1 £ ACQ =
= 20.56ms
k3
4.78
(6)
When ADS8568’s sampling rate (fS) is 4 KSPS, the operating acquisition time is,
1
1
t ACQ =
- t CONV =
´ 106 - 1.7ms = 248.3ms
fS
4k
(7)
Calculate the required time constant of ADC,
t
248.3ms
t2 £ ACQ =
= 51.95ms
k3
4.78
(8)
When ADS8568’s sampling rate (fS) is 1 KSPS, the operating acquisition time is,
1
1
t ACQ =
- t CONV = ´ 106 - 1.7ms = 998.3ms
fS
1k
(9)
Calculate the required time constant of ADC:
t
998.3ms
t3 £ ACQ =
= 208.85ms
k3
4.78
(10)
But the time constant of an input circuit using the first-order RC filter configuration in Figure 2, is:
tTOT = (RS + RFLT )´ (CFLT + CSH ) = 10KW ´ (22nF + 20pF ) = 220.2ms
(11)
Where RS = 0 Ω and CSH = 20 pF for ±2 VREF input range to ADS8568.
This time constant is larger because of the large values of resistor (RFLT) and capacitor (CFLT), and
observably cannot meet the requirement for Equation 7 and Equation 8, cannot track the voltage of the
input signal and cannot charge the ADC’s internal sampling capacitor to the proper value during the
operating acquisition time, also affecting and limiting system performance. But, τTOT is very close to τ3 in
Equation 10 and basically does not degrade the performance of the signal chain for the sampling rate in
Equation 10. The following comparison tests demonstrate this too.
If a second-order RC filter is used, the time constant is much larger and also cannot meet the requirement
of charging the SAR ADC’s internal sampling capacitor.
Because no amplifier is used as an active filter in Figure 2, the RC filter acts as all filter functions. The
input signal from power lines is only a 50-Hz frequency signal, so to get a better filter effect, the low cut-off
frequency RC filter is often used. That is why the larger resistor and capacitor values are selected. The
cut-off frequency of the first-order RC filter designed in Figure 2 is:
1
1
=
= 723.4Hz
f-3dB =
2p (RS + RFLT )CFLT 2p ´ 10k ´ 22nF
(12)
Sometimes, the lower cut-off frequency RC filter is used; for example, 361.7 Hz with 20-kΩ resistor and
22-nF capacitor.
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So for the driver circuit design of the switched-capacitor input structure SAR ADC without any front-end
amplifier, it is critical to consider the trade-off between the time constant and the cut-off frequency of the
filter, it is also a challenge to balance this trade-off.
2.4
Improvement Techniques
The time constant is determined directly by the values of resistor RFLT and capacitor CFLT or the amount of
filter order. From Equation 2, two techniques are used to meet this equation, to resolve the system
performance issue and challenge in the circuit in Figure 2, increasing the acquisition time (tACQ) of ADC
directly and decreasing the filter orders or the component value of the RC filter.
2.4.1
Increase Acquisition Time
According to Equation 1, the sampling rate (fS) of SAR ADC is reduced to increase the acquisition time
(tACQ). The acquisition time can be increased from 98.3 μs to 248.3 μs by reducing the sampling rate from
10 KSPS to 4 KSPS, furthermore, to 998.3 μs with a 1 KSPS sampling rate. These have been calculated
in Section 2.3 and the following comparison tests also demonstrate the system performance improvement
with acquisition time extension.
2.4.2
Decrease the Filter Orders and Component Value
Another technique resolving this performance issue is reducing the filter order amount or the values of
resistor (RFLT) and capacitor (CFLT) directly. These techniques absolutely decrease the time constant in
Equation 1. The RC filter orders can be reduced from second order to first order, the capacitor value also
can be reduced from 22-nF to 820-pF. The following comparison tests also demonstrate the system
performance improvement by reducing the RC filter orders and the capacitor value. The big resistor is
reserved because of the isolation requirement.
3
Performance Test
3.1
Test System
Figure 5 shows the typical test system for AC performance in this report. The software for this report was
developed with Code Composer Studio™ V3.3 based on TI’s TMS320F28335 Digital Signal Processor
(DSP™) with an ADS8568 test board. The FFT wave forms are created in ADCPro software, which is
available for download from the Texas Instruments website www.ti.com.
Signal
Generator
Audio
Precision
AP2700
Series
Sine
Wave
Analog
Digital
Digital
ADS8568
Test
Board
CCS &
ADCPro
DSP
Emulator
PC
Figure 5. Performance Test System for the ADS8568 Circuit
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3.2
Performance Comparison Test
The following tests are based on the same circuit board. The test signal, VS, is the high-performance, lowdistortion, bipolar and 50-Hz sine-wave signal from the SYS-2722 generator of Audio Precision. The –0.5
dBFS signal amplitude of VS is used for the following tests in Table 1 through Table 3.
The FFT waveforms for these test data are shown in Section 6 through Section 8.
Table 1 is the system AC performance results based on the original design in Figure 2 with a secondorder RC filter (RFLT = 10 kΩ, CFLT = 22 nF). The system AC performance tests are done based on different
sampling rates of the ADS8568; 1 KSPS, 4 KSPS, and 10 KSPS for 20, 80, and 200 sample points per
cycle of sine wave. From the test data, the lower sampling rate for the same driver configuration, also the
longer acquisition time, and the better system AC performance, especially for THD, SINAD, and SFDR is
shown. The THD is improved from –65.46 dB with 10 KSPS sampling rate to 92.80 dB with 1 KSPS
sampling rate.
Table 1. Test Result for Second-Order Filter – RFLT = 10 kΩ, CFLT = 22 nF (unit: dBc)
Sampling Speed
SNR
THD
SINAD
SFDR
10 KSPS
85.05
–65.46
65.41
67
4 KSPS
84.69
–74.74
74.32
76.2
1 KSPS
86.35
–92.80
85.47
94.1
If reducing the filter orders from second to first order of the RC filter in Figure 2, the same tests are
finished and the new test results are listed in Table 2. The measurement results show that increasing the
acquisition time, reducing the sampling rate from 10 KSPS to 1 KSPS, improves the system AC
performance. With the longer acquisition time, the THD improves from –79.97 dB to –100.88 dB. The test
results in Table 2 also prove the performance improvement with the time constant reduction by reducing
the filter orders.
Table 2. Test Result for First-Order Filter – RFLT = 10 kΩ, CFLT = 22 nF (unit: dBc)
Sampling Speed
SNR
THD
SINAD
SFDR
10 KSPS
85.92
–70.97
70.83
73.3
4 KSPS
85.32
–82.32
80.56
84.6
1 KSPS
86.96
–100.88
86.79
105.8
For the first-order filter, continue reducing the value for CFLT from 22-nF to 820-pF, the test results in
Table 3 for this configuration show that the system AC performance is significantly improved. With the
lower sampling rate and longer acquisition time, the THD improves from –96.88 dB to –103.61 dB. The
THD and SFDR performances are much better than before, especially for same higher sampling rate, the
improvement in THD is approximately 26 dB from 22-nF to 820-pF CFLT.
Table 3. Test Result for First-Order Filter – RFLT = 10 kΩ, CFLT = 820 pF (unit: dBc)
Sampling Speed
SNR
THD
SINAD
SFDR
10 KSPS
86.08
–96.88
85.73
106.8
4 KSPS
85.03
–99.30
84.87
105.8
1 KSPS
85.56
–103.61
85.49
107.4
These measurement results show and prove that the length of the acquisition time, the RC filter orders
and the value of components in the RC filter, affect the system performance. The system improvement is
obvious by decreasing the sampling rate and reducing the filter orders and the value of the components of
the filter.
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Conclusion
4
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Conclusion
This application report presents the popular driver circuits without an amplifier to SAR ADC in industrial
application, discusses the challenges along with the driving circuit of the switched-capacitor input structure
SAR ADC, and analyzes the root reason and trade-offs between the performance demand and RC filter
design. Based on the input signal, ADC’s sampling rate, input capacitor and resistor of filter, and the
system performance demand, it is important to balance these critical conditions. Two improvement
techniques are introduced with demonstration tests in this report. This application report is also suitable for
the ADS8548 and ADS8528, TI’s SAR ADCs.
5
References
1. ADS8568, ADS8548, ADS8528 Data Sheet (SBAS543A)
2. Oljaca, M. and B. Baker. (2007). External components improve SAR-ADC accuracy. EDN. June 7,
2007. Download at: www.edn.com/article/CA4314401
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Appendix A. FFT for Second-Order Filter (RFLT = 10 kΩ, CFLT = 22 nF)
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6
Appendix A. FFT for Second-Order Filter (RFLT = 10 kΩ, CFLT = 22 nF)
Figure 6. FFT for 10-KSPS Sampling Rate (VS = –0.5 dBFS)
Figure 7. FFT for 4-KSPS Sampling Rate (VS = –0.5 dBFS)
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Appendix A. FFT for Second-Order Filter (RFLT = 10 kΩ, CFLT = 22 nF)
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Figure 8. FFT for 1-KSPS Sampling Rate (VS = –0.5 dBFS)
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Appendix B. FFT for First-Order Filter (RFLT = 10 kΩ, CFLT = 22 nF)
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Appendix B. FFT for First-Order Filter (RFLT = 10 kΩ, CFLT = 22 nF)
Figure 9. FFT for 10-KSPS Sampling Rate (VS = –0.5 dBFS)
Figure 10. FFT for 4-KSPS Sampling Rate (VS = –0.5 dBFS)
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Appendix B. FFT for First-Order Filter (RFLT = 10 kΩ, CFLT = 22 nF)
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Figure 11. FFT for 1-KSPS Sampling Rate (VS = –0.5 dBFS)
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Appendix C. FFT for First-Order Filter (RFLT = 10 kΩ, CFLT = 820 pF)
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Appendix C. FFT for First-Order Filter (RFLT = 10 kΩ, CFLT = 820 pF)
Figure 12. FFT for 10-KSPS Sampling Rate (VS = –0.5 dBFS)
Figure 13. FFT for 4-KSPS Sampling Rate (VS = –0.5 dBFS)
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Revision History
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Figure 14. FFT for 1-KSPS Sampling Rate (VS = –0.5 dBFS)
Revision History
Changes from Original (November 2012) to A Revision ................................................................................................ Page
•
Changed format to latest TI application report template.
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Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
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