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Texas Instruments Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat Application notes
Application Report
SLAA617 – December 2013
Maximizing SFDR Performance in the GSPS ADC:
Spur Sources and Methods of Mitigation
Marjorie Plisch
ABSTRACT
The SFDR performance of an ADC is limited by the largest spur in the spectrum from DC to Fs / 2. These
spurs can either be reduced or avoided entirely for maximum SFDR performance, based on the
application. This reference design explores the reason behind spurs in the 10-bit and 12-bit GSPS ADC
family. The specific products covered are: ADC12D1800RF, ADC12D1600RF, ADC12D1000RF,
ADC12D800RF, ADC12D500RF, ADC12D1800, ADC12D1600, ADC12D1000, ADC10D1500, and
ADC10D1000. For simplicity, ADC12Dx00RF refers to the ADC12D800RF and ADC12D500RF.
4
5
Contents
GSPS ADC Architecture Background .................................................................................... 3
Sources of Spurs ............................................................................................................ 4
2.1
Interleaving Spurs .................................................................................................. 4
2.2
Fixed Frequency Spurs ........................................................................................... 8
2.3
Non-Linearity Spurs .............................................................................................. 11
Methods of Mitigation ..................................................................................................... 15
3.1
ADC Features ..................................................................................................... 15
3.2
Digital Correction ................................................................................................. 17
3.3
Frequency Planning .............................................................................................. 17
3.4
Dithering the Input ................................................................................................ 18
3.5
Systems Solution by Application ............................................................................... 19
Conclusion .................................................................................................................. 19
References ................................................................................................................. 19
1
ADC Architecture by Sampling Rate
1
2
3
List of Figures
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
.....................................................................................
ADC10D1000 Block Diagram .............................................................................................
4x Interleaved Ideal ADC ..................................................................................................
2x Interleaved Non-Ideal ADC ............................................................................................
Typical GSPS ADC Block Diagram .......................................................................................
Single Converter With No Input ...........................................................................................
Single Converter With Input ...............................................................................................
Dual Sub-Converter With No Input .......................................................................................
Dual Sub-Converter With Input............................................................................................
Quad Sub-Converter With No Input ......................................................................................
Quad Sub-Converter With Input ..........................................................................................
ADC12D1800RF DES-Mode Interleaving Spurs ........................................................................
Sub-Converter Clock Coupling ............................................................................................
SDR and DDR Modes ......................................................................................................
ADC12D1800RF in DES Mode With No Analog Input ...............................................................
ADC12D1600RF Harmonic Index Versus Level ......................................................................
3
3
4
5
5
6
6
6
6
7
7
7
8
9
10
12
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17
ADC12D800RF Single-Converter Harmonic Spurs ...................................................................
18
ADC12D1000RF Dual Sub-Converter Harmonics ....................................................................
13
19
Close-In IMD3
..............................................................................................................
ADC12D1800RF IMD3 ....................................................................................................
ADC12D1800RF With and Without Calibration........................................................................
ADC12D1800RF DES Timing Code Versus Spur Magnitude .......................................................
Example of Frequency Planning.........................................................................................
ADC12D1800RF Without Dither .........................................................................................
ADC12D1800RF With Dither.............................................................................................
14
20
21
22
23
24
25
12
14
16
16
17
18
18
List of Tables
2
1
GSPS ADC Functional Blocks
............................................................................................
4
2
Sub-converters Per Product ...............................................................................................
6
3
Sub-Converter Clock Spur Location ......................................................................................
8
4
DCLK Spur Location ........................................................................................................
9
5
System Clock Spur Location .............................................................................................
10
6
GSPS ADC Distortion by Source ........................................................................................
11
7
ADC Features to Address Spurs ........................................................................................
15
8
Improvements in Harmonic With Dither Example: ADC12D1800RF AIN = –13 dBFS ............................
18
9
System Solutions ..........................................................................................................
19
10
Solutions Recommendations.............................................................................................
19
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GSPS ADC Architecture Background
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1
GSPS ADC Architecture Background
This reference design explains how to minimize spurs in the GSPS ADC family in order to achieve the
best SFDR performance. To understand the sources of the spurs, understanding the choice of architecture
is necessary.
Figure 1 shows typical architectural options for ADCs by sampling rate. The absolute rate that determines
the low or high value changes as technology advances. Higher sampling rates also generally imply lower
resolutions. The flash converter is the fastest (ultra-high) architecture and is where the GSPS ADC
architecture originates.
Architecture
Additionally, techniques of folding, interpolating, and interleaving modify the flash architecture to achieve a
low-power design which is practical to implement. The basic flash architecture requires 2N comparators
and latches for an N-bit converter. For a 12-bit converter, there are 4096 comparators and latches, which
consumes a large amount of power and die area. Folding and interpolating are techniques to reduce and
reuse the comparators and latches, which reduces area and power consumption. Interleaving is a
technique commonly used to achieve high sample rates.
Integrating
Low
SAR
Sigma-Delta
Pipelined
Medium
High
Flash
(Interpolating)
(Folding)
(Interleaving)
Ultra-High
Sampling Rate
GSPS ADC
Figure 1. ADC Architecture by Sampling Rate
Figure 2 shows the block diagram for the ADC10D1000 device. Only one interleaved channel is shown,
although this device can be interleaved up to four-times (4x) in DES Mode. This diagram shows some of
the blocks which affect linearity performance including the track-and-hold, folding, and interpolating.
V-cal
R-MUX
±VIN
MUX
2nd int
1
Buffer
T&H
Encoder:
st
2
st
1 T&H
C
nd
Buffer
20
Recursive Error
Correction &
base-3 to base-2
conversion
2
3
Cascaded Amps 1 — 5
Amp 0
10 DOUT
Amp 6
3
VRT
9 5%
Fine
Ref.
Ladder
Amp
Array
x 27
Averaging
Resistors
Amp
Array
x 27
Folding
by 3X
Averaging &
Interpolation
by 3X
Amp
Array
x 27
Folding
by 3X
Figure 2. ADC10D1000 Block Diagram
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Table 1 lists the functional blocks of the GSPS ADC. Each block is included for a specific reason, such as
to achieve the target performance, die size, or sampling rate. However, the use of a block often results in
added distortion. For more information on the GSPS ADC architecture, see [1].
Table 1. GSPS ADC Functional Blocks
Block
2
Description
Pros
Cons
Track-and-hold Track and hold analog input signal
Improves performance at low
FIN
Can reduce maximum
sampling rate
Folding
Fold transfer function into sub-ranges
Reduces number of latches to
improve power and area
Introduces distortion
Interpolating
Interpolate conversion between series of
amplifiers
Reduces number of amplifiers
to improve power and area
Introduces distortion
Interleaving
Time-interleave multiple ADC cores
Achieves higher sampling rates
Introduces distortion from
mismatch factors
Calibrating
Trim bias currents in linear amplifiers
Reduces distortion
Time offline to calibrate
Sources of Spurs
There are several sources of spurs for the GSPS ADC family. These sources include:
• Mismatch between sub-converters in an interleaved ADC architecture
• Coupling from system clocks
• Non-linearities of the ADC
In
•
•
•
2.1
general, these spurs are categorized into three areas:
Interleaving spurs
Fixed frequency spurs
Input frequency-dependent spurs
Interleaving Spurs
In order to achieve higher sampling rates, multiple ADCs can be interleaved into a single, composite ADC.
Each ADC sub-converter has a certain offset and gain characteristic. The offset is the average code
produced by the sub-converter with no analog input. Assuming that the transfer curve of the ADC is linear,
the gain is the analog input amplitude which produces the maximum output code.
Figure 3 shows an example of an ideal 4x-interleaved ADC. All four ADCs sample the same analog input
signal, 90 degrees out of phase with respect to one another.
ADC1
Signal
Input BUFFER
ADC2
ADC3
Time
Alignment
ADC4
Clock
Input
0°
Clock
90°
Phase
Frequency = FS Generator 180°
270°
Frequency = FS / 4
Figure 3. 4x Interleaved Ideal ADC
4
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However, the reality is that interleaving is a non-ideal process. Figure 4 shows the primary sources of
mismatch. Gain error, DC offset, and timing skew cause systematic errors in the sampled signal, which
result in predictable spurs in the composite spectrum.
GERR
Signal
Input
ADC1
BUFFER
ADC2
VOFFSET
-ERR
Clock
Input
Clock
0°
Phase
Frequency = FS Generator 180° Frequency = FS / 2
Figure 4. 2x Interleaved Non-Ideal ADC
The GSPS ADC family can have 1, 2, or 4 interleaved sub-converters, based on the device and mode. All
of TI's 10-bit and 12-bit GSPS ADCs are dual-channel devices which can be interleaved into a virtual
single-channel device that operates at twice the dual-channel sampling rate. This interleaved mode is
referred to as Dual-Edge Sampling Mode (DES Mode) because one channel is sampled on the rising edge
of the sampling clock and the other channel is sampled on the falling edge. Non-DES Mode refers to the
non-interleaved dual-channel mode. Figure 5 is a typical simplified block diagram for most GSPS ADC
datasheets. Figure 5 shows one ADC for the I-channel and one ADC for the Q-channel.
Figure 5. Typical GSPS ADC Block Diagram
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In the implementation, however, most of the GSPS ADCs actually have two internally interleaved subconverters per channel (see Table 2). These two sub-converters are referred to as I1 and I2, and Q1 and
Q2. The ADC12Dx00RF device is a unique product because it has only one converter per channel.
Table 2. Sub-converters Per Product
Product
Sub-converters
(Non-DES Mode)
Sub-converters
(DES Mode)
ADC10D1500, ADC10D1000
2
4
ADC12D1800, ADC12D1600, ADC12D1000
2
4
ADC12D800RF, ADC12D500RF
1
2
ADC12D1800RF, ADC12D1600RF, ADC12D1000RF
2
4
Note that this reference design is a practical overview of interleaving spurs. There are other effects which
can contribute to interleaving spurs, but offset mismatch, gain mismatch, and timing skew cover the first
order effects. For detailed information including calculations, other effects contributing to interleaving
spurs, and the magnitude of spur which results from the level of each type of mismatch, please see [2].
MAGNITUDE
DC
MAGNITUDE
DC
FIN
For a single converter, the FFT results in a spur at DC, which represents the offset of the converter. The
application of an input signal, FIN, simply results in a tone at FIN in addition to the spur at DC. Note that the
following diagrams only illustrate the locations of spurs and that the magnitude of the spurs is not to scale.
An example of a single sub-converter is the ADC12D800RF or ADC12D500RF device in Non-DES Mode.
FREQUENCY
Figure 6. Single Converter With No Input
FREQUENCY
Figure 7. Single Converter With Input
FREQUENCY
Figure 8. Dual Sub-Converter With No Input
6
FS / 2
FS / 2 ± FIN
MAGNITUDE
DC
FS / 2
MAGNITUDE
DC
FIN
When two sub-converters are interleaved, the offset of each sub-converter is slightly different, that is offset
mismatch, which produces a tone at FS / 2. The tone at FS / 2 is in addition to the average offset of the
composite interleaved ADC, which produces a tone at DC. Gain mismatch between the two subconverters produces a tone at FS / 2 – FIN. In an ideal scenario, the two sub-converters sample one after
the other with uniform time intervals. Any deviation from this idea scenario is timing skew. Timing skew
between the two sub-converters additionally contributes to the tone at FS / 2 – FIN. An example of two
interleaved sub-converters is the ADC12D1800, ADC12D1600, or ADC12D1000 device in Non-DES
Mode, or the ADC12D800RF or ADC12D500RF device in DES Mode.
FREQUENCY
Figure 9. Dual Sub-Converter With Input
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FS / 2
FS / 2 ± FIN
FS / 4 + FIN
FS / 4
FS / 4 ± FIN
MAGNITUDE
DC
FS / 2
MAGNITUDE
DC
FS / 4
FIN
Similarly, when an ADC is composed of four interleaved sub-converters, the offset mismatch produces
spurs at FS / 2 and FS / 4, and the composite offset produces a spur at DC. If the sub-converters sample in
time—Bank 1, Bank 2, Bank 3, and Bank 4—the gain mismatch and timing skew between Bank 1 and
Bank 3, and between Bank 2 and Bank 4 produces tones at FS / 4 ± FIN. Gain mismatch and timing skew
between the composite (Bank 1 and Bank 3) ADC and the composite (Bank 2 and Bank 4) ADC produces
a tone at FS / 2 – FIN. An example of four interleaved sub-converters is the ADC12D1800, ADC12D1600,
or ADC12D1000 device in DES Mode.
FREQUENCY
FREQUENCY
Figure 10. Quad Sub-Converter With No Input
Figure 11. Quad Sub-Converter With Input
Figure 12 is an example FFT of the ADC12D1800RF in DES Mode with an input signal. In this Mode, four
sub-converters are interleaved. The interleaving spurs can be seen at FS / 4 ± FIN, and FS / 2 – FIN.
FS / 4 + FIN
FS / 2 – FIN
FS / 4 – FIN
4x Interleaving Spurs
Figure 12. ADC12D1800RF DES-Mode Interleaving Spurs
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2.2
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Fixed Frequency Spurs
In addition to the spurs which result from offset mismatch in an interleaved ADC, there are also spurs
which result from coupling from on-chip clocks. These clocks are the sub-converter sampling clock, the
data clock (DCLK), and an additional system clock. These spurs always appear in known fixed-frequency
locations which are related to the sampling clock, FCLK. When there are multiple sources of a fixedfrequency spur, the power of that spur is a sum of the power from each source. Because these spurs are
predictable, they are simpler to account for in a system design. For example, in a multi-channel
application, a fixed-frequency spur can be arranged to land on a channel boundary to avoid interference
with system performance.
2.2.1
Fixed Frequency Spurs: the Sub-Converter Clock
Each sub-converter is clocked at FCLK or FCLK / 2, based on the device used. The local sampling clock to
each sub-converter can couple to the output, which generates a spur at a fixed frequency related to FCLK
(see Figure 13). For example, the ADC10D1000 device has FCLK = 1000 MHz and two sub-converters per
channel. These two sub-converters run at FCLK / 2 = 500 MHz. If the ADC is configured into the DES
Mode, then FS = 2000 MSPS and the sub-converter clock coupling into the output appears at FS / 4, which
is 2000 MHz / 4 = 500 MHz. If the ADC is configured into the Non-DES Mode, then FS = 1000 MHz and
the sub-converter clock coupling into the output appears at FS / 2, which is 1000 MHz / 2 = 500 MHz.
N
Sub-converter Q1
FCLK / 2
N
Sub-converter Q2
0°
FCLK
÷2
FCLK / 2
180°
Figure 13. Sub-Converter Clock Coupling
Based on the mode used, such as DES Mode or Non-DES Mode, and the device, this spur is located at
DC, FS / 4, or FS / 2 (see Table 3).
Table 3. Sub-Converter Clock Spur Location
8
Product
FCLK (MHz)
Sub-Converters /
Channel
Sub-Converter
Clock (MHz)
DES Mode Spur
Location
Non-DES Mode Spur
Location
ADC10D1000
1000
2
500
FS / 4
FS / 2
ADC10D1500
1500
2
750
FS / 4
FS / 2
ADC12D1000
1000
2
500
FS / 4
FS / 2
ADC12D1600
1600
2
800
FS / 4
FS / 2
ADC12D1800
1800
2
900
FS / 4
FS / 2
ADC12D500RF
500
1
500
FS / 2
DC
ADC12D800RF
800
1
800
FS / 2
DC
ADC12D1000RF
1000
2
500
FS / 4
FS / 2
ADC12D1600RF
1600
2
800
FS / 4
FS / 2
ADC12D1800RF
1800
2
900
FS / 4
FS / 2
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2.2.2
Fixed Frequency Spurs: the Data Clock
Coupling from the data clock (DCLK) into the output can also contribute to a fixed frequency spur. The
frequency at which the spur appears is determined by the output mode. The possible output modes are:
Non-Demux Mode (NDM), Demux Mode, single data-rate (SDR), and dual-data rate (DDR). Note that not
all of these modes are available on every GSPS ADC (see the respective datasheet for details). In NonDemux Mode, the data for an N-bit ADC is produced at the output of each channel on an N-bit bus at the
sampling rate. In Demux Mode, the data is produced on two N-bit busses at half the sampling rate. The
Demux Mode is generally used to ease the difficulty of data capture at high speed by reducing the data
rate by half. However, Demux Mode does require twice the number of data busses.
In SDR Mode, the DCLK frequency is the same as the data. Data transitions on either the rising or falling
edge of DCLK. In DDR Mode, the DCLK frequency is half of the data rate. Data transitions on both rising
and falling edges of DCLK (see Figure 14).
Data
SDR DCLK
DDR DCLK
Figure 14. SDR and DDR Modes
For example, if the ADC12D800RF is used in Non-Demux SDR Mode, then DCLK = 800 MHz. If the
device is used in the DES Mode, then FS = 1600 MSPS and the DCLK generates a spur at FS / 2, which is
1600 MHz / 2. If the device is used in the Non-DES Mode, then FS = 800 MSPS and the DCLK generates
a spur at FS / 2. Table 4 lists a summary of DCLK Spur Locations.
Table 4. DCLK Spur Location (1)
Product
(1)
NDM SDR
DCLK (MHz)
NDM DDR
DCLK (MHz)
Demux SDR
DCLK (MHz)
Demux DDR
DCLK (MHz)
DES-Mode Spur Locations
Non-DES Mode Spur
Locations
ADC10D1000
500
250
FS / 4
FS / 8
FS / 2
FS / 4
ADC10D1500
750
375
FS / 4
FS / 8
FS / 2
FS / 4
ADC12D1000
500
250
FS / 4
FS / 8
FS / 2
FS / 4
ADC12D1600
800
400
FS / 4
FS / 8
FS / 2
FS / 4
ADC12D1800
900
450
FS / 4
FS / 8
FS / 2
FS / 4
ADC12D500RF
500
250
250
ADC12D800RF
800
400
400
FS / 2 FS / 4 FS / 4
FS / 2 FS / 4 FS / 4
FS
FS / 2 FS / 2
FS
FS / 2 FS / 2
ADC12D1000RF
500
250
FS / 4
FS / 8
FS / 2
FS / 4
ADC12D1600RF
800
400
FS / 4
FS / 8
FS / 2
FS / 4
ADC12D1800RF
900
450
FS / 4
FS / 8
FS / 2
FS / 4
Note: Not all modes are available on each device. The table has been left blank where the mode is unavailable.
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Fixed Frequency Spurs: the System Clock
Coupling from another system clock also contributes to a fixed frequency spur. This clock is heavily
loaded, so it does contribute a non-negligible spur to the output spectrum. This clock is used for internal
circuitry which is related to a proprietary implementation of the architecture. Based on the setting of the
LFS bit (Low Frequency Select), the location of the spur is affected.
Table 5. System Clock Spur Location
2.2.4
Product
DES-Mode Spur
Location
LFS = 0
DES-Mode Spur
Location
LFS = 1
Non-DES Mode Spur
Location
LFS = 0
Non-DES Mode Spur
Location
LFS = 1
ADC10D1000
FS / 16
FS / 8
FS / 8
FS / 4
ADC10D1500
FS / 16
FS / 8
FS / 8
FS / 4
ADC12D1000
FS / 16
FS / 8
FS / 8
FS / 4
ADC12D1600
FS / 16
FS / 8
FS / 8
FS / 4
ADC12D1800
FS / 16
FS / 8
FS / 8
FS / 4
ADC12D500RF
FS / 8
FS / 4
FS / 4
FS / 2
ADC12D800RF
FS / 8
FS / 4
FS / 4
FS / 2
ADC12D1000RF
FS / 16
FS / 8
FS / 8
FS / 4
ADC12D1600RF
FS / 16
FS / 8
FS / 8
FS / 4
ADC12D1800RF
FS / 16
FS / 8
FS / 8
FS / 4
Fixed Frequency Spurs: An Example
Figure 15 shows an example of a fixed frequency spur. The ADC12D1800RF device is configured into
DES Mode with a Demux DDR DCLK and with no analog input signal. For this mode, FS = 3.6 GSPS. The
spur present at 900 MHz = FS / 4 is visible in the spectrum, although there is no analog input. As listed in
Table 3, Table 4, and Table 5, determining the sources of the FS / 4 spur is possible. In this example, the
spur at FS / 4 is from a combination of the sub-converter clock coupling and the DCLK.
FS / 4 = –75 dBFS
Figure 15. ADC12D1800RF in DES Mode With No Analog Input
10
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2.3
2.3.1
Non-Linearity Spurs
Harmonic Spurs
The source of harmonic distortion in the GSPS ADC is from non-linearities, which are contributions from
all of the sources combined and are not individually distinguished. The frequency location is easy to
predict (harmonic) but the amplitude of the distortion is not.
Table 6 lists the sources of harmonic distortion. The track-and-hold at the front end of the ADC produces
lower-order harmonics of the input signal which roll off with the analog input bandwidth. The power of
these harmonics, as related to the power of the input signal follows the standard relationship, such as for
an amplifier. Higher-order harmonics are produced in the interpolating, folding architecture and are
produced according to the folding-interpolating factor. The levels of these higher-order harmonics follow a
non-linear relationship to the power of the input signal. As the higher-order spurs fold back-and-forth in the
sampled spectrum, these spurs give the appearance of grass just above the noise floor in an FFT. At the
output of the ADC, the summed power of the lower-order and higher-order harmonics can be observed
together.
Table 6. GSPS ADC Distortion by Source
Source of Distortion
Harmonics Produced
Rolls Off With
Relationship to Input Power
Track-and-hold
Lower-order harmonics
Analog input bandwidth
Standard relationship
Amplifiers in interpolating, folding
architecture
Higher-order harmonics
Folding-interpolating factor
Non-linear relationship
The harmonic distortion produced by the track-and-hold follows the standard relationship to input power
for a non-linear circuit, the same as an amplifier. First, consider the non-linear system shown in
Equation 1.
v o (t) = a1VIN (t) + a2 VIN2 (t) + a3 VIN3 (t) + a4 VIN4 (t) + a5 VIN5 (t) + K
(1)
For differential circuits, such as track-and-hold, the even harmonics are ideally zero, and HD3 >> HD5
which is approximated with Equation 2.
v o (t) @ a1VIN (t) + a3 VIN3 (t)
(2)
For a sinusoidal input, calculate with Equation 3.
VIN (t) = A cos (wt)
3
(3)
3
v o (t) @ a1A cos (wt) + a3 A cos (wt)
é
é a3 A 3 ù
3a3 A 3 ù
= êa1A +
ú cos (wt) + ê
ú cos (3wt)
4 úû
êë
êë 4 úû
HD1
HD3
(4)
Equation 4 is defined as Equation 5.
v o (t) º HD1 cos (wt) + HD3 cos (3wt)
HD1 = a1A
HD3 =
a3 A 3
4
(5)
Therefore, for the standard non-linear circuit, if the input level, A, is decreased by 1 dB, then HD3
decreases by 3 dB because HD1 is proportional to A and HD3 is proportional to A3. The track-and-hold
follows this relationship and therefore the level of the lower-order harmonics such as HD2, HD3, HD4, HD5,
and others can be strongly influenced by increasing or decreasing input signal power. However, the
higher-order harmonics observe a highly non-linear relationship to the input power and higher-order
harmonics do not significantly decrease with a decrease of input signal power. Because higher-order
harmonics do not significantly decrease, the maximum SFDR, as limited by harmonics, can be achieved at
the maximum input signal power.
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Figure 16 shows the harmonic level for different input signal levels. The harmonic index was only reported
up to HD25, but the harmonics also continue beyond that point. HD3 is typically the highest level harmonic
because it is the lowest-index non-even harmonic. Lower-order harmonics, approximately HD2 to HD9 for
this example, are dominated by the effect of non-linearities in the track-and-hold, and roll off with the input
bandwidth. Higher-order harmonics, HD2 to HD25, resulting from the folding-interpolating architecture
remain present over harmonic index and input level with a fairly consistent range of amplitudes (–85
dBFS, –100 dBFS). The folding-interpolating also generates harmonic content at lower indices down to
HD2, but the effect of the track-and-hold dominates at lower-order harmonics.
±65
AIN
AIN = ±1 dBFS
AIN = ±13 dBFS
AIN
AIN =
AIN
= ±25
±25 dBFS
dBFS
±70
Level (dBFS)
±75
±80
±85
±90
±95
±100
±105
±110
0
5
10
15
20
25
Harmonic Index
C002
Figure 16. ADC12D1600RF Harmonic Index Versus Level
Figure 17 shows the FFT for the ADC12D800RF with FS = 800 MSPS and MSPS = 125 MHz. In this case,
the SFDR is limited by the HD3 spur located at 375 MHz to 70 dBc. For this plot the data was processed
twice. The blue plot shows the original data that was processed first. For this data, the blue grass, which is
the harmonic content, can be observed above the noise floor. The same data was processed again (red
plot), with the harmonic content mathematically removed by notching a small amount of bins around each
harmonic location.
0
= Original FFT
= FFT processed to remove harmonics
Magnitude (dBFS)
-20
-40
HD3
-60
-80
-100
-120
0
100
200
300
400
Frequency (MHz)
Figure 17. ADC12D800RF Single-Converter Harmonic Spurs
12
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Figure 18 shows the FFT for the ADC12D1000RF with FS = 1000 MSPS and MSPS = 125 MHz. This ADC
has two sub-converters, each running at 500 MSPS and interleaved to achieve an overall 1000 MSPS.
For this case, the worst spur is from gain mismatch and timing skew between the sub-converters which
results in a spur at FS / 2 – FIN.
0
= Original FFT
= FFT processed to remove harmonics
Magnitude (dBFS)
-20
FS / 2 ± FIN
-40
-60
-80
-100
-120
0
100
200
300
400
500
Frequency (MHz)
Figure 18. ADC12D1000RF Dual Sub-Converter Harmonics
Note that for both FFTs in Figure 17 and Figure 18, the ADC is performing under worst-case conditions for
this particular architecture (such as a single, CW tone). A wideband input signal results in less spurious
content generated because transitions on the transfer curve are more random. Therefore, evaluating
wideband applications under actual operating conditions, not only with a CW test tone, is important.
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Sources of Spurs
2.3.2
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Third-Order Intermodulation Distortion
Although there are actually four third-order intermodulation distortion products (IMD3), only the two close-in
ones are typically considered because these are the terms which are difficult to filter out from the band of
interest. For input frequencies at f1 and f2, the IMD3 terms are located at 2f2 – f1 and 2f1 – f2, see Figure 19.
f1 and f2 are shown at different levels to exaggerate the difference between them, but in practice they are
set to the same level. IMD3 is defined with Equation 6.
IMD3 = min (f1, f2 ) - max(2f2 - f1, 2f1 - f2 )
(6)
Amplitude
IMD3
2f1 ± f2
f1
2f2 ± f1
f2
Frequency
Figure 19. Close-In IMD3
Figure 20 shows the IMD3 for the ADC12D1800RF at various input levels. The results are less linear for
lower-input amplitude signals, as well as lower-input frequencies. The less-linear results occur because for
higher input frequencies and levels, the IMD3 is most strongly a function of the track-and-hold. Because
IMD3 is primarily a function of the analog input, IMD3 performance, as shown in Figure 20, is similar for the
ADC12D1600RF, ADC12D1000RF, ADC12D800RF, and ADC12D500RF.
±40
IMD3
IMD3 ±7
±7dBFS
dBFS
IMD3
IMD3 ±10
±10 dBFS
dBFS
IMD3 ±13
±13 dBFS
dBFS
IMD3
IMD3 ±16
±16 dBFS
dBFS
IMD3
IMD
±19
dBFS
IMD33 ±19 dBFS
±45
IMD3 (dBc)
±50
±55
±60
±65
±70
±75
±80
±85
0
500
1000
1500
2000
2500
FIN (MHz)
3000
3500
4000
C003
Figure 20. ADC12D1800RF IMD3
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3
Methods of Mitigation
A number of options are available to minimize any spurs and maximize the SFDR performance. These
options include features of the GSPS ADC, digital correction, frequency planning, dithering the input, and
systems solutions.
3.1
ADC Features
The GSPS ADCs include certain features which can minimize spurs, such as calibration, offset adjust, fullscale range adjust, duty cycle correct, DES timing adjust, and sub-converter timing adjust. Note that not
every feature is available on every ADC (see Table 7).
Calibration— This feature is designed to trim the analog input differential termination resistors, the CLK
input resistor, and set internal bias currents which affect the linearity of the converter. Calibrating
minimizes full-scale error, offset error, DNL and INL. Calibration must be run in order to achieve the
full rated performance because it is the principal feature used to maximize SFDR.
I-channel and Q-channel offset adjust— The offset for each I-channel and Q-channel can be adjusted
independently with 15-bits of precision. However, individual sub-converter offset adjust is not
available on every device. This feature can be used to correct for any residual offset error between
the I-channel and Q-channel which would result in a spur at FS / 2.
I-channel and Q-channel FSR adjust— The input full-scale range for each I-channel and Q-channel may
be adjusted independently with 12-bits of precision plus polarity. However, individual sub-converter
FSR adjust is not available on every device. This feature is used to correct for any residual gain
error between the I-channel and Q-channel which results in a spur at FS / 2 – FIN.
Duty Cycle Correct— The Sampling Clock phase between the I-channel and Q-channel is automatically
and continuously adjusted in the background. The Duty Cycle Correct feature addresses the
variable component of the clock phase error in DES Mode. The feature is enabled by default and TI
recommends to leave the feature enabled.
DES timing adjust— The Sampling Clock phase between the I- and Q-channel can be adjusted manually
from the nominal mid-range setting. Using the DES Timing Adjust feature addresses the residual
static timing skew offset of the clock phase error in DES Mode.
Table 7. ADC Features to Address Spurs
Feature
ADC10D1x00
ADC12D1x00
ADC12Dx00RF
ADC12D1x00RF
DES Mode Spurs Addressed
Calibration
Yes
Yes
Yes
Yes
DC, FS / 4, FS / 2, FS / 2 – FIN,
FS / 4 ± FIN
I/Q-channel
offset adjust
Yes
Yes
Yes
Yes
FS / 2
I/Q-channel
FSR adjust
Yes
Yes
Yes
Yes
FS / 2 – FIN
Duty cycle correct
Yes
Yes
Yes
Yes
FS / 2 – FIN
DES timing adjust
No
Yes
Yes
Yes
FS / 2 – FIN
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Methods of Mitigation
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Calibration is the main feature of the GSPS ADC to linearize the performance. For example, Figure 21
shows the ADC12D1800RF device in Non-DES Mode with and without calibration for FIN = 997.47 MHz.
Calibration yields a performance improvement in over 2 ENOB. The un-calibrated performance with
calibration vectors reset to the default values, as shown in Figure 21, is not typically seen because the
ADC performs a calibration upon power-up. However, performing another calibration after applying the
desired mode and allowing for self-heating is necessary to achieve the optimized performance.
Un-Calibrated
ENOB = 6.62
Calibrated
ENOB = 8.85
Figure 21. ADC12D1800RF With and Without Calibration
The DES Timing Adjust is a good example of an analog correction of interleaving spurs on the GSPS
ADC. Figure 22 shows that as the timing codes are changed, the magnitude of the DES timing spur,
located at FS / 2 – FIN, decreases with the decreasing timing skew. Each code skews the sample instant of
the I-channel, with respect to the Q-channel. At the relative minimum point, the DES timing spur is 13 dB
less than the next highest spur, which is HD3.
Timing Spur Magnitude (dBFS)
0
Timing
TimingSpur
Spur
±10
HD3
HD3
±20
±30
±40
±50
±60
±70
±80
±90
0
20
40
60
80
100
DES Timing Adjust Code
120
140
C001
Figure 22. ADC12D1800RF DES Timing Code Versus Spur Magnitude
16
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3.2
Digital Correction
While the GSPS ADCs offer features to enable analog correction of interleaving spurs, using digital
correction to address interleaving spurs is also possible. For resolutions greater than 8 bits, achieving the
level of matching required for analog correction is a challenge. One drawback to analog correction is that
a feature setting, which optimizes the performance under a given set of conditions such as temperature or
analog input frequency, may not be optimal at a different temperature or input frequency.
For digital correction, the errors can be estimated and corrected with coefficients by post-processing the
data. The algorithm detects the errors in either the time or frequency domain, and converge on correction
coefficients. Digital correction adds complexity to the system, but can also optimize performance under a
wider variety of operating conditions.
3.3
Frequency Planning
Frequency planning is used to ensure that lower-order harmonics do not interfere with the band of interest.
TI offers a tool called the ADC Harmonic Calculator to determine the location of harmonics (see the tool
folder for more information and to download the calculator, www.ti.com/tool/adc-harmonic-calc). This tool,
however, does not include the effect of harmonics and interleaving. Figure 23 shows an example of how to
plan around lower-order harmonics for the ADC12D1800 in DES Mode. The input signal bandwidth is 60
MHz centered at 1000 MHz and no harmonic falls back into the band of interest until HD6. Frequency
planning works well for applications which are over-sampled.
Inputs Here
Signal BW
Filter BW
Signal Center Freq
ADC Sample Rate
Results
60.00
100.00
1000.00
3600.00
Min Freq
Max Freq
Overlaps signal
HD3
HD2
Signal
1030
1700
970.6
1500
0
HD4
750
450
0
HD5
HD6
600
200
0
1650
1150
0
HD7
1500
900
1
HD8
550
3
0
HD9
1200
400
1
1800
350
0
10
HD9
HD8
9
8
7
HD6
HD7
HDX
6
HD5
5
4
HD3
HD4
3
HD2
2
Band
1
0
0
500
1000
1500
ADC Output Frequency (MHz)
2000
C004
Figure 23. Example of Frequency Planning
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Methods of Mitigation
3.4
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Dithering the Input
FS/2 – FIN
Adding dither the analog input signal can improve harmonic performance by randomizing transitions
across the ADC transfer function. However, adding dither to the input signal reduces the maximum input
signal level which can be applied before clipping the ADC. If the dither is added as band-limited white
noise to the spectrum outside the band of interest, then the dither can easily be filtered out. See Figure 24
and Figure 25 for an example. Table 8 lists improvements in harmonic distortion. Dithering the input only
reduces the level of the harmonics, but does not affect the interleaving spurs.
FIN
Without Dither
FS/2 – FIN
Figure 24. ADC12D1800RF Without Dither
FIN
With Dither
Figure 25. ADC12D1800RF With Dither
Table 8. Improvements in Harmonic With Dither
Example: ADC12D1800RF AIN = –13 dBFS
18
Harmonic
No Dither
(dBc)
With Dither
(dBc)
HD2
–65
–70
5
HD3
–64
–74
10
HD4
–77
–77
0
HD5
–70
–75
5
HD6
–67
–77
10
HD7
–66
–78
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Maximizing SFDR Performance in the GSPS ADC: Spur Sources and
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Improvement
(dB)
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3.5
Systems Solution by Application
Some fixed frequency spurs from the DCLK, offset mismatch, and sub-converter clock can be addressed
by carefully choosing the DCLK Mode, system architecture, and GSPS ADC selection.Table 9 lists some
examples of system solutions.
Table 9. System Solutions
Example
Spur Source
Solution
A spectrum analyzer uses the ADC12D800RF
interleaved and cannot tolerate a strong spur in
the middle of the spectrum.
DCLK running in Demux SDR Mode
causes a spur at FS / 4
Iinstead choose the Non-Demux
SDR DCLK, which moves the
spur to FS / 2.
A wideband communications application uses the
ADC12D1800RF interleaved to achieve high
sampling bandwidth.
A long-range tactical radar with FS = 750 MSPS
cannot tolerate interleave images .
4
DCLK produces spur at FS / 8 or FS / 4
Offset mismatch spur at FS / 4
Sub-converter clock spur at FS / 4
Most members of the GSPS ADC family
have interleaved channels, which produce
image spurs
Adjust the sampling clock so that
the fixed-frequency spurs land on
channel boundaries.
Use the ADC12D800RF, which
has only one converter per
channel.
Conclusion
In order to achieve high-resolution, high-sampling rate ADCs, certain techniques were chosen which also
resulted in spurious content. The impact of spurs on system performance can be minimized with a better
understanding of the spurs. Spurs in the GSPS ADC family occur because of non-linearities, interleaving,
and system clocks. Techniques to address these spurs include ADC features such as calibration, use of
dithering, digital correction, and frequency planning. Input signals that consist of multiple wideband or CW
tones act like dither and reduce the impact of non-linearities. Therefore testing with single CW-tone inputs
may not adequately or relevantly show performance for an actual application. Table 10 lists a summary of
spurious sources and solutions.
Table 10. Solutions Recommendations
Spur
Dominant Source
Solution
Lower-order harmonics
Non-linearity in track-and-hold
Higher-order harmonics
Folding-interpolating architecture
IMD3
Non-linearity in track-and-hold, folding-interpolating architecture
Calibration
Frequency planning
Calibration
Dithering
ADC selection
DC, FS / 4, FS / 2
Sub-converter offset mismatch in interleaving architecture
ADC features
FS / 2 – FIN, FS / 4 ± FIN
Sub-converter gain mismatch and timing skew in interleaving
architecture
FS / 8, FS / 4, FS / 2
Coupling from DCLK
DCLK selection
DC, FS / 2
Coupling from sub-converter clock
ADC selection
Digital correction
5
References
1. A 1.8V 1.0Gsps 10b Self-Calibrating Unified-Folding-Interpolating ADC with 9.1 ENOB at Nyquist
Frequency (Taft 2009)
2. Explicit Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems (Kurosawa 2002)
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