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Texas Instruments DAC348x Device Configuration and Synchronization Application notes
Application Report
SLAA584 – April 2013
DAC348x Device Configuration and Synchronization
Kang Hsia ........................................................................................................... HSP High Speed DC
ABSTRACT
The DAC348x family is a family of digital-to-analog converter (DAC) devices with many digital features
such as FIFO, interpolation filters, quadrature modulator correction circuits, and mixers. It also has
flexibility for multi-device synchronization to ensure output phase alignment for each device. In order to
operate the DAC correctly, the internal digital logics must be synchronized correctly at start-up. The intent
of this application note is to provide references for the digital blocks in the DAC348x devices and
describes the steps needed to synchronize these blocks. The same principle can be applied to other
Texas Instruments (TI) DAC devices such as the DAC328x family and the DAC317x family.
Contents
Key Words ................................................................................................................... 2
FIFO Architecture for Synchronization ................................................................................... 3
2.1
The Purpose of the FIFO ......................................................................................... 3
2.2
FIFO Operation ..................................................................................................... 7
2.3
Optimize FIFO Location for Single Sync Source Mode ..................................................... 15
2.4
Dual Sync Sources Mode ....................................................................................... 17
2.5
Optimal FIFO Position Setup for Dual Sync Sources Mode ................................................ 24
3
Digital Logic Synchronization ............................................................................................ 25
3.1
FIFO and Data Formatter (Configured and Synchronized Upon Initial Start-Up): ....................... 25
3.2
Clock Divider (Configured and Synchronized upon Initial Start-Up): ...................................... 26
3.3
Double Buffered Registers (Adjustable During System Operation). ....................................... 26
3.4
NCO Accumulator (Adjustable During System Operation) .................................................. 28
3.5
DAC348x Digital Logic Synchronization Summary ........................................................... 30
4
Start-Up Sequence ........................................................................................................ 31
4.1
Example Start-Up Routine (Based on DAC345H84 Configuration) ........................................ 32
5
References ................................................................................................................. 33
Appendix A
....................................................................................................................... 34
Appendix B
....................................................................................................................... 35
1
2
List of Figures
1
Setup and Hold Time Diagram ............................................................................................ 3
2
Typical Alignment Requirement for Data and Clock Sources ......................................................... 4
3
FIFO used to Relax Alignment Requirement
5
4
Typical System Implementation for DAC Devices with FIFO
6
5
6
7
8
9
10
11
12
13
14
...........................................................................
.........................................................
DAC348x FIFO Structure ..................................................................................................
Single Sync Source Mode .................................................................................................
Write Pointer Synchronization Signal Handoff Across the FIFO ......................................................
Meta-stability of the Synchronization Signal Handoff across the FIFO .............................................
Reset Time Difference of FIFO Read Pointer Position in Single Sync Source Mode ............................
DAC#1 FIFO Write/Read Sequence (Read Sequence Occurs On Time) .........................................
DAC#2 FIFO Write/Read Sequence (Read Sequence Occurs Later by One Sample) .........................
Byte Wide Data Transmission Format ..................................................................................
Word Wide Data Transmission Format .................................................................................
Single Sync Mode Using SIF_SYNC ...................................................................................
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8
9
10
10
11
11
12
13
13
1
Key Words
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15
Reset Time Difference of FIFO Read Pointer in SIF_SYNC Mode ................................................. 14
16
DAC#3 FIFO Write/Read Sequence (Read Sequence Occurs Ahead by One Sample)
17
FIFO Memory Buffer for Both the Write and Read Direction ........................................................ 15
18
Possible Alarm Conditions (Assuming RP4 Occurs at the Moment)
19
20
........................
...............................................
FIFO Offset Adjustment Algorithm .....................................................................................
Dual Sync Sources Mode ................................................................................................
14
15
17
18
21
Multi-Device Synchronization Example: Path#2 Has Additional Two Sample Delay when Compared to
Path#1 ...................................................................................................................... 19
22
Multi-Device Synchronization Example: Data Sequence versus Time between Path#1 and Path#2
23
Multi-Device Synchronization Example: FIFO State Snap-Shots
24
25
26
27
28
29
30
31
32
33
34
35
36
37
.........
..................................................
Multi-Device Synchronization Example: SYNC Pulse Loading for Logic Synchronization.......................
Typical Dual Sync Sources System Setup with DAC348x in External Clock Mode ..............................
Timing Diagram for LVPECL Synchronization Signals of DAC3484................................................
Typical Dual Sync Sources System Setup with DAC348x in On-Chip PLL Mode ................................
DAC348x On-Chip PLL DACCLK and OSTR Generation ...........................................................
FIFO Offset Adjustment for Dual Sync Sources Mode ...............................................................
Simplified Clock Divider Block Diagram ...............................................................................
Double-Buffered Registers ...............................................................................................
NCO Block Diagram.......................................................................................................
NCO Accumulator Operation with Repetitive Synchronization Signals ............................................
DAC#1 FIFO Write/Read Sequence (Read Sequence Occurs On Time) .........................................
DAC#2 FIFO Write/Read Sequence (Read Sequence Occurs Later by One Sample) ..........................
DAC#1 FIFO Write/Read Sequence (Read Sequence Occurs On Time) .........................................
DAC#3 FIFO Write/Read Sequence (Read Sequence Occurs Ahead by One Sample).........................
19
21
22
22
23
23
24
25
26
27
28
29
34
34
35
35
List of Tables
1
FIFO-Out Clock Rate ....................................................................................................... 9
2
FIFO Alarm Distribution versus FIFO Offset Location (Single Sync Source Mode – ISTR only) ............... 16
3
FIFO Alarm Distribution versus FIFO Offset Location (Single Sync Source Mode – SIF_SYNC only) ........ 16
4
DAC348x Double-Buffered Registers and the Associated Auto-Sync Registers
5
6
7
8
1
.................................
DAC348x Double-Buffered Synchronization Sources Description ..................................................
Synchronization Sources for NCO Accumulator ......................................................................
DAC348x Device Logics Synchronization Sources ...................................................................
Example Start-Up Routine (Based on DAC34SH84 Configuration) ................................................
27
27
28
30
32
Key Words
DAC3482, DAC3484, DAC34H84, DAC34SH84, DAC3282, DAC3283, DAC3174, FIFO, Synchronization
Acronyms
PVT: = shift in process, voltage, and temperature
FIFO:
First-In-First-Out memory buffer
RP:
read pointer of the FIFO
WP:
write pointer of the FIFO
ISTR:
FIFO input pointer strobe (DAC34H84 and DAC34SH84 control input)
FRAME:
functions similarly as ISTR. Also establishes data boundaries. (DAC3282,
DAC3283, DAC3482, and DAC3484 control input)
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SYNC:
OSTR:
DACCLK:
DATACLK:
FIFO-Out Clock:
Reset/Synchronization
Sources:
2
functions similarly as ISTR. The ISTR/FRAME and SYNC inputs may be
used interchangeably for the FIFO for flexibility. The choice between the two
inputs depends on factors such as PCB trace routing preference and digital
logic initialization sequence. The user may need to pay attention to the
specific inputs that can be used to initialize the various circuits in the
DAC348x family. For instance, this input serves as the only input that can
reset the on-chip PLL N-divider in order to synchronize the multi-device
PLLs. The ISTR/FRAME input does not have such capability.
FIFO output pointer strobe
DAC sampling clock. This is the final DAC update rate (FDAC) after the
interpolation stages
clock used to latch the LVDS data input
FIFO output pointer clock, where N is the interpolation factor. It is derived
from the DACCLK and could be DACCLK/N or DACCLK/2/N depending on
the DAC configuration mode.
sources to synchronize the digital logics. These are typically FRAME, ISTR,
SYNC, OSTR, and SIF_SYNC
FIFO Architecture for Synchronization
The DAC348x family (along with the DAC328x and DAC317x family) has new FIFO architecture allowing
synchronization of multiple devices. This FIFO architecture ensures that the latency of each DAC device is
the same, which allows the multiple DAC outputs to be phase aligned. Multi-device synchronization is
useful for systems such as beam-forming, active antenna array systems, diversity, and so forth.
2.1
The Purpose of the FIFO
Typically, the modern digital communication transmitter system consists of a clock generation source,
digital data source, and digital to analog converters (DAC). The DAC accepts the data from the data
source, and the DAC clock provides the time reference to latch the data into the DAC. The TI datasheet
(SLAS748, SLAS749) has specifications of the setup and hold timing requirements (that is, tS and tH,
respectively) for the input data and the DAC clock. Figure 1 shows the setup and hold time diagram.
CLOCK
tS
tH
DATA
tS = setup time
tH = hold time
Figure 1. Setup and Hold Time Diagram
System designers must ensure the data source and clock source are aligned to meet the DAC setup and
hold time requirement for correct output waveform. The time alignment (T_ALIGN) must be maintained over
the entire system operating range. Any shift in the data source or the DAC clock could cause bit errors
because the data cannot be registered correctly.
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- Shift in reference over PVT
- Shift in synthesizer over PVT
T_ALIGN
Clock
Source
T_ALIGN must be
maintained
DAC Clock
Data
Data
Source
DAC
- Shift in setup/hold time over PVT
- PCB trace variation
Figure 2. Typical Alignment Requirement for Data and Clock Sources
Figure 2 shows some of the challenges for meeting the requirements include the shift of reference and
clock synthesizer phase variation in clock source over process, voltage, and temperature (PVT), shift of
data source output timing specification over PVT, and addition of PCB trace delay variations. These
variables add system timing constraints and present constant challenges to designers when ensuring biterror free operation.
To relax the system timing requirement, most of the TI interpolation and straight DACs have integrated
FIFO (First-In-First-Out). The FIFO is located at the boundary between the input data and the internal
DAC digital blocks. The memory depth is usually 8 or 16 samples deep, and two pointers (write and read
pointers) provide reference to the memory during normal operation. Warning flags such as collision alarm
are determined by these two pointers.
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The purpose of the FIFO can be portrayed as an elastic buffer, which means the current data sample
does not have to be written and read at the same time. The write operation can occur sometime before
the read operation, as long as the time variation between the two operations is within the memory depth.
As shown in Figure 3, the ultimate goal for the FIFO is to absorb the timing variations between the input
data stream and the DAC sampling clock, thus relaxing the system timing.
Clock
Source
Current samples are loaded into
the current write pointer WP0
Data
Source
Write
0
1
2
3
4
5
6
7
DAC Clock
DAC
Read
Earlier samples are read from
read pointer RP4
Figure 3. FIFO used to Relax Alignment Requirement
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TI's DAC328x, DAC317x, and DAC348x families require two clock sources: the DATACLK and the
DACCLK, in order to function correctly. The DATACLK provides the time reference to latch in the digital
data correctly, while the DACCLK provides the clock to the DAC cores and internal digital logics. As
shown in Figure 4 of a typical system, the FPGA or custom ASIC provides the data stream along with the
DATACLK. The clock generation and distribution device, such as the TI CDCE62005 or LMK04800 family,
provides the reference clock to the FPGA and also the DACCLK source to the DAC.
LMK04800
CDCE62005
Clock
Source
DACCLK
DATACLK
Data
Source
FIFO
0
1
2
3
4
5
6
7
Data
FPGA
ASIC
DATACLK Domain
FIR Filters
Mixers
QMC Circuits
DAC
DACCLK Domain
Figure 4. Typical System Implementation for DAC Devices with FIFO
If the DACs do not have a FIFO, then the system must provide the DATACLK and DACCLK, which are
precisely aligned. The threshold for the alignment is typically listed as T_ALIGN requirement in the
datasheet. With the FIFO bypassed in the DAC, the input data must be handed to the internal digital logics
within a certain time frame in order for the DAC to operate properly. The T_ALIGN requirement basically
meets the timing constraints for the internal digital logics. For a typical system, this T_ALIGN requirement
adds additional design time and cost since designers must account for the delays in the data source in
order to match the alignment requirement properly.
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2.2
FIFO Operation
Write Pointer (WP)
Reset Position
ISTR/FRAME
0
1
2
3
4
5
6
7
Rising_ISTR
DATACLK
Rising_SYNC
SYNC
0
DATACLK
SIF_SYNC_R
1
2
4
8
DATACLK
DATACLK
syncsel_fifoin(3:0)
Read Pointer (RP)
Reset Position
fifo_offset(2:0)
FIFO-Out Clock
1 2 4 8
SIF_SYNC
SIF_SYNC_R
SCLK
Rising_ISTR
't
Rising_SYNC
't
SPI (SCLK Domain)
syncsel_fifoout(3:0)
SIF_SYNC_R
'T
FIFO-Out Clock
0
DATACLK
FIFO-Out
Clock
1
FIFO-Out Clock
DACCLK
OSTR
(from LVPECL receiver)
PFD
(from PLL N Divider)
PLL_ENA
DATACLK Domain
DACCLK Domain
The ISTR/FRAME and SYNC are resampled again by the FIFO-Out Clock. This is the main cause of the metastability
in brute force handoff. Other delay differences include bond wire difference and propagation delay of the
ISTR/FRAME and SYNC net. The ISTR/FRAME and SYNC take one path for the write pointer side and another path
for the read pointer side.
Figure 5. DAC348x FIFO Structure
Figure 5 shows the generic FIFO architecture of the DAC348x family. Similar concepts can be applied to
the DAC328x and DAC317x families. As mentioned previously, the FIFO is located between the boundary
of the DATACLK and DACCLK domain. The FIFO is 8 samples deep, where the write pointer (WP) and
read pointer (RP) indicate the current memory location. The write pointer can be synchronized by
ISTR/FRAME, SYNC, or SIF_SYNC. The read pointer can be synchronized by ISTR/FRAME, SYNC,
SIF_SYNC, or OSTR.
Among the DAC328x, DAC317x, and DAC348x family, the most innovative feature for the FIFO is the
ability to select and use different synchronization sources to synchronize the FIFO. Depending on the
implementation method, the overall latency of the DAC can be controlled. The following sections describe
the operations of each mode:
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2.2.1
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Single Sync Source Mode
Write Pointer (WP)
Reset Position
ISTR/FRAME
0
1
2
3
4
5
6
7
Rising_ISTR
DATACLK
Rising_SYNC
SYNC
0
DATACLK
SIF_SYNC_R
1
2
4
8
DATACLK
DATACLK
syncsel_fifoin(3:0)
Read Pointer (RP)
Reset Position
fifo_offset(2:0)
FIFO-Out Clock
1 2 4 8
SIF_SYNC
SIF_SYNC_R
SCLK
Rising_ISTR
't
Rising_SYNC
't
SPI (SCLK Domain)
syncsel_fifoout(3:0)
SIF_SYNC_R
'T
FIFO-Out Clock
0
DATACLK
FIFO-Out
Clock
1
FIFO-Out Clock
DACCLK
OSTR
(from LVPECL receiver)
PFD
(from PLL N Divider)
PLL_ENA
DATACLK Domain
DACCLK Domain
The ISTR/FRAME and SYNC are resampled again by the FIFO-Out Clock. This is the main cause of the metastability
in brute force handoff. Other delay differences include bond wire difference and propagation delay of the
ISTR/FRAME and SYNC net. The ISTR/FRAME and SYNC take one path for the write pointer side and another path
for the read pointer side.
Figure 6. Single Sync Source Mode
In Single Sync Source mode (Figure 6), the FIFO write and read pointers are reset from the same source,
either LVDS ISTR/FRAME or LVDS SYNC. The FIFO-Out Clock, which is derived from the DACCLK,
resamples the write pointer reset signal and generates the FIFO read pointer reset signal. This process
effectively hands off the FIFO read pointer signal from the DATACLK domain to the DACCLK domain.
(Figure 7). Since the two clocks are asynchronous, there is a small but distinct possibility of a metastability during the signal handoff.
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0
1
2
3
4
5
6
7
Read Pointer (RP)
Reset Position
fifo_offset(2:0)
FIFO-Out Clock
1 2 4 8
Rising_ISTR
't
Rising_SYNC
't
syncsel_fifoout(3:0)
'T
DATACLK
FIFO-Out
Clock
Figure 7. Write Pointer Synchronization Signal Handoff Across the FIFO
The meta-stability of the signal handoff is shown in Figure 8. The rising edge transition of the ISTR signal,
for example, is sampled by the DATACLK to reset the write pointer. The same ISTR signal crosses the
clock domain and is sampled by the FIFO-Out Clock. The FIFO-Out clock is derived internally from the
DACCLK, and is related to the DAC setting and interpolation factor. Table 1 shows the FIFO-Out Clock
rate related to the DAC sampling rate and interpolation factor, N. For instance, N = 2 for 2x interpolation.
Table 1. FIFO-Out Clock Rate
Device
FIFO Out Clock
DAC3484
DACCLK/N
DAC3482 Byte Wide Mode
DACCLK/N
DAC3482 Word Wide Mode
DACCLK/2/N
DAC34H84
DACCLK/N
DAC34SH84
DACCLK/N
Since the ISTR signal is asynchronous to the FIFO-Out clock, the signal could be sampled either one
FIFO-Out Clock cycle earlier or one cycle later. Figure 8 has two FIFO-Out clock possibilities. FIFO-Out
Clock (2) arrives earlier than FIFO-OUT Clock (1) by small time difference. The read pointer reset now
happens at a later time. Moreover, the consequence is that the read pointer cannot be precisely reset at
some defined time instant. This poses a limitation for multi-device synchronization because the latency of
multiple DAC devices may have variations due to the reset time uncertainty of the read pointer position.
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Rising_ISTR
DATACLK
WP Reset
Rising_ISTR
Two FIFO-Out Clock waveforms are shown because
Rising_ISTR is asynchronous to FIFO-Out Clock.
FIFO-Out Clock (1)
FIFO-Out Clock (1) and RP RESET (1) = Possibility #1
FIFO-Out Clock (2) and RP RESET (2) = Possibility #2
RP RESET (1)
FIFO-Out Clock (2)
RP RESET (2)
'T is very small
Figure 8. Meta-stability of the Synchronization Signal Handoff across the FIFO
The FIFO in this mode can still absorb the data delay differences due to variations in the digital source
output paths or board-level wiring. However, it is not possible to ensure that multiple DAC devices have
the same latency because the read pointer location of the DAC devices cannot be precisely aligned. For
instance, Figure 9 shows two DAC devices in Single Sync Source mode. To keep the analysis simple, this
example utilizes DAC input with double-data rate format (DDR), which latches one channel data on the
rising edge of DATACLK and another channel data on the falling edge of DATACLK (that is, DAC3482
Word Wide Input Format or the DAC34H84 Input Format). The first DAC (DAC#1) resets the read pointer
to position number four, RP4, immediately upon the first rising edge of FIFO-OUT Clock because the ISTR
transition has enough setup and hold time. This is the ideal case where both the read pointer and write
pointer are reset to the default position at the same time instance.
For the second DAC (DAC#2), the read pointer position resets to RP4 on the second rising edge of FIFOOUT Clock. The ISTR transition does not have enough setup and hold time for the first rising edge of
FIFO-OUT clock and have to wait for the second rising clock edge to register the reset.
I0
Q0
I1
Q1
I2
Q2
I3
Q3
I0
Rising_ISTR
Rising_ISTR
DATACLK
DATACLK
WP RESET
WP0 WP1
FIFO-Out
Clock
RP RESET
WP RESET
Q0
I1
Q1
I2
Q2
I3
Q3
WP0 WP1
FIFO-Out
Clock
RP4
RP5
RP RESET
RP4
RP5
DAC#1
DAC#2
Read Sequence Occurs on Time
Read Sequence Occurs Later by One Sample
Figure 9. Reset Time Difference of FIFO Read Pointer Position in Single Sync Source Mode
When comparing between the two DACs, the read pointer position slips by one sample. Figure 10 and
Figure 11 elaborate the write and read sequence over the next eight time instance (see Appendix A for a
side-by-side comparison). For DAC #1, data S0 is loaded into the write memory location #0 at time
instance #0, and also write sequence #0. Read memory location #4 does not have any data at the time
until four sequences later. After eight sequences, write sequence #8 load data S8 into write memory
location #8, and earlier sample S4 is loaded into the DAC at time instance #8.
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NOTE: During DAC initialization, the DAC output is held at mid-code by driving the TXENABLE pin
LOW. The DAC can start transmitting the data once the FIFO are filled with proper samples
by pulling TXENABLE pin HIGH.
I0
Q0
I1
Q1
I2
Q2
I3
Q3
Time instance #0
write sequence #0
Rising_ISTR
DATACLK
WP RESET
WP0
WP1
W0
W1
W2
W3
W4
W5
W6
W7
S0
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
XX
XX
XX
XX
R4
R5
R6
R7
R0
R1
R2
R3
W8
W1
W2
W3
W4
W5
W6
W7
S8
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
S4
S5
S6
S7
R4
R5
R6
R7
R8
R9
R10
R11
Time instance #0
write sequence #0
read sequence #0
FIFO-Out Clock
RP RESET
RP4
RP5
Time instance #8
write sequence #8
Previous Events
Current Events
Upcoming Events
Time instance #8
write sequence #8
read sequence #8
Figure 10. DAC#1 FIFO Write/Read Sequence (Read Sequence Occurs On Time)
The same derivation is done on the second case DAC#2. For this case, the read pointer reset does not
occur until time instance #1 and write sequence #1 complete. Therefore, the read pointer reset is delayed
by one sample. After eight sequences, the earlier data S3 is loaded into the DAC at time instance #8.
Note that DAC#1 and DAC#2 have one sample difference at the same exact time instance.
I0 Q0 I1 Q1 I2 Q2 I3 Q3
Time instance #0
write sequence #0
Time instance #1
write sequence #1
Rising_ISTR
DATACLK
WP RESET
WP0
WP1
W0
W1
W2
W3
W4
W5
W6
W7
S0
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
XX
XX
XX
XX
R4
R5
R6
R7
R0
R1
R2
R3
W8
W1
W2
W3
W4
W5
W6
W7
S8
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
S4
S5
S6
S7
R4
R5
R6
R7
R8
R9
R10
R11
Time instance #1
write sequence #1
read sequence #0
FIFO-Out Clock
RP RESET
RP4
RP5
Time instance #8
write sequence #8
Previous Events
Current Events
Upcoming Events
Time instance #8
write sequence #8
read sequence #7
Figure 11. DAC#2 FIFO Write/Read Sequence (Read Sequence Occurs Later by One Sample)
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The synchronization signal such as ISTR/FRAME or SYNC has to cross the DATACLK domain to the
DACCLK domain, and the clock domain crossing could introduce timing variation in time unit of DACCLK.
Along with the reset time meta-stability of the FIFO read pointer, the total latency variation could have time
units of both the FIFO-Out Clock period and DACCLK period. Furthermore, although less likely, other
factors such as DATACLK to DACCLK skew, PVT, and internal signal transition variation due to internal
net bond wire differences can introduce additional latency control variables.
Ultimately, if the Single Sync Source mode is used, the write pointer and read pointer delta among the
DAC devices cannot be precisely controlled, and the overall latency of all the DAC devices cannot be
matched. Although this mode is very suitable for simple system implementation without additional timing
control, it is not practical for applications requiring multi-device synchronization or precise latency control.
To facilitate latency synchronization, TI recommends Dual Sync Sources mode.
2.2.2
Single Sync Source mode with SIF_SYNC
Besides synchronizing the FIFO write and/or read pointers, the ISTR/FRAME or the SYNC signal also
aligns the FIFO’s internal data formatter to ensure the I and Q signals are aligned properly. For instance,
Figure 12 shows the data format of the DAC3484 in byte wide interface mode. The rising edge of
DATACLK occurs at the upper eight bits of sample A and sample B (that is, A[15:8] and B[15:8]), while the
falling edge of DATACLK occurs at the lower eight bits of sample A and sample B (that is, A[7:0] and
B[7:0]). The rising edge transition of ISTR/FRAME or SYNC signal is used to indicate the beginning of
sample A. If the FRAME or SYNC signal does not make the transition correctly, the internal pattern could
be swapped since the rising edge of DATACLK could also occur at the beginning of sample B. The same
concept also applies to the DAC328x and DAC317x families.
SAMPLE 0
SAMPLE 1
D[15:8]P/N
A0
[15:8]
A0
[7:0]
B0
[15:8]
B0
[7:0]
A1
[15:8]
A1
[7:0]
B1
[15:8]
B1
[7:0]
D[7:0]P/N
C0
[15:8]
C0
[7:0]
D0
[15:8]
D0
[7:0]
C1
[15:8]
C1
[7:0]
D1
[15:8]
D1
[7:0]
DATACLKP/N (DDR)
t(FRAME_SYNC)
Sync
Option #1
FRAMEP/N
Optional
Parity Bit
t(FRAME_SYNC)
Sync
Option #2
SYNCP/N
T0534-01
Figure 12. Byte Wide Data Transmission Format
For the DAC3482 in word wide mode, DAC34H84, and DAC34SH84, each sample is located on the
distinctive DATACLK edge as shown in Figure 13. Even if the ISTR/FRAME or SYNC signal is not
present, the samples will not be swapped in position.
12
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SAMPLE 0
D[15:0]P/N
I0
[15:0]
SAMPLE 1
Q0
[15:0]
I1
[15:0]
Q1
[15:0]
SAMPLE 2
I2
[15:0]
Q2
[15:0]
SAMPLE 3
I3
[15:0]
Q3
[15:0]
DATACLKP/N (DDR)
t(FRAME_SYNC)
Sync
Option #1
Optional
Parity Bit
FRAMEP/N
t(FRAME_SYNC)
Sync
Option #2
SYNCP/N
T0523-01
Figure 13. Word Wide Data Transmission Format
In some applications where the FPGA or ASIC has limited IO pins, the control signal can be eliminated by
using the SIF_SYNC SPI register bit. The FIFO (and other parts of the circuit such as NCO, QMCs, and
so forth) can be synchronized by a rising edge transition of the SPI register bit – SIF_SYNC. Figure 14
shows the signal path for the SIF_SYNC. A rising edge transition of the SIF_SYNC bit in CONFIG31 is
first registered by the SPI bus in the SCLK domain. The signal is then re-sampled by the DATACLK to
synchronize the FIFO write pointer position. It is also re-sampled by the FIFO-OUT Clock to synchronize
the FIFO read pointer position.
Write Pointer (WP)
Reset Position
ISTR/FRAME
0
1
2
3
4
5
6
7
Rising_ISTR
DATACLK
SYNC
Rising_SYNC
0
DATACLK
SIF_SYNC_R
1
2
4
8
DATACLK
DATACLK
syncsel_fifoin(3:0)
Read Pointer (RP)
Reset Position
fifo_offset(2:0)
FIFO-Out Clock
1 2 4 8
SIF_SYNC
SIF_SYNC_R
SCLK
Rising_ISTR
't
Rising_SYNC
't
syncsel_fifoout(3:0)
SIF_SYNC_R
'T
FIFO-Out Clock
0
SPI (SCLK Domain)
DATACLK
FIFO-Out
Clock
1
FIFO-Out Clock
DACCLK
OSTR
(from LVPECL receiver)
PFD
(from PLL N Divider)
PLL_ENA
DATACLK Domain
DACCLK Domain
Figure 14. Single Sync Mode Using SIF_SYNC
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Since the SIF_SYNC signal is asynchronous to both the DATACLK and FIFO-OUT Clock, not only it is
possible that the read pointer position may vary from time-to-time and device-to-device, the sample
sequence loaded into the FIFO memory may also be different. The example in Figure 15 demonstrates
this idea.
SIF_SYNC is asynchronous to both the DATACLK and
DACCLK. It is possible that the sync event occurs before or
after the first sample with respect to other DAC devices.
I0
Q0
I1
Q1
I2
Q2
I3
Q3
I0
SIF_SYNC
SIF_SYNC
DATACLK
DATACLK
WP RESET
WP RESET
WP0 WP1
FIFO-Out
Clock
Q0
I1
Q1
I2
Q2
WP0
WP1
RP4
RP5
I3
Q3
FIFO-Out
Clock
RP RESET
RP4
RP5
RP RESET
DAC#1
DAC#3
Read Sequence Occurs on Time
Read Sequence Occurs Ahead by One Sample
Figure 15. Reset Time Difference of FIFO Read Pointer in SIF_SYNC Mode
The ideal DAC#1 (also shown in the previous section) has both write pointer and read pointer reset at
sample S0. In DAC#3, the SIF_SYNC source arrived one sample later. The write pointer and read pointer
reset to default at S1 instead of S0, and effectively, DAC#3 loads the same memory into the FIFO one
sample earlier than DAC#1 (Figure 16). Comparing Figure 10 and Figure 16 indicates the sample time
difference (see Appendix B).
SIF_SYNC is asynchronous to both the DATACLK
and DACCLK. It is possible that the sync event occurs
before or after the first sample with respect to other
DAC devices.
Time instance #0
write sequence #0
I1
Q1
I2
Q2
I3
Q3
I4
Q4
SIF_SYNC
DATACLK
WP RESET
WP0
WP1
RP4
RP5
W0
W1
W2
W3
W4
W5
W6
W7
S1
S2
S3
S4
S5
S6
S7
S8
S1
S2
S3
S4
XX
XX
XX
XX
R4
R5
R6
R7
R0
R1
R2
R3
W8
W1
W2
W3
W4
W5
W6
W7
S9
S2
S3
S4
S5
S6
S7
S8
S1
S2
S3
S4
S5
S6
S7
S8
R4
R5
R6
R7
R8
R9
R10
R11
Time instance #0
write sequence #0
read sequence #0
FIFO-Out Clock
RP RESET
Time instance #8
write sequence #8
Previous Events
Current Events
Upcoming Events
Time instance #8
write sequence #8
read sequence #8
Figure 16. DAC#3 FIFO Write/Read Sequence (Read Sequence Occurs Ahead by One Sample)
Primarily, this mode allows the user to save I/O pins in the FPGA or ASIC. With the existing read pointer
uncertainty and also the addition of write sequence uncertainty (due to the asynchronous nature of
SIF_SYNC to both the DATACLK and the DACCLK), latency control remains a challenge and is not
practical in this mode. If the system requires multi-device synchronization, TI recommends the Dual Sync
Sources mode.
14
DAC348x Device Configuration and Synchronization
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2.3
Optimize FIFO Location for Single Sync Source Mode
The default FIFO write pointer position of WP0 and read pointer position RP4 creates the optimal FIFO
setup. The read pointer position is placed in the middle of the FIFO to absorb timing variations in either
the write direction or the read direction shown in Figure 17. An example for the worst-case timing variation
in the write direction would be the DATACLK and the data stopped completely while the read operation
continues with the DACCLK running. In the default setup, the FIFO could absorb, at most, three samples
before collision. The same principle can be applied to the worst-case timing variation in the read direction
where the DACCLK and the read operation stop completely while the write operation continues. In this
case, the FIFO could also absorb three samples before collision. Since the FIFO loops around, the optimal
write pointer position is in the beginning and the read pointer position is in the middle.
0
1
2
3
4
5
6
7
Write pointer continues to run
0
1
2
3
4
5
6
7
Write pointer stucked at WP0
3 memory depth available
before FIFO collision
Read pointer stucked at RP4
Read pointer continues to run
3 memory depth available
before FIFO collision
Figure 17. FIFO Memory Buffer for Both the Write and Read Direction
Since the Single Sync Source mode is not recommended for applications requiring precise latency control,
the following section only describes the optimal setup for system with single DAC device or multi-DAC
devices system without the need for latency synchronization. As mentioned in the previous section, the
Single Sync Source mode could cause the read pointer position to slip in either direction. For the
SIF_SYNC operation, both the write pointer position and read pointer position could slip in either direction.
Therefore, it is possible that the spacing between the read pointer position and write pointer position is not
optimal at start-up.
To help designers optimize the FIFO setup at start-up, the DAC families includes FIFO alarms to indicate
the pointer position delta. The three primary alarms are FIFO 2-away, FIFO 1-away, and FIFO collision.
FIFO 2-away indicates that the absolute read and write pointer position difference (that is, either write to
read pointer position or read to write pointer position) has two spaces. FIFO 1-away indicates that the
absolute pointer position difference have one space. FIFO collision indicates that the FIFO pointers have
collided and requires re-synchronization. Figure 18 shows the possible conditions to trigger the alarms.
WP2
WP6
2-away alarms
(two possible positions)
1-away alarm
(two possible positions)
collision alarm
(one position only)
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
WP3
RP4
WP5
RP4
WP4
RP4
Figure 18. Possible Alarm Conditions (Assuming RP4 Occurs at the Moment)
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The alarm registers in the DAC family have a memory system and do not self-clear upon system recovery.
This is important for the designer if the system diagnosis algorithm only consisted of polling architecture
(as opposed to both polling and interrupt service routine). If the alarms do self-clear upon system
recovery, there are possibilities that the polling interval missed the alarm, and the system will not be able
to detect the alarm and issue remedies for the error.
NOTE: The DAC family does have a dedicated alarm signal output to trigger the interrupt service
routine (ISR), if the system design requires such provision.
Upon system power up, the alarm registers could detect various alarms due to power up transitions. For
instance, the DACCLK could be running before the DATACLK, and the FIFO alarms could trigger.
Therefore, it is important to clear the alarm registers by writing all zeros to the alarms registers before
reading back the register. After the system clocks and the DAC have settled, the system diagnosis
algorithm should check the alarms registers. If the FIFO alarms remain triggered, the read pointer position
(programmed in the FIFO offset register) can be adjusted accordingly to clear the alarms and optimize the
FIFO spacing.
Table 2 shows the typical FIFO alarm behavior of each read pointer position after the initial start-up
synchronization. The experiment consists of five independent tests of eight different start-ups. For each
start-up, the FIFO write pointer position is always reset to WP0, and the FIFO read pointer position is
programmed from RP0 to RP7. Therefore, different FIFO alarms will trigger at each start-up.
Table 2. FIFO Alarm Distribution versus FIFO Offset Location (Single Sync Source Mode – ISTR
only)
Read Pointer Position
Test #1
Test #2
Test #3
Test #4
Test #5
RP0
collision
collision
collision
collision
collision
RP1
1
1
1
1
1
RP2
2
2
2
2
2
RP3
no
no
no
no
no
RP4
no
no
no
no
no
RP5
no
no
no
no
no
RP6
2
2
2
2
2
RP7
1
1
1
1
1
When compared among the power up status with various FIFO offset position, the data has shown the
optimal green region where the least amount of FIFO alarms occurred. The actual green region may shift
due to the design of Single Sync Source mode, DATACLK to DACCLK skew, sequence of DATACLK and
DACCLK presence, and PVT. If the optimal region of FIFO offset is found, the FIFO offset adjustment
process can quickly yield the best FIFO pointer position.
Table 3 shows the test result of Single Sync Source mode with SIF_SYNC. Note that the SIF SYNC only
mode has more variations of the alarm distribution due to the SIF_SYNC being asynchronous to both the
DATACLK and DACCLK.
Table 3. FIFO Alarm Distribution versus FIFO Offset Location (Single Sync Source Mode –
SIF_SYNC only)
16
Read Pointer Position
Test #1
Test #2
Test #3
Test #4
Test #5
RP0
1 away
1 away
1 away
1 away
collision
RP1
2 away
1 away
2 away
1 away
2 away
RP2
0
0
2 away
0
0
RP3
0
0
0
0
0
RP4
0
0
0
0
0
RP5
2 away
0
2 away
0
0
RP6
2 away
2 away
2 away
2 away
1 away
RP7
1 away
1 away
1 away
1 away
1 away
DAC348x Device Configuration and Synchronization
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The following software loop in Figure 19 demonstrates the alarm checking algorithm and the associated
FIFO offset adjustment for optimal write and read pointer spacing. Each path starts off with the default
FIFO offset and the checking of the FIFO alarms. Depending on the alarms detected, the FIFO offset is
adjusted accordingly. After the adjustment, the alarms are rechecked to ensure the FIFO has the optimal
spacing. Since the FIFO pointers in this mode have uncertainties in the exact pointer position, the loop
has implemented additional error checking and FIFO offset corrections. Each path can be reused
depending on the alarm status.
Default
Offset
Check
Alarm
No
alarm
Exit
2 away
alarm
1 away
alarm
collision
alarm
Offset
+1
Offset
+2
Offset
+3
Check
Alarm
Check
Alarm
Check
Alarm
No
Alarm
2 away
alarm
1 away
alarm
No
Alarm
2 away
alarm
1 away
alarm
No
Alarm
2 away
alarm
1 away
alarm
collision
alarm
Exit
Repeat
2 away
Go to
1 away
Exit
Go to
2 away
Repeat
1 away
Exit
Go to
2 away
Go to
1 away
Repeat
Collision
Figure 19. FIFO Offset Adjustment Algorithm
The ultimate goal for optimizing the FIFO position in Single Sync Source mode is to adjust the read
pointer such that it has enough space from the write pointer in either direction of the FIFO space
movement. This will be the best approach for systems with a single DAC device or multi-DAC devices
system without the need for latency control.
2.4
Dual Sync Sources Mode
The Dual Sync Sources mode is the recommended mode of operation for those applications that require
precise control of the output timing and latency. In Dual Sync Sources mode (Figure 20), the FIFO write
and read pointers are synchronized independently by two sources. The FIFO write pointer is reset using
the LVDS ISTR/FRAME or SYNC signal, and the FIFO read pointer is reset using the OSTR signal (either
from external LVPECL source or the on-chip PLL’s internal PFD frequency). The OSTR signal can control
the latency (or phase) of the output for either a single chip or multiple chips. Multiple DAC devices can be
fully synchronized in this mode.
The ISTR/FRAME or SYNC signal should come from the data source and has the same timing
relationship as the DATACLK, and the OSTR signal comes from the clock source and has the same timing
relationship as DACCLK. This implementation does not need to re-sample the reset signal in two different
clock domains, thus eliminating the possibility of meta-stability during reset signal handoff.
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Write Pointer (WP)
Reset Position
ISTR/FRAME
0
1
2
3
4
5
6
7
Rising_ISTR
DATACLK
SYNC
Rising_SYNC
0
DATACLK
SIF_SYNC_R
1
2
4
8
DATACLK
DATACLK
syncsel_fifoin(3:0)
Read Pointer (RP)
Reset Position
fifo_offset(2:0)
FIFO-Out Clock
1 2 4 8
SIF_SYNC
SIF_SYNC_R
SCLK
Rising_ISTR
't
Rising_SYNC
't
SPI (SCLK Domain)
syncsel_fifoout(3:0)
SIF_SYNC_R
'T
FIFO-Out Clock
0
DATACLK
FIFO-Out
Clock
1
FIFO-Out Clock
DACCLK
OSTR
(from LVPECL receiver)
PFD
(from PLL N Divider)
PLL_ENA
DATACLK Domain
DACCLK Domain
Figure 20. Dual Sync Sources Mode
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The two key principles in achieving the multi-device synchronization are the following:
1. The data is loaded into the FIFO in the same order and same FIFO location for all the DAC devices.
The ISTR/FRAME or SYNC signal needs to be aligned with the first sample properly in order to load
the data in the correct sequence.
2. All the DAC devices read the same FIFO location at the same time to achieve the same latency. In
order to meet this condition, the OSTR and DACCLK signals must have the same delay among the
DAC devices in order to reset the FIFO read pointer at the same time.
The following example demonstrates this idea. Shown in Figure 21, the system contains two data sources
and two DAC devices. Each data path to the DAC device has different time delay due to the shift in data
source timing over PVT and PCB trace variations. Path #1 has less delay than Path #2. To keep the
analysis simple again, this example utilizes DAC input with DDR format. The time difference between the
paths is two DATACLK cycles, or two samples in DDR fashion, which is shown in Figure 22.
Data
Source
#1
Data
Source
#2
Path #1 = 'T1
DAC
Device
#1
Path #2 = 'T2
In this example:
x 'T1 is less than 'T2
x The difference in time delay is due to shift in data
source timing over PVT and PCB trace variation
x 'T2 ± 'T1 = two DATACLK cycles or two
samples in DDR fashion. For example, DAC3482
Word Wide Input Format or DAC34H84 Input
Format
DAC
Device
#2
Figure 21. Multi-Device Synchronization Example: Path#2 Has Additional Two Sample Delay when
Compared to Path#1
Path #1
Path #2
{
DATACLK #1
{
DATACLK #2
ISTR #1
DATA #1
I0
Q0
I1
Q1
I2
Q2
I3
Q3
I4
Q4
I5
Q5
I6
Q6
I7
Q7
X
X
X
X
I0
Q0
I1
Q1
I2
Q2
I3
Q3
I4
Q4
I5
Q5
ISTR #2
DATA #2
'T2 - 'T1
Time
Figure 22. Multi-Device Synchronization Example: Data Sequence versus Time between Path#1 and
Path#2
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The rising edge of the ISTR signal has two purposes: to indicate the first sample of the data sequence,
and to reset the FIFO write pointer position to default WP0. This indication allows the data of different data
paths to be loaded in the same sequence regardless of the data path delay. At this point, this
implementation allows the system to meet the first requirement of multi-device synchronization.
To continue the demonstration, Figure 23 shows FIFO write process of the system. Three snap-shots of
the FIFO are demonstrated. The first snap-shot shows the time instance #2 where Path#1 is loading
sample S2, while Path#2 is loading the initial sample, S0. The second and third snap-shots show the
subsequent FIFO states three and six samples later, respectively.
The first and second snap-shots have demonstrated that the data sequences of the two paths are loaded
into the FIFO in the same order. Once the FIFOs of the two paths have been fully loaded, the same data
sample can be released from the FIFO at the same time. The synchronization of the FIFO release time is
based on the OSTR signal. Per the second requirement of multi-device synchronization, the system
implementation must guarantee that the OSTR and DACCLK timing are the same for all the DAC devices
in the system. Once this requirement is met, all the DAC devices can read the same data sequence at the
same time. Since the rest of the digital logics after the FIFO operate in the DACCLK domain, the DAC
devices in the system can achieve the same latency.
To simplify the analysis, the FIFO read process is not presented until the third snap-shot of the FIFO. In
actual system implementation, the FIFO write and read sequence is synchronized during the DAC
initialization stage, and the TXENABLE of the DAC is held LOW to disable the DAC output. In this
process, the FIFO memory can be flushed out without the DAC outputting transient waveforms, which may
damage subsequent signal chain devices. Once the FIFO is initialized properly with the proper samples
loaded, the TXENABLE can be pulled HIGH to enable the DAC output for transmission.
Ultimately, the FIFO absorbs the input path delay difference to allow equal latency after the FIFO. This
example has input path delay difference of two samples, which is within the FIFO depth. If the input path
delay is greater than the FIFO depth, then the FIFO cannot absorb the delay difference, and latency
alignment cannot be achieved.
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DAC348x Device Configuration and Synchronization
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Path #2
Path #1
Time instance #0
write sequence #0
Time instance #1
write sequence #1
Time instance #2
write sequence #2
W0
W1
W2
W3
W4
W5
W6
W7
S0
S1
S2
S3
S4
S5
S6
S7
Time instance #2
write sequence #0
W0
W1
W2
W3
W4
W5
W6
W7
S0
S1
S2
S3
S4
S5
S6
S7
W0
W8
W1
W2
W3
W4
W5
W6
W7
S0
S8
S1
S2
S3
S4
S5
S6
S7
W0
W8
W1
W2
W3
W4
W5
W6
W7
S0
S8
S1
S2
S3
S4
S5
S6
S7
Three Samples
Afterwards
Time instance #5
write sequence #5
W0
W8
W1
W2
W3
W4
W5
W6
W7
S0
S8
S1
S2
S3
S4
S5
S6
S7
Time instance #5
write sequence #3
Three Samples
Afterwards
Time instance #8
write sequence #8
W8
W1
W2
W3
W4
W5
W6
W7
S8
S1
S2
S3
S4
S5
S6
S7
Time instance #8
write sequence #6
Previous Events
Current Events
Upcoming Events
Samples in the FIFO are simultaneously
released. The release time is synchronized
by OSTR signal to the FIFO read pointer.
Figure 23. Multi-Device Synchronization Example: FIFO State Snap-Shots
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Beside data, control signals such as SYNC and ISTR, are treated as data and can be read from the FIFO
at the same time instance. An example is shown in Figure 24, where the rising edge of SYNC pulse is
registered at the same time sample S4 is latched. When all the DAC devices in the system release RP4 in
the FIFO, the SYNC pulse stamp is released. This stamp will be registered by the appropriate digital logics
(based on DAC programming) and used for logic synchronization. This is useful for synchronizing internal
digital logics such as NCO and QMC. These circuits can process the signal amplitude and phase. By
setting these circuits to look for the synchronized control signals, multiple devices can adjust the signal
amplitude and phase at the same precise moment.
{
Path #1
DATACLK #1
ISTR #1
DATA #1
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
SYNC#1
Rising edge of SYNC pulse is
registered and loaded into FIFO
write pointer WP4. It will be
read at the same time among all
the DAC devices to allow
synchronization of digital logics.
DATACLK #2
Path #2
{
ISTR #2
DATA #2
X
X
X
X
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
SYNC#2
Time
Figure 24. Multi-Device Synchronization Example: SYNC Pulse Loading for Logic Synchronization
Figure 25 shows the typical connection of the DAC348x family configured in external clock mode. With the
DATACLK serving as the timing reference, the logic device provides the data and the control signals such
as ISTR/FRAME and SYNC. On the other hand, the external clock synthesizer and distribution circuits,
such as the LMK04800 family and the CDCE62005, provides the OSTR signal. In this case the DACCLK
serves as timing reference, and the timing unit must ensure the OSTR and DACCLK signals going to each
DAC348x device have zero skew. The required timing diagram is shown in Figure 26.
DACCLKP/N
OSTRP/N
D[15:0]P/N
FPGA
DAC3484 DAC1
FRAMEP/N
Clock Generator
PLL/
DLL
LVDS Interface
LVPECL Outputs
Delay 1
DATACLKP/N
Variable delays due to variations in the FPGA(s) output
paths or board level wiring or temperature/voltage deltas
Outputs are
Phase Aligned
D[15:0]P/N
LVPECL Outputs
FRAMEP/N
Delay 2
DATACLKP/N
DAC3484 DAC2
OSTRP/N
DACCLKP/N
B0454-03
Figure 25. Typical Dual Sync Sources System Setup with DAC348x in External Clock Mode
22
DAC348x Device Configuration and Synchronization
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LVPECL Pairs (DAC3484 1)
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DACCLKP/N(1)
tS(OSTR)
tH(OSTR)
tSKEW ~ 0
LVPECL Pairs (DAC3484 2)
OSTRP/N(1)
DACCLKP/N(2)
tS(OSTR)
tH(OSTR)
OSTRP/N(2)
•
•
•
•
T0526-03
Figure 26. Timing Diagram for LVPECL Synchronization Signals of DAC3484
Figure 27 shows the typical connection of the DAC348x family configured with on-chip PLL mode. Similar
to the previous clocking mode, the logic device provides the data and the control signals such as
ISTR/FRAME and SYNC, with the DATACLK serving as the timing reference. Whereas the external
clocking mode requires timing unit to provide the necessary OSTR and DACCLK signals, the on-chip PLL
mode can generate the OSTR and DACCLK signals within the device itself.
DACCLKP/N
SYNCP/N
D[15:0]P/N
FPGA
DAC3484 DAC1
FRAMEP/N
Clock Generator
PLL/
DLL
LVDS Interface
Outputs
Delay 1
DATACLKP/N
Variable delays due to variations in the FPGA(s) output
paths or board level wiring or temperature/voltage deltas
Outputs are
Phase Aligned
D[15:0]P/N
Outputs
FRAMEP/N
DATACLKP/N
Delay 2
DAC3484 DAC2
SYNCP/N
DACCLKP/N
B0455-03
Figure 27. Typical Dual Sync Sources System Setup with DAC348x in On-Chip PLL Mode
To achieve synchronization, multiple DAC348x device on-chip PLLs must be synchronized in order to
have zero skew OSTR and DACCLK signals. As shown in Figure 28, the on-chip PLL is synchronized by
the rising edge of LVDS SYNC signal going to the N-divider circuit. The idea is that if the reference
frequencies of the PLLs are aligned in time, then the OSTR and DACCLK signals will also be aligned.
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FIFO Architecture for Synchronization
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External Loop Filter
0
DAC348x Input
DACCLK_internal
1
DACCLKP
DACCLKN
REFCLK
N
Divider
SYNCP
PLL_ENA
(Config24)
PFD &
CP
Prescaler
PLL_SYNC
SYNCN
Internal Loop Filter
VCO
M
Divider
1
OSTR (PLL generated)
OSTR_internal
OSTRP
0
OSTRN
PLL_ENA
(Config24)
Figure 28. DAC348x On-Chip PLL DACCLK and OSTR Generation
One important note about the OSTR signal in PLL mode is that the OSTR is the PFD frequency after the
N-divider. Therefore, the reference clock (REFCLK), N-divider, and M-divider must be configured to meet
the OSTR frequency requirement and also the PLL lock requirement.
2.5
Optimal FIFO Position Setup for Dual Sync Sources Mode
In Dual Sync Sources mode, the FIFO read pointers of multiple DAC devices can start at the same
location and same exact time instance given that the OSTR and DACCLK signals among all the devices
have the same delay. As long as the load sequences of each DAC devices are the same, the FIFO’s
memory depth can absorb some variations at the data input side. The FIFO has limited length and has to
absorb timing variations from both input and output pointer side. Therefore, it is important that the FIFO
position starts in an optimal position.
In the previous example of Path#1 and Path#2, both paths have to have the same read pointer position in
order to have the same latency. However, the write side of Path#1 has less delay than Path#2, and
Path#1 will load data into the FIFO earlier than Path#2. Therefore, Path#1 has a narrower FIFO write to
read pointer position gap than Path#2.
The FIFO offset adjustment procedure is shown in Figure 29. The green arrow shows the write-to-read
pointer gap, while the red arrow shows the read-to-write pointer gap. When the pointer gap is narrower,
the chance of FIFO collision is higher. Counting from the write pointer to read pointer, Path#1 with read
pointer position of 4 only has one memory gap. If somehow the DATACLK or DACCLK has interruption or
the skew has changed, for instance, the clock generator started to shift the delay of the OSTR and
DACCLK signals over PVT, the FIFO read pointer could reset earlier and cause collision.
24
DAC348x Device Configuration and Synchronization
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Before
After
FIFO write pointer
FIFO write pointer
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
5
5x gaps
1x gap
4x gaps
2x gaps
Path #1
FIFO read pointer set at space #4
4
4
5
5
5
6
6
6
6
7
7
7
7
FIFO write pointer
3x gaps
FIFO read pointer set at space #5
FIFO write pointer
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
5
4x gaps
Path #2
FIFO read pointer set at space #4
4
4
5
5
5
6
6
6
6
7
7
7
7
3x gaps
FIFO read pointer set at space #5
2x gaps
Figure 29. FIFO Offset Adjustment for Dual Sync Sources Mode
By changing FIFO read pointer position from RP4 to RP5, the write pointer to read pointer gap (shown in
green) has increased from one to two in Path#1. The read pointer to write pointer gap (shown in red) has
decreased from five gaps to four gaps, but it is the best option without disturbing the setup for Path#2. If
the read pointer position is increased further, then Path #2 will not have enough read pointer to write
pointer gap. If either the DATACLK or DACCLK is disturbed, the FIFO does not have much buffer and
collides with higher probability. As mentioned in the previous section, designers should check the FIFO
alarms upon start-up to ensure each device has optimal FIFO position.
3
Digital Logic Synchronization
Besides the FIFO, other digital logics such as clock divider, data formatter, mixers, and quadrature
modulator correction features, require initialization during start-up to ensure proper operation. Each of the
digital blocks is described in this section.
3.1
FIFO and Data Formatter (Configured and Synchronized Upon Initial Start-Up):
The FIFO synchronization method would depend on the end application requirement. Depending on the
Single Sync Source mode or Dual Sync Sources mode configuration, the syncsel_fifoin(3:0) and the
syncsel_fifoout(3:0) in Config32 register can be programmed accordingly.
For the DAC3482 and DAC3484, the data interface options can be either 16-bit word-wide interface or 8bit byte-wide interface. The FIFO includes a data formatter to format the FIFO memory accordingly. The
synchronization source can be selected by syncsel_dataformatter(1:0) in Config31, with the option
including the FRAME or SYNC. As mentioned previously, the rising edge of FRAME or SYNC can be used
to establish the data boundary to ensure the data are interpreted correctly.
The data formatter is not needed for the DAC34H84 and DAC34SH84 since the 32-bit interface forces the
A and C channels always latched on the rising edge of DATACLK and B and D channels always latched
on the falling edge of DATACLK.
The DAC3482 word-wide interface operates in the similar fashion and some users may choose to use
SIF_SYNC to synchronize the FIFO. In this case, the syncsel_dataformatter(1:0) in Config31 can be set to
10 or 11 option for no sync options.
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Clock Divider (Configured and Synchronized upon Initial Start-Up):
DACCLK (FS)
OSTR
DivB
0
ISTR
SYNC
0
SIF_SYNC
DivA
1
2
4
8
syncsel_fifoin(3:0)
(Config32)
reset
1
clkdiv_sync_ena
(Config0)
DivC
clkdiv_sync_sel
(Config31)
Figure 30. Simplified Clock Divider Block Diagram
The purpose of the clock divider is to provide divided-down clocks. Figure 30 shows the simplified clock
divider structure. The source of the clock divider comes from the DACCLK, and the clock divider can be
reset by the OSTR signal or the FIFO input pointer reset source.
The clock divider needs to be synchronized at start-up along with the FIFO and data formatter (if needed).
The clock divider synchronization source will be the same as the FIFO output pointer synchronization
source. In Single Sync Source mode, the clock divider will be synchronized by ISTR, SYNC, or
SIF_SYNC. In Dual Sync Sources mode, the clock divider will be synchronized by the OSTR signal (either
externally provided to the DAC348x or internally generated by the PLL PFD).
3.3
Double Buffered Registers (Adjustable During System Operation).
FIR filters and coarse mixers have pre-set algorithm values. Once these circuits are enabled at start-up
along with the start-up synchronization routine (that is, FIFO and clock divider synchronization), additional
synchronization is not required. Since the NCO and QMC logics have programmable algorithms, the
circuits require additional synchronization of the double-buffered register. A double-buffered register is
designed to prevent instantaneous change to logic behavior when the desired logic behavior requires
more than one serial port interface (SPI) configuration. For instance, the NCO register requires two 16-bit
frequency information and one 16-bit phase information. The SPI register is 16-bit per register, and if the
NCO logic changes instantaneously for every SPI write transaction, the output frequency may change
three times over the programming period before settling to the final output frequency. The same principle
applies to QMC gain/phase adjustment and QMC offset adjustment circuits. The double-buffered registers
prevent unintentional gain, phase, and/or offset corrections during the programming of the register.
26
DAC348x Device Configuration and Synchronization
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Programmable Values
for the Circuit
DAC348x
Double-Buffered Registers
Auto-Sync
SYNC
OSTR
SIF_SYNC
1
2
4
8
Double-Buffered Register
synchronization source selection. The
synchronization source can be more
than one as long as potential
synchronization conflict is avoided.
Figure 31. Double-Buffered Registers
For flexibility, the double-buffered register can have one or more synchronization sources. The sources
can be SIF_SYNC, SYNC, OSTR, or auto-sync. For synchronization using the SIF_SYNC, SYNC, and
OSTR, the corresponding rising edge transition of the signal creates a synchronization event. For autosync selection, the synchronization occurs only when specific registers are written, and the register may
not necessary be the last sequence of registers. Therefore, carefully plan out the synchronization method
and design the start-up sequence to include auto-sync registers for proper circuit initialization. Table 4
shows the double-buffered synchronization source select register for each digital block and the
corresponding auto-sync register, and the detailed description of synchronization sources can be found on
Table 5.
Table 4. DAC348x Double-Buffered Registers and the Associated Auto-Sync Registers
Digital Blocks
Double-Buffered Synchronization Source Selection
Auto-Sync Register
QMC Gain/Phase AB Channels
Config30
Config16
QMC Gain/Phase CD Channels
Config30
Config17
QMC Offset AB Channels
Config30
Config8
QMC Offset CD Channels
Config30
Config10
NCO Mixer AB Channels
Config31
Config18
NCO Mixer CD Channels
Config31
Config19
Table 5. DAC348x Double-Buffered Synchronization Sources Description
Synchronization
Source Selection
Synchronization Source
Description
8
SIF_SYNC
Rising edge transition of the SIF_SYNC bit in Config31, bit2
4
SYNC
Rising edge transition on the LVDS SYNC. FIFO must be enabled
2
OSTR
Rising edge transition on the OSTR signal (either externally provided on the LVPECL
OSTRp/n source or internally generated PFD)
1
Auto-Sync from Register Write
writing to the auto-sync register
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Programmable digital logics such as NCO and QMC circuits allow the system to change the DAC output
values as the DAC is running. The output adjustments require the double-buffered synchronization
sources as mentioned above, and these sources can be the same sources for the FIFO, data formatter,
and the clock divider synchronization sources. Accidental reset to the FIFO, data formatter, and the clock
divider may cause unexpected output behavior. Therefore, it is important for users to avoid this type of
conflicts in system design.
For instance, when the LVDS SYNC or external LVPECL OSTR signal is used to synchronize the doublebuffered registers, the occurrence of the rising edge signal transition must match the clock timing (that is,
DATACLK for SYNC and DACCLK for OSTR) and must not disrupt the FIFO flow. The design of the
signal transition must occur at the beginning of the eight sample spaces.
If the programming of the double-buffered logics could affect the FIFO, data formatter, or clock divider
operation, a good design practice is to disable FIFO, data formatter, and clock-divider synchronization
when the same synchronization sources are shared. After the initial synchronization of the FIFO, data
formatter, and clock divider, these circuits can be programmed to not pay attention to the synchronization
sources.
Finally, the easiest way is to plan out the synchronization signal such that the synchronization sources for
the double-buffered registers are different than the FIFO, the data formatter, and the clock divider. For
instance, the auto-sync register write feature is a dedicate synchronization source for the double-buffered
registers.
3.4
NCO Accumulator (Adjustable During System Operation)
The NCO accumulator is used to generate the desired sine and cosine term from a look-up table. After
loading the frequency and phase information into the NCO double buffered registers, the NCO
accumulator requires a reset to ensure that a correct, known state is initialized. The NCO block diagram is
shown in Figure 32.
32
16
Frequency
Register
32
32
Σ
Accumulator
CLK
32
16
16
Σ
sin
Look-Up
Table
16
cos
RESET
16
fDAC
NCO SYNC
via
syncsel_NCO[3:0]
Phase
Register
B0026-03
Figure 32. NCO Block Diagram
Table 6 shows the synchronization sources for the NCO accumulator.
Table 6. Synchronization Sources for NCO Accumulator
28
Synchronization
Source Selection
Synchronization Source
Description
8
SIF_SYNC
Rising edge transition of the SIF_SYNC bit in Config31, bit2
4
SYNC
Rising edge transition on the LVDS ISTR. FIFO must be enabled
2
OSTR
Rising edge transition on the OSTR signal (either externally provided on the
LVPECL OSTRp/n source or internally generated PFD)
1
ISTR
Rising edge transition on the LVDS ISTR. FIFO must be enabled
DAC348x Device Configuration and Synchronization
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Per register Config21 of the DAC348x, the sources can be SIF_SYNC, SYNC, OSTR, or ISTR. If the end
application does not require specific timing or phase synchronization, the rising edge transition of the
SIF_SYNC bit is the easiest to implement and sufficient for most of the general purpose NCO accumulator
initialization. While the ISTR, SYNC, and/or OSTR can be used for accumulator reset, the primary
intention of these synchronization methods is to ensure the NCOs of multiple DAC devices reset at the
same instance of time to achieve output phase alignment.
As mentioned in Section 2.4, the ISTR and/or SYNC are treated as data in the FIFO. If the ISTR and/or
SYNC data are loaded to the devices of the same system in the correct sequence, then the signal data is
read at the same time instance. The signal data resets the NCO accumulator at the same time instance,
thus achieving phase synchronization of multiple NCOs.
When the OSTR option is selected, the synchronization signal is either the external OSTR signal or the
internally generated OSTR signal from the on-chip PLL N-divider. As part of the multi-device
synchronization requirement, the OSTR signals to the multiple devices must be time aligned. Therefore,
the NCO accumulators of multiple devices will also be aligned.
Synchronizing the NCO accumulator may pose some issues due to the repeating nature of some
synchronization sources and the looping structure of the NCO accumulator. When the synchronization
signal is repetitive (that is, ISTR and OSTR signals used in Dual Sync Sources mode), then the NCO
frequency must be some integer multiple of the synchronization frequency. As shown in Figure 33, if the
periodic synchronization signal does not allow the complete cycling of the NCO accumulator, the output of
the NCO will be distorted.
Synchronization Signal
restarts the accumulator
NCO Accumulator
Synchronization Signal
restarts the accumulator
NCO Accumulator
The NCO frequency is an integer multiple of
the synchronization signal. The NCO can cycle
through completely before the next reset.
The NCO frequency is not integer multiple of synchronization
signal. The NCO cannot cycle through completely before the
next reset. Output waveforms are distorted.
Figure 33. NCO Accumulator Operation with Repetitive Synchronization Signals
The requirements for the NCO accumulator synchronization signals:
Single Pulse Signal
There is no requirement for the NCO frequency to be an evenly-divisible quotient of FDAC if a single pulse
OSTR signal is used to reset the FIFO and NCO during initialization.
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Periodic Signal
The periodic synchronization signals are used in Dual Sync Sources mode where the ISTR (or SYNC) and
OSTR are used to synchronized the FIFO write and read pointers. In this case, the synchronization signal
frequency must meet both the FIFO block requirement and the NCO accumulator requirement.
• FIFO: Refer to the DAC348x family device datasheet for FIFO synchronization requirements.
• NCO accumulator: The synchronization signal frequency must be an integer-divisible quotient of the
NCO frequency. This allows the NCO counter to complete the cycle at least once without interruption.
• To meet both requirements, the synchronization signal frequency must be the least common multiple
(LCM) of both the FIFO block requirement and NCO accumulator requirement.
• The example below shows the DAC34H84 NCO using the OSTR signal when the DAC34H84 is in
Dual Sync Sources mode.
fDAC
given n is an integer
n × interpolation × 8
f
f
fOSTR _ NCO _ SYNC = NCO = f DAC× m given m is an integer
f DAC
m
fNCO
fOSTR _ FIFO
=
fOSTR _ FIFO _ NCO _ SYNC
fOSTR _ FIFO _ NCO _ SYNC
ffDAC
m × fDAC
given
is an integer to find LCM.
×
m
f
fNCO
f
DAC
LCM (n × interpolation × 8, ,
)
fNCO
fNCO
fDAC
=
=
fDAC × m m × n × interpolation × 8
n × interpolation × 8 ×
fNCO
=
(1)
3.5
DAC348x Digital Logic Synchronization Summary
Table 7 summarizes the synchronization source options for each of the DAC348x device logics.
Table 7. DAC348x Device Logics Synchronization Sources
Circuits
Sync Sources
30
FIFO
Data
Formatter
Clock Divider
NCO
Accumulator
NCO Double
Buffered
QMC
Gain/Phase
QMC Offset
ISTR/FRAME
ISTR/FRAME
ISTR/FRAME
SIF_SYNC
SIF_SYNC
SIF_SYNC
SIF_SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SIF_SYNC
SIF SYNC
OSTR
OSTR
OSTR
OSTR
OSTR
OSTR
ISTR
Auto-sync
from register
write
Auto-sync
from register
write
Auto-sync
from register
write
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Start-Up Sequence
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4
Start-Up Sequence
The section goes over the recommended start-up sequence for the DAC348x family. The important steps
are to synchronize the FIFO, clock divider, and the data formatter (if needed) as the first step. The
programmable logics such as QMC and NCO can be synchronized afterwards as the DAC is running.
Designers must be careful to avoid accidental synchronizations to unintended logics in order to prevent
unexpected output behavior. An example start-up sequence is listed at the end of this application note.
1. Ensure the TXENABLE or TXENA pin are low. This disables any potential data transmission to the
output.
2. Supply voltages to DACVDD, DIGVDD, CLKVDD, VFUSE, AVDD, IOVDD, and PLLAVDD. These
supplies can be powered up simultaneously or in any order. There are no specific requirements on the
ramp rate for the supplies.
3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be
provided after the SIF register programming.
4. Toggle the RESETB pin for a minimum 25-ns active-low pulse width.
5. Program the SIF registers.
6. FIFO configuration needed for synchronization:
(a) Program syncsel_fifoin(3:0) (config32, bit <15:12>) to select the FIFO input pointer sync source.
(b) Program syncsel_fifoout(3:0) (config32, bit <11:8>) to select the FIFO output pointer sync source.
(c) Program syncsel_data formatter(1:0) (config31, bit <3:2>) to select the FIFO Data Formatter sync
source.
7. Clock divider configuration needed for synchronization:
(a) Program clkdiv_sync_sel (config32, bit <0>) to select the clock divider sync source.
(b) Program clkdiv_sync_ena (config0, bit<2>) to “1” to enable clock divider sync.
8. Provide all LVDS inputs (DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N and
PARITYP/N) simultaneously. Synchronize the FIFO and clock divider by providing the pulse or periodic
signals needed. For example, provide a pulse on the ISTRP/N LVDS pair and the pulse on the
OSTRP/N LVPECL pair in Dual Sync Source Mode.
9. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses
needed for synchronization:
(a) The clock divider operates in the DACCLK domain and provides the divided-down clocks for the
digital circuits inside the DAC. Therefore, for Single Sync Source Mode where the clock divider
sync source is either ISTRP/N or SYNCP/N, clock divider syncing must be disabled after DAC348x
initialization and before the data transmission by setting clkdiv_sync_ena (config0, bit 2) to “0”.
Enabling the clock divider syncing at all time for Single Sync Source Mode is not recommended
due to the possible phase ambiguity between the DATACLK and DACCLK clock domains
(b) For Dual Sync Source Mode, where the clock divider sync source is from the OSTR signal (either
from external OSTRP/N or internal PLL N divider output), the clock divider syncing may be enabled
at all time.
(c) Optionally, disable FIFO syncing by setting syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to “0000”
after the FIFO input and output pointers are initialized.
10. Enable transmit of data by asserting the TXENABLE/TXENA pin or set sif_txenable to “1”.
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Example Start-Up Routine (Based on DAC345H84 Configuration)
Device Configuration:
fDATA = 737.28 MSPS
Interpolation = 2x
Input data = baseband data
fOUT = 122.88 MHz
PLL = Enabled
Full Mixer = Enabled
NCO = Enabled
Dual Sync Sources Mode
PLL Configuration:
fREFCLK = 737.28 MHz at the DACCLKP/N LVPECL pins
fDACCLK = fDATA × Interpolation = 1474.56 MHz
fVCO = 2 × fDACCLK = 2949.12 MHz (keep fVCO between 2.7 GHz to 3.3 GHz)
PFD = fOSTR = 46.08 MHz
N = 16, M = 32, P = 2, single charge pump
PLL_VCO(5:0) = “011100” (28)
NCO Configuration:
fNCO = 122.88 MHz
fNCO_CLK = 1474.56 MHz
freq = fNCO × 232 / 1228.8
= 357913941
= 0x15555555
phaseaddAB(31:0) and/or phaseaddCD(31:0) = 0x15555555
NCO synchronization method = rising edge of LVDS SYNC
Table 8. Example Start-Up Routine (Based on DAC34SH84 Configuration)
32
Step
Read/Write
Address
Value
Description
1
N/A
N/A
N/A
Set TXENA Low
2
N/A
N/A
N/A
Power Up the device
3
N/A
N/A
N/A
Apply LVPECL DACCLKP/N for PLL reference clock
4
N/A
N/A
N/A
Toggle RESETB pin
5
Write
0x00
0xF19F
QMC offset and correction enabled, 2x int, FIFO enabled, Alarm enabled, clock divider sync enabled, inverse sync
filter enabled.
6
Write
0x01
0x040E
Single parity enabled, FIFO alarms enabled (2 away, 1 away, and collision).
7
Write
0x02
0x7052
Output shut-off when DACCLK gone, DATACLK gone, and FIFO collision. Mixer block with NCO enabled, twos
complement.
8
Write
0x03
0xA000
Output current set to 20mAFS with internal reference and 1.28 kΩ RBIAS resistor.
9
Write
0x07
0xD8FF
Un-mask FIFO collision, DACCLK-gone, and DATACLK-gone alarms to the Alarm output.
10
Write
0x08
N/A
Program the desired channel A QMC offset value. (Causes Auto-Sync for QMC AB-Channels Offset Block)
11
Write
0x09
N/A
Program the desired FIFO offset value and channel B QMC offset value.
12
Write
0x0A
N/A
Program the desired channel C QMC offset value. (Causes Auto-Sync for QMC CD-Channels Offset Block)
13
Write
0x0B
N/A
Program the desired channel D QMC offset value.
14
Write
0x0C
N/A
Program the desired channel A QMC gain value.
15
Write
0x0D
N/A
Coarse mixer mode not used. Program the desired channel B QMC gain value.
16
Write
0x0E
N/A
Program the desired channel B QMC gain value.
17
Write
0x0F
N/A
Program the desired channel C QMC gain value.
18
Write
0x10
N/A
Program the desired channel AB QMC phase value. (Causes Auto-Sync QMC AB-Channels Correction Block)
19
Write
0x11
N/A
Program the desired channel CD QMC phase value. (Causes Auto-Sync for the QMC CD-Channels Correction
Block)
20
Write
0x12
N/A
Program the desired channel AB NCO phase offset value. (Causes Auto-Sync for Channel AB NCO Mixer)
21
Write
0x13
N/A
Program the desired channel CD NCO phase offset value. (Causes Auto-Sync for Channel CD NCO Mixer)
DAC348x Device Configuration and Synchronization
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Table 8. Example Start-Up Routine (Based on DAC34SH84 Configuration) (continued)
5
Step
Read/Write
Address
Value
Description
22
Write
0x14
0x5555
Program the desired channel AB NCO frequency value
23
Write
0x15
0x1555
Program the desired channel AB NCO frequency value
24
Write
0x16
0x5555
Program the desired channel CD NCO frequency value
25
Write
0x17
0x1555
Program the desired channel CD NCO frequency value
26
Write
0x18
0x2C50
PLL enabled, PLL N-dividers sync enabled, single charge pump, prescaler = 2.
27
Write
0x19
0x20F4
M = 32, N = 16, PLL VCO bias tune = “01”
28
Write
0x1A
0x7010
PLL VCO coarse tune = 28
29
Write
0x1B
0x0800
Internal reference
30
Write
0x1E
0x9999
QMC offset AB, QMC offset CD, QMC correction AB, and QMC correction CD can be synced by sif_sync or autosync from register write
31
Write
0x1F
0x4440
Mixer AB and CD values synced by SYNCP/N. NCO accumulator synced by SYNCP/N. FIFO data formatter synced
by ISTRP/N.
32
Write
0x20
0x2400
FIFO Input Pointer Sync Source = ISTR
FIFO Output Pointer Sync Source = OSTR (from PLL N-divider output)
Clock Divider Sync Source = OSTR
33
N/A
N/A
N/A
Provide all the LVDS DATA and DATACLK
Provide rising edge FRAMEP/N and rising edge SYNCP/N to sync the FIFO input pointer and PLL N-dividers.
34
Read
0x18
N/A
Read back pll_lfvolt(2:0). If the value is not optimal, adjust pll_vco(5:0) in 0x1A.
35
Write
0x05
0x0000
Clear all alarms in 0x05.
36
Read
0x05
N/A
Read back all alarms in 0x05. Check for PLL lock, FIFO collision, DACCLK-gone, DATACLK-gone, and so forth. Fix
the error appropriately. Repeat step 34 and 35 as necessary.
37
Write
0x1F
0x4442
Sync all the QMC blocks using sif_sync. These blocks can also be synced via auto-sync through appropriate register
writes.
38
Write
0x00
0xF19B
Disable clock divider sync.
39
Write
0x1F
0x4448
Disable FIFO data formatter sync. Set sif_sync to “0” for the next sif_sync event.
40
Write
0x20
0x0000
Disable FIFO input and output pointer sync.
41
Write
0x18
0x2450
Disable PLL N-dividers sync.
42
N/A
N/A
N/A
Set TXENA high. Enable data transmission.
References
1.
2.
3.
4.
5.
6.
7.
8.
9.
DAC3482 datasheet (SLAS748)
DAC3484 datasheet (SLAS749)
DAC34H84 datasheet (SLAS751)
DAC34SH84 datasheet (SLAS808)
DAC3282 datasheet (SLAS646)
DAC3283 datasheet (SLAS639)
DAC3174 datasheet (SLAS837)
LMK04800 datasheet (SNAS489)
CDCE62005 datasheet (SCAS862)
SLAA584 – April 2013
Submit Documentation Feedback
DAC348x Device Configuration and Synchronization
Copyright © 2013, Texas Instruments Incorporated
33
www.ti.com
Appendix A
Figure 34 and Figure 35 are simply repeats of Figure 10 and Figure 11, added to this appendix for the
purpose of a side-by-side comparison .
I0
Q0
I1
Q1
I2
Q2
I3
Q3
Time instance #0
write sequence #0
Rising_ISTR
DATACLK
WP RESET
WP0
WP1
W0
W1
W2
W3
W4
W5
W6
W7
S0
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
XX
XX
XX
XX
R4
R5
R6
R7
R0
R1
R2
R3
W8
W1
W2
W3
W4
W5
W6
W7
S8
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
S4
S5
S6
S7
R4
R5
R6
R7
R8
R9
R10
R11
Time instance #0
write sequence #0
read sequence #0
FIFO-Out Clock
RP RESET
RP4
RP5
Time instance #8
write sequence #8
Previous Events
Current Events
Upcoming Events
Time instance #8
write sequence #8
read sequence #8
Figure 34. DAC#1 FIFO Write/Read Sequence (Read Sequence Occurs On Time)
I0 Q0 I1 Q1 I2 Q2 I3 Q3
Time instance #0
write sequence #0
Time instance #1
write sequence #1
Rising_ISTR
DATACLK
WP RESET
WP0
WP1
W0
W1
W2
W3
W4
W5
W6
W7
S0
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
XX
XX
XX
XX
R4
R5
R6
R7
R0
R1
R2
R3
W8
W1
W2
W3
W4
W5
W6
W7
S8
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
S4
S5
S6
S7
R4
R5
R6
R7
R8
R9
R10
R11
Time instance #1
write sequence #1
read sequence #0
FIFO-Out Clock
RP RESET
RP4
RP5
Time instance #8
write sequence #8
Previous Events
Current Events
Upcoming Events
Time instance #8
write sequence #8
read sequence #7
Figure 35. DAC#2 FIFO Write/Read Sequence (Read Sequence Occurs Later by One Sample)
34
DAC348x Device Configuration and Synchronization
Copyright © 2013, Texas Instruments Incorporated
SLAA584 – April 2013
Submit Documentation Feedback
www.ti.com
Appendix B
Figure 36 and Figure 37 are repeats of Figure 10 and Figure 16, added to this appendix for the purpose of
a side-by-side comparison .
I0
Q0
I1
Q1
I2
Q2
I3
Time instance #0
write sequence #0
Q3
Rising_ISTR
DATACLK
WP RESET
WP0
WP1
W0
W1
W2
W3
W4
W5
W6
W7
S0
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
XX
XX
XX
XX
R4
R5
R6
R7
R0
R1
R2
R3
W8
W1
W2
W3
W4
W5
W6
W7
S8
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
S4
S5
S6
S7
R4
R5
R6
R7
R8
R9
R10
R11
Time instance #0
write sequence #0
read sequence #0
FIFO-Out Clock
RP RESET
RP4
RP5
Time instance #8
write sequence #8
Previous Events
Current Events
Upcoming Events
Time instance #8
write sequence #8
read sequence #8
Figure 36. DAC#1 FIFO Write/Read Sequence (Read Sequence Occurs On Time)
SIF_SYNC is asynchronous to both the DATACLK
and DACCLK. It is possible that the sync event occurs
before or after the first sample with respect to other
DAC devices.
Time instance #0
write sequence #0
I1
Q1
I2
Q2
I3
Q3
I4
Q4
SIF_SYNC
DATACLK
WP RESET
WP0
WP1
RP4
RP5
W0
W1
W2
W3
W4
W5
W6
W7
S1
S2
S3
S4
S5
S6
S7
S8
S1
S2
S3
S4
XX
XX
XX
XX
R4
R5
R6
R7
R0
R1
R2
R3
W8
W1
W2
W3
W4
W5
W6
W7
S9
S2
S3
S4
S5
S6
S7
S8
S1
S2
S3
S4
S5
S6
S7
S8
R4
R5
R6
R7
R8
R9
R10
R11
Time instance #0
write sequence #0
read sequence #0
FIFO-Out Clock
RP RESET
Time instance #8
write sequence #8
Previous Events
Current Events
Upcoming Events
Time instance #8
write sequence #8
read sequence #8
Figure 37. DAC#3 FIFO Write/Read Sequence (Read Sequence Occurs Ahead by One Sample)
SLAA584 – April 2013
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DAC348x Device Configuration and Synchronization
Copyright © 2013, Texas Instruments Incorporated
35
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