# Texas Instruments | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | Application notes | Texas Instruments Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) Application notes

```Application Report
SBAA173A – November 2009 – Revised November 2010
Determining Minimum Acquisition Times for SAR ADCs
When a Step Function is Applied to the Input
Miro Oljaca and Keith Sanborn ......................................................................... Data Acquisition Products
ABSTRACT
This application report analyzes a simple method for calculating minimum acquisition times for
successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the
ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined
for the case when a step function is applied to the input of the driving circuit. Three different test cases are
subsequently evaluated using both precise and approximated equations.
Contents
1
Introduction .................................................................................................................. 1
2
3
Mathematical Analysis of the Equivalent Circuit ........................................................................ 3
4
Minimum Acquisition Time ................................................................................................. 4
5
Test Cases ................................................................................................................... 5
6
Conclusion ................................................................................................................... 7
7
References ................................................................................................................... 7
Appendix A
........................................................................................................................ 8
Appendix B
....................................................................................................................... 10
Appendix C
....................................................................................................................... 12
List of Figures
1
1
Typical SAR ADC Input Driving Circuit................................................................................... 2
2
Simplified SAR ADC Input Driving Circuit
3
SAR ADC Input Driving Circuit Represented as a Second-Order, Low-Pass Filter ................................ 2
4
Second-Order Filter with Voltages and Currents Defined ............................................................. 3
5
Plots of Equations (8), (9), and (10) versus Time
6
Case (a) ...................................................................................................................... 6
7
Case (b) ...................................................................................................................... 6
8
Case (c) ...................................................................................................................... 6
...............................................................................
......................................................................
2
4
Introduction
When it comes to designing the proper input driving circuit for analog-to-digital converters (ADCs),
emphasis is generally placed on the calculation of the RC filter in front of the analog input and the
selection of an operational amplifier (see Reference 1). The selection of the external RC components
depends on the internal structure, sampling sequence, and charge injection of the successive
approximation register (SAR) ADC (see Reference 2 through Reference 4). Knowledge of the internal
ADC input structure, especially the value of the sampling capacitor, will assist users in optimizing the
external RC components in order to obtain the maximum specified device performance (see Reference 5).
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The calculation of the external RC filter is usually carried out with the assumption that the analog input
sampling switch resistance is negligible (see Reference 5). In the following analysis, the analog input
sampling switch resistance will be included.
2
A typical analog input driving circuit for the ADC includes an operational amplifier (op amp) as well as an
input RC filter composed of RIN and CIN as shown in Figure 1. The signal is then fed through the sampling
switch SW with an equivalent on-resistance RSW to the sampling capacitor CSH. The input switch is
composed of a CMOS transmission gate or similar structure. The equivalent on-resistance of the
transistors is not linear and depends on the input signal level (see Reference 6). For this analysis, the
average on-resistance of the switch measured in the linear region of operation will be used.
RIN
RSW
VIN(t)
SW
CESD
CIN
CSH
Figure 1. Typical SAR ADC Input Driving Circuit
Furthermore, the op amp is assumed to have ideal characteristics. As a result, it can be modeled as an
ideal voltage source. By modeling the op amp in this way, the circuit from Figure 1 can be simplified as
Figure 2 shows.
RIN
RSW
CESD
CIN
VIN(t)
SW
CSH
Figure 2. Simplified SAR ADC Input Driving Circuit
The ESD protection circuit at the input of the ADC has an equivalent capacitance CESD. This capacitance
is the parallel combination of the protection circuit from the input pin to the power-supply rail and ground.
The equivalent capacitance of CESD is in the range of 4 pF to 10 pF. On the other hand, the input filter
capacitance CIN is in the range of 1 nF to 10 nF. If CIN >> CESD, then CESD can be ignored.
Besides treating the op amp in Figure 1 as ideal, this analysis investigates the case of the input signal to
the converter changing state after the sampling switch SW has closed. This situation may occur if the
input signal suddenly changes during the acquisition period for a SAR ADC with a single input channel.
SAR ADCs with an integrated multiplexer may also experience this situation when changing input
channels. Under these conditions, the input signal can be represented as a unit step function with voltage
VIN. Furthermore, the circuit in Figure 2 can be represented as a second-order, low-pass filter. The circuit
for this case with updated variables is shown in Figure 3.
R1 = RIN
t=0
VIN(t) = VIN ´ u(t)
R2 = RSW
C1 = CIN + CESD
C2 = CSH
Figure 3. SAR ADC Input Driving Circuit Represented as a Second-Order, Low-Pass Filter
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Mathematical Analysis of the Equivalent Circuit
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The worst case occurs when the input signal switches from zero or negative full-scale (NFS) to the input
voltage VIN or positive full-scale (PFS). In order to analyze the circuit in Figure 3 under worst-case
conditions, the initial voltages on capacitors C1 and C2 are set to zero or NFS. Figure 4 shows the Laplace
transform of the circuit in Figure 3 with the initial conditions, reference currents, and voltages that are used
in the analysis.
R1
I(s)
VIN/s
R2
V1(s)
1/sC1
V2(s)
I2(s)
1/sC2
I1(s)
Figure 4. Second-Order Filter with Voltages and Currents Defined
The primary goal of this analysis is to determine the minimum acquisition time (tACQ) for the voltage on
capacitor C2 to settle within 1/2 LSB of the input signal for an N-bit SAR ADC as a function of R1, C1, R2,
and C2. In order for this analysis to be performed, an expression for the voltage V2 across capacitor C2 as
a function of time must be calculated. The next section in this application report focuses on this
calculation.
3
Mathematical Analysis of the Equivalent Circuit
The Laplace transform of voltage V2 in Figure 4 is:
space
V2(s) = A(s) ´ VIN
(1)
where:
1
1
A(s) = wn2 ´ ´ 2
s s + 2zwns + wn2
(2)
The calculations for Equation 1 and Equation 2 are shown in Appendix A. The inverse Laplace transform
of Equation 2 is:
A(t) = wn2 ´
1 - z2
-z
1
-zw t
-zw t
´ e n ´ sin(wn 1 - z2 t)
´ e n ´ cos(wn 1 - z2 t) + 2
+
wn2 wn2(z2 - 1)
wn 1 - z2
(3)
After simplifying and applying Euler's formula, Equation 3 can be re-written as follows (see Appendix B for
further details):
1
2
2
2
2
´ z + z - 1 ´ e-w (z - z - 1)t - z - z - 1 ´ e-w (z + z - 1)t
A(t) = 1 2
2 z -1
n
(
(
(
(
n
(4)
Equation 4, in turn, can be expressed as:
- t
- t
1
´ (z + z2 - 1) ´ e t1 - (z - z2 - 1) ´ e t2
A(t) = 1 2
2 z -1
(5)
where time constants t1 and t2 are defined as Equation 6 and Equation 7, respectively:
t1 =
1
wn(z - z2 - 1)
(6)
t2 =
1
wn(z + z2 - 1)
(7)
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Minimum Acquisition Time
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In order to observe the effects of these two time constants, Equation 5 can be rewritten as:
A(t) = 1 - [k1(t) - k2(t)]
(8)
where:
k1(t) =
z + z2 - 1
2 z2 - 1
- t
t1
´e
(9)
and
k2(t) =
z - z2 - 1
2 z2 - 1
- t
t2
´e
(10)
The plots of Equation 8, Equation 9, and Equation 10 as a function of time are shown in Figure 5.
The following values were used in Figure 5: R1 = 100 Ω, R2 = 800 Ω, C1 = 1000 pF, and C2 = 40 pF.
These component values set a = 100 ns, b = 4 ns, and c = 32 ns. These values, in turn, establish wn =
17.678 Mrad/s and z = 1.202. Furthermore, the time constants are calculated to be t1 = 105.721 ns and t2
= 30.267 ns.
1.50
A(t) = 1 - k1(t) + k2(t)
k1(t)
k2(t)
Amplitude (Normalized)
1.25
1.00
0.75
0.50
0.25
0
0
200
400
600
800
1000
1200
1400
Time (ns)
Figure 5. Plots of Equations (8), (9), and (10) versus Time
As shown in Figure 5, k2(t) is going to decay faster than k1(t) when t2 << t1. In fact, Equation 6 and
Equation 7 show that t1 will always be greater than t2 . Under these conditions, Equation 8 can be
approximated as a function with only time constant t1, or:
A(t) » 1 -
z + z2 - 1
2 z2 - 1
- t
t1
´e
(11)
4
Minimum Acquisition Time
In order for the voltage on capacitor C2 in Figure 3 to settle within 1/2 LSB of the input signal for an N-bit
1
A(t) ³ 1 - N+1
2
(12)
If k1(t) >> k2(t) at the minimum acquisition time, then A(t) in Equation 12 may be approximated by
Equation 11. When this approximation is done, the minimum acquisition time tACQ for an N-bit ADC is (see
Appendix C for calculations):
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Test Cases
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1
wn(z - z2 - 1)
´ N ´ ln(2) + ln
(
z + z2 - 1
z2 - 1
(
tACQ ³
(13)
5
Test Cases
In order to evaluate if the approximation derived in Equation 11 is valid, the following test cases were
analyzed for a 16-bit ADC (N = 16):
(a) R1C1 = R2C2 × 100
(b) R1C1 = R2C2
(c) R1C1 = R2C2 / 100
The results of these cases are displayed in Table 1.
Table 1. Results of Three Test Cases
Case
Parameter
(b)
(c)
Units
R1
100
100
10
Ω
C1
1000
1000
1000
pF
R2
20
2000
2000
Ω
C2
50
50
50
pF
1.59
1.59
159
MHz
MHz
f1 =
1
2pR1C1
f2 =
1
2pR2C2
159
1.59
1.59
f2/f1
100
1
0.01
(1)
a
100
100
1
ns
b (1)
5
5
0.5
ns
(1)
1
100
100
ns
c
(1)
100
10
100
z (1)
5.300
1.025
5.075
t1
105.048
125.000
100.505
ns
t2
0.952
80.000
0.995
ns
tACQ
1.239
1.601
1.185
ms
wn
(1)
(a)
Refer to Appendix A for equations.
By using the acquisition times from Table 1, the final voltage on the sampling capacitor of the ADC from
Figure 1 was calculated for each test case by using Equation 11 and Equation 8. The difference in the
final voltage calculated with Equation 11 and Equation 8 for each test case is negligible. This investigation
clearly shows that using the simplified Equation 11 to calculate the final voltage on the sampling capacitor
does not introduce any significant error compared to using the exact formula (Equation 8). This result is
further supported by the plots in Figure 6 through Figure 8.
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Test Cases
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1.50
Amplitude (Normalized)
1.25
1.00
0.75
0.50
A(t) = 1 - k1(t) + k2(t)
k1(t)
k2(t)
1 - k1(t)
0.25
0
0
200
400
600
800
1000
1200
1400
Time (ns)
Figure 6. Case (a)
1.50
Amplitude (Normalized)
1.25
1.00
0.75
A(t) = 1 - k1(t) + k2(t)
k1(t)
k2(t)
1 -1k1(t)
0.50
0.25
0
0
200
400
600
800
1000
1200
1400
Time (ns)
Figure 7. Case (b)
1.50
Amplitude (Normalized)
1.25
1.00
0.75
A(t) = 1 - k1(t) + k2(t)
k1(t)
k2(t)
1 -1k1(t)
0.50
0.25
0
0
200
400
600
800
1000
1200
1400
Time (ns)
Figure 8. Case (c)
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Conclusion
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6
Conclusion
This application report provides a simple analytical method for calculating minimum acquisition times for
SAR ADCs. The input structure of the ADC is analyzed together with the driving circuit. The voltage on the
sampling capacitor is then determined for the case when a step function occurs on the input of the driving
circuit. Three different test cases were calculated using exact equations as well as simplified ones. The
difference in the final acquired voltage calculated with these two equations was negligible.
7
References
The following documents are available for download through the indicated web sites.
1. Oljaca, M. and B. Baker. (2008). Start with the right op amp when driving SAR ADCs. EDN. October
16, 2008. Pp. 43-58.
2. Downs, R. and M. Oljaca. (2005). Designing SAR ADC drive circuitry, Part I: A detailed look at SAR
3. Downs, R. and M. Oljaca. (2005). Designing SAR ADC drive circuitry, Part II: Input behavior of SAR
4. Downs, R. and M. Oljaca. (2005). Designing SAR ADC drive circuitry, Part III: Designing the optimal
input drive circuit for SAR ADCs. Analog Zone.
5. Baker, B. and M. Oljaca. (2007). External components improve SAR-ADC accuracy. EDN. June 7,
2007. Pp. 67-75.
6. Oljaca, M. (2004). Understand the limits of your ADC input circuit before starting conversions. Analog
Zone.
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Appendix A
The voltage and currents in the circuit of Figure 4 can be described with the following equations:
I (s)
V1(s) = 1
sC1
(14)
V2(s) =
I2(s)
sC2
(15)
V1(s) - V2(s) = R2I2(s)
(16)
VIN
- V1(s) = R1I(s)
s
(17)
I(s) = I1(s) + I2(s)
(18)
Equation 14, Equation 15, and Equation 17 can be rewritten as:
I1(s) = sC1V1(s)
(19)
I2(s) = sC2V2(s)
(20)
I(s) =
VIN V1(s)
sR1
R1
(21)
Substituting Equation 19 through Equation 21 into Equation 18 yields:
VIN = (s2R1C1 + s)V1(s) + s2R1C2V2(s)
(22)
Using Equation 20 in Equation 16 produces:
V1(s) = (sR2C2 + 1)V2(s)
(23)
Substituting Equation 23 into Equation 22 produces:
VIN = (s2R1C1 + s)(sR2C2 + 1) + s2R1C2 ´ V2(s)
(24)
By using these constants:
a = R1C1
b = R1C2
c = R2C2
Equation 24 can be simplified to:
VIN = s (sa + 1)(sc + 1) + sb ´ V2(s)
(25)
The voltage V2(s) can be described as a function of the input step signal VIN by rearranging Equation 25 to
yield:
1
1´ 1´
´ VIN
V2(s) =
ac s
a+b+c 1
2
+
s +s
ac
ac
(26)
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Appendix A
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The coefficients in Equation 26 can be represented as:
a+b+c
= 2zwn
ac
(27)
and
1
= w n2
ac
(28)
Substituting Equation 27 and Equation 28 into Equation 26 produces:
V2(s) = A(s) ´ VIN
(29)
where:
A(s) = wn2 ´
1
1
´
s s2 + 2zwns + w 2
n
(30)
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Appendix B
The equation:
2
A(t) = wn2 ´
1-z
-z
1
-zw t
-zw t
´ e n ´ cos(wn 1 - z2 t) + 2
´ e n ´ sin(wn 1 - z2 t)
+
2
wn2 wn2(z2 - 1)
wn 1 - z
(31)
Can be reduced to:
A(t) = 1 - e
-zwnt
´ cos(wn 1 - z2 t) +
z
1 - z2
´ sin(wn 1 - z2 t)
(32)
The arguments of the cosine and sine terms in Equation 32 can be defined as:
x = wn 1 - z 2 t
(33)
Since:
1 - z2 = i z2 - 1
(34)
Equation 33 can be re-arranged to be:
x = iy
(35)
where:
y = wn z 2 - 1 t
(36)
Euler's formula can be used to represent the cosine and sine terms in Equation 32 as:
e-y + ey
cos(iy) =
2
(37)
and
sin(iy) =
e-y - ey
2i
(38)
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Appendix B
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Substituting Equation 35 and Equation 36 into Equation 37 and Equation 38 yields:
-wn z2 - 1t
e
cos(wn 1 - z2 t) =
+e
2
wn z2 - 1t
(39)
and
sin(wn 1 - z2 t) =
-wn z2 - 1t
e
-e
2i
wn z2 - 1t
(40)
Using Equation 39 and Equation 40 in Equation 32 produces:
A(t) = 1 - e
´
(
-wn z2 - 1t
e
+e
2
wn z2 - 1t
-wn z2 - 1t
e
z
+
1 - z2
-e
2i
´
wn z2 - 1t
(
-zwnt
(41)
Substituting Equation 34 for the square-root portion in the denominator of right-hand term in Equation 41
yields:
A(t) = 1 - e
(
-wn z2 - 1t
e
´
+e
2
wn z2 - 1t
+
-wn z2 - 1t
e
z
i z2 - 1
´
-e
2i
wn z2 - 1t
(
-zwnt
(42)
By re-arranging the terms, Equation 42 can be simplified to:
1
2
2
2
´ z + z - 1 ´ e-w (z - z - 1)t - z - z - 1 ´ e-w (z +
A(t) = 1 2
2 z -1
n
(
(
(
(
n
z2 - 1)t
(43)
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Appendix C
For k1(t) >> k2(t), Equation 5 reduces to:
A(t) » 1 -
z + z2 - 1
2 z2 - 1
- t
t1
´e
(44)
In order for Equation 44 to satisfy the criteria in Equation 12 for the minimum acquisition time tACQ:
1
2N + 1
z + z2 - 1
³
2 z2 - 1
-
tACQ
´ e t1
(45)
Re-arranging the terms in Equation 45 and solving for tACQ yields:
z + z2 - 1
z2 - 1
(
(
tACQ ³ t1 ´ N ´ ln(2) + ln
(46)
Using Equation 6 to replace t1 in Equation 46 produces the inequality:
1
2
wn(z - z - 1)
(
´ N ´ ln(2) + ln
z + z2 - 1
z2 - 1
(
tACQ ³
(47)
Revision History
Changes from Original (November, 2009) to A Revision ............................................................................................... Page
•
•
Corrected equations for test cases 1 and 3 ........................................................................................... 5
Corrected typos in Table 1; changed units for f1 and f2 to MHz from kHz ......................................................... 5
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
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