Texas Instruments | Q3 2007 Issue Analog Applications Journal | Application notes | Texas Instruments Q3 2007 Issue Analog Applications Journal Application notes

Texas Instruments Q3 2007 Issue Analog Applications Journal Application notes
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High-Performance Analog Products
Analog Applications
Journal
Third Quarter, 2007
© Copyright 2007 Texas Instruments
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Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Data Acquisition
Calibration in touch-screen systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
A touch-screen controller does not need any calibration by itself. However, a touch-screen system
requires a calibration routine after power up to align and scale the touch panel with the system’s LCD.
This article presents the theoretic concepts and methods for calibrating touch-screen systems.
Software-programming algorithms and their implementation are also discussed.
Power Management
Power-management solutions for telecom systems improve performance,
cost, and size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Factors driving power-management requirements in telecom systems are size, thermal management,
cost, and electrical performance. This article provides a basic understanding of the evolution of boardmounted power systems, and how the latest generation of plug-in power modules can achieve higher
performance and lower cost—in a smaller footprint.
TPS6108x: A boost converter with extreme versatility. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
The highly integrated TPS6108x boost converters have adjustable outputs of up to 27 V with input
voltages as low as 2.5 V and are available in the 3 × 3-mm QFN package. This article touches on
powering OLED and LCD displays, driving white LEDs as display backlights, and some of the protection
features built into the TPS6108x devices.
Get low-noise, low-ripple, high-PSRR power with the TPS717xx . . . . . . . . . . . . . . . . . 17
A linear regulator can be the best choice when the output ripple of a switching regulator is likely to
interfere with sensitive circuitry. This article highlights the TPS717xx devices that can achieve high
PSRR over a wide bandwidth with very low quiescent current. It also provides guidance on component
selection and layout techniques for maximizing PSR and minimizing the regulator’s self-generated
white noise.
Simultaneous power-down sequencing with the TPS74x01 family of
linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
While DSP and FPGA core and I/O power-rail start-up sequencing requirements are quite common,
power-down sequencing requirements are rare but not without precedent. This article describes two
different methods for implementing simultaneous power-down sequencing with the TPS74x01 family of
linear regulators.
Index of Articles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TI Worldwide Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
To view past issues of the
Analog Applications Journal, visit the Web site
www.ti.com/aaj
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Introduction
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Introduction
Analog Applications Journal is a collection of analog application articles
designed to give readers a basic understanding of TI products and to provide
simple but practical examples for typical applications. Written not only for
design engineers but also for engineering managers, technicians, system
designers and marketing and sales personnel, the book emphasizes general
application concepts over lengthy mathematical analyses.
These applications are not intended as “how-to” instructions for specific
circuits but as examples of how devices could be used to solve specific design
requirements. Readers will find tutorial information as well as practical
engineering solutions on components from the following categories:
• Data Acquisition
• Power Management
Where applicable, readers will also find software routines and program
structures. Finally, Analog Applications Journal includes helpful hints and
rules of thumb to guide readers in preparing for their design.
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Calibration in touch-screen systems
By Wendy Fang, Precision Analog Applications, High-Performance Analog,
and Tony Chang, Precision Analog Nyquist, High-Performance Analog
Introduction
Figure 1. Typical four-wire resistive touch-screen system
Today, more and more different fields are adopting
touch screens or touch panels for applications
LCD
with human/machinery or human/computer interAnalog Input
Circuitry
I2C or SPI Bus
faces. Figure 1 is a block diagram of a touch-screen
Resistive
TouchX+, X–, Y+, Y–
system where the touch screen sensor lies on top
Host
Touch
Screen
Processor
Interrupt
of the system’s display, in this case an LCD panel.
Screen
Controller
The touch-screen controller in Figure 1 does not
need any calibration by itself. However, products
or instrumentation equipped with a touch screen
Analog Interface
Digital Interface
normally require a calibration routine upon
power up because it is difficult to perfectly align
a touch screen’s coordinates with those of the
display underneath it. Calibration is necessary when the
electrostatic discharge and electromagnetic pulses caused
coordinates of the area touched on the screen are not sufby users and their environments. This article does not
ficiently close to the coordinates on the display. Without
address noise issues. For more information on handling
proper calibration, software may not respond correctly
noise, please see Reference 1.
when a soft button or icon is pressed.
Scaling factors and mechanical misalignments originate in
This article presents concepts and methods for the calithe parts and assembly of the touch screen and the display.
bration of touch-screen systems. Software-programming
Typically, the touch-screen controller and display in a
algorithms and their implementation are also discussed.
system do not have the same resolution, so scaling factors
are needed to match their coordinates to each other. For
Touch-coordinate errors
example, consider a touch-screen system that uses an LCD
When pressure is applied to the touch screen, the touchwith a resolution of 1024 (X coordinate) × 768 (Y coordiscreen controller senses it and takes a measurement of
nate) and the Texas Instruments TSC2005 touch-screen
the X and Y coordinates. Several sources of error can
controller with 12-bit (4096 × 4096) resolution. The scaling
affect the accuracy and reliability of this measurement.
factors to match them are kX = SX/S′X = 1024/4096 = 0.25
The majority of these errors can be attributed to electrical
for the X-axis coordinate and kY = SY/S′Y = 768/4096 = 0.1875
noise, scaling factors, and mechanical misalignments.
for the Y-axis coordinate, where SX is the LCD’s X-axis
Electrical noise comes from the display and backlight,
resolution, S′X is the touch-screen controller’s X-axis
the human interface, the panel surface’s vibration, and the
resolution, SY is the LCD’s Y-axis resolution, and S′Y is the
touch-screen controller’s Y-axis resolution. Thus, a touchscreen controller’s X coordinate, X′, should be understood
Figure 2. Scaling factors on the Y axes of LCD
by the LCD (the host) as X = kX × X′; and a touch-screen
and touch screen
controller’s Y coordinate, Y′, should be understood by the
LCD (the host) as Y = kY × Y′.
LCD Grid
In the preceding example, kX and kY are simple linear
Touch-Screen Grid
Shared Grid Lines
scaling factors based on the resolution specifications for
Touch Point P
the display and touch-screen controller. “Real-world”
(X, Y) = (2, 2)
scaling factors may vary from part to part and may need
(X', Y') = (2, 2.222)
to be calibrated to reduce or eliminate any mismatch. An
SY = 3.6
P
S'Y = 4
example is shown in Figure 2, where the X-axis scale is the
kY = SY /S'Y
same on the LCD and the touch screen, or kX = SX/S′X = 1;
kY = 0.9
but the Y-axis scale on the LCD is larger than that on the
touch screen, with the scaling factor of kY = SY /S′Y = 3.6/4
= 0.9. Thus, a point P (X′, Y′) = (2, 2.222) on the touch
SX = S'Y = 4
screen should be scaled to (X, Y) = (2, 2) for the LCD
kX = SX /S'X = 1
(the host).
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Mechanical misalignment between the display and the
touch screen includes moving and rotation errors, as
shown in Figure 3. Figure 3a shows the relative position
shifts of ΔX in the X direction and ΔY in the Y direction;
and Figure 3b shows the relative rotation, Δθ, between the
LCD and the touch screen.
Consider a point P, read as (X′, Y′) on the touch screen.
The display should read a moving error like that shown in
Figure 3a as (X′ + ΔX, Y′ + ΔY). For a rotation error like
that shown in Figure 3b, the point on the touch screen is
(R × cosθ, R × sinθ), or on the display is [R × cos(θ–Δθ),
R × sin(θ–Δθ)], where R is the distance from origin C, or
(0, 0), to the point P.
Mathematical expression
factor in Figure 2 and the moving and rotation errors in
Figure 3, the touch-screen coordinate X can be expressed as
X = k X × R × cos(θ − Δθ) + ΔX
= k X × R × cos θ × cos( Δθ) + k X × R × sin θ × sin( Δθ) + ΔX
= k X × X ′ × cos( Δθ) + k X × Y ′ × sin( Δθ) + ΔX
= α X × X ′ + β X × Y ′ + ΔX,
where X′ = R × cosθ, Y′ = R × sinθ, αX = kX × cos(Δθ), and
βX = kX × sin(Δθ). Similarly, the touch-screen coordinate Y
can be expressed as
Y = k Y × R × sin(θ − Δθ) + ΔY
= k Y × R × sin θ × cos( Δθ) − k Y × R × cos θ × sin( Δθ) + ΔY
= k Y × Y ′ × cos( Δθ) − k Y × X ′ × sin( Δθ) + ΔY
Calibration of the touch screen translates the coordinates
reported by the touch-screen controller into coordinates
that accurately represent the point and image location on
the display or LCD. The result of calibration is a set of
scaling factors that allow correction of the moving and
rotation errors that are due to mechanical misalignments.
Consider the point P, represented as (X, Y) on the display
and (X′, Y′) on the touch panel. Counting in the scaling
Figure 3. Mechanical misalignments
(1)
(2)
= α Y × X ′ + β Y × Y ′ + ΔY,
where αY = – kY × sin(Δθ), and βY = kY × cos(Δθ).
From Equations 1 and 2 it is obvious that, to get the
coefficients αX, αY, βX, βY, ΔX, and ΔY, at least three independent points are needed. The points are independent if
they are not on one linear line (see Figure 4). Assuming
that (X1, Y1), (X2, Y2 ), and (X3, Y3 ) are three independent
Figure 4. Independent (not on one linear line)
and dependent points
}
ΔX
LCD Grid
Touch-Screen Grid
Touch Point P
(X, Y) = (X' + ΔX, Y' + ΔY)
(X 2 ,Y2 )
(X 1, Y1)
P (X, Y)
(X', Y')
(X 3 ,Y3)
} ΔY
(a) Moving error
(a) Three independent points
LCD Grid
Touch-Screen Grid
Touch Point P
(X, Y) =
[R × cos(θ–Δθ), R × sin(θ–Δθ)]
(X', Y') = (R × cosθ, R × sinθ)
(X 3 ,Y3)
(X 2 ,Y2 )
P (X, Y)
(X', Y')
θ – Δθ
θ
(X 1, Y1)
Δθ
C
C
(b) Rotation error
(b) Three dependent points
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points selected on the LCD, and (X′1, Y′1), (X′2, Y′2 ), and
(X′3, Y′3 ) are the corresponding points on the touch screen,
Equations 1 and 2 can be used to write Equation 3:
Figure 5. Examples for selecting
calibration points
X1 = α X × X1′ + β X × Y1′ + ΔX
X 2 = α X × X ′2 + β X × Y2′ + ΔX
X 3 = α X × X 3′ + β X × Y3′ + ΔX
(X 2 ,Y2 )
(3)
(X 1, Y1)
Y1 = α Y × X1′ + β Y × Y1′ + ΔY
Y2 = α Y × X ′2 + β Y × Y2′ + ΔY
(X 3 ,Y3)
Y3 = α Y × X 3′ + β Y × Y3′ + ΔY
Equation 3 can be rewritten in matrix form:
⎛ Y1 ⎞
⎛ X1 ⎞
⎛ αY ⎞
⎛ αX ⎞
⎜ X ⎟ = A × ⎜ β ⎟ and ⎜ Y ⎟ = A × ⎜ β ⎟ ,
⎜ 2⎟
⎜ 2⎟
⎜ Y⎟
⎜ X⎟
⎜⎝ ΔY ⎟⎠
⎜⎝ ΔX ⎟⎠
⎜⎝ Y ⎟⎠
⎜⎝ X ⎟⎠
3
3
(a) Three points
(4)
where
⎛ X1′
A = ⎜ X ′2
⎜
⎜⎝ X ′
3
Y1′ 1⎞
Y2′ 1⎟ .
⎟
Y3′ 1⎟⎠
(X 2 ,Y2 )
(X 1, Y1)
Calibration methods
(X5 ,Y5)
The three independent calibration points shown in
Equation 4 should be sufficient to get the scaling factors
required to correct the mechanical misalignment between
the touch screen and the system display.
To resolve Equation 4, both sides can be multiplied by
the inverse of matrix A to get
⎛ X1 ⎞
⎛ Y1 ⎞
⎛ αY ⎞
⎛ αX ⎞
⎜ β ⎟ = A −1 × ⎜ X ⎟ and ⎜ β ⎟ = A −1 × ⎜ Y ⎟ ,
⎜ 2⎟
⎜ 2⎟
⎜ Y⎟
⎜ X⎟
⎜⎝ ΔY ⎟⎠
⎜⎝ ΔX ⎟⎠
⎜⎝ X ⎟⎠
⎜⎝ Y ⎟⎠
3
3
(5)
where
is the inverse of matrix A. The three points—
(X1, Y1), (X2, Y2), and (X3, Y3)—are designed/selected on
the display surface; and the elements in matrix A are
measured from the touch screen during calibration.
Example 1: Three-point calibration
On a display with 256 × 768 resolution, three calibration
points are chosen: (64, 384), (192, 192), and (192, 576).
Refer to Figure 5a. During calibration, the three points
(678, 2169), (2807, 1327), and (2629, 3367) are measured
from a touch panel with 12-bit or 4096 × 4096 resolution.
Equation 4 can then be populated with these known values.
⎛ Y1 ⎞ ⎛ 384⎞
⎜ Y ⎟ = ⎜ 192⎟
⎜ 2⎟ ⎜
⎟
⎜⎝ Y ⎟⎠ ⎜⎝ 576⎟⎠
3
(X4 ,Y4 )
(b) Five points
Applying Equation 5 results in αX = 0.0623, βX = 0.0054,
ΔX = 9.9951, αY = –0.0163, βY = 0.1868, and ΔY = –10.1458.
Thus the equation for X, from Equation 1, is
X = 0.0623 × X′ + 0.0054 × Y′ + 9.9951;
A–1
⎛ X1 ⎞ ⎛ 64 ⎞
⎜ X ⎟ = ⎜ 192⎟
⎜ 2⎟ ⎜
⎟
⎜⎝ X ⎟⎠ ⎜⎝ 192⎟⎠
3
(X 3 ,Y3)
and the equation for Y, from Equation 2, is
Y = –0.0163 × X′ + 0.1868 × Y′ – 10.1458.
In many applications, users may use more than three
points in their calibration routines to average or filter the
noisy readings from the touch-screen controller. For calibration with n > 3,
⎛ X1 ⎞
⎛ Y1 ⎞
⎛ αX ⎞
⎛ αY ⎞
⎜X ⎟
⎜Y ⎟
2
2
⎜
⎟
⎜ ⎟ = A× β
and ⎜ ⎟ = A × ⎜ β Y ⎟ ,
⎜ X⎟
⎜ ⎟
⎜ M ⎟
⎜ M ⎟
⎜⎝ ΔX ⎟⎠
⎜⎝ ΔY ⎟⎠
⎜ ⎟
⎜ ⎟
⎝ Xn ⎠
⎝ Yn ⎠
(6)
where A is an n × 3 matrix with n > 3 and rank (A) = 3, or
⎛ X1′
⎜ X′
A=⎜ 2
⎜ M
⎜
⎝ Xn′
⎛ 678 2169 1⎞
A = ⎜ 2807 1327 1⎟
⎜
⎟
⎝ 2629 3367 1⎠
Y1′ 1⎞
Y2′ 1⎟
⎟.
M M⎟
Yn′ 1⎟⎠
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To resolve Equation 6, both sides can be multiplied by A’s
pseudo-inverse matrix, (AT × A)–1 × AT, where AT is A’s
transpose matrix. That is, the unknown variables αX, βX,
ΔX, αY, βY, and ΔY are resolved from
⎛ αX ⎞
⎜ β ⎟ = AT × A
⎜ X⎟
⎜⎝ ΔX ⎟⎠
(
)
−1
measured from the touch panel: (1698, 2258), (767, 1149),
(2807, 1327), (2629, 3367), and (588, 3189).
⎛ X1 ⎞ ⎛ 128⎞
⎜X ⎟ ⎜
⎟
⎜ 2 ⎟ ⎜ 64 ⎟
⎜ X 3 ⎟ = ⎜ 192⎟
⎜ ⎟ ⎜
⎟
⎜ X 4 ⎟ ⎜ 192⎟
⎜ ⎟ ⎜⎝ 64 ⎟⎠
⎝ X5 ⎠
⎛ X1 ⎞
× A × ⎜⎜ X 2 ⎟⎟ and
⎜⎝ X ⎟⎠
3
T
⎛ Y1 ⎞ ⎛ 384⎞
⎜Y ⎟ ⎜
⎟
⎜ 2 ⎟ ⎜ 192⎟
⎜ Y3 ⎟ = ⎜ 192⎟
⎜ ⎟ ⎜
⎟
⎜ Y4 ⎟ ⎜ 576⎟
⎜ ⎟ ⎜⎝ 576⎟⎠
⎝ Y5 ⎠
(7)
⎛ αY ⎞
⎜ β ⎟ = AT × A
⎜ Y⎟
⎜⎝ ΔY ⎟⎠
(
)
−1
⎛ 1698
⎜ 767
⎜
A = ⎜ 2807
⎜
⎜ 2629
⎜⎝ 588
⎛ Y1 ⎞
× A × ⎜⎜ Y2 ⎟⎟ .
⎜⎝ Y ⎟⎠
3
T
The solution of Equation 7 is the least-square-error
estimation2 of these unknown variables.
The same system as in Example 1 is used, but five calibration points on the display are chosen: (128, 384), (64, 192),
(192, 192), (192, 576), and (64, 576). Refer to Figure 5b.
Equation 6 can then be populated with the five points
To perform these calibration methods in an
embedded system, the linear algebra equation
set, Equation 4 or Equation 6, must be resolved.
The solution can be derived simply from Cramer’s
rule: For the linear equation set b = A × x, b is
a known real vector equal to (b1, b2, . . . , bn)T;
A is a known real, square, full-rank matrix; and
x is an unknown real vector equal to
(x1, x2, . . . , xn)T. The unknown elements in x
can be calculated by x1 = Δ1/Δ, x2 = Δ2/Δ, . . . ,
xn = Δn/Δ, where Δ is the determinant of matrix
A, det(A); Δk = det(Ak) for k = 1, 2, . . . , n; and
the matrix Ak is the matrix A but with its kth
column replaced by the vector x.
Three-point calibration algorithm
Assuming that the dimension of A is 3 × 3,
Equation 8 can be determined from Equation 4,
based on Cramer’s rule:
α x = Δ x1 Δ , β x = Δ x 2 Δ , ΔX = Δ x 3 Δ ,
α y = Δ y1 Δ , β y = Δ y 2 Δ , and ΔY = Δ y 3 Δ .
(8)
Variables in Equation 8 are defined in the sidebar
on page 9.
n-point calibration algorithm
As in Equation 6, it can be assumed that the
dimension of A is n × 3 with n > 3. To get the
least-square solutions of the linear equation
set, Equation 7 must first be rewritten as
1⎞
1⎟
⎟
1⎟
⎟
1⎟
1⎠⎟
Using Equation 7 provides a solution similar to that
found in Example 1:
Example 2: Five-point calibration
Calibration algorithms
2258
1149
1327
3367
3189
X = 0.0623 × X′ + 0.0054 × Y′ + 10.0043, and
Y = –0.0163 × X′ + 0.1868 × Y′ – 10.1482.
⎛ X1 ⎞
⎛ Y1 ⎞
⎛ αY ⎞
⎛ αX ⎞
⎜ β ⎟ = A −1 × ⎜ X ⎟ and ⎜ β ⎟ = A −1 × ⎜ Y ⎟ ,
⎜ 2⎟
⎜ 2⎟
⎜ Y⎟
⎜ X⎟
⎜⎝ ΔY ⎟⎠
⎜⎝ ΔX ⎟⎠
⎜⎝ X ⎟⎠
⎜⎝ Y ⎟⎠
3
3
(9)
where A = AT × A, (X1, X2, X3)T = AT × (X1, X2, X3)T, and (Y1, Y2, Y3)T
= AT × (Y1, Y2, Y3)T. Then, based on Cramer’s rule, Equation 10 can be
determined:
α x = Δ x1 Δ , β x = Δ x 2 Δ , ΔX = Δ x 3 Δ ,
(10)
α y = Δ y1 Δ , β y = Δ y 2 Δ , and ΔY = Δ y 3 Δ ,
where
Δ = n × (a × b − c 2 ) + 2 × c × d × e − a × e2 − b × d 2 ,
Δ x1 = n × ( X1 × b − X 2 × c ) + e × ( X 2 × d − X1 × e) + X 3 × (c × e − b × d ) ,
Δ x 2 = n × ( X 2 × a − X1 × c ) + d × ( X1 × e − X 2 × d ) + X 3 × (c × d − a × e) ,
Δ x 3 = X 3 × (a × b − c 2 ) + X1 × (c × e − b × d ) + X 2 × (c × d − a × e) ,
Δ y1 = n × ( Y1 × b − Y2 × c ) + e × ( Y2 × d − Y1 × e) + Y3 × (c × e − b × d ) ,
Δ y 2 = n × ( Y2 × a − Y1 × c ) + d × ( Y1 × e − Y2 × d ) + Y3 × (c × d − a × e) , and
(
)
Δ y 3 = Y3 × a × b − c 2 + Y1 × (c × e − b × d ) + Y2 × (c × d − a × e) ; and
n
n
n
n
n
k =1
k =1
k =1
k =1
k =1
a = ∑ X ′k2, b = ∑ Yk′ 2, c = ∑ X ′k × Yk′ , d = ∑ X ′k , e = ∑ Yk′ ,
n
n
n
k =1
k =1
k =1
X1 = ∑ X ′k × X k , X 2 = ∑ Yk′ × X k , X 3 = ∑ X k ,
n
n
n
k =1
k =1
k =1
Y1 = ∑ X ′k × Yk , Y2 = ∑ Yk′ × Yk , and Y3 = ∑ Yk .
8
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Data Acquisition
Texas Instruments Incorporated
Definitions for Equation 8
X1′
Δ = det( A ) = X ′2
X 3′
Y1′ 1
Y2′ 1 = ( X1′ − X 3′ ) × ( Y2′ − Y3′ ) − ( X ′2 − X 3′ ) × ( Y1′ − Y3′ )
Y3′ 1
X1
Δ x1 = det ( A x1 ) = X 2
X3
Y1′ 1
Y2′ 1 = ( X1 − X 3 ) × ( Y2′ − Y3′ ) − ( X 2 − X 3 ) × ( Y1′ − Y3′ )
Y3′ 1
X1′
Δ x 2 = det ( A x 2 ) = X ′2
X 3′
X1 1
X 2 1 = ( X1′ − X 3′ ) × ( X 2 − X 3 ) − ( X ′2 − X ′3 ) × ( X1 − X 3 )
X3 1
Δ x3
X1′
= det ( A x 3 ) = X ′2
X ′3
( )
Δ y1 = det A y1
Y1
= Y2
Y3
X1′
Δ y 2 = det A y 2 = X ′2
X ′3
( )
( )
Δ y 3 = det A y 3
X1′
= X ′2
X 3′
Y1′
Y2′
Y3′
X1
X 2 = X1 × ( X ′2Y3′ − X 3′ Y2′ ) − X 2 × ( X1′ Y3′ − X 3′ Y1′ ) + X 3 × ( X1′ Y2′ − X ′2Y1′ )
X3
Y1′ 1
Y2′ 1 = ( Y1 − Y3 ) × ( Y2′ − Y3′ ) − ( Y2 − Y3 ) × ( Y1′ − Y3′ )
Y3′ 1
Y1 1
Y2 1 = ( X1′ − X 3′ ) × ( Y2 − Y3 ) − ( X ′2 − X 3′ ) × ( Y1 − Y3 )
Y3 1
Y1′
Y2′
Y3′
Y1
Y2 = Y1 × ( X ′2Y3′ − X 3′ Y2′ ) − Y2 × ( X1′ Y3′ − X ′3 Y1′ ) + Y3 × ( X1′ Y2′ − X ′2Y1′ )
Y3
Algorithm implementation
References
To implement the preceding calibration algorithms, one of
the first tasks after system power up is to develop and run
a software routine to perform the following steps:
• Select the display calibration points (Xk, Yk) for
k = 1, 2, . . . , n and n ≥ 3.
• Call the touch-screen controller function to access
touch-screen data.
• Touch the first point (X1, Y1) on the display, acquire
data from the touch-screen controller, and save the
touch coordinates (X′1, Y′1).
• Repeat the previous step to get all (X′k, Y′k) for
k = 2, 3, . . . , n and n ≥ 3.
• Call the function to calculate αx, βx, ΔX, αy, βy, and ΔY—
for example, call Equation 10 for five-point calibration.
For more information related to this article, you can download an Acrobat Reader file at www-s.ti.com/sc/techlit/
litnumber and replace “litnumber” with the TI Lit. # for
the materials listed below.
Document Title
TI Lit. #
1. Wendy Fang, “Reducing Analog Input Noise in
Touch Screen Systems,” Application Report
sbaa155
2. Frank L. Lewis, Optimal Estimation: With
an Introduction to Stochastic Control
Theory (John Wiley & Sons, Inc., 1986).
—
Related Web sites
dataconverter.ti.com
www.ti.com/sc/device/partnumber
Replace partnumber with ADS7843, ADS7845, ADS7846,
TSC2003, TSC2004, TSC2005, TSC2006, TSC2007, or
TSC2046
9
Analog Applications Journal
3Q 2007
www.ti.com/aaj
High-Performance Analog Products
Power Management
Texas Instruments Incorporated
Power-management solutions for telecom
systems improve performance, cost, and size
By Brian C. Narveson, Analog Applications Manager, Power Marketing Development – High Performance Analog Group,
and Adrian Harris, Application Specialist, Plug-In Power – High Performance Analog Group
Deregulation and competition in wire line and wireless
infrastructure telecommunications systems have accelerated the need for lower-cost equipment solutions with everincreasing bandwidth. The challenge of power-management
requirements for telecom equipment continues to grow.
Increasingly, designers are asked to provide more voltage
rails for a variety of digital signal processors (DSPs), field
programmable gate arrays (FPGAs), application-specific
integrated circuits (ASICs), and microprocessors. In short,
they are required to generate more voltages, at higher currents, more efficiently, with less noise, in a smaller space.
And, if that isn’t challenge enough, the solution has to cost
less, too!
Deploying access equipment closer to the subscriber
requires smaller enclosures (pad and pole mounting) that
must survive in a tougher environment. Infrastructure
equipment is being designed for smaller footprints, as
central office space comes at a premium. Factors driving
power management are size, thermal management, cost,
and electrical performance (regulation, transient response,
and noise generation). This article provides a basic understanding of the evolution of board-mounted power systems,
and how the latest generation can achieve higher performance and lower cost—in a smaller footprint.
Figure 1. Typical DPA architecture
48 V
Isolated
DC/DC
+3.3 V at 5 A
48 V
Isolated
DC/DC
+2.5 V at 6.5 A
48 V
Isolated
DC/DC
+1.8 V at 11 A
48 V
Isolated
DC/DC
+1.2 V at 20 A
Size/efficiency/cost
The need to address size, efficiency, and cost simultaneously has ignited renewed interest in power architectures.
The first generation of board-mounted power used a power
architecture known as a distributed power architecture
(DPA) (see Figure 1). This architecture used an isolated
(brick) power module for every voltage rail. It worked well
when there were limited rails, but cost and PCB space
increased significantly with each added voltage rail.
Sequencing of the voltage rails also was difficult and
required adding external circuitry, which in turn increased
cost and board space.
To deal with the size and cost constraints of DPA, secondgeneration systems moved to a fixed-voltage intermediate
bus architecture (IBA) (Figure 2). An IBA uses a single,
isolated-brick power module and many nonisolated, pointof-load (POL) DC/DC converters. The POLs can be either
power modules, such as the Texas Instruments (TI) PTH
series, or discrete buck converters. The isolated converter
works over the same input-voltage range as the first generation, either 36 to 75 V or 18 to 36 V. It creates an IBA
supply that is regulated to 3.3 V, 5 V, or 12 V. The voltage
choice is up to the system designer. This design results in
less board space, lower cost, and easier sequencing of the
Figure 2. Fixed-voltage IBA
48 V
Isolated
DC/DC
12 V
Auto-TrackTM
Point
of
Load
PTH
+3.3 V at 5 A
Point
of
Load
PTH
+2.5 V at 6.5 A
Point
of
Load
PTH
+1.8 V at 11 A
Point
of
Load
PTH
+1.2 V at 20 A
10
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Power Management
Texas Instruments Incorporated
voltages due to features such as TI’s Auto-Track™. The
only drawback of this architecture is reduced efficiency
due to the double conversion required for each voltage.
Today, most telecom systems use a fixed-voltage IBA.
However, a higher-efficiency and smaller-footprint solution
is needed as access-equipment designs evolve to sealed
enclosures with no forced air cooling. As every designer
knows, the best way to get rid of heat in a system is not to
create it. The main focus for improving efficiency is the
front-end isolated converter, since all of the power goes
through it. The proven way to increase isolated-converter
efficiency is to run the converter at a fixed duty cycle and
not regulate the output. This method led to the unregulated intermediate bus architecture (Figure 3).
This architecture uses an unregulated bus converter
that creates an output voltage as a ratio of the input voltage. In the example, an ALD17 5:1 converter creates an
output voltage that is 1/5 of the input. This technique allows
a 150-W system/board to be designed with a 1/16 brick,
achieving 96% efficiency for the first conversion stage.
Unregulated voltage became possible when wide-input
(4.5- to 14-V) PWMs and power modules such as TI’s T2
products were introduced. This architecture is limited by
the bus converters’ maximum input range of 36 to 55 V to
keep the input voltage to POLs less than 12 V. The 12-V
maximum is necessary because, for POLs to generate
output voltages of 1 V or less, the input voltage cannot
exceed 10 to 12 times the output. However, an increasing
number of telecom original equipment manufacturers
(OEMs) are considering a move to this limited input range
for the significant cost savings, size reduction, and efficiency improvements obtained with this architecture.
Some telecom OEMs insist on maintaining the traditional,
wider input-voltage specification of 36 to 75 V with input
transients of up to 100 V. For these requirements, the
power industry has responded with the quasiregulated
IBA (Figure 4). The main difference between this and the
unregulated IBA is that if the input voltage exceeds 55 to
60 V, the quasiregulated IBA regulates the output voltage
to around 10 V. The drawback of this approach is that the
isolated power module must increase in size to accommodate the regulation circuitry, and its efficiency is reduced
when the input voltage exceeds 55 V. An example of this
kind of product is the TI PTQB series.
Figure 3. Unregulated IBA
36 to
55 V
Isolated
ALD17
5:1
1/16
150 W
~9.6 V
Auto-TrackTM
SmartSync
Point
of
Load
T2
+3.3 V at 5 A
Point
of
Load
T2
+2.5 V at 6.5 A
Point
of
Load
T2
+1.8 V at 11 A
Point
of
Load
T2
+1.2 V at 20 A
Figure 4. Quasiregulated IBA
36 to
75 V
Isolated
PTQB
6:1
1/4
>200 W
Auto-TrackTM
SmartSync
~8 V
Point
of
Load
T2
+3.3 V at 5 A
Point
of
Load
T2
+2.5 V at 6.5 A
Point
of
Load
T2
+1.8 V at 11 A
Point
of
Load
T2
+1.2 V at 20 A
11
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3Q 2007
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High-Performance Analog Products
Power Management
Texas Instruments Incorporated
Architecture comparison
Figure 5. Comparison of architectures
The remaining challenge for the designer is to meet the
increasing electrical demands of the high-performance
DSPs and ASICs at the heart of each system. Primary
performance issues are voltage regulation, current transient
response, and noise.
Regulation and current transient response are closely
linked. To get higher performance with lower power in a
smaller size, digital semiconductors are fabricated with
smaller-geometry transistors that require ever-decreasing
voltages. Sub-1-V core-voltage requirements are now
becoming the standard. Along with this low voltage have
come increasingly tighter tolerances. It is now common
practice to specify a total voltage tolerance of 3% that
includes line (variations in input voltage), load (small
deviations in load current), time, temperature, and current
transients. This leaves the power designer with only 30 mV
of headroom to accommodate everything the digital system
requires. About half of the tolerance budget (15 mV) is
usually absorbed by the DC parameters of line, load, time,
and temperature. The remaining 15 mV is then available to
deal with sudden changes in current (1 to 3 clock cycles)
due to computational or data-transmission loads.
This tolerance budget challenges the power-system
designer to minimize voltage deviation in the presence of
these current transients. If the core voltage (VCC ) exceeds
the specified tolerance limits, the digital IC may initiate a
reset or have logic errors. To prevent this, designers need
to pay close attention to the transient performance of the
120
128
Cost ($)
100
80
80.3
75.30
60
69.3
40
20
0
DPA
FixedVoltage
Quasiregulated
Unregulated
Architecture
(a) Cost comparison
10000
PCB Space (mm2)
Electrical performance
140
8000
8288
6000
4000
4286
3578
2000
0
2542
DPA
FixedVoltage
Quasiregulated
Unregulated
Architecture
(a) Board size comparison
88.0
87.40
87.28
86.0
Efficiency (%)
To provide a meaningful comparison, each example in
Figures 2, 3, and 4 has identical output-voltage and current
requirements. The examples are based on a theoretical
base station utilizing multiple high-performance DSPs with
associated analog and digital circuits. The output voltages
are 3.3 V at 5 A, 2.5 V at 6.5 A, 1.8 V at 11 A, and 1.2 V at
20 A. For a comparison of the architectures described
earlier, see Figure 5. The graphs indicate that the ultimate
dream is indeed possible. A quasiregulated or unregulated
power system can provide higher efficiency in less space
at lower cost. The most notable improvement of the quasi/
unregulated IBA over the second-generation, fixed-voltage
IBA is efficiency. As shown in Figure 5, power-conversion
efficiency increased by almost 7%. This translates to a
thermal load reduction of 14 W for a 200-W system.
Power modules were used in these examples because
they provide the greatest power density and are the solution of choice at many telecom OEMs. Discrete POLs can
be used in all systems to reduce cost, but the board space
will increase by a factor of two.
84.0
82.0
80.74
80.0
78.0
DPA
FixedVoltage
Unregulated
Architecture
(a) System efficiency comparison
12
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Power Management
Texas Instruments Incorporated
POL modules being used. Digital loads such as the latest
gigahertz DSPs require extremely fast transient responses
with very low voltage deviation. To achieve these targets,
many additional output capacitors are usually added to
the DC/DC converter to provide hold-up time until its
feedback loop can respond. The power module, including
this added capacitance to meet transient-voltage tolerances, represents the complete power solution.
Capacitors have been evolving over the years, with volumetric efficiencies getting better all the time. Even with
higher volumetric efficiency, the overall power solution
can be over twice the size of the power module alone. This
requires a large allocation on the PCB that is usually not
available in today’s physically smaller systems. What’s
more, the cost of power-supply materials can be more
than double the cost of the power module when the cost
of capacitors is added in.
With innovations in DC/DC power-module technology,
system designers now are able to achieve faster transient
response and less voltage deviation while using less output
capacitance. An example is the T2 series next-generation
PTH modules (Figure 6) from TI. These devices incorporate a new patented technology called TurboTrans™ that
allows custom tuning of the module to meet a specific
transient-load requirement. Tuning is accomplished with a
single external resistor.
TurboTrans can achieve up to an eightfold reduction in
output capacitance, which lowers the cost of capacitors and
saves PCB space. Another benefit of this technology is that
using a capacitor with ultralow equivalent series resistance
(ESR) provides enhanced module-circuit stability. These
newer Oscon, polymer-tantalum, and ceramic output capacitors have the additional benefit of being able to withstand
high-temperature, lead-free soldering processes.
The final performance hurdle for isolated and POL
converters is noise. When switching POLs run at different
frequencies and share a common input bus, frequencies
resulting from the sum and difference of those frequencies
can create beat frequencies that make EMI filtering difficult.
Figure 6. T2 series power modules
with TurboTrans™
As an example, if a system has two POLs with one operating
at 300 kHz and a second at 301 kHz, the beat frequency is
1 kHz. This can require larger, more complex system filters.
T2 power modules from TI have a SmartSync feature that
lets the designer synchronize the switching frequency of
multiple T2 modules to a specific frequency, which eliminates beat frequencies and makes EMI filtering easier.
SmartSync can be used to set the frequency so that switching noise is minimized in a particular frequency band (i.e.,
xDSL transmission frequencies). TurboTrans and SmartSync
are standard features on T2 power modules that add no
additional cost to the systems described earlier.
A telecom system built with state-of-the-art power
modules allows the system designer to reduce system size,
decrease dissipated power, meet the power demands of
high-performance digital circuits, and reduce the cost of
power compared to regulated-voltage IBA systems.
Related Web site
power.ti.com
13
Analog Applications Journal
3Q 2007
www.ti.com/aaj
High-Performance Analog Products
Power Management
Texas Instruments Incorporated
TPS6108x: A boost converter with
extreme versatility
By Jeff Falin
Senior Applications Engineer
The TPS61080 and TPS61081 are
highly integrated boost converters
that have adjustable outputs of up
to 27 V with input voltages as low
as 2.5 V. The difference between
the two versions is the currentlimit rating of the integrated power
switches (typically 0.5 A and 1.3 A,
respectively). The TPS6108x boost
converters have a traditional
current-mode-control scheme and
a constant pulse-width-modulation
(PWM) frequency for low-noise
operation. The switching frequency
can be configured to either 600 kHz
for light-load efficiency or 1.2 MHz
for smaller, external components.
With integrated feedback compensation, internal power switches,
and fast PWM switching, the
3 × 3-mm QFN package enables an
extremely small boost converter for
a wide variety of applications. An
example is a 12- or 24-V industrial
power rail from a 3.3- or 5-V bus.
Additional features include high
efficiency, an adjustable reference
voltage, and redundant protection
circuits—all of which make the
TPS6108x ideal for boosting the
3.6-V Li-ion battery voltage used in
most portable applications. The
converters also support the higher
voltages needed for powering thinfilm-transistor (TFT) LCDs, OLED
displays, WLED backlights, or
camera flashlights.
Figure 1. Typical application for a 12-V boosted output
L1: 4.7 µH
TPS61081
VIN
3.6 V
VIN
EN
C1
4.7 µF
L
SW
OUT
R1
442 kΩ
FSW
SS
CS
47 nF
GND
C2
82 pF
FB
PGND
R3
100 Ω
VOUT
12 V
260 mA
C3
4.7 µF
R2
50 kΩ
Figure 2. Efficiency with VIN = 3.6 V
90
80
Efficiency (%)
Introduction
70
60
50
40
30
0
50
Powering displays
Figure 1 shows the converter in a typical boost configuration that provides a regulated output voltage. When up to
20 V and 100 mA are required to drive each column of a
passive-matrix OLED (PMOLED), the 1.3-A switch rating
makes the TPS61081 the best choice. When less than 10 V
and only tens of milliamps per column for the active-matrix
OLED (AMOLED) are provided, the 0.5-A switch rating of
the TPS61080 may be more appropriate. In either case,
100
150
Output Current, IO (mA)
200
250
the low-RDS(on) internal switches and the choice of switching frequency provide optimal supply efficiency. Figure 2
shows efficiency data for a 12-V output when a Li-ion battery with a typical 3.6-V source voltage is used.
To support the gates of the TFT drivers for active-matrix
LCDs or OLED displays, the high-voltage rail must be
capable of fast transients. The TPS61080 has current-mode
control and optimized internal compensation; and it can
operate at 1.2 MHz with a 4.7-µH inductor, making it ideal
14
High-Performance Analog Products
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Power Management
Texas Instruments Incorporated
for fast-transient response. Figure 3 shows the transient response of the TPS61080, which was configured as shown in Figure 1 except for an additional
4.7-µF output capacitor.
Figure 3. Transient response of TPS61080
WLED-display backlight driver
As shown in Figure 4, most boost converters can be
used to power WLEDs if the voltage-feedback network is replaced with the WLED strings and a series
current-sense resistor, R3. The TPS6108x can be
used to drive several series WLEDs in parallel for
backlighting larger displays.
The voltage across the current-sense resistor is fed
back to provide regulation. Traditional boost converters use 1.2-V feedback voltages; therefore, the power
loss due to R3 is PLOST = IWLED2 × R3 = 1.2 V × IWLED.
The TPS6108x converters have an SS pin that is used
to provide variable soft startup for boosted voltageregulation applications. The SS pin can also be used
to lower the FB-pin reference voltage and to reduce
sense-resistor power loss in a WLED current-regulation
application. Simply connecting a resistor, R1, from the SS
pin to GND will lower the FB-pin reference voltage. The
reference voltage equates to the resistance of R1 times the
SS-pin bias current (ISS = 5 µA typical), resulting in the
WLED current calculation:
I WLED =
12-VDC VOUT (100 mV/div)
IOUT (100 mA/div)
ISS × R1
R3
A second resistor, R2, in series with the FET and Q1 and
in parallel with R1 provides analog dimming by lowering
the regulated FB-pin voltage across the sense resistor.
Protection
Two of the most common boost-converter design challenges
are how to handle the conduction path from input to output and how to prevent overvoltage. The conduction path
creates three problems: leakage voltage under shutdown,
Time (50 µs/div)
inrush current during startup, and excessive short-circuit
current. To address these issues, the TPS6108x has an integrated isolation switch that opens during shut-down mode
to prevent a possible current path. This isolation switch and
the soft-start circuitry also control inrush current during
startup to prevent the input supply from drooping and
possibly causing system instability. The TPS6108x keeps
the isolation FET off until the EN pin is pulled high and VIN
rises above the undervoltage-lockout threshold. The Vgs of
the isolation FET is clamped so that its high on-resistance
limits the inrush current related to charging the output
capacitor to VIN. When the output capacitor reaches VIN , the
IC fully turns on the low RDS(on) isolation FET and activates
soft start as programmed by the soft-start capacitor on the
SS pin. In the event that VOUT stays below VIN for more
than 2 ms, indicating a short-circuit condition, the isolation
Figure 4. TPS61081 WLED backlight driver circuit
L1
4.7 µH
TPS61081
VIN
5V
R2
80 kΩ
VIN
C1
4.7 µF
R1
80 kΩ
L
10 Strings
10.5 V/200 mA
SW
EN
FSW
OUT
SS
GND
FB
PGND
PWM
Signal
C2
4.7 µF
R3
1Ω
15
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High-Performance Analog Products
Power Management
Texas Instruments Incorporated
FET turns off and the IC will not restart until the EN pin
toggles or VIN goes through power-on reset (POR).
The TPS6108x also has pulse-by-pulse overcurrent limiting, which turns off the power switch once the inductor
current reaches a preset value (0.7 A for the TPS61080 and
1.6 A for the TPS61081). The power switch turns back on
at the beginning of the next switch cycle. When the inductor current stays above the short-circuit current limit for
more than 13 µs or the VOUT -pin voltage goes 1.4 V below
VIN , the IC assumes that there is a short-circuit condition
and turns off the isolation FET. After 57 ms, the IC attempts
to restart. If a momentary short is cleared, the output
returns to its regulation voltage and switches normally. For
a permanent short, the isolation FET turns off again and
waits for POR or EN-pin toggling. Although the isolation
switch has a low RDS(on) for minimum power loss, shorting
the VIN and L pins can bypass the switch and further
enhance the efficiency.
When the TPS61081 is configured for regulated current
output as shown in Figure 4, the output voltage could run
away if the output impedance becomes too high (i.e., if a
WLED burns out or the load is disconnected). To prevent
the power switch from exceeding its maximum voltage
rating, the overvoltage-protection (OVP) circuit turns off
the power switch when the output voltage exceeds the OVP
threshold. When the output voltage falls below the OVP
threshold, the converter resumes normal PWM operation.
Conclusion
This extremely versatile, integrated-FET boost converter
is ideal for industrial, medical, telecom, and consumer
applications that require boosted voltages. Features such
as variable-reference voltage and multiple-protection
circuitry make the TPS6108x also well-suited for powering
LCDs and OLED displays.
Reference
For more information related to this article, you can download an Acrobat Reader file at www-s.ti.com/sc/techlit/
litnumber and replace “litnumber” with the TI Lit. # for
the materials listed below.
Document Title
TI Lit. #
1. “High Voltage DC/DC Boost Converter with
0.5-A/1.3-A Integrated Switch,” TPS61080/1
Datasheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .slvs644
Related Web sites
power.ti.com
www.ti.com/sc/device/TPS61080
www.ti.com/sc/device/TPS61081
16
High-Performance Analog Products
www.ti.com/aaj
3Q 2007
Analog Applications Journal
Power Management
Texas Instruments Incorporated
Get low-noise, low-ripple, high-PSRR
power with the TPS717xx
By Jeff Falin
Senior Applications Engineer
Introduction
While highly efficient switching power supplies are commonly used for long battery life in portable end equipment
such as mobile phones and PDAs, the internal circuitry of
some of these devices is sensitive to noise and therefore does
not operate properly when powered from a switching power
supply with output ripple. Audio circuitry, PLLs, RF transceivers, and DACs are just a few examples of such circuits.
Linear regulators are ideal for powering these circuits.
Figure 1 shows a simplified block diagram of a linear
regulator using a p-channel MOSFET (pFET) as a pass
element. AOL is the open-loop gain of the error amplifier,
and gm is the pass-element transconductance. The error
amplifier controls the voltage at the gate of the pass element
so that the current through the FET keeps the output
voltage regulated relative to the internal reference voltage.
Assuming that the low-pass filter (LPF) formed by RLPF
and CLPF eliminates nearly all internal-reference noise, the
output voltage should be ripple- and noise-free for frequencies within the bandwidth of the regulator’s control loop.
The concept is easy to understand, but achieving a high
power-supply rejection ratio (PSRR) over a wide bandwidth
with very low quiescent current and in a small package
requires innovative circuits. This article highlights the
TPS717xx single-output linear regulator, which provides
high power-supply rejection (PSR) over a wide bandwidth
with very low quiescent current and in a small package.
Similar, dual-output versions are available with the TPS718xx
and TPS719xx families. This article also provides guidance
on component selection and layout techniques for maximizing PSR and minimizing the regulator’s self-generated
white noise.
What is the PSRR?
The PSRR is a measure of a circuit’s PSR expressed as a
ratio of output noise to noise at the power-supply input. It
provides a measure of how well a circuit rejects ripple at
various frequencies injected from its input power supply.
In the case of linear regulators, PSRR is a measure of the
regulated output-voltage ripple compared to the inputvoltage ripple over a wide frequency range and is expressed
in decibels (dB). If the pass element in Figure 1 is treated
as a variable resistance, RDS, and the error amplifier and
bandgap reference are assumed to have been designed to
Figure 1. Simplified block diagram of a
linear regulator
CPAR1
Z CL
Z OL
RDS
Rds
R1
–gm
+
A OL
–
CPAR2
R ESR
R2
VIN +
–
Bandgap
Reference
Voltage
COUT
R LPF
Quickstart
CLPF
minimize pass-through of the input-voltage ripple, then
the PSR is simply a voltage divider, expressed as
ZOL || ZCL
PSR =
.
ZOL || ZCL + R DS
In this equation, ZOL is the output impedance at the
regulator’s output, ignoring the effect of the regulator’s
feedback loop:
ZOL = (ZCOUT + R ESR ) || ( R1 + R 2) || CPAR 2,
where ZCOUT and RESR are the output capacitor’s impedance
and equivalent series resistance (ESR), respectively, and
CPAR2 is the parasitic capacitance of the output components
and PCB. ZCL is the impedance looking back into the output of the regulator, including the effect of the regulator’s
feedback loop:
Z || R DS || CPAR1
ZCL = OL
,
g m × A OL × f × β
where CPAR1 is the passive-element parasitic capacitance,
f is the ripple frequency, and β is the feedback factor,
β=
R2
.
R1 + R 2
17
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PSRR (dB)
Figure 2 shows the general shape of a PSRR
Figure 2. PSRR graph
curve, where fP(dom) is the dominant pole and
fUG is the unity-gain bandwidth. If the error
amplifier is compensated to have a single-pole
s
⎡
⎤
1+
⎢
⎥
response, then the Region 1 PSR for amplifier
fP( dom )
ZOL
⎛
⎞
⎥
−20 log ⎜
frequencies below fUG can be approximated
−20 log ⎢
⎛1 + s ⎞ ⎥
⎢
⎝ ZOL + R DS ⎟⎠
by the equation on the left side of the graph.
⎢ g m A OL β ⎜
⎥
⎟
fUG ⎠
⎝
Designing the regulator with a high-gain,
⎢⎣
⎥⎦
wide-bandwidth error amplifier can therefore
Region 1
Region 2
provide high PSR over a wide range of frequencies. In Region 2, above the control-loop
Region 3
bandwidth, the regulator is no longer effective
at providing PSR, so the PSRR reduces to a
simple voltage divider as shown on the right
side of the curve. As ZCOUT decreases relative
to RDS, the PSR provided by the passive comIf RESR is large
ponents on the board increases. If COUT has
high RESR, the PSR peaks sooner. In Region 3,
the IC and board parasitic capacitances (CPAR1
fP(dom)
fUG
and CPAR2) dominate, resulting in a capacitive
Frequency,
f
(log
Hz)
voltage divider, which typically causes the
PSR to decrease again. A larger output capacitor with less ESR will typically improve PSRR
in this region, but it can also actually decrease
the PSRR at some frequencies. This occurs because
and 2 of Figure 2. Figure 3 shows the TPS717xx’s PSRR
increasing the output capacitor may lower fP(dom) and/or
varying with load current. As load current increases, RDS
fUG, depending on how the regulator is compensated,
decreases; therefore ZCL decreases, since a MOSFET’s
thereby causing the open-loop gain to roll off sooner.
output impedance is inversely proportional to its drain
current. In many regulators, where fP(dom) varies with ZCL,
Maximizing PSR
increasing the load current also pushes fP(dom) to higher
The TPS717xx family of regulators has incorporated both
frequencies, which increases the feedback-loop bandwell-known and patentable circuit techniques to provide
width. As shown in Figure 3, the net effect of increasing
high PSR over a wide frequency range. An example of the
the load current is reduced PSRR.
PSRR is shown in Figure 3.
The differential DC voltage between input and output
With the simple model previously explained, it can be
also affects PSR. As VIN – VOUT is lowered, the pFET
shown that the TPS717xx’s dominant pole with COUT = 1 µF
(which provides gain) is driven out of the active (saturais at approximately 20 to 30 kHz and the unity-gain fretion) region of operation and into the triode/linear region,
quency is near 400 kHz. Since PSR is a function of the openwhich causes the feedback loop to lose gain. Therefore,
loop gain, as the gain varies so will the PSR in Regions 1
the PSR of the regulator decreases as VIN approaches
VOUT . The lowest PSR, approaching 0 dB, occurs when the
device is in dropout (VIN ≈ VOUT ). In this situation, the RC
Figure 3. TPS717xx PSRR graph
filter formed by the linear regulator’s pass-element RDS
and output capacitor determines PSR.
Low noise
80
150 mA
70
10 mA
PSRR (dB)
60
50
40
75 mA
30
20
VIN – VOUT = 1 V
COUT = 1 µF
CNR = 10 nF
10
0
10
100
1k
10 k
100 k
Frequency (Hz)
1M
10 M
A linear regulator’s self-generated noise is sometimes
confused with its PSRR. However, noise is generated by
the transistors and resistors in the regulator’s internal
circuitry as well as by the external feedback resistors.
Transistors generate shot noise and flicker noise, both of
which are directly proportional to current flow. Flicker
noise is indirectly proportional to frequency and so is
higher at low frequencies. The resistive element of
MOSFETs also generates thermal noise like resistors.
Thermal noise is directly proportional to temperature, the
resistor’s resistance value, and the current flow through
the transistors. Transistors and resistors closest to the
error-amplifier inputs in the small-signal path cause the
18
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most output noise because their noise is amplified by the
regulator’s closed-loop gain (ACL = VOUT /VBandgap = 1/β =
1 + R1/R2). The noise contribution from components later
in the signal path is insignificant when compared to the
noise at the error-amplifier inputs. In fact, when modestsized feedback resistors are used, most of the regulator’s
noise comes from the amplified bandgap reference. As
shown in Figure 1, the simplest way to reduce the bandgap
noise is to use a low-pass filter (LPF) consisting of an
internal resistor, RLPF , and an external capacitor, CLPF .
At startup, this filter would slow down the output-voltage
rise without the aid of the “quickstart” transistor. When
the quickstart transistor is used, it shorts out the RLPF for
a short time at startup so the regulator output can rise
quickly. Larger noise capacitors such as CLPF in Figure 1
will reduce the output noise produced by the bandgap
until the regulator’s other noise sources begin to dominate.
Using a noise capacitor that is too large results in the
quickstart circuit timer expiring before the RLPF × CLPF
time constant. In this case, the output voltage will rise
quickly to a level below regulation and then rise very
slowly to its final regulated value.
A regulator’s noise output is characterized by two measurements. One is its spectral noise density, a curve that
—–
shows noise (µV/√Hz ) versus frequency. The other is the
RMS of the spectral noise density integrated over a finite
frequency range, also commonly called output-noise voltage (µVrms ). Figure 4 shows the TPS717xx’s spectral noise
density with different CNR values, where CNR is the same
as CLPF in Figure 1.
When noise specifications of different regulators are
compared, it is imperative that the two regulators’ noise
measurements be taken over the same frequency range
and at the same output voltage and current values. When
output noise values for regulators at two different output
voltages are compared, an approximate noise value can be
used that is computed by scaling one of the noise measurements by the ratio of the two output voltages. When a
Output Spectral Noise Density (µV/ Hz)
Figure 4. TPS717xx spectral noise density
30
IOUT = 10 mA
COUT = 1 µF
25
20
15
10 CNR =
10 nF
CNR =
5
100 nF
0
100
CNR = 0 nF
CNR = 1 nF
10 k
1k
Frequency (Hz)
100 k
noise-capacitor pin is not available, adding a capacitor
across R1 reduces the noise by reducing the closed-loop
gain at high frequencies. However, this could potentially
slow down start-up time, since the capacitor would have
to be charged by the current in the resistor divider; adding
such a capacitor could also potentially make the feedback
loop unstable.
Component selection and board layout
Proper board layout and capacitor selection are critical to
maximizing PSR and minimizing noise. Low-ESR output
capacitors maximize PSR at high frequencies but may
increase noise. The reason for this is that the low impedance created by the output capacitor and its ESR may
improve stability and PSR by removing peaking in the
control loop at frequencies near fP(dom), but removing this
peaking would also provide higher gain for the internal
noise sources. To maximize PSR and minimize noise, it is
recommended that VIN and VOUT have separate ground
planes that are connected at the regulator’s ground pin.
The input, output, and noise-reduction capacitors should
be very close to the IC, with the ground of the noisereduction capacitor as close to the regulator’s ground pin
as possible.
Conclusion
Linear regulators are ideal for providing a low-ripple,
low-noise power rail to sensitive analog circuitry. The
TPS717xx single-output and TPS718xx/TPS719xx dualoutput linear regulators are specifically designed for
providing high PSR over a wide frequency range with low
noise. These linear regulators also consume very little
quiescent current when powered and even less when shut
down, helping maximize battery life in portable powered
applications that need bursts of regulator power only at
irregular intervals.
References
For more information related to this article, you can download an Acrobat Reader file at www-s.ti.com/sc/techlit/
litnumber and replace “litnumber” with the TI Lit. # for
the materials listed below.
Document Title
TI Lit. #
1. Vishal Gupta, Gabriel A. Rincón-Mora, and
Prasun Raha, “Analysis and Design of
Monolithic, High PSR, Linear Regulators for
SoC Applications,” http://users.ece.gatech.edu/
rincon-mora/publicat/journals/socc04_psr.pdf
—
2. John C. Teel, “Understanding noise in
linear regulators” . . . . . . . . . . . . . . . . . . . . . . . . .slyt201
3. John C. Teel, “Understanding power supply
ripple rejection in linear regulators” . . . . . . . . . .slyt202
Related Web site
power.ti.com
19
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Simultaneous power-down sequencing with
the TPS74x01 family of linear regulators
By Jeff Falin
Senior Applications Engineer
Introduction
Figure 1. Block diagram of TPS74301 providing
power-up/down sequencing
In the past, ensuring successful power up
for DSPs and FPGAs in electronic equipment was a challenge. The most recent
5V
VIN
PH
3.3 V
DSPs and FPGAs have more relaxed
CO1
requirements for core and I/O power
TPS54610
EN
66 µF
up/down. However, a few still specify
VSENSE
SS/ENA
power-up ramp rates and recommend
GND
RL1
sequential sequencing for predictable and
332 W
repeatable startup. Even fewer specify
power-down requirements, including ramp
rates and/or sequences. In most cases, the
3.74 kW
ultimate goal of these requirements is to
VIN
PH
1.8 V
ensure that the DSP and FPGA power rails
TPS54680
do not have a larger differential voltage
66 µF
TRACKIN
than that for which they were designed,
VSENSE
GND
even during the brief periods at power
up/down. Otherwise, immediate or cumula9.76 kW
tive damage to internal circuits, which
reduces long-term reliability, can occur.
Therefore, the ideal method for DSP and
FPGA power up/down is for all rails to rise
10 kW
8.66 kW
and fall at the same time and rate.
Two or more power-rail ICs are said to
VIN TRACK
VOUT
1.5 V
1.0
have been simultaneously sequenced on
CO2
µF
TPS74301
4.12 kW
power up when they track one another with
330 µF
EN
the same rising dv/dt, and the lower rail
FB
4.7
VBIAS GND
RL2
stops at its regulated voltage while the
µF
4.75 kW
upper rail continues to its higher regulated
voltage. Various devices, including the
TPS74301 linear regulator, have a tracking
Pull-Down Circuitry RPD
input to provide simultaneous power-up
5
V
sequencing. Simultaneous sequencing on
10 kW
7.5 W
power up/down is implemented by replacQ2
100
kW
ing the converter’s error-amplifier reference
Q1
voltage with the tracking input signal while
the signal is less than the reference voltage.
However, for power-down sequencing to
work, the converter must have circuitry to
pull down the output under light load.
Switching converters such as the TPS54x80
capacitor to discharge through the load resistance. Figure 1
family can easily pull down the output by modulating the
shows a block diagram of the TPS74301 configured to
duty cycle. Most linear regulators do not have pull-down
track the 3.3-V rail from a TPS54610. See Reference 1
circuitry; so, even though the linear regulator tries to
for a complete schematic of TPS54xxx devices.
lower the output voltage, it must wait for the output
20
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Figure 2 shows simultaneous power up of the 3.3-V and
1.5-V rails. Figure 3 shows that, with the pull-down
circuitry (low-cost, bipolar transistors Q1 and Q2 and their
supporting components) removed, the TPS74301 output
voltage does not track down because the power-down load
resistance is too high. The pull-down circuitry shown in
Figure 2. TPS74301 1.5-V output with
power-up sequencing
Figure 1 adds the pull-down resistor, RPD, in parallel with
RL2, which lowers the regulator’s load resistance and its
RC time constant (RL2 × CO2) during power down. This
means that the TPS74301 output will track down as shown
in Figure 4, since the RPD || (RL2 × CO2) time constant is
less than the RL1 × CO1 time constant.
Figure 3. TPS74301 1.5-V output without
power-down sequencing
3.3 V (500 mV/div)
3.3 V (500 mV/div)
EN (1 V/div)
1.8 V (500 mV/div)
1.8 V (500 mV/div)
EN (1 V/div)
1.5 V (500 mV/div)
1.5 V (500 mV/div)
Timebase (1 ms/div)
Timebase (10 ms/div)
Figure 4. TPS74301 1.5-V output with
power-down sequencing
3.3 V (500 mV/div)
EN (1 V/div)
1.8 V (500 mV/div)
1.5 V (500 mV/div)
Timebase (5 ms/div)
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The circuit in Figure 5 shows how to
make all versions of the TPS74x01 family
achieve “pseudo” simultaneous powerup/down sequencing by having VOUT follow
VIN. When VIN is less than the sum of the
output voltage and the regulator’s dropout
voltage (VDO) for a given output load, the
regulator’s pass element is operating in
dropout. Therefore, if the load during
power up/down is heavy enough, the regulator’s output voltage could be below the
voltage being tracked by VDO(max). Note that
the soft-start capacitor, CSS, must be set so
that the TPS74x01 output ramps up faster
than VIN.
Figures 6 and 7 show power-up/down
sequencing using the nontracking TPS74801
and TPS74201, respectively, with a 1.5-A
output load and VOUT = 1.5 V. Since the
TPS74801 has a higher dropout than the
TPS74201, the difference between VOUT =
1.5 V and VIN = 1.8 V is more noticeable in
Figure 6 than in Figure 7. Figures 8 and 9
show the same results but with no load connected to the output and with VOUT = 1.5 V.
Notice in Figures 8b and 9b that on power
down the output voltage stays high for a
brief time (creating a ledge of sorts) until
the pass element’s reverse diode turns on to
assist in discharging the output capacitance.
Figure 5. Block diagram of TPS74x01 providing pseudo
power-up/down sequencing
5V
VIN
PH
3.3 V
CO1
TPS54610
SS/ENA
66 µF
FB
RL1
332 Ω
10 kΩ
VIN
PH
1.8 V
TPS54680
TRACKIN
66 µF
FB
GND
9.76 kΩ
1.0 µF
VIN
VOUT
TPS74x01
VBIAS
SS GND
CSS
4.7 µF
1.5 V
CO2
4.12 kΩ
330 µF
FB
RL2
4.75 kΩ
Figure 6. TPS74801 1.5-V output with RL2 = 1 Ω
3.3 V (500 mV/div)
3.3 V (500 mV/div)
EN (1 V/div)
EN (1 V/div)
1.8 V (500 mV/div)
1.8 V (500 mV/div)
1.5 V (500 mV/div)
1.5 V
(500 mV/div)
Timebase (2 ms/div)
Timebase (500 µs/div)
(a) Pseudo power-up sequencing with VIN connected to
1.8-V output
(b) Pseudo power-down sequencing with VIN connected to
1.8-V output
22
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Figure 7. TPS74201 1.5-V output with RL2 = 1 Ω
3.3 V (500 mV/div)
3.3 V (500 mV/div)
EN (1 V/div)
1.8 V (500 mV/div)
EN (1 V/div)
1.8 V (500 mV/div)
1.5 V
(500 mV/div)
1.5 V (500 mV/div)
Timebase (2 ms/div)
Timebase (1 ms/div)
(a) Pseudo power-up sequencing with VIN connected to
1.8-V output
(b) Pseudo power-down sequencing with VIN connected to
1.8-V output
Figure 8. TPS74801 1.5-V output with no load
3.3 V (500 mV/div)
3.3 V (500 mV/div)
EN (1 V/div)
EN (1 V/div)
1.8 V (500 mV/div)
1.8 V (500 mV/div)
1.5 V (500 mV/div)
1.5 V
(500 mV/div)
Timebase (2 ms/div)
Timebase (500 µs/div)
(a) Pseudo power-up sequencing with VIN connected to
1.8-V output
(b) Pseudo power-down sequencing with VIN connected to
1.8-V output
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Figure 9. TPS74201 1.5-V output with no load
3.3 V (500 mV/div)
3.3 V (500 mV/div)
EN (1 V/div)
EN (1 V/div)
1.8 V (500 mV/div)
1.8 V (500 mV/div)
1.5 V (500 mV/div)
1.5 V
(500 mV/div)
Timebase (1 ms/div)
Timebase (2 ms/div)
(a) Pseudo power-up sequencing with VIN connected to
1.8-V output
(b) Pseudo power-down sequencing with VIN connected to
1.8-V output
Conclusion
Reference
To meet DSP and FPGA power-on requirements, many
new DC/DC converters provide methods for controlling
startup. Some also have integrated features to assist with
those few DSPs and FPGAs that have power-down
requirements. The TPS74x01 family of linear regulators
easily provides simultaneous power-up sequencing and,
with the assistance of simple pull-down circuitry and/or
careful sizing of the load resistance at power down, provides two different methods for achieving simultaneous
power-down sequencing.
For more information related to this article, you can download an Acrobat Reader file at www-s.ti.com/sc/techlit/
litnumber and replace “litnumber” with the TI Lit. # for
the materials listed below.
Document Title
TI Lit. #
1. “TPS54680EVM-228 6-Amp,
TPS54880EVM-228 8-Amp, SWIFT™
Regulator Evaluation Module,” User’s Guide . . .slvu077
Related Web sites
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www.ti.com/sc/device/partnumber
Replace partnumber with TPS54610, TPS54680,
TPS74201, TPS74301, or TPS74801
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Analog Applications Journal
Index of Articles
Texas Instruments Incorporated
Index of Articles
Title
Issue
Page
Lit. No.
Data Acquisition
Aspects of data acquisition system design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . . .1
Low-power data acquisition sub-system using the TI TLV1572 . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . . .4
Evaluating operational amplifiers as input amplifiers for A-to-D converters . . . . . . . . . . . . . . . . .August 1999 . . . . . . .7
Precision voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . . .1
Techniques for sampling high-speed graphics with lower-speed A/D converters . . . . . . . . . . . . .November 1999 . . . .5
A methodology of interfacing serial A-to-D converters to DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . . .1
The operation of the SAR-ADC based on charge redistribution . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .10
The design and performance of a precision voltage reference circuit for 14-bit and
16-bit A-to-D and D-to-A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . .1
Introduction to phase-locked loop system modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . .5
New DSP development environment includes data converter plug-ins . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . . .1
Higher data throughput for DSP analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . . .5
Efficiently interfacing serial data converters to high-speed DSPs . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .10
Smallest DSP-compatible ADC provides simplest DSP interface . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . . .1
Hardware auto-identification and software auto-configuration for the
TLV320AIC10 DSP Codec — a “plug-and-play” algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . . .8
Using quad and octal ADCs in SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .15
Building a simple data acquisition system using the TMS320C31 DSP . . . . . . . . . . . . . . . . . . . . .February 2001 . . . . .1
Using SPI synchronous communication with data converters — interfacing the
MSP430F149 and TLV5616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . . .7
A/D and D/A conversion of PC graphics and component video signals, Part 1: Hardware . . . . .February 2001 . . . .11
A/D and D/A conversion of PC graphics and component video signals, Part 2: Software
and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . .5
Intelligent sensor system maximizes battery life: Interfacing the MSP430F123
Flash MCU, ADS7822, and TPS60311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . . .5
SHDSL AFE1230 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . . .5
Synchronizing non-FIFO variations of the THS1206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .12
Adjusting the A/D voltage reference to provide gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . . .5
MSC1210 debugging strategies for high-precision smart sensors . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . . .7
Using direct data transfer to maximize data acquisition throughput . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . .14
Interfacing op amps and analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . . .5
ADS82x ADC with non-uniform sampling clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . . .5
Calculating noise figure and third-order intercept in ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .11
Evaluation criteria for ADSL analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .16
Two-channel, 500-kSPS operation of the ADS8361 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . . .5
ADS809 analog-to-digital converter with large input pulse signal . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . . .8
Streamlining the mixed-signal path with the signal-chain-on-chip MSP430F169 . . . . . . . . . . . . .3Q, 2004 . . . . . . . . . .5
Supply voltage measurement and ADC PSRR improvement in MSC12xx devices . . . . . . . . . . . .1Q, 2005 . . . . . . . . . .5
14-bit, 125-MSPS ADS5500 evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . .13
Clocking high-speed data converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . .20
Implementation of 12-bit delta-sigma DAC with MSC12xx controller . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . .27
Using resistive touch screens for human/machine interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . . .5
Simple DSP interface for ADS784x/834x ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . .10
Operating multiple oversampling data converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . . .5
Low-power, high-intercept interface to the ADS5424 14-bit, 105-MSPS converter for
undersampling applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . .10
Understanding and comparing datasheets for high-speed ADCs . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . . .5
Matching the noise performance of the operational amplifier to the ADC . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . . .5
Using the ADS8361 with the MSP430 USI port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . . .5
Clamp function of high-speed ADC THS1041 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . . .5
Conversion latency in delta-sigma converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . . .5
Calibration in touch-screen systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2007 . . . . . . . . . .5
SLYT191
SLYT192
SLYT193
SLYT183
SLYT184
SLYT175
SLYT176
SLYT168
SLYT169
SLYT158
SLYT159
SLYT160
SLYT148
SLYT149
SLYT150
SLYT136
SLYT137
SLYT138
SLYT129
SLYT123
SLYT114
SLYT115
SLYT109
SLYT110
SLYT111
SLYT104
SLYT089
SLYT090
SLYT091
SLYT082
SLYT083
SLYT078
SLYT073
SLYT074
SLYT075
SLYT076
SLYT209A
SLYT210
SLYT222
SLYT223
SLYT231
SLYT237
SLYT244
SLYT253
SLYT264
SLYT277
25
Analog Applications Journal
3Q 2007
www.ti.com/aaj
High-Performance Analog Products
Index of Articles
Texas Instruments Incorporated
Title
Issue
Page
Lit. No.
Power Management
Stability analysis of low-dropout linear regulators with a PMOS pass element . . . . . . . . . . . . . . .August 1999 . . . . . .10
Extended output voltage adjustment (0 V to 3.5 V) using the TI TPS5210 . . . . . . . . . . . . . . . . . .August 1999 . . . . . .13
Migrating from the TI TL770x to the TI TLC770x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . .14
TI TPS5602 for powering TI’s DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . . .8
Synchronous buck regulator design using the TI TPS5211 high-frequency
hysteretic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . .10
Understanding the stable range of equivalent series resistance of an LDO regulator . . . . . . . . . .November 1999 . . .14
Power supply solutions for TI DSPs using synchronous buck converters . . . . . . . . . . . . . . . . . . .February 2000 . . . .12
Powering Celeron-type microprocessors using TI’s TPS5210 and TPS5211 controllers . . . . . . . .February 2000 . . . .20
Simple design of an ultra-low-ripple DC/DC boost converter with TPS60100 charge pump . . . .May 2000 . . . . . . . .11
Low-cost, minimum-size solution for powering future-generation CeleronTM-type
processors with peak currents up to 26 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . .14
Advantages of using PMOS-type low-dropout linear regulators in battery applications . . . . . . .August 2000 . . . . . .16
Optimal output filter design for microprocessor or DSP power supply . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .22
Understanding the load-transient response of LDOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .19
Comparison of different power supplies for portable DSP solutions
working from a single-cell battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .24
Optimal design for an interleaved synchronous buck converter under high-slew-rate,
load-current transient conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .15
–48-V/+48-V hot-swap applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .20
Power supply solution for DDR bus termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . .9
Runtime power control for DSPs using the TPS62000 buck converter . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .15
Power control design key to realizing InfiniBandSM benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . .10
Comparing magnetic and piezoelectric transformer approaches in CCFL applications . . . . . . . .1Q, 2002 . . . . . . . . .12
Why use a wall adapter for ac input power? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . .18
SWIFT TM Designer power supply design program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .15
Optimizing the switching frequency of ADSL power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .23
Powering electronics from the USB port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .28
Using the UCC3580-1 controller for highly efficient 3.3-V/100-W isolated supply design . . . . . . .4Q, 2002 . . . . . . . . . .8
Power conservation options with dynamic voltage scaling in portable DSP designs . . . . . . . . . . .4Q, 2002 . . . . . . . . .12
Understanding piezoelectric transformers in CCFL backlight applications . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . .18
Load-sharing techniques: Paralleling power modules with overcurrent protection . . . . . . . . . . . .1Q, 2003 . . . . . . . . . .5
Using the TPS61042 white-light LED driver as a boost converter . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . .7
Auto-TrackTM voltage sequencing simplifies simultaneous power-up and power-down . . . . . . . . .3Q, 2003 . . . . . . . . . .5
Soft-start circuits for LDO linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . .10
UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 1 . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . .13
UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 2 . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .21
LED-driver considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .14
Tips for successful power-up of today’s high-performance FPGAs . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . .11
A better bootstrap/bias supply circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . .33
Understanding noise in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . . .5
Understanding power supply ripple rejection in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . . .8
Miniature solutions for voltage isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . .13
New power modules improve surface-mount manufacturability . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . .18
Li-ion switching charger integrates power FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . .19
TLC5940 dot correction compensates for variations in LED brightness . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . .21
Powering today’s multi-rail FPGAs and DSPs, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . . .9
TPS79918 RF LDO supports migration to StrataFlash® Embedded Memory (P30) . . . . . . . . . . .1Q, 2006 . . . . . . . . .14
Practical considerations when designing a power supply with the TPS6211x . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . .17
TLC5940 PWM dimming provides superior color quality in LED video displays . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . .10
Wide-input dc/dc modules offer maximum design flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . .13
Powering today’s multi-rail FPGAs and DSPs, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . .18
TPS61059 powers white-light LED as photoflash or movie light . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . . .8
TPS65552A powers portable photoflash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . .10
Single-chip bq2403x power-path manager charges battery while powering system . . . . . . . . . . . .3Q, 2006 . . . . . . . . .12
Complete battery-pack design for one- or two-cell portable applications . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . .14
A 3-A, 1.2-VOUT linear regulator with 80% efficiency and PLOST < 1 W . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . .10
SLYT194
SLYT195
SLYT196
SLYT185
SLYT186
SLYT187
SLYT177
SLYT178
SLYT170
SLYT171
SLYT161
SLYT162
SLYT151
SLYT152
SLYT139
SLYT140
SLYT130
SLYT131
SLYT124
SLYT125
SLYT126
SLYT116
SLYT117
SLYT118
SLYT105
SLYT106
SLYT107
SLYT100
SLYT101
SLYT095
SLYT096
SLYT097
SLYT092
SLYT084
SLYT079
SLYT077
SLYT201
SLYT202
SLYT211
SLYT212
SLYT224
SLYT225
SLYT232
SLYT233
SLYT234
SLYT238
SLYT239
SLYT240
SLYT245
SLYT246
SLYT247
SLYT248
SLYT254
26
High-Performance Analog Products
www.ti.com/aaj
3Q 2007
Analog Applications Journal
Index of Articles
Texas Instruments Incorporated
Title
Issue
Page
Lit. No.
Power Management (Continued)
bq25012 single-chip, Li-ion charger and dc/dc converter for Bluetooth® headsets . . . . . . . . . . . .4Q, 2006
Fully integrated TPS6300x buck-boost converter extends Li-ion battery life . . . . . . . . . . . . . . . .4Q, 2006
Selecting the correct IC for power-supply applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007
LDO white-LED driver TPS7510x provides incredibly small solution size . . . . . . . . . . . . . . . . . . .1Q, 2007
Power management for processor core voltage requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007
Enhanced-safety, linear Li-ion battery charger with thermal regulation and
input overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007
Current balancing in four-pair, high-power PoE applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007
Power-management solutions for telecom systems improve performance, cost, and size . . . . . .3Q, 2007
TPS6108x: A boost converter with extreme versatility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2007
Get low-noise, low-ripple, high-PSRR power with the TPS717xx . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2007
Simultaneous power-down sequencing with the TPS74x01 family of linear regulators . . . . . . . .3Q, 2007
. . . . . . . . .13
. . . . . . . . .15
. . . . . . . . . .5
. . . . . . . . . .9
. . . . . . . . .11
SLYT255
SLYT256
SLYT259
SLYT260
SLYT261
. . . . . . . . . .8
. . . . . . . . .11
. . . . . . . . .10
. . . . . . . . .14
. . . . . . . . .17
. . . . . . . . .20
SLYT269
SLYT270
SLYT278
SLYT279
SLYT280
SLYT281
TIA/EIA-568A Category 5 cables in low-voltage differential signaling (LVDS) . . . . . . . . . . . . . . .August 1999 . . . . . .16
Keep an eye on the LVDS input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . .17
Skew definition and jitter analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .29
LVDS receivers solve problems in non-LVDS applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .33
LVDS: The ribbon cable connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . .19
Performance of LVDS with different cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .30
A statistical survey of common-mode noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .30
The Active Fail-Safe feature of the SN65LVDS32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .35
The SN65LVDS33/34 as an ECL-to-LVTTL converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .19
Power consumption of LVPECL and LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . .23
Estimating available application power for Power-over-Ethernet applications . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .18
The RS-485 unit load and maximum number of bus connections . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .21
Failsafe in RS-485 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . .16
Maximizing signal integrity with M-LVDS backplanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . .11
Device spacing on RS-485 buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . .25
Improved CAN network security with TI’s SN65HVD1050 transceiver . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . .17
Detection of RS-485 signal loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . .18
Enabling high-speed USB OTG functionality on TI DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . .18
SLYT197
SLYT188
SLYT179
SLYT180
SLYT172
SLYT163
SLYT153
SLYT154
SLYT132
SLYT127
SLYT085
SLYT086
SLYT080
SLYT203
SLYT241
SLYT249
SLYT257
SLYT271
Interface (Data Transmission)
Amplifiers: Audio
Reducing the output filter of a Class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . .19
Power supply decoupling and audio signal filtering for the Class-D audio power amplifier . . . . .August 1999 . . . . . .24
PCB layout for the TPA005D1x and TPA032D0x Class-D APAs . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .39
An audio circuit collection, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .39
1.6- to 3.6-volt BTL speaker driver reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .23
Notebook computer upgrade path for audio power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .27
An audio circuit collection, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .41
An audio circuit collection, Part 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .34
Audio power amplifier measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .40
Audio power amplifier measurements, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . .26
SLYT198
SLYT199
SLYT182
SLYT155
SLYT141
SLYT142
SLYT145
SLYT134
SLYT135
SLYT128
Amplifiers: Op Amps
Single-supply op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . .20
Reducing crosstalk of an op amp on a PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . .23
Matching operational amplifier bandwidth with applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .36
Sensor to ADC — analog interface design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . .22
Using a decompensated op amp for improved performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . .26
Design of op amp sine wave oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .33
Fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .38
The PCB is a component of op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .42
Reducing PCB design costs: From schematic capture to PCB layout . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .48
Thermistor temperature transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .44
Analysis of fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .48
SLYT189
SLYT190
SLYT181
SLYT173
SLYT174
SLYT164
SLYT165
SLYT166
SLYT167
SLYT156
SLYT157
27
Analog Applications Journal
3Q 2007
www.ti.com/aaj
High-Performance Analog Products
Index of Articles
Texas Instruments Incorporated
Title
Issue
Page
Lit. No.
Amplifiers: Op Amps (Continued)
Fully differential amplifiers applications: Line termination, driving high-speed ADCs,
and differential transmission lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .32
Pressure transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .38
Frequency response errors in voltage feedback op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .48
Designing for low distortion with high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .25
Fully differential amplifier design in high-speed data acquisition systems . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .35
Worst-case design of op amp circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .42
Using high-speed op amps for high-performance RF design, Part 1 . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .46
Using high-speed op amps for high-performance RF design, Part 2 . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . .21
FilterProTM low-pass design tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . .24
Active output impedance for ADSL line drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . .24
RF and IF amplifiers with op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . .9
Analyzing feedback loops containing secondary amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . .14
Video switcher using high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . .20
Expanding the usability of current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . .23
Calculating noise figure in op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .31
Op amp stability and input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .24
Integrated logarithmic amplifiers for industrial applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .28
Active filters using current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . .21
Auto-zero amplifiers ease the design of high-precision circuits . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . .19
So many amplifiers to choose from: Matching amplifiers to applications . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . .24
Instrumentation amplifiers find your needle in the haystack . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . .25
High-speed notch filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . .19
Low-cost current-shunt monitor IC revives moving-coil meter design . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . .27
Accurately measuring ADC driving-circuit settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . .14
New zero-drift amplifier has an IQ of 17 µA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . .22
SLYT143
SLYT144
SLYT146
SLYT133
SLYT119
SLYT120
SLYT121
SLYT112
SLYT113
SLYT108
SLYT102
SLYT103
SLYT098
SLYT099
SLYT094
SLYT087
SLYT088
SLYT081
SLYT204
SLYT213
SLYT226
SLYT235
SLYT242
SLYT262
SLYT272
General Interest
Synthesis and characterization of nickel manganite from different carboxylate
precursors for thermistor sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .52
Analog design tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .50
Spreadsheet modeling tool helps analyze power- and ground-plane voltage drops
to keep core voltages within tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . .29
SLYT147
SLYT122
SLYT273
28
High-Performance Analog Products
www.ti.com/aaj
3Q 2007
Analog Applications Journal
TI Worldwide Technical Support
Texas Instruments Incorporated
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Important Notice: The products and services of Texas Instruments
Incorporated and its subsidiaries described herein are sold subject to TI’s
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or endorsement thereof.
A062907
Auto-Track, FilterPro, SWIFT and TurboTrans are trademarks of Texas Instruments. The Bluetooth word mark and
logos are owned by the Bluetooth SIG, Inc., and any use of such marks by Texas Instruments is under license.
Celeron is a trademark and StrataFlash is a registered trademark of Intel Corporation. InfiniBand is a service
mark of the InfiniBand Trade Association. All other trademarks are the property of their respective owners.
SLYT276
29
Analog Applications Journal
3Q 2007
www.ti.com/aaj
High-Performance Analog Products
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