Texas Instruments | ADS8342 ADC SAR Inputs | Application notes | Texas Instruments ADS8342 ADC SAR Inputs Application notes

Texas Instruments ADS8342 ADC SAR Inputs Application notes
Application Report
SBAA127 – January 2005
ADS8342 SAR ADC Inputs
Miroslav Oljaca, Brian Mappes
......................................................................... Data Acquisition Products
ABSTRACT
Successive approximation register analog-to-digital converters (SAR ADCs) present a
challenging load to the circuitry that drives the analog inputs. Specifications in data
sheets may mislead the user into thinking that analog inputs, for example, are static,
when in fact they create a highly dynamic load that requires specially designed buffer
circuitry. This article looks at the architecture of modern SAR ADCs, specifically the
ADS8342, and examines the sampling and conversion processes in detail. This
analysis highlights the considerations needed for designing input buffer circuitry to drive
these ADCs with optimal results.
1
2
3
4
5
Contents
The SAR ADC Structure ...........................................................................
The Sampling Process in Detail ..................................................................
Charge Distribution During the Sampling Process .............................................
Conversion ..........................................................................................
Conclusion ...........................................................................................
1
2
6
7
9
List of Figures
1
2
3
4
5
6
7
1
Representative SAR Input Stage .................................................................
Initial Phase of the Sampling Period .............................................................
Resetting the Value of the Capacitive Conversion Network ..................................
Sampling of the Input Signal ......................................................................
Initial Phase of the Conversion Cycle ............................................................
Capacitive Conversion Network for 16-Bit SAR ADS8342 ....................................
Simplified Circuit of SAR ADS8342 ..............................................................
2
3
3
4
5
5
6
The SAR ADC Structure
Figure 1 presents the simplified structure of the ADS8342 showing the converter core and front-end input
circuitry. The negative input signal to the ADC core, VIN–, is connected to the signal ground or COMMON
pin. The positive input signal to the ADC core, VIN+, comes from the four-position multiplexer. In this way,
the ADS8342 is able to sample four different input signals. At the core of the ADC, the 16-bit capacitive
conversion network of the ADS8342 is replaced with three representative capacitors. Looking at these
three bits, we will examine an equivalent 3-bit conversion sequence. The most significant bit (MSB)
capacitor for ADS8342 has a value of 20pF. The next capacitor to the MSB capacitor will have half its
value, or 10pF. In this example we have a 3-bit converter so the least significant bit (LSB) capacitor will
have one quarter of the MSB capacitor value, or 5pF. To make conversion ideal, a termination capacitor
having the same value as the LSB capacitor is added. The effect of this is that the sum of all the
capacitors below the MSB becomes 20pf, the same as the MSB.
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ADS8342 SAR ADC Inputs
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The Sampling Process in Detail
COMMON
20pF
VIN−
S20
Comparator
20pF
AIN0
AIN1
S30
Control
Logic
VMID
Data
OUT
S40
VIN+
20pF
AIN2
S0
AIN3
VREF
10pF
5pF
S1
S2
5pF
Buffer
REFIN
REFIN
Figure 1. Representative SAR Input Stage
The positive analog input, VIN+, is sampled by the MSB capacitor through switch S0 and the capacitive
conversion network composed of three capacitors and two switches, S1 and S2. The negative analog
input, VIN–, is sampled by two MSB-valued capacitors in series through switch S20.
The external reference voltage is applied to the REFIN input and is buffered by the internal buffer, then
distributed to all switches that are part of the conversion process. On the other hand, switches S30 and
S40 are connected to the middle voltage VMID.
The comparator input signals are connected in parallel to switches S30 and S40. During conversion, the
comparator output will be processed by the control logic, which will properly set up switches S0, S1 and
S2.
Note that this type of architecture is for the ADS8342 and similar, bipolar input range parts. Other parts
may be similar but not identical.
2
The Sampling Process in Detail
At the end of the conversion process, the ADS8342 will automatically go into the sampling process. The
position of the switches S0, S1 and S2 in the capacitive conversion network are unknown. Switch S0 can
be closed to either ground or the reference voltage. The status of the switches depends of the results of
the previous conversion.
We know that during conversion, switch S20 is always connected to the ground. The sampling process will
initiate closing switches S30 and S40. This shorts the comparator inputs and connects them to the middle
voltage VMID. This beginning of the sampling cycle is shown in Figure 2.
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SBAA127 – January 2005
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The Sampling Process in Detail
20pF
VIN−
S20
Comparator
20pF
S30
VMID
Control
Logic
Data OUT
S40
20pF
VIN+
S0
VREF
10pF
5pF
S1
S2
5pF
Buffer
REFIN
Figure 2. Initial Phase of the Sampling Period
Because the positions of switches S1 and S2 are unknown, the equivalent capacitance of the network is
also unknown. For proper sampling, the capacitive conversion network must have an equivalent
capacitance that is equal to the MSB capacitor. To obtain this value, switches S1 and S2, in the following
step, must connect their associated capacitors to the reference voltage. (In this way, the positive input, as
well as the negative input, of the comparator will be connected over the MSB capacitor equivalent value to
VREF.) This will reset the capacitor conversion network value and is shown in Figure 3.
20pF
VIN−
S20
Comparator
20pF
S30
VMID
Control
Logic
Data OUT
S40
20pF
VIN+
S0
VREF
10pF
5pF
S1
S2
5pF
Buffer
REFIN
Figure 3. Resetting the Value of the Capacitive Conversion Network
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ADS8342 SAR ADC Inputs
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The Sampling Process in Detail
Up to this point, all changes only affect the internal operation of the ADS8342. The analog input signals
were not affected by these changes. In the next step, input switches S0 and S20 close, and the input
signal will be sampled on the input MSB capacitors. This period is the most critical period for the input
buffer circuit. To obtain accurate results from the conversion, the input buffer must be capable of charging
the sampling MSB capacitors to the proper value during the sampling period. The sampling of the input
signal is shown in Figure 4.
20pF
VIN−
S20
Comparator
20pF
S30
VMID
Control
Logic
Data OUT
S40
20pF
VIN+
S0
VREF
10pF
5pF
S1
S2
5pF
Buffer
REFIN
Figure 4. Sampling of the Input Signal
After charging the sampling capacitor with the input voltage, the preparation for the conversion cycle starts
by opening switches S30 and S40. Once these two switches are open, the charge on the sampling
capacitors will be frozen. This leads to the end of the sampling period, with the disconnection of the MSB
capacitors from the analog inputs VIN+ and VIN– and connecting them to ground with switches S0 and S20.
The end of the sampling period and start of the conversion cycle is shown in Figure 5.
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ADS8342 SAR ADC Inputs
SBAA127 – January 2005
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The Sampling Process in Detail
20pF
VIN−
S20
Comparator
20pF
S30
VMID
Control
Logic
Data OUT
S40
20pF
VIN+
S0
VREF
10pF
5pF
S1
S2
5pF
Buffer
REFIN
Figure 5. Initial Phase of the Conversion Cycle
This representative analysis is done on a 3-bit ADC and a capacitive conversion network composed of
three capacitors and two switches. This capacitive conversion network can be replaced with the real one
from the ADS8342 as shown in Figure 6.
Comparator
Capacitive Conversion Network
C
VIN+
S0
VREF
C/21
C/22
C/23
C/215
S1
S2
S3
S15
C/215
Buffer
Figure 6. Capacitive Conversion Network for 16-Bit SAR ADS8342
The sampling or MSB capacitor connected to switch S0 has the standardized value C or 20pF. The
capacitive conversion network as presented in Figure 6 has an equivalent capacitive value equal to the
value of the MSB capacitor, C. For the 16-Bit SAR ADS8342, the capacitive conversion network will be
composed of 16 capacitors and 15 switches. The first capacitor has a value that is one-half of the
standardized MSB capacitor value, or (0.5×C). The second capacitor has a value that is one-fourth the
value of C, the third one has a value that is one-eighth the value of C, and so on. The last two capacitors
each have a value that is 1/215th part of the value of C. The resolution of the SAR ADC is equivalent to the
number of switches and capacitors that are in the capacitive conversion network, and their respective
values.
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ADS8342 SAR ADC Inputs
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Charge Distribution During the Sampling Process
3
Charge Distribution During the Sampling Process
To explain the question of charge distribution during the sampling and conversion period, we will use the
simplified circuit of the ADS8342 as shown in Figure 7. This circuit is a combination of the circuits from
Figure 2 and Figure 6.
C N1
VIN−
VCNEG
S20
Comparator
CN2
S30
VMID
CP1
VIN+
Control
Logic
VCPOS
ΣCREF
S0
VREF
Data OUT
S40
ΣCGND
CP2
Buffer
REFIN
Figure 7. Simplified Circuit of SAR ADS8342
In order to analyze this circuit, we will start by describing the position of the sampling or MSB capacitor.
The MSB capacitor (CP1) is connected to switch S0 and the positive input, and has the standardized value
C, or 20pF. The sampling capacitor (CN1) that is connected to switch S20 and the negative input also has
the standardized value C. The capacitive conversion network as presented in Figure 6 has an equivalent
capacitive value equal to the value of the MSB capacitor C, and is presented as capacitor CP2 in Figure 7.
The position of switches S1 to S15 is unknown, so the sum of all capacitors connected to the reference
voltage will be presented as ΣCREF, and all capacitors connected to ground as ΣCGND. The comparator
negative input has voltage VCNEG and positive input VCPOS.
The measured signal is connected to the positive input VIN+ and negative input VIN–. As described in
Section 2, the sampling of the input signal starts by closing switches S30 and S40. In this way, the
positive input voltage VCPOS to the comparator is equal to the middle voltage, VMID. Simultaneously, the
negative input voltage VCNEG to the comparator is also equal to VMID. The next step is to close switches S1
to S15 to VREF. Switches S0 and S20 remain open. Now the ADC is ready to sample the input signal. The
sampling process starts by closing input switches S0 and S20 to the input analog signal.
After a transition period, the voltages stabilize and the new situation is present. The existing configuration
from Figure 7 demonstrates the positive charge, QPS, that charges capacitors CP1 and CP2. Equation 1
explains this charge distribution sequence.
Q PS CP1 VMIDV IN C P2 V MIDV REF
(1)
Following the same procedure, the negative charge QNS that charges capacitors CN1 and CN2 is described
by Equation 2.
Q NS CN1 VMIDV IN C N2 V MIDV REF
(2)
The next step in the sampling process starts by opening switches S30 and S40. In this way, the negative
VCNEG and positive VCPOS input voltages into the comparator are not tied together anymore. The charge
QPS on the capacitors CP1 and CP2, as well as the charge QNS on the capacitors CN1 and CN2, will be
frozen.
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SBAA127 – January 2005
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Conversion
Next, the input switches S0 and S20 open. To initiate the comparison or the conversion process, switches
S0 and S20 will be close to ground. The positive comparator input voltage VCPOS will have a new value,
VX. Now the charge of the two capacitors CP1 and CP2 can be described by Equation 3.
Q PC1 CP1 VXV GND C P2 V XV REF
(3)
Following the same procedure, the charge of capacitors CN1 and CN2 and the negative comparator input
voltage VCNEG will have the new value VY, and can be described by Equation 4.
Q NC1 CN1 VYV GND C N2 V YV REF
(4)
The charges of capacitors CP1 and CP2 during the sampling and conversion processes are the same.
Combining Equation 1 and Equation 3, the result is Equation 5.
C P1 V MIDVIN CP2 VMIDV REF C P1 V XVGND CP2 VXV REF
(5)
Solving Equation 5 for VX is shown in Equation 6.
CP1
C P1
V X VMID
V IN VGND
C P1CP2
C P1CP2
(6)
Substituting VGND with 0, the result is Equation 7.
CP1
V X VMID
V IN
C P1CP2
(7)
A similar procedure is then applied to the negative side of the input stage. If the charges of capacitors CN1
and CN2 during the sampling and conversion are the same, we can combine Equation 2 and Equation 4,
as presented in Equation 8.
C N1 V MIDVIN CN2 VMIDV REF C N1 V YVGND CN2 VYV REF
(8)
Solving Equation 8 for VY is shown in Equation 9.
C N1
CN1
V Y VMID
V IN VGND
C N1CN2
C N1CN2
(9)
Substituting VGND with 0, the result is given in Equation 10.
C N1
V Y VMID
V IN
C N1CN2
4
(10)
Conversion
When the sampling of the input signal ends, the conversion process begins by opening switches S30 and
S40, capturing the input analog signal. Next, the sample switches S0 and S20 are opened, as explained in
Section 3. Descriptions in this section refer to Figure 7.
4.1
The Negative Input Signal
First, let us look at the negative input signal side. We will refer to the comparator negative input node at
S30 as VCNEG. The negative input signal side is set up as an input-signal-voltage-dependent reference for
the comparator. Switch S20 switches from VIN– to VGND. The charge stored in the negative input signal
side capacitors CN1 and CN2, during conversion QNC, is ideally the same as the charge stored during
sampling QNS. As a result, the charge sum on capacitors CN1 and CN2 is conserved.
Capacitors CN1 and CN2 are equal and have the same value. The negative input comparator voltage VY
(referring to Equation 10) is now VCNEG, and is constant during the entire conversion period; it can be
described by Equation 11. Additionally, because VMID is connected to the analog ground, it is replaced
with 0.
C N1
V CNEG V IN
CN2C N2
(11)
In the case of the ADS8342, VIN– is connected and equal to VGND; consequently, very little charge
redistribution occurs on the negative input signal side during and after sampling.
SBAA127 – January 2005
ADS8342 SAR ADC Inputs
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Conversion
4.2
The Positive Input Signal
The conversion process is made by comparing the dynamic signal VCPOS with the constant voltage VCNEG
described by Equation 11. In Figure 7, capacitor CP2 is an equivalent presentation of the sum of the
capacitors, ΣCREF, connected to the reference voltage VREF, and the sum of the capacitors, ΣCGND,
connected to the ground voltage VGND, over associated switches S1 through S15 (see Figure 6). During
the conversion, the distribution of the capacitors ΣCREF and ΣCGND will change, so that the difference
between voltages VCPOS and VCNEG is minimized.
On the positive input signal side, the transition from sampling into testing the MSB is similar to the
negative input signal side. We will refer to the comparator positive input node at S40 as VPOS (see
Figure 5). The positive input signal side is set up as a variable input signal voltage for the comparator.
Switch S0 switches from VIN+ to VGND and switches S1 through S15 remain connected to VREF (see
Figure 6). The charge stored in the positive input signal side capacitors CP1 and CP2, during conversion
QPC, is ideally equivalent to the charge stored during sampling QPS. The charge on the total capacitor
array is the same during conversion as during sampling. CP1 and CP2 is conserved. Thus, the VPOS is used
in Equation 12 to describe the charge on the capacitive conversion network during the conversion
process.
Q PC1 CP1C P2 V CPOSC REF V REFCGND VGND
(12)
4.3
Testing the Bits
At the end of the first clock cycle, voltages VCPOS and VCNEG are compared by the comparator, resolving
the value of the MSB to either a 1 or a 0. This value will be latched into the SAR control logic. If the value
is 1, the CP1 capacitor remains connected over switch S0 to VGND. If the value is 0, it will be connected
over the same switch to VREF.
To understand the rest of the conversion process, we need to refer to the capacitive conversion network
presented in Figure 7. At the same clock edge, the control logic of the SAR converter shifts to test the
next most significant bit, which will be referred to as bit2. Switch S1 from Figure 6 switches from VREF to
ground. The charge on the capacitor array will again be redistributed, placing a load on the reference
buffer.
The state of the capacitor array is now a function of the decision made during the MSB test. Each bit test
that follows will be a function of the preceding bit test. The voltage on VCPOS becomes dependent on
which capacitors from the capacitive conversion network are connected to VREF and which are connected
to VGND. Under these conditions, combining Equation 1 and Equation 12, the positive input voltage VCPOS
to the comparator can be described by Equation 13 through Equation 15.
C P1 V IN C P2 V REF CP1C P2 VCPOS C REF VREFC GND V GND
(13)
V CPOS C P1
CP2
C REF
V IN V REF
V REF
CP1C P2
C P1C P2
CP1C P2
V CPOS C P1
C P1
CREF
V IN 1
VREF
V REF
CP1C P2
C P1CP2
C P1C P2
(14)
(15)
In each of these equations, ΣCREF (as explained previously) represents the sum of all capacitors at the
comparator positive input tied to the reference voltage VREF.
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SBAA127 – January 2005
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Conclusion
4.4
The End of Conversion
This testing sequence continues until the final bit is tested. We can assume that at the end of the
conversion, the negative input signal into the comparator VCNEG is equal to the positive input signal into
the comparator VCPOS. Combining Equation 11 and Equation 15, we can relate VCPOS and VCPOS by
Equation 16. The purpose of the conversion is to drive the positive input signal into the comparator VCPOS
to the same value of VCNEG.
CN1
CP1
C P1
C REF
VIN V IN 1
VREF
V REF
C N1CN2
C P1C P2
CP1C P2
C P1CP2
(16)
It is interesting to note that for any given resolution, with any given input signal, the state of the capacitors
at the end of conversion is given by Equation 17, which is obtained by solving Equation 16 for the input
signal, or (VIN+ – VIN–). The values of capacitors CN1 and CP1 are equal and will be replaced with C1;
because the values of CN2 and CP2 are equal, as well, these will be replaced with C2.
V INVIN C 1C 2
C REF
C1
1
C1
C 1C2
C 1C2
V
REF
(17)
Moreover, because C1 and C2 have the same value, we can replace them with C in Equation 18, giving us
a final equation that describing the conversion process.
V INVIN CC
REF
1 V REF
(18)
The more positive the value of the input signal, or (VIN+ – VIN–), the greater the proportion of capacitors
that are tied to the reference voltage VREF. At positive full-scale, VIN+ – VIN– = +VREF, and all capacitors
from the capacitor conversion network will be tied to VREF. Alternately, if VIN+ – VIN– = –VREF, then no
capacitors are tied to VREF, or all of them are tied to VGND.
Since that ΣCREF /C is in the range of 0 to 2, then we can see that the input analog signal VIN+ – VIN– is in
the range from –VREF up to +VREF, from Equation 18.
Note that the ADS842 complements the most significant bit in the output code. The MSB indicates
negative signals with a '1'. If the MSB is a '1' internally, indicating the input signal is positive, it will be a '0'
in the output code.
5
Conclusion
This application report has highlighted several key considerations for designing input buffer circuitry in
order to drive SAR ADCs with optimum performance. The first step in designing driver or buffer circuits for
analog input into the ADC is a full understanding of the input structure operation. This understanding leads
to a complete grasp of the performance requirements for the buffer circuit. It is not simply looking at the
circuit that will enable better design; the dynamic circuit input requires careful layout and component
selection, which is not obvious at first glance.
SBAA127 – January 2005
ADS8342 SAR ADC Inputs
9
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