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Texas Instruments Data Capture with Multiple ADS1244 or ADS1245 Devices in Parallel Application notes
Application Report
SBAA116 – June 2004
Data Capture with Multiple ADS1244/45 Devices in Parallel
Jason Bridgmon ....................................................................................... Data Acquisition Products
ABSTRACT
The ADS1244 and ADS1245 are excellent low-power, high-precision analog-to-digital converters (ADCs). Either device can be easily inserted into a single channel measurement
system. When designing these ADCs into a multi-channel parallel measurement system,
some care must be taken when creating the digital interface that communicates with the
devices. This application note discusses several important considerations when using the
ADS1244/45 devices in multi-channel parallel measurement systems.
1
Using Multiple ADS1244/45 Devices in Parallel
Figure 1 shows a generic, parallel, multi-channel measurement system design for the ADS1244/45. The
ADS1244/45s provide a short pulse when data is ready. In a parallel measurement system, these pulses
can be shifted up to 500µs apart from each other, despite the devices sharing the same clock signal. (See
the Multichannel Systems section of the ADS1244 and the ADS1245 data sheets for further explanation.)
In order to obtain synchronous measurements from ADS1244/45s that are configured in parallel, simply
monitoring one DOUT pin for the Data Ready Pulse is not sufficient to start data capture from all linked
devices simultaneously.
SBAA116 – June 2004
Data Capture with Multiple ADS1244/45 Devices in Parallel
1
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Clock Source
SCLK
ADS1244/45
VREF
1
GND
CLK 10
2
VREFP
SCLK
9
3
VREFN
DRDY/DOUT
8
4
AINN
DVDD
7
5
AINP
AVDD
6
1
GND
2
VREFP
SCLK
9
3
VREFN
DRDY/DOUT
8
4
AINN
DVDD
7
5
AINP
AVDD
6
DOUT1
DVDD
AVDD
ADS1244/45
VREF
CLK 10
DOUT2
DVDD
AVDD
ADS1244/45
VREF
1
GND
CLK 10
2
VREFP
SCLK
9
3
VREFN
DRDY/DOUT
8
4
AINN
DVDD
7
5
AINP
AVDD
6
DOUTN
DVDD
AVDD
Figure 1. Standard Multi-Channel Configuration
The most convenient method for ensuring that all the parallel devices are synchronized is to shift in 25
SCLK pulses, which will shift out 24 bits of data on the DOUT pin and set DOUT high. At this point,
monitor all the DOUT pins until they are all low; then, read the next data out. If input pins on the read-back
device are available, an OR gate attached to the DOUT lines in parallel may make the software or
firmware programming easier. (See Figure 2.)
2
Data Capture with Multiple ADS1244/45 Devices in Parallel
SBAA116 – June 2004
www.ti.com
1
2
24
25
1
2
24
25
SCLK
DOUT 1
DOUT 2
DOUT N
All Channels
have new data ready
when all DOUT pins are low.
25 SCLK pulses
force DOUT pins high.
New data ready again.
Figure 2. Read-Back Timing
2
Self-Calibration and Device Start-Up
The issue of start-up conditions must also be addressed. When the devices power-up and begin receiving
clock pulses, self-calibration is performed if SCLK is low. DOUT then begins to indicate that data is ready.
If SCLK is high at start-up, however, the ADS1244/45 enters into Sleep Mode and does not perform a
self-calibration. (See Figure 3.)
1
2
25
26
1
2
SCLK
DOUT 1
DOUT 2
DOUT N
Power-up
into Sleep mode.
Part out of Sleep mode;
issue 26 SCLKs
for calibration.
All channels have new data ready
when all DOUT pins are low.
Figure 3. Power-Up Calibration Timing
There are numerous advantages to postponing the calibration and enabling start-up in Sleep Mode, in
addition to easy parallel device control. If the board has a fast-ramping power supply and slow-ramping
reference, or a reference with large capacitors that takes a long time to settle, then this method is
particularly applicable and desirable, because the potential for error is greatly reduced.
Once a device has powered up into Sleep Mode, it is also convenient to use the same hardware-,
firmware-, or software-detect circuitry for the initial calibration operation. When an ADS1244/45 is in Sleep
Mode, take SCLK low, then wait for all the DOUT lines to also go low. At this point, shift in 26 SCLK
pulses to initiate the calibration process.
The DOUT lines will immediately go high after the 25th SCLK pulse, if not already high, and will stay high
until calibration is finished and the next data is ready. Follow the standard 25 SCLK pulse read-back
technique discussed earlier to verify that each of the daisy-chained devices are read back in parallel.
SBAA116 – June 2004
Data Capture with Multiple ADS1244/45 Devices in Parallel
3
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3
Going Further
This parallel readback technique is also applicable to another member of the TI delta-sigma family, the
ADS1224. This device has more features than the ADS1244/45, which may be more suited to particular
applications. It uses the same 2-wire interface as the ADS1244, but the ADS1224 has a sample rate of
240SPS, which is considerably faster than the ADS1244. It has a pin-selectable high-impedance input
buffer and an input multiplexer with four differential channels, for even more data channel support per
chip. The ADS1224 also has an on-chip temperature sensor, which makes it well-suited for use in
applications where temperature drift and calibration are particular concerns.
4
References
ADS1224 Datasheet (SBAS286A)
ADS1244 Datasheet (SBAS273)
ADS1245 Datasheet (SBAS287A)
To obtain a copy of the referenced documents, visit the Texas Instruments web site at www.ti.com. x
indicates the current revision letter for each document.
4
Data Capture with Multiple ADS1244/45 Devices in Parallel
SBAA116 – June 2004
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