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Texas Instruments Interface LM12454/8 Data Acq Sys Chips to Microprocessors & Microcontrollers Application notes
LM12454,LM12458,LM12H458,LM12L458
AN-906 Interfacing the LM12454/8 Data Acquisition System Chips to
Microprocessors and Microcontrollers
Literature Number: SNAA010
National Semiconductor
Application Note 906
Farid Saleh
August 1993
TABLE OF CONTENTS
Ð A 32-word FIFO register for storage of conversion
results.
Ð Interrupt control logic with interrupt generation for 8 different conditions.
Ð A 16-bit timer register.
Ð Circuitry for synchronizing signal acquisition with external events.
Ð A parallel microprocessor interface with selectable 8-bit
or 16-bit data access.
Because of its functionality and flexibility, working with the
LM12454/8 family may appear to be an overwhelming task
at first glance. However, this is not the case when the user
gains a basic understanding of the device’s functional units
and the philosophy of its operation. This note shows how
easy it is to use the LM12454/8 family and walks the user
through the straightforward steps of the interfacing and programming of the device.
The LM12454/8 family has 6 members. The members and
their differences are shown in Table I. For simplicity, the
DAS abbreviation will be used throughout this Application
Note as a generic name for any member of the family. Similarly, the drawings illustrate only the 8 input versions of the
family. Note that this Application Note should be used in
conjunction with the device data sheet and assumes the
reader has some degree of familiarity with the device. However, a brief overview of the DAS and information related to
the subjects being discussed are given here.
1.0 INTRODUCTION
2.0 GENERAL OVERVIEW
2.1 The DAS Programming Model
2.2 Programming Procedure
2.3 A Typical Program Flowchart and Alternative
Approaches
2.4 The DAS/Processor Interface
3.0 INTERFACING THE DAS TO HPCTM
MICROCONTROLLERS
3.1 Complete Address Decoding
3.2 Minimal Address Decoding
3.3 Timing Analysis
3.3.1 Complete Address Decoding Circuit
3.3.2 Minimal Address Decoding Circuit
4.0 A SYSTEM EXAMPLE: A SEMICONDUCTOR
FURNACE
4.1 System Requirements and Assumptions
4.2 DAS Setup and Register Programming
4.3 Microcontroller Programming
4.3.1 HPC Assembly Routines for the Semiconductor
Furnace Example
1.0 INTRODUCTION
The LM12454/8 family of data acquisition system (DAS)
chips offers a fully differential self-calibrating 12-bit a sign
A/D converter with differential reference, 4 or 8 input analog
multiplexer and extensive flexible and programmable logic.
The logic embodies different units to perform specific tasks,
for instance:
Ð An instruction RAM for stand-alone execution (after being programmed by the host) with programmable acquisition time, input selection, 8-bit or 12-bit conversion
mode, etc.
Ð Limit registers for comparison of the inputs against high
and low limits in ‘‘watchdog’’ mode.
2.0 GENERAL OVERVIEW
2.1 The DAS Programming Model
Figure 1 illustrates the functional block diagram or user programming model of the DAS. (This diagram is not meant to
reflect the actual implementation of the DAS internal building blocks.) The DAS model consists of the following
blocks:
Ð A flexible analog multiplexer with differential output at
the front end of the device.
Interfacing the LM12454/8 Data Acquisition System Chips
to Microprocessors and Microcontrollers
Interfacing the LM12454/8
Data Acquisition System
Chips to Microprocessors
and Microcontrollers
TABLE I: Members of the LM12454/8 Family
Operating
Supply Voltage
(V)
Number of
MUX Inputs
Internal
Reference
Low Voltage
Flag
LM12454
5
5.0 g 10%
4
Yes
Yes
LM12458
5
5.0 g 10%
8
Yes
Yes
LM12H454
8
5.0 g 10%
4
Yes
Yes
LM12H458
8
5.0 g 10%
8
Yes
Yes
LM12L454
6
3.3 g 10%
4
No
No
LM12L458
6
3.3 g 10%
8
No
No
HPCTM is a trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/H/11908
RRD-B30M75/Printed in U. S. A.
AN-906
Clock
Frequency
(Max, MHz)
Device
Number
TL/H/11908 – 1
FIGURE 1. DAS Functional Block Diagram, Programming Model
tions are used in the watchdog mode and the user defined
limits are stored in them. Each watchdog instruction has 2
limits associated with it (usually the low and high limits, but
two low or two high limits may be programmed instead). The
DAS can start executing from Instruction 0 and continue
executing the next instructions up to any user specified instruction and, then ‘‘loops back’’ to Instruction 0. This
means that not all 8 instructions need to be executed in the
loop. The cycle may be repeatedly executed until stopped
by the user. The user should access the Instruction RAM
only when the instruction sequencer is stopped.
The FIFO Register is used to store the results of the conversion. This register is ‘‘read only’’ and all the locations are
accessed through a single address. Each time a conversion
is performed the result is stored in the FIFO and the FIFO’s
internal write pointer points to the next location. The pointer
rolls back to location 1 after a write to location 32. The
same flow occurs when reading from the FIFO. The internal
FIFO writes and the external FIFO reads do not affect each
other’s pointer locations.
The CONFIGURATION Register is the main ‘‘control panel’’
of the DAS. Writing 1s and 0s to the different bits of the
Configuration Register commands the DAS to perform different actions such as start or stop the sequencer, reset the
pointers and flags, enter standby mode for low power consumption, calibrate offset and linearity, and select sections
of the RAM.
The INTERRUPT ENABLE Register lets the user activate up
to 8 sources for interrupt generation. It also holds two user
programmable values. One is the number of conversions to
be stored in the FIFO register before the generation of the
data ready interrupt. The other value is the instruction number that generates an interrupt when the sequencer reaches
that instruction.
The INTERRUPT STATUS and LIMIT STATUS Registers
are ‘‘read only’’ registers. They are used as vectors to indicate which conditions have generated the interrupt and
what limit boundaries have been passed. Note that the bits
Ð A fully-differential, self-calibrating 12-bit a sign A/D
converter.
Ð A 32-word FIFO register as the output data buffer.
Ð An instruction RAM that can be programmed to repeatedly perform a series of conversions and comparisons
on the selected input channels.
Ð A series of registers for overall control and configuration
of the DAS operation and indication of internal operational status.
Ð Interrupt generation logic to request service from the
processor under specified conditions.
Ð Parallel interface logic for input/output operations between the DAS and the processor. All the registers
shown in the diagram can be read and most of them can
also be written to by the user through the input/output
block.
Ð A controller unit that controls the interactions of the different blocks inside the DAS and performs the conversion, comparison and calibration sequences.
The DAS has 3 different modes of operation: 12-bit a sign
conversion, 8-bit a sign conversion and 8-bit a sign comparison, (also called ‘‘watchdog’’ mode). In the watchdog
mode no conversion is performed, but the DAS samples an
input and compares it with the values of the two limits
stored in the Instruction RAM. If the input voltage is above
or below the limits (as defined by the user) an interrupt can
be generated to indicate a fault condition.
The INSTRUCTION RAM is divided into 8 separate words,
each with 48 (3x16) bit length. Each word is separated into
three 16-bit sections. Each word has a unique address and
different sections of the instruction are selected by the 2-bit
RAM pointer (RP) in the configuration register. As shown in
Figure 1 , the Instruction RAM sections are labeled Instructions, Limits Ý1 and Limits Ý2. The Instruction section
holds operational information such as; the input channels to
be selected, the mode of operation for each instruction, and
how long the acquisition time should be. The other two sec-
2
Defining a general programming procedure is not practical
due to the extreme flexibility of the DAS and the variety of
the applications. However, the following typical procedure
demonstrates the basic concepts of the DAS start-up routine:
Ð Reset the DAS by setting the RESET bit and select RAM
section ‘‘00’’ through the Configuration register.
Ð Load instructions to the Instruction RAM (1 to 8 instructions).
Ð Select RAM section ‘‘01’’ (if used) through the Configuration register.
Ð Load limits Ý1, 1 to 8 values (if used).
are set in the status registers upon occurrence of their corresponding interrupt conditions, regardless of whether the
condition is enabled for external interrupt generation.
The TIMER Register can be programmed to insert a delay
before execution of each instruction. A bit in the Instruction
register enables or disables the insertion of the delay before
the execution of an instruction.
Appendix A shows all the DAS accessible registers and a
brief description of their bits assignments. These bit assignments are discussed in detail in the data sheet and are repeated here for reference. There are also empty register
models available on the same pages that can be used as a
programming tool. The designer can fill these register models with ‘‘1s’’ and ‘‘0s’’ during design based on system requirements. The user can also use these sheets for design
documentation.
Ð Select the RAM section ‘‘10’’ (if used) through the Configuration register.
Ð Load limits Ý2, 1 to 8 values (if used).
Ð Initialize the Interrupt Enable register, by selecting the
conditions to generate an interrupt at the INT pin (if
used).
Ð Program the Timer register for required delay (if used).
Ð Start the sequencer operation by setting the START bit
in the Configuration register. Set the other bits in the
Configuration register as required at the same time.
After the DAS starts operating, the processor may respond
to interrupts from the DAS or it may interrogate the DAS at
any time.
2.2 Programming Procedure
The DAS is designed for control by a processor. However,
the functionality of the DAS off loads the processor to a
great extent, resulting in reduction of the software overhead. At the start, the processor downloads a set of operational instructions to the DAS’ RAM and registers and then
gives a start command to the DAS. The DAS performs continuous conversions and/or comparisons as dictated by the
instructions and loads the conversion results in the FIFO.
From this point the processor has two basic options for interaction with the DAS. The DAS can generate an interrupt
to the processor when the predetermined number of conversion results are stored in the FIFO or when any other
interrupt conditions have occurred. The processor will then
service the interrupt by reading the FIFO or taking corrective
action, depending on the nature of the interrupt. Alternatively, rather than responding to an interrupt, the processor at
any time can read the data or give a new command to the
DAS.
2.3 A Typical Program Flowchart and Alternative Approaches
A typical DAS program flowchart is shown in Figure 2 . Figure 2a shows the initialization of the DAS and the start of
the conversions. Figure 2b shows the general form of the
DAS interrupt service routine. It is assumed that the DAS
interacts with the processor through an interrupt line. This
means the host processor generally is busy with other tasks
and responds to the DAS through its interrupt service routine.
3
TL/H/11908 – 2
FIGURE 2a. A Typical Program Flowchart for the DAS Initialization and Start of Conversions
4
TL/H/11908 – 3
FIGURE 2b. A Typical Program Flowchart for the DAS Interrupt Service Routine
5
the logic family being used, and the loading (resistive and
capacitive) on the data bus being driven by the DAS, all can
affect conversion noise. Nevertheless, reading during conversions has been shown not to cause serious accuracy
problems in most systems.
There are two timing issues regarding the reading during
conversion.
During any read or write from or to the DAS, the DAS internal clock will stop while the CS is low. This is done for
synchronization between external and internal bus activities,
thus preventing internal conflicts. Note that reads and writes
are asynchronous to internal bus activities. A pause of internal clock cycles will increase the total acquisition plus conversion time for each instruction. The amount of this time
increase is variable and is not easily predictable, because
the processor and the DAS work asynchronously. As a result, the user should not perform reads during conversions if
the fixed time intervals between the signal acquisitions are
critical in the system performance.
The second timing issue depends on the speed of the conversions and the speed of the read cycles from the FlFO.
The rule is to read the FIFO fast enough that old data will
not be overwritten with new data during continuous conversions.
Returning to the flowchart, the main task of the interrupt
service routine is to read the DAS’ Interrupt Status register
and test its bits for the source of the interrupt. The interrupt
service routine shows all the interrupt bits in the DAS being
tested. However, real systems often use only a few number
of the interrupts, so the extra bit tests should be eliminated
from the routine. Also, the sequence in which the bits are
tested depends on the priority level of the interrupts in the
system. The tasks to be performed for each interrupt are
mainly system related and are not elaborated upon in the
flowchart. If conversions are stopped at the start of the interrupt service, one possibility is to restart conversion before returning from the interrupt service routine. Otherwise
conversions will be restarted again at some other point in
the system routines.
There is a processor initialization step at the start of the
flowchart. It is included as a reminder that some specific
processor initialization may be needed just for interaction
with the DAS.
The DAS initialization steps are a series of write operations
to the DAS registers. These steps are the same as mentioned in Section 2.2.
A full calibration cycle is usually performed after setting the
DAS’ registers. This is required for 12-bit accuracy. You may
choose to perform one full calibration at power up, or periodic calibrations at specified time intervals, or conditionbased calibrations, e.g., calibrations after a specified
change in temperature. Calibration is done by writing the
appropriate control code to the Configuration register. A full
calibration cycle takes about 1 ms (989 ms) with a 5 MHz
clock and about 0.6 ms (618 ms) with an 8 MHz clock. You
can insert a delay after starting a calibration cycle, or can
detect the end of calibration by an interrupt, or by reading
the Interrupt Status register for the corresponding flag bit. In
the flowchart, the end-of-calibration detection is handled in
the interrupt service routine. The full calibration cycle affects some of the DAS’ internal flags and pointers that will
influence the execution of the first instruction after calibration. To avoid false instruction execution, the DAS should be
reset after a calibration cycle. This is shown on the flowchart for the interrupt service routine.
After a calibration, the DAS is ready to start conversions.
Conversion is initiated by writing to the configuration register
and setting the START bit to ‘‘1’’. The data to be written to
the configuration register is shown in binary format in the
flowchart. The bits shown by ‘‘P’’ (program) are the control
bits that determine different modes of operation during conversions. All the other bits should be programmed as
shown. As mentioned before, the host processor can perform data manipulation and other control tasks after starting
the DAS, and will respond to the DAS interrupts as required.
At the start of the interrupt service routine (Figure 2b ), a
zero is written to START bit in the Configuration register, to
stop the conversion. Stopping the conversion is not necessarily needed unless it is required for accuracy or timing
purposes. Generally the results of conversions will be noisier and less accurate if reads or writes to and from the DAS
are performed while it is converting. However, the degree of
this inaccuracy depends on many aspects of system design
and is not easy to quantify. Power supply and ground routing, supply bypassing, speed of logic transitions on the bus,
2.4 The DAS/Processor Interface
The interface between the processor and the DAS is similar to a memory or I/O interface. Some possible DAS/
microcontroller interface schemes are shown in Figures 3 ,
4 and 5 .
TL/H/11908 – 4
FIGURE 3. LM12458 to HPC or 8051 Microcontroller Interface
6
TL/H/11908 – 5
FIGURE 4. LM12458 to 68HCII Microcontroller Interface
TL/H/11908 – 6
FIGURE 5. LM12458 to HPC or 8051 Microcontroller Interface (Minimum System)
external address latches are not required by the system.
The DAS can be accessed in either 8-bit or 16-bit data
width. BW (Bus Width) input pin selects the 8-bit or 16-bit
access. In 8-bit access mode, each 16-bit I/O register is
accessed in 2 cycles. Address line A0 selects the lower or
upper portions of a 16-bit register. In 16-bit access mode,
address line A0 is a ‘‘don’t care’’. As shown in the Figures
6a and 6b , the DAS appears to the processor as 14 separate 16-bit or 28 separate 8-bit I/O locations.
From the processor’s point of view, the DAS is a group of
I/O registers with specific addresses. Figure 6 illustrates the
DAS registers with their address assignments and the DAS
interface buses and control signals. The DAS provides standard architecture for address, data and control buses for
parallel interface to processors. The DAS can be interfaced
to both multiplexed and non-multiplexed address/data bus
architectures. An ALE input and internal latches allow the
DAS to interface to a multiplexed address/data bus when
7
TL/H/11908 – 7
FIGURE 6a. DAS Registers, Address Assignments, Interface Buses and Control Signals for 8-Bit Bus Width
TL/H/11908 – 8
FIGURE 6b. DAS Registers, Address Assignments, Interface Buses and Control Signals for 16-Bit Bus Width
8
formance 16-bit microcontrollers. The HPC family is available in a variety of versions suitable for specific applications. The reader is encouraged to refer to HPC family data
sheets for complete information, available versions, and
their specifications. The HPC46083, a 16-bit microcontroller
with 16-bit multiplexed data and address lines, is one of the
simplest members of the family. It is a complete microcontroller containing all the necessary system timing, internal
logic, ROM, RAM, and I/O, and is optimized for implementing dedicated control functions in a variety of applications.
Its architecture recognizes a single 64k byte of address
space containing all the memory, registers and I/O addresses (memory-mapped I/O). The addressing space of the first
512 bytes (0000H to 01 FFH) contains 256 bytes of on-chip
user RAM and internal registers. (The address values are
given in hexadecimal format with suffix ‘‘H’’ as an indicator.)
The last 8 kbytes of the address space (E000H to FFFFH)
are on-chip ROM used mainly for program storage. In the
following applications, the HPC46083 is setup for the expanded mode (as opposed to the single-chip mode) of operation that allows the external address range (0200H to
DFFFH) to be accessed. The external data bus in the HPC
family is configurable as 8-bit or 16-bit, allowing it to efficiently interface with a variety of peripheral devices.
Interrupt handling is accomplished by the HPC46083’s vector interrupt scheme. There are eight possible interrupt
sources for the HPC46083. Four of these are maskable external interrupt inputs. These inputs can be programmed for
different schemes, e.g., interrupt at low level, high level, rising edge or falling edge. One of these interrupts is used for
interface with the DAS. The term ‘‘HPC’’ will be used
throughout the remainder of this discussion to refer to the
HPC46083.
Two different interface circuits are presented in Figures 7
and 8 . The first circuit in Figure 7 uses complete address
decoding with the external address latches. This scheme
assumes the HPC is accessing other devices using other
address ranges. The circuit in Figure 8 assumes the DAS is
the only (or one of a few) peripherals interfaced to the HPC,
so incomplete address decoding is used for minimum interface logic. Note that the address decoding schemes used in
these circuits are only two of many different possibilities and
are presented as generic forms of address decoding. These
circuits are used as vehicles to illustrate the issues regarding the interface, and different schemes with other logic
families or PAL devices can also be used for interface circuits.
The interface should provide the address, data and control
signals to the DAS with the following requirements:
Ð An address decoder is needed to generate a chip-select
for the DAS within the required address range.
Ð The switching relationship between ALE, CS, RD, WR,
address bus and data bus should satisfy the DAS timing
requirements. (Please refer to the data sheet for timing
requirements.)
Ð When the DAS is working in an interrupt-driven I/O environment, a suitable service request link between the
DAS and the system should be provided. This can be as
simple as connecting the DAS’ INT output to a processor’s interrupt input or as sophisticated as using interrupt
arbitration logic (interrupt controller) in systems that
have many I/O devices.
Figure 3 illustrates the generic interface for the National
Semiconductor’s HPC family of 16-bit microcontrollers and
the 8051 family of 8-bit microcontrollers. Figure 4 illustrates
the interface for the 68HC11 family of microcontrollers or
the processors with similar control bus architecture. The circuits in Figures 3 and 4 are the maximum system schemes
assuming the microcontroller is accessing other peripherals
in addition to the DAS, therefore external address latches
and an address decoder are required to select the DAS as
well as the other peripherals. The size and complexity of the
address decoder, however, depends on the system. In a
minimum system scheme, the DAS can be interfaced to the
microcontroller with minimal external logic for address latches and address decoder. This is shown in Figure 5 . Note
that the DAS’ CS signal is also latched with the ALE inside
the DAS, so a higher order address bit can be used to drive
CS input. In this scheme a wide range of addresses (with
many bits as ‘‘don’t cares’’) are used to access the DAS.
Care must be taken not to use this address range for any
other memory or I/O locations. For example, lets assume bit
A15 is used for CS, and must be 1 (inverter in place) to
select the DAS. As a result, all the 32k of the upper address
range is used for the DAS. However, address bits A5 to A14
are ‘‘don’t cares’’ and the DAS can be mapped anywhere
within the upper 32k of the address range.
3.0 INTERFACING THE DAS TO HPC
MICROCONTROLLERS
In this section we are going to develop a detailed interface
circuit between the HPC46083 microcontroller and the DAS.
The HPC46083 is a member of the HPC family of high per-
9
10
FIGURE 7. The DAS/HPC Microcontroller Interface (Complete Address Decoding)
TL/H/11908 – 9
11
FIGURE 8. The DAS/HPC Microcontroller Interface (Minimal Address Decoding)
TL/H/11908 – 10
The DAS can still be accessed with the same address range
in the Figure 7 circuit, which is 0200H to 021BH. However,
many address bits are ‘‘don’t care’’ in this case. The binary
form of the DAS register addresses for the circuit in Figure 8
is: 0XXX,XX1X,000P,PPP0. The P’s indicate program bits,
these will be programmed to select different registers. The
X’s are ‘‘don’t care’’ bits. The rest of the bits should be
programmed as shown.
The 3-to-8 line decoder (U5) outputs, Y1 to Y7, can still be
used to access other peripherals, those peripherals should
have internal latches for the address and chip-select as
well. For example, up to eight DAS chips can be interfaced
to an HPC using the circuit in Figure 8 , for monitoring and
data logging of 64 analog input channels. If the interface is
for one DAS only, the DAS’ CS input can be generated with
minimum of 2 gates, as shown within the dashed-lines on
Figure 8 , replacing the U5.
The critical DAS timing requirement for the circuit in Figure 8
is the address and chip-select setup time to ALE going low.
The HPC running at 20 MHz clock frequency cannot satisfy
this timing specification. As a result, the clock speed of the
HPC is lowered to 11.09 MHz to meet the DAS requirement.
This point is also discussed further in the Timing Analysis
section.
3.1 Complete Address Decoding
Figure 7 shows the circuit with complete address decoding
to generate the DAS’ CS signal. The DAS is accessed as
memory mapped I/O at the start of the external address
range (0200H to 021BH), and 16-bit data access is selected
for the DAS. External address latches, U2 and U3,
(74HC573) are used for the HPC’s multipIexed 16-bit data/
address lines. As a result, the ALE input of the DAS is tied
high. An 8-bit magnitude comparator, U4, (74HC688) decodes the high order address byte [A15...A8] by comparing
it with the logic input from the address range selector jumpers on header JP1. The jumper setting shown in Figure 7 is
02H. The output of the magnitude comparator enables 3-to8 line decoder chip, U5, (74HC138). The 3-to-8 line decoder
inputs are address lines A5 to A7. The output Y0 of the 3-to8 line decoder is activated for the 32 locations of address
space from 0200H to 021FH. This output (Y0) is used for
the DAS’ CS input. Address lines A1 to A4 are directly connected to the DAS address inputs. The A0 input of the DAS
is tied to ground since 16-bit data access is used and A0 is a
‘‘don’t care’’. The DAS uses 28 bytes of address locations
with addresses from 0200H to 021BH.
The DAS signal timing requires that its CS be active at least
20 ns before RD or WR. This requirement cannot be met
with the HPC running at 20 MHz clock frequency. In order to
compensate for the propagation delays in the address latches and decoder, 2 inverting buffers (U7), are placed in the
RD control line. The need for these inverters will be discussed further in the following Timing Analysis section. The
WR line does not require this delay compensation.
The DAS’ INT output drives the INT4 input of the HPC. This
allows the DAS to request service when acquired data is
ready or for any other condition for which processor attention is needed. The selection of INT4 is arbitrary, and any
other external interrupt input could have been used. In a real
system, selection of a processor interrupt input will be
based on the number of interrupt driven I/O devices and the
priority for each device.
The DAS’ clock is driven with an 8 MHz crystal clock module. The output of the clock module is separately buffered
for the DAS. This keeps the DAS’ clock clean and minimizes
interference that might be generated and induced by other
devices using the same clock line.
3.3 Timing Analysis
The user should perform a timing analysis along with the
interface hardware design to ensure proper transaction of
information between the processor and the DAS. For example the buffers in the RD input of the DAS in Figure 7 are
necessary to ensure proper timing. Similarly, the clock frequency of the HPC in Figure 8 was reduced to ensure proper timing. For every new circuit design the DAS timing specifications for read and write cycles should be compared with
the HPC (or the processor being used) timing specifications.
Any mismatch between the timing characteristics must be
compensated by hardware design changes or software
techniques.
3.3.1 Complete Address Decoding Circuit
Study of the switching characteristics of the DAS and the
HPC (running at 20 MHz) shows that the read cycle timing is
more stringent than that of the write cycle. The timing diagram (Figure 9 ) shows the timing relationship for the signals
involved in a read cycle. The first three signals are generated by the HPC (ALE, ADD/DATA, RD), and are shown with
their minimum timing relationships. The three other signals
are CS and RD received by the DAS, and DATA(DAS) which
is sent to the HPC. The CS’ longest propagation delay
through the address latch (U3), magnitude comparator (U4),
and 3-to-8 line decoder (U5) starts from the moment an
address becomes valid. This propagation delay is, typically,
54 ns up to worst case of 116 ns.
3.2 Minimal Address Decoding
The circuit in Figure 8 does not use the external address
latches (U2, U3), the 8-bit magnitude comparator (U4), and
the address setting jumpers (JP1). The 3-to-8 line decoder
(U5) is still used and is enabled by the address/data lines
DA9 and DA15. DA9 should be ‘‘1’’ to enable U5. This is
selected to prevent address conflict between the DAS and
the HPC internal RAM and registers, which use the address
range 0000H to 01FFH with DA9 equal to ‘‘0’’. DA15 should
be ‘‘0’’ to enable U5. This is selected to prevent conflict
between the DAS and the HPC internal ROM, which uses
the address range E000H to FFFFH with DA15 equal to ‘‘1’’.
The Y0 output of U5 is still driving the DAS’ CS input. The
ALE output of the HPC directly drives the DAS’ ALE input.
The ALE latches the address and CS lines on the DAS’
internal latches at the start of any data transfer cycle with
the DAS.
Note: Maximum propagation delays for 74HC series logic devices are for
4.5V supply, 50 pF load and b 40§ C to 85§ C temperature range. Typical values are for the same conditions at 25§ C.
This delay, referred to the falling edge of the RD(HPC), is 16
ns to 78 ns. The DAS requires that its RD becomes active
20 ns after its CS. This requirement compels insertion of
delay on the HPC’s RD line before it is received by the DAS.
Referenced to the HPC’s RD signal falling edge the DAS’
should receive a RD signal that is delayed by 36 ns to 98 ns
(16 a 20 ns to 78 a 20 ns). Inverting buffers U7B and U7C
12
all of the HPC’s features are available for use in the application. The HPC Designer’s Kit also closely resembles the real
processor’s switching characteristics.
(75HC540) provide RD signal delay between the HPC and
the DAS. The two buffers’ propagation delay specification is
typically 24 ns and the maximum is 50 ns. This is less than
the 36 ns to 98 ns requirement drawn from the analysis.
However, practical measurements have shown that this delay is sufficient within a temperature range of 0§ C to 50§ C.
This discrepancy results from the fact that the operating
conditions on the specification sheets (loading capacitance,
supply voltage) for the logic devices are more severe than
the ones in the practical circuit. However, if the circuit is to
perform reliably in worst case conditions, extra delay may
be inserted in the RD line.
The second timing requirement is the data setup time referenced to the rising edge of the HPC’s RD line. The DAS
data outputs will be valid from a typical 10 ns to a maximum
of 80 ns after the falling edge of its RD line. The HPC requires 45 ns of setup time and has a RD pulse width of
140 ns (1 wait state), resulting in 95 ns of total delay in the
RD buffers and data latency of the DAS. Again, at the extreme limits of the operating conditions, the valid data might
miss the 45 ns of required setup time, so the insertion of 1
extra wait state (100 ns) in the read cycle of the HPC is
required. The design shown here is an example to demonstrate necessary design considerations and may not be the
best possible solution for every application.
The circuit of Figure 7 was implemented and tested using
the ‘‘HPC Designer’s Kit’’ development system. The development system performs the HPC real time emulation and
Figure 10 shows scope photos of the CS, RD and WR signals from the Figure 7 circuit, using the HPC development
system. Figure 10a shows a read and a write cycle when no
inverter is added in the RD line. There is plenty of setup time
for CS to WR but not for CS to RD. Figure 10b shows a
close look of the CS to RD setup time of Figure 10a . The
setup time is 18 ns (at room temperature), very close to 20
ns, but not enough margin for circuit and temperature variations. Figure 10c shows a close look of the CS and RD
signals after adding the inverters in the RD line. The setup
time has increased to 30 ns with 10 ns of margin to cover
for circuit variations and temperature changes.
3.3.2 Minimal Address Decoding Circuit
Study of the switching characteristics for the circuit of Figure 8 shows that the DAS address and CS setup times to
ALE low are not satisfied when the HPC is running at
20 MHz. The HPC generates a valid address only 18 ns
(min) before its ALE goes low at this speed (see Figure 9 ).
The DAS needs 40 ns of setup time. The solution is reducing the HPC’s clock frequency. The HPC running at 10 MHz
will have a minimum setup time of 43 ns. There is some
extra delay for the DAS’ CS through U5 that must also be
considered. This is the input to output propagation delay of
U5, from the moment that address lines become valid to the
point that the DAS’ CS (Y0 output of U5) goes low.
TL/H/11908 – 11
FIGURE 9. DAS/HPC Interface Timing Diagram (Complete Address Decoding)
13
TL/H/11908–12
TL/H/11908 – 15
a) A Write and a Read Cycle,
No Inverter in RD Line
a) A Read and a Write Cycle with Zero Wait State
TL/H/11908 – 16
TL/H/11908–13
b) A Read Cycle with One Wait State
b) A Close Look at the CS to RD
Setup Time, No Inverter in RD Line
TL/H/11908 – 17
c) A Read Cycle with Zero Wait State
TL/H/11908–14
FIGURE 11. Scope Photos of ALE, CS, RD
and WR Signals at the DAS, Figure 8 Circuit
c) A Close Look at the CS to RD
Setup Time, 2 Inverters in RD Line
FIGURE 10. Scope Photos of CS, RD and
WR Signals at the DAS, Figure 7 Circuit
The circuit of Figure 8 was also implemented and tested
using the HPC development system. Figure 11 shows scope
photos of the ALE, CS, RD and WR signals at the DAS
inputs for the Figure 8 circuit.Figure 11a shows a read and a
write cycle with zero wait states. Notice that the read and
write pulse rising edges occur after the CS signal. This does
not matter since CS is internally latched. Figures 11b and
11c give a more detailed view of the read cycles with 1 and
0 wait states, demonstrating about 180 ns shorter read cycle with no wait states. There is also about 38 ns of CS to
Practical measurements have shown reliable data transfer
between the DAS and the HPC with the HPC running at
11.09 MHz clock at room temperature.
As a result of the HPC’s lower clock frequency, the external
data transfer can be performed with zero wait state, as opposed to the circuit of Figure 7 where 1 wait state is essential. This speeds up the external read and write cycles and is
especially useful when multiple successive reads are performed from the FIFO.
14
Ð Gas flow, F, drops below a minimum limit.
ALE low setup time. This is still about 2 ns less than the
published DAS specifications. Although, practical tests resulted in reliable data transfer, to ensure dependable operation for the extremes of the circuit parameters and temperature variations, designers should use 10 MHz or less clock
frequency for the HPC.
Ð Pressure, P, exceeds a maximum limit.
Figure 12 shows a diagram of a typical measurement arrangement in a semiconductor furnace. A flow sensor measures the gas flow in the furnace chamber’s duct. A pressure sensor measures the pressure in the chamber. Three
temperature sensors measure the furnace temperature at
the middle and each end of the furnace.
The following assumptions are also made for the system:
Ð All the signals from the sensors are conditioned (gain
and offset adjusted) to provide voltage levels within
0V – 2.5V for the DAS inputs.
Ð The output of all signal conditioning circuits are single
ended with respect to analog ground.
Ð The signal at the output of the flow sensor signal conditioner has 600X source impedance.
Ð The DAS reference voltage is 2.5V, i.e., VREF a e 2.5V
and VREFb e AGND.
Ð The circuits in Figure 7 or 8 (either one) is used for the
furnace measurement and monitoring system. The following discussions and the program codes will be valid
for both circuits.
Ð An approximate throughput rate of 50 Hz is desired for
each set of measurement results (a set of results every
20 ms). However, due to the slow varying nature of the
input signals, precisely controlled throughput rate is not
essential for proper system performance.
4.1 System Requirements and Assumptions
To control the operation of the furnace the following five
measurements must be made:
Ð Absolute temperature at T1, with 12-bit resolution.
Ð Relative temperature, T1 to T2, with 12-bit a sign resolution.
Ð Relative temperature, TI to T3, with 12-bit a sign resolution.
Ð Gas flow, F, through the chamber, with 8-bit resolution.
Ð Pressure, P, in the chamber, with 8-bit resolution.
There are three alarm conditions that are also being monitored:
Ð Gas flow, F, exceeds a maximum limit.
4.2 DAS Setup and Register Programming
Based on the system requirements, we can proceed with
the DAS setup and register settings.
The five sensor outputs are assigned to the first five DAS
inputs:
Ð IN0: T1
Ð IN1: T2
Ð IN2: T3
Ð IN3: F
Ð IN4: P
Ð IN5: Not used - Tied to GND
Ð IN6: Not used - Tied to GND
Ð IN7: Not used - Tied to GND
4.0 A SYSTEM EXAMPLE: A SEMICONDUCTOR
FURNACE
In this application example the DAS measures the inputs
from five sensors in a semiconductor furnace. We assume
one of the circuits in Figures 7 or 8 is used as the furnace
data acquisition and control system. The system requirements will be defined and based on these requirements the
DAS programming values for the DAS registers will be specified. A typical assembly routine for the HPC will also be
presented for the DAS initialization and data capture.
Single Ended 0V–2.5V Signals to the DAS Inputs
FIGURE 12. Diagram of a Typical Measurement Arrangement in a Semiconductor Furnace
15
TL/H/11908 – 22
interrupt (from the DAS to the HPC) when a specified
number of results are contained in the FIFO.
Seven DAS instructions are needed for measurement and
limit monitoring. Five perform the conversions and two perform the ‘‘watchdog’’ function for comparison of ‘‘F’’ and
‘‘P’’ against programmed limits. Note that the variable ‘‘F’’
needs only 1 instruction to monitor both high and low limits.
The following procedures are assumed for system operations:
Ð The seven instructions are executed in sequence from 0
to 6 with zero delay between them.
Ð After execution of instruction Ý6 the DAS loops back to
instruction Ý0 and continues. Each loop is called an instruction loop.
Ð A delay is added, using the Timer register, before instruction Ý0 to provide 50 Hz throughput rate.
Ð Each instruction loop generates 5 conversion results.
The FIFO is filled with 30 (6 sets of 5) results and is then
read by the microcontroller. This is done by having an
Ð Conversion will not be stopped during FIFO reads.
Reads are performed during last comparison instruction
(Ý6) and during the delay before instruction Ý0. The
reads add extra delay after each six instruction loop, but
the amount of the delay is negligible compared to the
20 ms loop duration. (See Section 2.3 for a discussion
on reading during conversion and the interruption of the
internal clock during reads and writes.)
The input from the flow sensor has a 600X source impedance, so it requires additional acquisition time. Referring to
the equation in the DAS data sheet, for the 8-bit and
‘‘watchdog’’ mode, the acquisition time value (D) programmed in bits D12 through D15 of the Instruction register
should be equal to 2 (D e 0.36 c Rs(kX) c fclk(MHz) e 0.36 c
0.6 c 8 e 1.73).
Now the contents of the DAS registers can be specified.
INSTRUCTION REGISTER:
Ð Sync and Pause bits are not used.
Instruction Register definition:
D15
D14
D13
D12
Acquisition Time
D11
D10
D9
D8
W-dog
8/12
Timer
Sync
D7
D6
D5
D4
VINb
D3
D2
VIN a
D1
D0
Paus.
Loop
Instruction Ý0: Measuring T1, Single Ended, 12-Bit, Timer enabled
VIN a e IN0 (T1), VINb e AGND
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Instruction Ý1: Measuring T1–T2, Differential mode, 12-Bit a sign
VIN a e IN0 (T1), VINb e IN1 (T2)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Instruction Ý2: Measuring T1–T3, Differential mode, 12-Bit a sign
VIN a e IN0 (T1), VINb e IN2 (T3)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Instruction Ý3: Measuring F, Single Ended, 8-Bit, D e 2
VIN a e IN3 (F), VINb e AGND
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
1
0
0
0
0
0
0
1
1
0
0
Instruction Ý4: Watchdog mode, F, Single Ended, D e 2
VIN a e IN3 (F),
VINb e AGND
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
0
0
0
0
0
0
0
1
1
0
0
Instruction Ý5: Measuring P, Single Ended, 8-Bit
VIN a e IN4 (P), VINb e AGND
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
Instruction Ý6: Watchdog mode, P, Single Ended, Loop bit enabled
VIN a e IN4 (P), VINb e AGND
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
Instruction Ý7: Not Used
16
Instructions Ý4 and Ý6 also have limit values. Instruction Ý4 has two limit values and instruction Ý6 has only one limit value.
These values are referred to as FÐMIN, FÐMAX, PÐMAX.
Instruction RAM, Limits definition:
D15
D14
D13
D12
D11
D10
Don’t Care
D9
D8
l/k
Sign
D7
D6
D5
D4
D3
D2
D1
D0
D3
D2
D1
D0
D2
D1
D0
D2
D1
D0
Limit
Instruction Ý4, Limit Ý1
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
1
0
D7
D6
D5
D4
FÐMAX
Instruction Ý4, Limit Ý2
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
FÐMIN
Instruction Ý6, Limit Ý1
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
1
0
D7
D6
D5
D4
D3
PÐMAX
Instruction Ý6, Limit Ý2, Limit value equal negative full-scale to prevent false interrupts.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
0
0
0
1
0
1
0
1
INTERRUPT ENABLE REGISTER:
Ð INT0: Comparison Limit:
Enable
Ð INT1: Instruction Number:
Disable
Ð INT2: FIFO Full:
Enable
Ð INT3: Auto Zero Complete:
Disable
Ð INT4: Calibration Complete:
Enable
Ð INT5: Pause:
Disable
Ð INT6: Low Supply:
Disable
Ð INT7: Standby Return:
Disable
Ð Programmed instruction number: 0, Not used
Ð Programmed number of results in FIFO: 30 (11110 binary)
Interrupt Enable Register
D15
D14
D13
D12
D11
Number of results in FIFO
1
1
1
1
D10
D9
D8
Instruction Number
0
0
0
0
17
CONFIGURATION REGISTER:
Ð No auto zero or calibration before each conversion.
Ð Instruction number on bits D13 to D15 of the conversion results.
Ð Sync bit is not used and can be programmed as either input or output.
Configuration Register, Start Conversion Command
D15
D14
D13
D12
Don’t Care
0
0
0
0
D11
D10
Diag.
Test
0
0
D9
D8
RAM
Pointer
0
D7
D6
D5
D4
D3
D2
D1
D0
Sync
I/O
A/Z
Each
Chan
Mask
Standby
Full
Cal
Auto
Zero
Reset
Start
0
0
0
0
0
0
0
1
0
Configuration Register, Reset Command
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Configuration Register, Full Calibration Command
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Configuration Register, RAM bank 1 Selection Command (Conversion is stopped)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Configuration Register, stopping the Conversion Command
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIMER REGISTER:
To calculate the timer preset value, we must first calculate the total instruction execution time. The following table shows the
number of clock cycles for each instruction. Please see datasheet, Section 4.0 (Sequencer), for the discussion of the states and
their duration.
State 5
Number
of Clock
Cycles
9
44
55
1
9
44
55
1
9
44
55
1
1
2
21
25
4
1
1
2
5
15
5
1
1
6
21
29
6
1
1
6
Instruction
State 0
State 1
State 7
0
1
1
1
1
2
1
3
Ý
State 6
State 4
5
1
5
1
5
Total:
18
19
253
Read:
There is a total of 253 clock cycles required for instruction
execution. The Timer delay includes a fixed 2 clock cycles
that must be added to 253, resulting in
MOV DPTR,ÝDAS REG ADD
MOVX A,@DPTR
MOV [destination],A
INC DPTR
MOVX A,@DPTR
The above examples assume 16-bit addressing, however
registers R0 or R1 of the 8051 can be used in place of
DPTR for 8-bit addressing.
The 68HC11 family can access external memory mapped
I/O directly. The data should be preloaded to the accumulator for writes and the accumulator is the destination for
reads. Although, the 68HC11 is an 8-bit processor, it has
16-bit data transfer instructions that uses a double accumulator (A a B, called D) and performs 2 transfer cycles using
a single instruction. The basic instructions are ‘‘LDD’’ (load
double accumulator) and ‘‘STD’’ (store double accumulator).
Write:
ÝDAS DATA
LDD
STD
DAS REG ADD
Read:
LDD
DAS REG ADD
253 a 2 e 255 clock cycles.
The total time for 255 clock cycles would be:
255 c (/8 MHz e 31.875 ms.
This time must be subtracted from 20 ms to get the Timer
delay.
20 ms b 31.875 ms e 19.968 ms.
A Timer count is 32 clock cycles, with an 8 MHz clock
(125 ns period), each Timer count is
32 c 125 ns e 4 ms.
The timer preset value is then
19.968 ms d 4 ms e 4992,
with a hex value of 1380H.
Once the required contents of the DAS registers have been
determined, the next step is to program the processor to
interact with the DAS.
4.3 Microcontroller Programming
Interaction between a microcontroller and the DAS is basically accomplished by read and write operations, the microcontroller’s external data transfer instructions are used for
communications with the DAS.
A write operation to the DAS needs 2 variables: The DAS
register address and the data to be written. A read operation
from the DAS needs only the register address. The DAS
register address and data will be referred to as DASÐ
REGÐADD and DASÐDATA in the following examples.
Examples of assembly mnemonics for the DAS read and
write operations are presented below for the HPC, 8051,
and 68HC11 microcontroller families:
The HPC family can directly write 16-bit data to a memorymapped I/O. Its main data transfer instruction is ‘‘LD’’
(load). Each read or write is only one instruction.
Write:
LD
DAS REG ADD,ÝDAS DATA
Read:
[destination],DAS REG ADD
LD
The 8051 family accesses an external memory-mapped I/O
indirectly through the DPTR (data pointer) register. The data
should be preloaded to the accumulator for writes and the
accumulator is the destination for reads. The transfer is 8-bit
and two cycles are needed for 16 bits of data. The basic
instruction are ‘‘MOV’’ (move), ‘‘MOVX’’ (move external) and
‘‘INC’’ (increment).
Write:
MOV
DPTR,ÝDAS REG ADD
MOV
A,DAS DATA(low byte)
MOVX @DPTR,A
INC
DPTR
MOV
A,DAS DATA(high byte)
MOVX @DPTR,A
4.3.1 HPC Assembly Routines for the Semiconductor
Furnace Example
The program listing in Figure 13 is the HPC assembly routine for the semiconductor furnace application example. The
program contains only the DAS initialization and the DAS
interrupt service routine. A complete program for the application will have all the data manipulation and control functions, which are not discussed here.
The routines closely follow the procedure in the flowcharts
of Figure 2 and are extensively commented to be self-explanatory. The routines also separated according to the
flowchart sections. The main difference between the routines and the flowchart is that the DAS is not stopped at the
start of the interrupt service routine.
The interrupt service routine uses the IFBIT (if bit is true)
instruction to test for the state of the interrupt status bits.
This is very handy for control applications.
The READÐFIFO routine reads the FIFO contents and
stores them to a specified block of memory starting at the
location called DASÐRESULT. The size of the block and,
consequently, the number of FIFO locations being read is
programmable (30 locations on the listing). The routine is
only 5 lines of assembly. It uses the multi-function ‘‘XS’’
(exchange and skip) instruction to perform the data transfer,
address increment or decrement, and a compare for decision making. The first LD instruction in the READÐFIFO
routine loads the HPC’s B and K registers with the starting
address and the ending address of the memory block. The
second instruction reads a word (16-bit) from the FIFO to
‘‘A’’ (accumulator). The XS instruction stores A in the memory location pointed to by B, increments B by 2 (for 2 bytes)
and then compares B with K to test for the end of the memory block. If the end of the block has not been reached, the
program jumps back to load the next word from the FIFO,
otherwise the program skips the ‘‘JP’’ (jump) instruction and
returns from the service routine.
19
TL/H/11908 – 18
FIGURE 13. HPC Assembly Program Listing (Continued)
20
TL/H/11908 – 19
FIGURE 13. HPC Assembly Program Listing (Continued)
21
TL/H/11908 – 20
FIGURE 13. HPC Assembly Program Listing
22
APPENDIX A: Registers Bit Assignments and Programmer’s Notes
CONFIGURATION REGISTER (Read/Write):
D15
D14
D13
D12
Don’t Care
D0:
D1:
D2:
D3:
D4:
D5:
D6:
D7:
D9 – D8:
D10:
D11:
D15 – D12:
D11
D10
Diag.
Test
D9
D8
RAM
Pointer
D7
D6
D5
D4
D3
D2
D1
D0
Sync
I/O
A/Z
Each
Chan
Mask
Standby
Full
Cal
Auto
Zero
Reset
Start
- Start: 0 e Stops the instruction execution. 1 e Starts the instruction execution
- Reset: When set to 1, resets the Start bit, also resets all the bits is status registers and resets the
instruction pointer to zero, will automatically reset itself to zero after 2 clock pulses
- Auto-Zero: When set to 1 a long auto-zero calibration cycle is performed
- Full Calibration: When set to 1 a full calibration cycle is performed
- Standby: When set to 1 the chip goes to low-power standby mode, resetting the bit will return the chip to
active mode after a power-up delay
- Channel Mask: 0 e Bits 13 to 15 of the conversion result hold the instruction number to which the result belongs,
1 e Bits 13 to 15 of the result hold the extended sign bit
- A/Z Each: When set to 1 a short auto-zero cycle if performed before each conversion
- Sync I/O: 0 e Sync pin is input, 1 e Sync pin is output
- RAM Pointer: Selects the sections of the instruction RAM, 00 e Instructions, 01 e Limits Ý1, 10 e Limits Ý2
- This bit is used for production testing, must be kept zero for normal operation
- Diagnostic: When set to 1 perform diagnostic conversion along with a properly selected instruction
- Don’t care
PROGRAMMER’S NOTES:
Configuration Registers: Address:
Note:
D15
D14
D13
D12
Symbol:
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Hexadecimal value:
Configuration Register: Address:
Note:
D15
D14
D13
D12
Symbol:
D11
D10
D9
D8
Hexadecimal value:
Configuration Register: Address:
Note:
D15
D14
D13
D12
Symbol:
D11
D10
D9
D8
Hexadecimal value:
23
APPENDIX A: Registers Bit Assignments and Programmer’s Notes
INSTRUCTION RAM (Read/Write): (Continued)
Instruction:
D15
D14
D13
D12
Acquisition Time
D0:
D1:
D11
D10
D9
D8
W-dog
8/12
Timer
Sync
D7
D6
D5
D4
VIN b
D3
D2
VIN a
D1
D0
Paus.
Loop
- Loop: 0 e Go to next instruction, 1 e Loop back to instruction Ý0
- Pause: 0 e No pause, 1 e Pause, don’t do the instruction, Start bit in configuration register resets to 0 when a
pause encountered, a 1 written to Start bit restarts the instruction execution
- VIN a : Selects which input channel is connected to A/D’s non-inverting input
D4 – D2:
D7 – D5:
D8:
- VINb: Selects which input channel is connected to A/D’s inverting input
- Sync: 0 e Normal operation, internal timing, 1 e S/H and conversion (comparison) timing, is controlled by SYNC
input pin
- Timer: 0 e No timer operation, 1 e Instruction execution halts until timer counts down to zero
D9:
D10:
D11:
D15 – D12:
- 8/12: 0 e 12-bit a sign resolution, 1 e 8-bit a sign resolution
- Watchdog: 0 e No watchdog comparision, 1 e Instruction performs watchdog comparisons
- Acquisition Time: Determines S/H acquisition time
For 12-bit a sign: (9 a 2D) clock cycles, For 8-bit a sign: (2 a 2D) clock cycles
D e Content of D15–D12, RS e Input source resistance
For 12-bit a sign: D e 0.45 x RS [kX] x fCLK [MHz]
For 8-bit a sign: D e 0.36 x RS [kX] x fCLK [MHz]
PROGRAMMER’S NOTES:
Instruction Ý 0: Address:
Note:
D15
D14
D13
Symbol:
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hexadecimal value:
Instruction Ý 1: Address:
Note:
D15
D14
D13
Symbol:
D12
D11
D10
Hexadecimal value:
Instruction Ý 2: Address:
Note:
D15
D14
D13
Symbol:
D12
D11
D10
Hexadecimal value:
Instruction Ý3: Address:
Note:
D15
D14
D13
Symbol:
D12
D11
D10
Hexadecimal value:
24
APPENDIX A: Registers Bit Assignments and Programmer’s Notes
INSTRUCTION RAM (Read/Write): (Continued)
PROGRAMMER’S NOTES:
Instruction Ý 4: Address:
Note:
D15
D14
D13
Symbol:
D12
D11
Hexadecimal value:
Instruction Ý 5: Address:
Note:
D15
D14
D13
D14
D13
D12
D11
D14
D13
D8
D7
D6
D5
D4
D3
D2
D1
D0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Symbol:
D12
D11
Hexadecimal value:
Instruction Ý 7: Address:
Note:
D15
D9
Symbol:
Hexadecimal value:
Instruction Ý 6: Address:
Note:
D15
D10
D10
Symbol:
D12
D11
D10
Hexadecimal value:
25
APPENDIX A: Registers Bit Assignments and Programmer’s Notes
INSTRUCTION RAM (Read/Write): (Continued)
Limits Ý 1
D15
D14
D13
D12
D11
D10
Don’t Care
D9
D8
l/k
Sign
D7
D6
D5
D4
D3
D2
D1
D0
Limit
D7 – D0:
D8:
D9:
- Limit: 8-bit limit value
- Sign: Sign bit for limit value, 0 e Positive, 1 e Negative
- l/k: High or low limit determination, 0 e Inputs lower than limit generate interrupt, 1 e Inputs higher than limit
generate interrupt
D15 – D10 - Don’t Care
PROGRAMMER’S NOTES:
Instruction Ý 0, Limit Ý 1: Address:
Symbol:
Note:
D15
D14
D13
D12
D11
D10
Hexadecimal value:
Instruction Ý 1, Limit Ý 1: Address:
Note:
D15
D14
D13
D12
D14
D13
D12
D11
D10
D14
D13
D12
D11
D10
D14
D13
D12
D11
D10
D14
D13
D12
D11
D10
D14
D13
D12
D11
D10
D14
D13
D12
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Symbol:
D11
D10
Hexadecimal value:
Instruction Ý 7, Limit Ý 1: Address:
Note:
D15
D4
Symbol:
Hexadecimal value:
Instruction Ý 6, Limit Ý 1: Address:
Note:
D15
D5
Symbol:
Hexadecimal value:
Instruction Ý 5, Limit Ý 1: Address:
Note:
D15
D6
Symbol:
Hexadecimal value:
Instruction Ý 4, Limit Ý 1: Address:
Note:
D15
D7
Symbol:
Hexadecimal value:
Instruction Ý 3, Limit Ý 1: Address:
Note:
D15
D8
Symbol:
Hexadecimal value:
Instruction Ý 2, Limit Ý 1: Address:
Note:
D15
D9
D9
D8
Symbol:
D11
D10
D9
D8
Hexadecimal value:
26
APPENDIX A
INSTRUCTION RAM (Read/Write): (Continued)
Limits Ý2
D15
D14
D13
D12
D11
D10
Don’t Care
D7 – D0:
D8:
D9:
D15 – D10
D9
D8
l/k
Sign
D7
D6
D5
D4
D3
D2
D1
D0
Limit
- Limit: 8-bit limit value
- Sign: Sign bit for limit value, 0 e Positive, 1 e Negative
- l/k: High or low limit determination, 0 e Inputs lower than limit generate interrupt, 1 e Inputs higher than limit
generate interrupt
- Don’t Care
PROGRAMMER’S NOTES:
Instruction Ý 0, Limit Ý 2: Address:
Note:
D15
D14
D13
D12
Symbol:
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hexadecimal value:
Instruction Ý 1, Limit Ý 2: Address:
Note:
D15
D14
D13
D12
Symbol:
D11
D10
D9
Hexadecimal value:
Instruction Ý 2, Limit Ý 2: Address:
Note:
D15
D14
D13
D12
Symbol:
D11
D10
D9
Hexadecimal value:
Instruction Ý 3, Limit Ý 2: Address:
Note:
D15
D14
D13
D12
Symbol:
D11
D10
D9
Hexadecimal value:
Instruction Ý 4, Limit Ý 2: Address:
Note:
D15
D14
D13
D12
Symbol:
D11
D10
D9
Hexadecimal value:
Instruction Ý 5, Limit Ý 2: Address:
Note:
D15
D14
D13
D12
Symbol:
D11
D10
D9
Hexadecimal value:
Instruction Ý 6, Limit Ý 2: Address:
Note:
D15
D14
D13
D12
Symbol:
D11
D10
D9
Hexadecimal value:
Instruction Ý 7, Limit Ý 2: Address:
Note:
D15
D14
D13
D12
Symbol:
D11
D10
D9
Hexadecimal value:
27
APPENDIX A: Registers Bit Assignments and Programmer’s Notes
INTERRUPT ENABLE REGISTER (Read/Write):
D15
D14
D13
D12
D11
D10
Number of results in FIFO to
Generate Interrupt (INT2)
D9
D8
Instruction Number
to Generate Interrupt
(INT1)
D7
D6
D5
D4
D3
D2
D1
D0
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
Bits Ý 0 to 7 enable interrupt generaton for the following conditions when the bit is set to 1.
D0:
- INT0: Generates interrupt when a limit is passed in watchdog mode
D1:
- INT1: Generates interrupt when the programmed instruction (D10 – D8) is reached for execution
D2:
- INT2: Generates interrupt when number of conversion results in FIFO is equal to the programmed
value (D15–D11)
D3:
- INT3: Generates interrupt when an auto-zero cycle is completed
D4:
- INT4: Generates interrupt when a full calibration cycle is completed
D5:
- INT5: Generates interrupt when a pause condition is encountered
D6:
- INT6: Generates interrupt when low power supply is detected
D7:
- INT7: Generates interrupt when the chip is returned from standby and is ready
D10 – D8:
- Programmable instruction number to generate an interrupt when that instruction is reached foR execution
D15 – D11: - Programmable number of conversion results in the FIFO to generate an interrupt
PROGRAMMER’s NOTES:
Interrupt Enable Register: Address:
Note:
D15
D14
D13
D12
D11
Symbol:
D10
D9
Hexadecimal value:
Interrupt Enable Register: Address:
Note:
D15
D14
D13
D12
D8
D7
D6
D5
D4
D3
D2
D1
D0
Symbol:
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hexadecimal value:
TIMER REGISTER (Read/Write):
D15
D14
D13
D12
N e Timer Preset Value
Timer delays the execution of an instruction if Timer bit is set in the instruction.
The time delay in number of clock cycles is:
Delay e 32 x N a 2 [Clock Cycles]
PROGRAMMER’s NOTES:
Timer Register: Address:
Note:
D15
D14
D13
Symbol
D12
D11
D10
D9
Hexadecimal value:
Timer Register: Address:
Note:
D15
D14
D13
D8
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Symbol:
D12
D11
D10
D9
D8
Hexadecimal value:
28
APPENDIX A: Registers Bit Assignments and Programmer’s Notes
FIFO REGISTER (Read only):
D15
D14
D13
D12
Instruction Number
or Extended Sign
D11 – D0:
D12:
D15 – D13:
D11
D10
D9
D8
D7
Sign
D6
D5
D4
D3
D2
D1
D0
Conversion Result
- Conversion Result:
For 12-bit a sign: 12-bit result value
For 8-bit a sign: D11–D4 e result value, D3 – D0 e 1110
- Sign: Conversion result sign bit, 0 e Positive, 1 e Negative
- Instruction number associated with the conversion result or the extended sign bit for 2’s complement
arithmetic, selected by bit D5 (Chan Mask) of Configuration Register
PROGRAMMER’S NOTES:
FIFO Register: Address:
Note:
Symbol:
INTERRUPT STATUS REGISTER (Read only):
D15
D14
D13
D12
D11
Number of results in FIFO
D10
D9
D8
Instruction Number
Being executed
D7
D6
D5
D4
D3
D2
D1
D0
INST7
INST6
INST5
INST4
INST3
INST2
INST1
INST0
BITS Ý 0 to 7 are interrupt flags (vectors) that will be set to 1 when the following conditions occur. The bits set to 1 whether
the interrupt is enabled or disabled in the Interrupt Enable register. The bits reset to 0 when the register is read, or by a
device reset through Configuration register.
D0:
- INST0: Is set to 1 when a limit is passed in watchdog mode
D1:
- INST1: Is set to 1 when the programmed instruction (D10 – D8) is reached for execution
D2:
- INST2: Is set to 1 when number of conversion results in FIFO is equal to the programmed value (D15 – D11)
D3:
- INST3: Is set to 1 when an auto-zero cycle is completed
D4:
- INST4: Is set to 1 when a full calibration cycle is completed
D5:
- INST5: Is set to 1 when a pause condition is encountered
D6:
- INST6: Is set to 1 when low power supply is detected
D7:
- INST7: Is set to 1 when the chip is returned from standby and is ready
D10 – D8: - Holds the instruction number being executed or will be executed during a Pause or Timer delay
D15 – D11: - Holds the present number of conversion results in the FIFO while the device is running
PROGRAMMER’S NOTES:
Interrupt Status Register: Address:
Note:
Symbol:
29
Interfacing the LM12454/8 Data Acquisition System Chips
to Microprocessors and Microcontrollers
APPENDIX A: Registers Bit Assignments and Programmer’s Notes
LIMIT STATUS REGISTER (Read only):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
Limits Ý2: Status
D4
D3
D2
D1
D0
Limits Ý1: Status
The bits in this register are limit flags (vectors) that will be set to 1 when a limit is passed. The bits are associated to
individual instruction limits as indicated below.
D0: - Limit Ý 1 of Instruction Ý 0 is passed
D1:
D2:
D3:
D4:
D5:
D6:
D7:
D8:
D9:
D10:
D11:
-
Limit
Limit
Limit
Limit
Limit
Limit
Limit
Limit
Limit
Limit
Limit
Ý 1 of Instruction Ý 1 is passed
D12:
D13:
D14:
D15:
-
Limit
Limit
Limit
Limit
Ý 2 of Instruction Ý 4 is passed
Ý 1 of Instruction Ý 2 is passed
Ý 1 of Instruction Ý 3 is passed
Ý 1 of Instruction Ý 4 is passed
Ý 1 of Instruction Ý 5 is passed
Ý 1 of Instruction Ý 6 is passed
Ý 1 of Instruction Ý 7 is passed
Ý 2 of Instruction Ý 0 is passed
Ý 2 of Instruction Ý 1 is passed
Ý 2 of Instruction Ý 2 is passed
Ý 2 of Instruction Ý 3 is passed
Ý 2 of Instruction Ý 5 is passed
Ý 2 of Instruction Ý 6 is passed
Ý 2 of Instruction Ý 7 is passed
PROGRAMMER’S NOTES:
Limit Status Register: Address
Note:
Symbol:
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