Texas Instruments | Using the ADS1202 Reference Design | Application notes | Texas Instruments Using the ADS1202 Reference Design Application notes

Texas Instruments Using the ADS1202 Reference Design Application notes
Application Report
SLAA186 – November 2003
Using the ADS1202 Reference Design
Data Acquisition Products
Tom Hendrick, Miroslav Oljaca
ABSTRACT
This application report describes the characteristics, operation, and use of the ADS1202
reference design. It includes two isolated ADS1202 circuits for a variety of applications
and a Sinc3 filter implemented in a Xilinx® XC2S150 field-programmable gate array
(FPGA). Optional optocouplers provide additional isolation. A complete circuit description
and schematic diagram are included.
Related Documentation from Texas Instruments
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Response Center at (800) 477-8924 or the Product Information Center (PIC) at (972) 644-5580.
When ordering, please identify this booklet by its title and literature number. Updated
documents can also be obtained through our website at www.ti.com.
Data Sheets:
ADS1202
TPS70358
Users Guides:
5-6K Interface Card
Application Notes:
ADS1202 Traffo
ADS1202 Opto Selection
ADS1202 Digital Filter
Clock Divider Circuit
Literature Number:
SBAS275
SLVS285
Literature Number:
SLAU104
Literature Number:
SBAA096
SBAA088
SBAA094
SBAA105
Xilinx is a registered trademark of Xilinx, Inc.
1
SLAA186
Application Overview
Features
•
Xilinx 150,000 Gate Spartan II FPGA – XC2S150
•
Two analog channels, with independent ADS1202 circuits
•
JTAG interface, ISP capable
•
SPI or McBSP operation
Introduction
The ADS1202 reference design provides two isolated ADS1202 circuits for a variety of
applications. It includes a Sinc3 filter implemented in a Xilinx XC2S150 FPGA. Optional
optocouplers can be used to provide electrical isolation.
The modular form factor of the reference design allows direct evaluation of ADS1202
performance and operating characteristics. This reference design is compatible with the 5-6K
interface board from Texas Instruments. See the 5-6K Interface Board User’s Guide (literature
number SLAU104) for more information.
Analog Interface
The ADS1202 reference design easily interfaces to multiple analog sources. Two-position screw
terminals J11 and J12 provide convenient access to the ADS1202 input pins. Each channel has
socketed components to easily implement input-filter options.
Each analog channel is electrically isolated for high-voltage applications when used with optional
optocouplers. Two-position screw terminals J13 and J16 provide convenient individual access
to each ADS1202 power connection.
Digital Interface
The ADS1202 reference design easily interfaces to multiple control platforms. Samtec part
numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient ten-pin dualrow header/socket combination at J2 and J8. This header/socket provides access to the digital
control and serial data pins of the ADS1202 reference design. The signals and pin assignments
are given in Table 1.
2
Using the ADS1202 Reference Design
SLAA186
Table 1.
Pin Number
Digital-Interface Connector
Signal
J2.1
J8.1
Unused
J2.3
J8.3
SCLK
J2.5
J8.5
CLKR
J2.7
J8.7
/SS
J2.9
J8.9
FS(R)
J2.11
J8.11
Unused
J2.13
J8.13
SDO
J2.15
J8.15
Unused
J2.17
J8.17
Unused
J2.19
J8.19
SPARE
Description
Serial clock; used in SPI mode
Serial clock; used in McBSP mode
Slave select; used in SPI mode
Frame sync; used in McBSP mode
Serial data output from FPGA (Sinc3 filter output)
Power Supplies
The ADS1202 reference design board requires separate 5-V dc supplies for each ADS1202
circuit and for the digital section. When used in combination with the 5-6K interface board, J17
(located on the bottom side of the board) provides connection to the common power bus
described in the 5-6K Interface Board User’s Guide (literature number SLAU104) for use with
the digital portion of the board. U1 provides 3.3 V and 2.5 V for the FPGA and optional
optocoupler circuits. The analog sections must be powered through J13 and J16.
When the reference design is used as a stand-alone module, the 5-V digital power is applied to
J1. Although filters are provided for all power supply inputs, optimal performance of the board
requires a clean, well-regulated power source.
Reference Design Operation
Analog input sources connect directly to J14 and J15. Note the polarity on the silkscreen for
proper signal connections. Two-pin headers J11 and J12 provide grounding options to the (–)
input of the ADS1202 device. Closing the jumper shorts the (–) input to ground through R24 and
R27 (refer to the schematic for additional details).
Digital control signals can be applied directly to J2 and J8 (top or bottom side). The ADS1202
reference design can also be connected directly to a DSP interface board. Connector J6 is
provided for mechanical stability only. No signals are applied to this connector.
The four-position dipswitch S2 selects decimation ratios and selects between McBSP or SPI
operation. When an S2 switch is in the ON position, a logic level 0 is applied to the respective
FPGA input pin.
Switch 2 position 1 selects the operating mode.
The ON position selects SPI mode. In this case, a burst clock is applied to the host processor,
and the host processor is to be set as an SPI slave device with CPOL = 0 and CPHA = 0.
Using the ADS1202 Reference Design
3
SLAA186
The OFF position selects McBSP mode and a continuous clock is applied to the host processor.
A frame sync pulse is provided via FSR to the DSP in this mode. The McBSP port must be set
to accept an active high FS with 0-bit data delay. In either mode, a periodic burst of eight 16-bit
words is supplied to the host, and the data rate depends on the decimation ratio.
Switch 2 positions 2, 3, and 4 select the decimation ratio. Table 2 describes the settings.
Table 2.
Decimation-Ratio Switch Settings
Switch 2 Position (ON = 0)
Decimation Ratio - Effective Resolution
2
3
4
0
0
0
4–6 bits
0
0
1
8–9 bits
0
1
0
16–12 bits
0
1
1
32–15 bits
1
0
0
64–18 bits
1
0
1
128–21 bits
1
1
0
256–24 bits
A 20-MHz crystal is supplied at position U3. This crystal can be replaced with a lower frequency
crystal to provide alternate clocks to the ADS1202. As configured, the ADS1202 reference
design is set for Mode 3 operation. The VHDL code for the FPGA can be modified for alternate
modes of operation. Jumpers J18 through J21 control the operating mode of the installed
ADS1202 devices. Opening the jumper applies a logic 1 on the ADS1202 mode pins. The clockconfiguration modes are described in Table 3.
Table 3.
Jumper
4
Clock Configuration
Description
J19/J21
J18/J20
Closed
Closed
Mode 0 operation; processor reads MDAT on rising clock edge only
Mode 1 operation; processor reads MDAT on every clock edge
Open
Closed
Closed
Open
Mode 2 operation; Manchester decoding required
Open
Open
Mode 3 operation; requires external clock (default condition)
Using the ADS1202 Reference Design
SLAA186
ADS1202 Reference Design Schematic and BOM
Table 4 provides the ADS1202 reference design bill of materials. The PC-board layers are
shown in Figure 1. The schematic for the ADS1202 reference design is included at the end of
this document. The Gerber files and VHDL code are available for download from the Texas
Instruments web site at www.ti.com. Use the keyword search and follow the links for document
number SLAA186.
Table 4.
Bill of Materials
Designator
C1 C17 C18
C2
C6
C3 C8 C9 C10 C11 C15
C19 C20 C21
C4 C5
C28 C29 C30 C31 C32 C33
C34 C35 C36 C37 C38 C39
C40 C41 C42 C43 C44
C14 C16
C22 C23 C24 C25 C26 C27
D1
J1 J13 J14 J15 J16
Description
TANT 100 µF 20V 10% RAD
TANT 47 µF 10V 20% SMD
TANT 22 µF 10V 20% SMD
0.1uF, 1206, ceramic, X7R, 50V, 10%
Manufacturer
AVX
Kemet
Kemet
Panasonic
Mfg. Part Number
TAP107K020CCS
T491B476M010AS
T491B226M010AS
ECJ-3VB1H104K
20VDC .22 µF TES-series SMD
0.1 µF, 0805, ceramic, X7R, 50V, 10%
Panasonic
Panasonic
ECS-T1DP224R
ECJ-2YB1H104K
J2 J6 J8 (top side)
J2 J6 J8 (bottom side)
J3
J5 J6 J7
J9
J10 J11 J12 J18 J19 J20
J21
J17 (bottom side)
L1
R1
R2
R3 R4 R5 R6 R7 R8 R9
R10 R28 R29 R30 R31
R11 R12 R13
R15
R16 R17 R18 R19
R20 R21 R22 R23
R24 R25 R26 R27
S1 S2
SW1
U1
U2
U3
U4
U5 U6
U7 U8
Various
Various
10-pin, dual-row, SMT header (20 Pos.)
10-pin, dual-row, SMT socket (20 Pos.)
6-pin , .1” header
3-pin , .1” header
8-pin , .1” header
2-pin , .1” header
EXC-EMT/EMI filter 2200 pF
CK05-style ceramic, radial, value TBD
1206-size SMT LED, amber
2-terminal screw connector
Panasonic
EXC-EMT222DT
Various
Various
Chicago Miniature
7010X7
Off Shore
ED1514
Technologies
Samtec
TSM-110-01-T-DV-P
Samtec
SSW-110-22-F-D-VS-K
Samtec
TSW-106-07-L-S
Samtec
TSW-103-07-L-S
Samtec
TSW-108-07-L-S
Samtec
TSW-102-07-L-S
5-pin, dual-row, SMT socket (10 pos.)
EMI filter
1206-size, 5%, 3.3 KΩ
1206-size, 5%, 560 Ω
0805-size, 5%, 10 KΩ
Samtec
Murata
Yageo America
Yageo America
Yageo America
SSW-105-22-F-D-VS-K
BNX002-01
9C12063A3301JLHFT
9C12063A5600JLHFT
9C08052A1002JLHFT
0805-size, 5%, 4.7 KΩ
0805-size, 5%, 0.0 Ω
1206-size, 5%, 330 Ω
0805-size, 5%, 470 Ω
1/4W axial lead, value TBD
Switch, DIP, half-pitch, 4-position
Switch, momentary pushbutton, NO
TPS70358
XC2S100
20-MHz, half-size oscillator
SRL CONFIG EEPROM 1M
Wire shunts, 2 ea., pins 2-7 and pins 3-6
ADS1202
Red test-point loop
Black test-point loop
Yageo America
Yageo America
Yageo America
Yageo America
Various
CTS
Panasonic
TI
Xilinx
CTS
Atmel
NA
TI
Keystone
Keystone
9C08052A4701JLHFT
9C08052A0R00JLHFT
9C12063A3300JLHFT
9C12063A4700JLHFT
Various
218-4LPST
EVQ-PJ
TPS70358PWP
XC2S100-5TQ144C
MXO45HS-20.0000
AT17LV010-10PC
NA
ADS1202IPWT
5000
5001
Using the ADS1202 Reference Design
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SLAA186
Figure 1.
6
Using the ADS1202 Reference Design
PC Board Layers and Silkscreens
1
2
3
4
5
6
Revision History
REV
+3.3V
R6
10K
R3
10K
8
7
6
5
+3.3V +3.3V +3.3V
+3.3V
+3.3V
+3.3V
35
16
18
19
20
22
23
26
27
29
21
28
30
31
5
12
3
4
6
7
10
11
13
15
1
DIPSWITCH-4
+2.5V
R11
4K7
TP11
TP13
TP8
TP10
TP12
108
+3.3V
+3.3V
J4
+3.3V
J5
+3.3V
J7
1
2
3
1
2
3
M0
M1
M2
/PROG
DONE
69
72
105
104
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCO
VCCO
I/O (D4) (500)
I/O (D5) (479)
I/O (D6) (476)
I/O (D7) (446)
I/O (INIT) (443)
I/O (506)
I/O (482)
I/O (473)
I/O (470)
I/O (452)
I/O, TRDY (512)
I/O, VREF (497)
I/O, VREF (461)
VCCO
M0 (291)
M1 (290)
M2 (292)
PROGRAM (442)
DONE (439)
PWDN
STATUS
107
143
135
128
119
110
98
89
81
73
61
52
45
33
25
17
8
B
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
2
3
109
111
106
M0
M1
M2
XC2S50-5TQ144C
I/O (224)
I/O (230)
I/O (248)
I/O (251)
I/O (254)
I/O (257)
I/O (260)
I/O (278)
I/O (284)
I/O (287)
I/O, TRDY (218)
I/O, VREF (233)
I/O, VREF (269)
+3.3V
+3.3V
C9
0.1uF
8
4
U3
VCC
OE
GND
OUT
+3.3V
VCCO
TMS
TCK
TDI
TDO
37
CCLK
36
+3.3V
+3.3V
41
48
51
40
42
43
47
TP3
50
38 BUSY
39 DIN
44
46
49
53
57
60
62
67
68
56
59
63
64
66
54
58
65
CCLK
2
5
CE
RST/OE
VCC
VPP
CLK
CEO
GND
DAT
8
7
+3.3V
1
2
3
4
5
6
7
8
J3
0.1uF
1
2
3
4
5
6
TCK
TDO
TDI
TMS
6
1
XC17S50A-PD8C
JTAG
DIN
C
J10
HEADER-2
Serial Data 1 and 2
+3.3V
J8
DR2
SCLK1
CLKR1
/SS1
FSR1
SIMO1
DR1
INT1
SCLK2
/INIT
INT2
SIMO2
FSR2
/SS2
CLKR2
70
J9
Slave-Serial
C8
U4
DONE 4
3
/INIT
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
J2
+3.3V
/PROG
R15
SCLK2
CLKR2
/SS2
FSR2
SIMO2
DR2
INT2
RST
0
VCCO
TP9
VCCO
142
2
32
34
D
+3.3V
R13
4K7
CCLK
DONE
DIN
/PROG
/INIT
/RST
71
TP7
TP6
I/O, VREF (566)
I/O, VREF (530)
I/O, IRDY (515)
I/O (575)
I/O (557)
I/O (554)
I/O (545)
I/O (521)
I/O (DOUT, BUSY) (584)
I/O (DIN, D0) (581)
I/O (D1) (551)
I/O (D2) (548)
I/O (D3) (527)
GCK0 (366)
I/O (370)
I/O (373)
I/O (397)
I/O (400)
I/O (409)
I/O (406)
I/O (403)
I/O (427)
I/O (433)
I/O (436)
I/O, VREF (382)
I/O, VREF (418)
TP5
C
124
123
121
120
118
117
116
114
113
112
126
122
115
TP4
VCCO
VCCO
127
+3.3V
TMS
TCK
TDI
TDO
CCLK (587)
88
87
86
84
83
78
79
80
76
75
74
85
77
DIPSWITCH-4
I/O, VREF (164)
I/O, VREF (200)
I/O, IRDY (215)
I/O (149)
I/O (155)
I/O (173)
I/O (176)
I/O (179)
I/O (182)
I/O (185)
I/O (203)
I/O (209)
90
8
7
6
5
VCCO
GCK2 (72)
I/O (66)
I/O (63)
I/O (39)
I/O (36)
I/O (33)
I/O (30)
I/O (9)
I/O, VREF (54)
I/O, VREF (18)
I/O (WRITE) (3)
I/O (CS) (0)
139
132
129
141
140
138
137
136
134
133
131
130
I/O, VREF (311)
I/O, VREF (347)
I/O (302)
I/O (320)
I/O (323)
I/O (326)
I/O (329)
I/O (332)
I/O (356)
GCK1 (365)
R7
10K
VCCO
R8
10K
102
94
103
101
100
99
MDAT2 96
MCLK2 95
93
91
S2
R9
10K
I/O, VREF (125)
I/O, VREF (89)
I/O (140)
I/O (134)
I/O (113)
I/O (110)
I/O (107)
I/O (104)
I/O (80)
GCK3 (73)
144
+3.3V
R10
10K
R12
4K7
U2
+3.3V
1
2
3
4
Approved
1
2
D
S1
R4
10K
9
14
24
55
82
92
97
125
1
2
3
4
R5
10K
ECN Number
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
B
+3.3V
1
5
FSR1
MDAT1
MCLK1
/SS1
CLKR1
SCLK1
SIMO1
DR1
INT1
CTS_MXO45
ti
A
+3.3V
+2.5V
A
12500 TI Boulevard. Dallas, Texas 75243
C28
0.1uF
C35
0.1uF
C42
0.1uF
C43
0.1uF
C29
0.1uF
C31
0.1uF
C38
0.1uF
C44
0.1uF
C30
0.1uF
C33
0.1uF
C37
0.1uF
C40
0.1uF
C32
0.1uF
C36
0.1uF
C39
0.1uF
C34
0.1uF
Title:
C41
0.1uF
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REV
ECN Number
Approved
U1
+5VD
1
L1
+5V_ISO
2
J1
D
C1
100uF
5VIN3
0IN3
3
D1
LED
C3
0.1uF
+
2
3
C5
0.22uF
4
+
BNX002
C4
0.22uF
VIN1
VIN1
10
11
VIN2
VIN2
R2
570
OUT1
OUT1
OUT2
OUT2
FB1
FB2
/RST
8
SEQ
7
/EN
1
9
12
GND
GND
GND
PG1
/MR2
/MR1
GND
GND
+3.3V
23
22
TP2
+2.5V
15
14
+
21
16
C6
22uF
+
TP1
D
C2
47uF
J6
18
/RST
19
TP14
RST
5
6
1
3
5
7
9
+5V_ISO
24
13
R1
3.3K
TPS703XXPWP
1
3
5
7
9
11
13
15
17
19
J17
2
4
6
8
10
+5Vd
2
4
6
8
10
12
14
16
18
20
SW1
C
C
+5V1
R28
+3.3V
C11
10K
R29
10K
R26
1
2
3
4
J15
C23
ANALOG INPUT
J12
R27
U8
M0
VIN+
VINM1
VDD
MCLK
MDAT
GND
8
7
6
5
0.1uF
C27
0.1uF
U6
VCC
A1
8
R17
350
R19
350
R23
470
R22
ADS1202PW
1
2
HEADER-2
+5V1
1
C21
470
2
3
4
K1
K2
VO1
A2
VO2
GND
+5V1
C25
7
MCLK1
6
5
MDAT1
FAI_HCPL-2631
J18
J19
1
2
1
2
HEADER-2
HEADER-2
B
B
+5IN1
+5V2
1
2
3
4
J14
C22
R24
J11
1
2
HEADER-2
A
U7
M0
VIN+
VINM1
VDD
MCLK
MDAT
GND
ADS1202PW
C26
8
7
6
5
0.1uF
VCC
A1
R16
350
0IN1
R18
350
R21
470
R20
470
2
3
K1
K2
VO1
7
MCLK2
6
5
MDAT2
+5IN2
A2
VO2
GND
J21
1
2
1
2
HEADER-2
FILTER
+5V2
3
C16
C17
100uF
C15
0.1uF
5VIN2
0IN2
FAI_HCPL-2631
J20
1
J13
4
+5V2
C24
8
C19
0.1uF
5VIN1
0.1uF
U5
C18
100uF
2
R25
ANALOG INPUT
+5V2
1
C14
C10
R31
C20
3
J16
+3.3V
10K
10K
+5V1
FILTER
2
R30
1
ti
HEADER-2
A
12500 TI Boulevard. Dallas, Texas 75243
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of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Amplifiers
Applications
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2003, Texas Instruments Incorporated
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