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Texas Instruments Resetting Non-FIFO Variations of the 12-bit THS1206 Application notes
Application Brief
SLAA145 - May 2002
Resetting Non-FIFO Variations of the 12-Bit THS1206
Tom Hendrick
Data Acquisition Products—Applications
ABSTRACT
The THS1207 and THS1209 are non-FIFO variations of the THS1206. They require some
special procedures for properly resetting and configuring the device. This application brief
helps explain the necessary steps required to get reliable data from these 12-bit, two and four
channel simultaneous sampling data converters.
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Resetting the SYNC Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3
Reading Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
List of Figures
1 THS1207 Configuration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 SYNC Pulse in 2, 3, and 4 Channel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
Introduction
The THS1207 and THS1209 are counterparts to the THS1206, 4 channels, 12-bit, simultaneous
sampling, 6 MSPS analog to digital converter. Aside from sampling rate and channel count, the
major difference in these parts is that the FIFO has been removed.
This application brief explains the necessary steps required to configure the device, as well as
read reliable, consistent data.
1
SLAA145
2
Resetting the SYNC Generator
Bit 1 of configuration register 1 (CR1), must be considered the SYNC generator reset bit
(SRST). This is similar to the THS1206 in that the THS1206 uses this bit to reset the FIFO to a
known starting position. Similar results are possible by writing a 1 to CR1, bit 1, during the
reset/configuration sequence of the THS1207 and THS1209.
This flow chart shows the initialization sequence of the THS1207. After power up, it is
necessary to perform a device reset by writing hex values 0x401 and 0x400 to the device.
If the default configuration values are desired, there is no need to perform any additional writes
to the device. The default value for configuration register 0 (CR0) is 0x020. The default value for
CR1 is 0x010.
Because the default configuration values select single channel operation, the SYNC pulse is
disabled, and there is no need to reset the SYNC generator.
If multiple channel operation is desired, it is necessary to set the SRST bit as part of the user
configuration write to CR1 (CR1 bit 1 = 1). It is not necessary to clear the SRST bit once it has
been set.
Start
Use Default
Values?
No
Yes
Write 0x401 to
THS1207
(Set Reset Bit in CR1)
Write 0x401 to
THS1207
(Set Reset Bit in CR1)
Clear RESET By
Writing 0x400 to CR1
Clear RESET By
Writing 0x400 to CR1
Write The User
Configuration to CR0
Write The User
Configuration to CR1
(Must Exclude RESET)
Continue
Figure 1. THS1207 Configuration Flow
2
Resetting Non-FIFO Variations of the 12-Bit THS1206
SLAA145
3
Reading Data
Proper data readings depend on the proper application of the read signal. As with the THS1206,
the THS1207 and THS1209 can be configured with independent, active low, read and write
strobes. Active low CS0 and active high CS1 provide chip selection to the device and can be
tied to static levels if desired.
With the non-FIFO devices, it is necessary to issue a read strobe after each CONV_CLK. It is
not appropriate to consider the SYNC pulse as an interrupt source to the host processor. The
SYNC pulse is merely an indiction that data currently available is the data acquired from channel
one.
The read SYNC pulse is not available when the device is configured for single channel
operation. The SYNC pulse is only active when two or more channels are selected for
conversion during the initialization sequence.
Data setup times are listed in the data sheets as tsu(CONV_CLK_READL). The read strobe
must be applied after this setup time but before the subsequent falling CONV_CLK edge. Failure
to read the data bus within each conversion cycle, or multiple reads during the same conversion
cycle, can cause the non-FIFO THS1207 and THS1209 SYNC pulse to behave erratically.
Resetting BIT 1 of CR1 clears erratic SYNC pulse behavior.
tsu(CONV_CLKL_READL)
CONV_CLK
READ
DATA
2CH Mode
3CH Mode
4CH Mode
Figure 2. SYNC Pulse in 2, 3, and 4 Channel Modes
Resetting Non-FIFO Variations of the 12-Bit THS1206
3
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