Texas Instruments | Using the Continuos Parallel Mode with the ADS7824 and ADS7825 | Application notes | Texas Instruments Using the Continuos Parallel Mode with the ADS7824 and ADS7825 Application notes

Texas Instruments Using the Continuos Parallel Mode with the ADS7824 and ADS7825 Application notes
®
USING THE CONTINUOUS PARALLEL MODE WITH THE
ADS7824 AND ADS7825
By Bonnie C. Baker
1
four channels continually as long as CS, R/C and PWRD are
LOW (see Table II). Selection as to which input channel will
be accessed first is done with either the PWRD function or the
CONTC pin. If PWRD is cycled, the first channel that will be
acquired will be channel 0, AIN0. If CONTC is cycled, the
register does not change and the current channel becomes the
first in the sequence. When CONTC is HIGH, A0 and A1
address inputs become outputs. When BUSY rises at the end
of a conversion, A0 and A1 will output the address of the
channel that will be converted next. Additionally, data will be
valid for the previous channel after BUSY rises. See Table II
and Figure 1 for channel selection timing in the continuous,
serial conversion mode.
The ADS7824 and ADS7825 are 12-bit and 16-bit converters
that have a four channel multiplexed front end. The channel
selection on the analog input of these converters is programmable by way of the pins on the devices, A0 and A1 (see Table
I). This feature provides the most flexibility by allowing the
user to change to the preferred input channel on the fly.
Additionally, the input channels can be cycled by utilizing the
continuous mode of the converter. This mode is easily enabled
by tying the CONTC pin high. In this mode, acquisition and
conversions will take place continually, cycling through all
four input channels without user intervention.
In the serial mode (PAR/SER = LOW), the continuous mode
(enabled with CONTC = HIGH) will cause the device to
acquire and converter the input signal and cycle through all
A0
A1
CONTC
DESCRIPTION
0
0
0
Enables AIN0. A0 and A1 are configured as input pins and the user provides instructions to the device to determine which
input will be accessed. This channel address is updated just before BUSY rises.
0
1
0
Enables AIN1. A0 and A1 are configured as input pins and the user provides instructions to the device to determine which
input will be accessed. This channel address is updated just before BUSY rises.
1
0
0
Enables AIN2. A0 and A1 are configured as input pins and the user provides instructions to the device to determine which
input will be accessed. This channel address is updated just before BUSY rises.
1
1
0
Enables AIN3. A0 and A1 are configured as input pins and the user provides instructions to the device to determine which
input will be accessed. This channel address is updated just before BUSY rises.
0
0
1
Enables AIN0. A0 and A1 are configured as output pins. A0 and A1 cycle sequentially from one channel to the next as long
as CONTC is HIGH. The channel that is being acquired or converted is output on these address lines. Data is valid for the
pervious channel. These channels are updated when BUSY rises.
0
1
1
Enables AIN1. A0 and A1 are configured as output pins. A0 and A1 cycle sequentially from one channel to the next as long
as CONTC is HIGH. Then channel that is being acquired or converted is output on these address lines. Data is valid for the
previous channel. These channels are updated when BUSY rises.
1
0
1
Enables AIN2. A0 and A1 are configured as output pins. A0 and A1 cycle sequentially from one channel to the next as long
as CONTC is HIGH. The channel that is being acquired or converted is output on these address lines. Data is valid for the
previous channel. These channels are updated when BUSY rises.
1
1
1
Enables AIN3. A0 and A1 are configured as output pins. A0 and A1 cycle sequentially from one channel to the next as long
as CONTC is HIGH. The channel that is being acquired or converted is output on these address lines. Data is valid for the
previous channel. These channels are updated when BUSY rises.
TABLE I. Channel Selection Truth Table for Addresses A0 and A1.
Conversion Currently in Progress:
BUSY
n–2
n–1
n
n+1
n+2
n+3
n+4
Channel Address for Conversion:
A0, A1
(Output)
n–2
n–1
n
n+1
n+2
n+3
n+4
n+5
t29
Results from Conversion:
D7-D0
n–3
n–2
n–1
n
n+1
n+2
n+3
n+4
FIGURE 1. Channel Selection Timing for Continuous Serial Communication (t29 = 20ns (max))
©
1997 Burr-Brown Corporation
SBAA019
AB-123
1
Printed in U.S.A. September, 1997
CS
R/C
BUSY
PWRD
X
X
↑
0
OPERATION
X
X
0
0
Conversion in process.
0
↓
1
0
Restarts continuous conversion process on next input channel.
The end of conversion ‘n’ (when BUSY rises) increments the internal channel latches and outputs the channel
address for conversion ‘n + 1’ on A0 and A1.
↓
0
1
0
Restarts continuous conversion process on next input channel.
X
X
X
1
All analog functions powered down. Conversion in process or initiated will yield meaningless data. Resets
selected input channel for next conversion to AIN0.
0
0
X
0
Places the converter in the serial out, continuous mode (PAR/SER = low)
TABLE II. Truth Table for the Continuous Mode when the A/D Converter is in the Serial Output Mode (PAR/SER = LOW). A0
and A1 become outputs in this mode. To remain in the continuous mode without interruption, CONTC = HIGH, CS
and R/C = LOW.
1/2 SN74123
A
&
B
+5V
Q
CLR
R1
CX
R1 = 20kΩ
C1 = 1pF
R/C HIGH ≅ 10µs
Q
C1
R2 = 9kΩ
C2 = 1pF
BYTE LOW ≅ 5µs
CX/RX
1/2 SN74123
A
&
B
+5V
Q
CLR
R2
CX
Q
C2
CX/RX
+5V
PWRD
CS
AIN0
AIN1
PAR/SER BYTE
CONTC
R/C
BUSY
ADS7824/25
AIN2
AIN3
GND
A0
PAR OUT
A1
REF
2.2µF
+
CAP
+
2.2µF
FIGURE 2. This Circuit can be Used to Place the ADS7824 or ADS7825 in the Continuous Mode if the Application Requires that
these Devices be Configured for a Parallel Output.
pin controls the output byte. The BYTE pin must be toggled
while BUSY is HIGH if the total of 12 bits in the case of the
ADS7824 and 16 bits in the case of the ADS7825 is required.
Consequently, the continuous, parallel mode for these devices
require some additional logic to toggle the R/C and BYTE pin.
In the parallel mode (PAR/SER = HIGH), the continuous
mode (enabled with CONTC = HIGH) will cause the device
to acquire and converter the input signal and cycle through all
four channels continually as long as CS and PWRD are LOW
(see Table III). In contrast to the serial mode, the parallel
output pins are in a high impedance setting unless R/C is
brought HIGH. Note that if R/C is kept HIGH, the converter
will not be in the continuous mode. Additionally, the BYTE
Figure 2 shows a circuit that can implement the continuous
mode while these devices are in the parallel mode without
2
processor intervention. In this circuit, the ADS7824 (or
ADS7825) is configured to operate in the continuous mode
with CONTC HIGH, PAR/SER HIGH, and CS LOW. On the
rising edge of BUSY, R/C is triggered high through a one shot,
SN74123. This one shot stays high as dictated by the values of
the resistor and capacitor, R1 and C1 and then falls. In this
manner, the parallel outputs of the ADS7824/25 are taken out
of their high impedance mode and the data from the previous
conversion is available on the output pins. In order to access
both the HIGH Byte and LOW Byte of the converted data, the
other half of the dual, SN74123 is used to toggle the BYTE pin
of the converter. Refer to Figure 3 for the timing details of this
circuit.
CS
R/C
BUSY
BYTE
PWRD
0
0
↑
X
0
As is with the serial continuous mode, the input channel
selection is done with either the PWRD function or the
CONTC pin. If PWRD is cycled, the first channel that will be
acquired will be channel 0, AIN0. If CONTC is cycled, the
register does not change and the current channel becomes the
first in the sequence. When CONTC is high, A0 and A1
address inputs become outputs. When BUSY rises at the end
of a conversion, A0 and A1 will output the address of the
channel that will be converted next. Data will be valid for the
previous channel after BUSY rises. The address lines are
updated when BUSY rises. See Table III and Figure 3 for
channel selection timing in the continuous, parallel conversion mode.
OPERATION
The end of conversion ‘n’ (when BUSY rises) increments the internal channel latches and outputs the
channel address for conversion ‘n + 1’ on A0 and A1.
0
0
0
X
0
Conversion in process.
0
↓
1
X
0
Restarts continuous conversion process on next input channel.
0
1
1
1
0
Disables Hi-Z mode at the parallel outputs and puts the MSB byte on the output pins.
0
1
1
0
0
Disables Hi-Z mode at the parallel outputs and puts the LSB byte on the output pins.
X
X
X
X
1
All analog functions powered down. Conversion in process or initiated will yield meaningless data.
Resets selected input channel for next conversion to AIN0.
TABLE III. Truth Table for the Continuous Mode when the A/D Converter is in the Parallel Output Mode (PAR/SER = HIGH,
CONT = HIGH, CS = LOW). A0 and A1 become outputs in this mode.
Throughput Rate at 25µs
BUSY
t31
R/C
t32
t12
BYTE
Parallel
Data Bus
Previous High Byte
(n – 1)
Hi-Z
State
Mode
Convert
A0, A1
(Output)
Previous Low Byte
(n – 1)
Acquire
N-1
Hi-Z
State
Convert
N
t29
MIN
t31
MAX UNITS
ns
0
t32
93
ns
t12
83
ns
t29
20
ns
t31 - BUSY LOW to R/C HIGH
t32 - R/C HIGH to Data Valid
t12 - BYTE to Data Valid
t29 - BUSY HIGH to Address Valid
FIGURE 3. Timing Diagram for Circuit Shown in Figure 2. In this diagram the byte control is arbitrary and the low byte can be
acquired before the high byte without any consequences on operation.
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third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
3
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