Texas Instruments | ADS8686SEVM-PDK | User Guides | Texas Instruments ADS8686SEVM-PDK User guides

Texas Instruments ADS8686SEVM-PDK User guides
User's Guide
SBAU319 – November 2019
ADS8686SEVM-PDK Evaluation Module
This user's guide describes the characteristics, operation, and use of the ADS8686S evaluation module
(EVM) performance demonstration kit (PDK). The ADS8686S is a 16-channel, integrated front-end data
acquisition (DAQ) system based on a dual, simultaneous-sampling, 16-bit successive approximation
(SAR) analog-to-digital converter (ADC). Each input channel on the device supports true bipolar input
ranges of ±10 V, ±5 V, or ±2.5 V with single-supply operation. The device includes an analog front-end
offering a 1-MΩ, constant resistive input impedance. The ADS8686SEVM supports all the mentioned
features and provides provisions for an external reference, user-selectable oversampling ratio, and
features 16 input channels. The EVM-PDK eases the evaluation of the ADS8686S device and any devices
derived from the ADS8686X family with hardware, software, and computer connectivity through the
universal serial bus (USB) interface. This user's guide includes complete circuit descriptions, schematic
diagrams, and a bill of materials using the ADS8686S device as an example throughout the document.
Throughout this document, the terms EVM-PDK and ADS8686SEVM are synonymous with the
ADS8686SEVM-PDK.
The following related documents are available through the Texas Instruments web site at www.ti.com.
Related Documentation
Device
SBAU319 – November 2019
Submit Documentation Feedback
Literature Number
ADS8686S
SBAS905
REF5025
SBOS410
TPS7A4700
SBVS204
OPA192
SBOS620
INA149
SBOS579
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
1
www.ti.com
1
2
3
4
5
6
7
Contents
Overview ...................................................................................................................... 4
1.1
ADS8686SEVM-PDK Features ................................................................................... 4
1.2
ADS8686SEVM Features .......................................................................................... 4
EVM Analog Interface ....................................................................................................... 5
2.1
ADS8686S Internal Reference and EVM Onboard Reference ............................................... 7
Digital Interfaces ............................................................................................................. 7
3.1
ADS8686S Digital Interface ....................................................................................... 7
Power Supplies .............................................................................................................. 8
4.1
Device Power Supplies ............................................................................................ 8
4.2
High-Voltage Power Supplies ..................................................................................... 9
Initial Setup .................................................................................................................. 10
5.1
Default Jumper Settings .......................................................................................... 10
5.2
EVM Graphical User Interface (GUI) Software Installation .................................................. 11
Operation .................................................................................................................... 14
6.1
EVM GUI Global Settings for ADC Control .................................................................... 16
6.2
Register Map Configurations .................................................................................... 17
6.3
Device Configuration ............................................................................................. 17
6.4
Time Domain Display Tool ....................................................................................... 20
6.5
Spectral Analysis Tool ............................................................................................ 21
6.6
Histogram Analysis Tool.......................................................................................... 22
6.7
Linearity Analysis Tool ............................................................................................ 23
Bill of Materials, PCB Layout, and Schematics......................................................................... 24
7.1
Bill of Materials .................................................................................................... 24
7.2
PCB Layout ........................................................................................................ 27
7.3
Schematics ......................................................................................................... 29
List of Figures
1
ADS8686SEVM Analog Input Connections for Channels .............................................................. 5
2
REF5025 2.5-V External Reference Source ............................................................................. 7
3
High-Voltage Power Supply for Amplifiers
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
2
............................................................................... 9
ADS8686SEVM Default Jumper Settings .............................................................................. 10
Software Installation Prompts ............................................................................................ 11
ADS8686S Device Driver Installation Wizard Prompts................................................................ 12
LabVIEW Run-Time Engine Installation ................................................................................. 12
Software Installation Complete Prompts ................................................................................ 13
ADS8686S EVM Folder Post-Installation ............................................................................... 13
ADS8686SEVM-PDK Hardware Setup and LED Indicators .......................................................... 14
Launch the ADS8686SEVM GUI Software ............................................................................. 15
EVM GUI Global Input Parameters ...................................................................................... 16
Register Map Configuration Display ..................................................................................... 17
Device Configuration in Software Mode ................................................................................. 18
Device Configuration Display in Hardware Mode ...................................................................... 19
Time Domain Display ...................................................................................................... 20
Spectral Analysis Tool ..................................................................................................... 21
Histogram Analysis Tool .................................................................................................. 22
Linearity Analysis Tool..................................................................................................... 23
ADS8686S EVM PCB: Top Overlay ..................................................................................... 27
ADS8686S EVM PCB Layer 1: Top Layer .............................................................................. 27
ADS8686S EVM PCB Layer 2: GND Plane ............................................................................ 27
ADS8686S EVM PCB Layer 3: Power Planes ......................................................................... 27
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
SBAU319 – November 2019
Submit Documentation Feedback
www.ti.com
24
ADS8686S EVM PCB Layer 4: Bottom Layer .......................................................................... 27
25
ADS8686S EVM PCB: Bottom Overlay ................................................................................. 27
26
ADS8686SEVM-PDK Schematic ......................................................................................... 29
27
ADS8686SEVM-PDK Schematic ......................................................................................... 30
28
ADS8686SEVM-PDK Schematic ......................................................................................... 31
29
ADS8686SEVM-PDK Schematic ......................................................................................... 32
30
ADS8686SEVM-PDK Schematic ......................................................................................... 33
31
ADS8686SEVM-PDK Schematic ......................................................................................... 34
List of Tables
1
Terminal Block Analog Interface Connections ........................................................................... 6
2
SMA Analog Interface ADC-A Connections .............................................................................. 6
3
SMA Analog Interface ADC-B Connections .............................................................................. 6
4
Digital I/O Connections for Connector J17 ............................................................................... 7
5
Default Jumper Configuration
6
7
8
............................................................................................
External Source Requirements for Evaluation of the ADS8686S ....................................................
External Source Requirements for ADS8686S Evaluation ...........................................................
ADS8686S EVM Bill of Materials ........................................................................................
10
21
23
24
Trademarks
Windows 7, Windows 8, Windows 10 are registered trademarks of Microsoft Corporation.
LabVIEW is a trademark of National Instruments.
Phoenix Contact is a trademark of Samtec, Inc.
All other trademarks are the property of their respective owners.
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
3
Overview
1
www.ti.com
Overview
The ADS8686SEVM-PDK is a platform for evaluating the performance of the ADS8686X family. The EVMPDK comes with the ADS8686S SAR ADC, a 16-channel, 16-bit, ±10-V, ±5-V, or ±2.5-V input range,
simultaneous-sampling ADC device. The evaluation kit includes the ADS8686SEVM board and the
precision host interface (PHI) controller board that enables the accompanying computer software to
communicate with the ADC over the USB for data capture and analysis.
The ADS8686SEVM board includes the ADS8686S SAR ADC and all peripheral analog circuits and
components required to extract optimum performance from the ADC.
The PHI board primarily serves three functions:
• Provides a communication interface from the EVM to the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS8686SEVM
• Supplies power to the digital circuitry on the ADS8686SEVM board
Along with the ADS8686SEVM and PHI controller board, this evaluation kit includes an A-to-micro-B USB
cable to connect to a computer.
1.1
ADS8686SEVM-PDK Features
The ADS8686SEVM-PDK includes the following features:
• Hardware and software required for diagnostic testing as well as accurate performance evaluation of
the ADS8686X family of SAR ADC devices
• USB digital power to enable digital communication
• The PHI controller that provides a convenient communication interface to the ADS8686S ADC over a
USB 2.0 (or higher) for digital input and output
• Easy-to-use evaluation software for Windows 7®,Windows 8®, and Windows 10® 64-bit operating
systems
• The software suite includes graphical tools for data capture, histogram analysis, spectral analysis, and
linearity analysis. This suite also has a provision for exporting data to a text file for post-processing.
1.2
ADS8686SEVM Features
The ADS8686SEVM includes the following features:
• Onboard SMB and terminal block connectors and RC input filters
• Jumper-selectable onboard precision 2.5-V voltage reference or the ADS8686X family devices internal
reference
• Jumper-selectable ±10-V, ±5-V, or ±2.5-V range
• Jumper-selectable channel sequence selection
• Onboard, ultralow noise, low-dropout (LDO) regulator for excellent 5.0-V, single-supply regulation of
the ADC and onboard voltage reference
4
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
SBAU319 – November 2019
Submit Documentation Feedback
EVM Analog Interface
www.ti.com
2
EVM Analog Interface
The ADS8686SEVM is designed for easy interfacing to analog sources. The four Phoenix Contact™ 8terminal headers paired with a respective screw connection tension sleeve, T2 thru T5, provides
convenient and interchangeable access points to all input channels (AIN_0A to AIN_7A and AIN_0B to
AIN_7B) of the device. In addition, the 16 SMB connectors footprints, J-1 to J-16, provide high-quality
connections to channels AIN_0A to AIN_7A and AIN_0B to AIN_7B. Figure 1 shows the ADS8686SEVM
analog input connections and input RC filters for channels AIN_0A to AIN_7A. Table 1 lists the analog
interface connections for header JP1 and Table 2 lists the analog interface connections for the SMB
connectors.
SMA Connector
J-1
ADS8686S
1 kŸ
0Ÿ
1
T2
Terminal Block
(8x1)
AIN_0A_P
`
2
Not
Installed
3
0Ÿ
1000 pF
Not
Installed
AIN_0A_GND
1 kŸ
0Ÿ
SMA Connector
J-9
1 kŸ
0Ÿ
1
T4
Terminal Block
(8x1)
AIN_0B_P
`
2
Not
Installed
3
0Ÿ
1000 pF
Not
Installed
AIN_0B_GND
1 kŸ
0Ÿ
Figure 1. ADS8686SEVM Analog Input Connections for Channels
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
5
EVM Analog Interface
www.ti.com
Table 1. Terminal Block Analog Interface Connections
Terminal # - Pin
Number
Signal
T2/3 - 1
AIN_0/7A_P
T2/3 - 2
AIN_0/7A_GND
T2/3 - 3
AIN_1/6A_P
T2/3 - 4
AIN_1/6A_GND
Description
Positive analog input for channel AIN0A OR positive analog input for channel AIN7A
Negative analog input for channel AIN0A OR negative analog input for channel AIN7A
Positive analog input for channel AIN1A OR positive analog input for channel AIN6A
T2/3 - 5
AIN_2/5A_P
T2/3 - 6
AIN_2/5A_GND
T2/3 -7
AIN_3/4A_P
T2/3 -8
AIN_3/4A_GND
Negative analog input for channel AIN1A OR negative analog input for channel AIN6A
Positive analog input for channel AIN2A OR positive analog input for channel AIN5A
Negative analog input for channel AIN2A OR negative analog input for channel AIN5A
Positive analog input for channel AIN3A OR positive analog input for channel AIN4A
T4/5 - 1
AIN_0/7B_P
T4/5 - 2
AIN_0/7B_GND
T4/5 - 3
AIN_1/6B_P
T4/5 - 4
AIN_1/6B_GND
T4/5 - 5
AIN_2/5B_P
T4/5 - 6
AIN_2/5B_GND
Negative analog input for channel AIN3A OR negative analog input for channel AIN4A
Positive analog input for channel AIN0B OR positive analog input for channel AIN7B
Negative analog input for channel AIN0B OR negative analog input for channel AIN7B
Positive analog input for channel AIN1B OR positive analog input for channel AIN6B
Negative analog input for channel AIN1B OR negative analog input for channel AIN6B
Positive analog input for channel AIN2B OR positive analog input for channel AIN5B
T4/5 -7
AIN_3/4B_P
T4/5 -8
AIN_3/4B_GND
Negative analog input for channel AIN2B OR negative analog input for channel AIN5B
Positive analog input for channel AIN3B OR positive analog input for channel AIN4B
Negative analog input for channel AIN3B OR negative analog input for channel AIN4B
Table 2. SMA Analog Interface ADC-A Connections
SMA Connector
Signal
Description
J-1
AIN_0A
Analog input for channel AIN_0A
J-2
AIN_1A
Analog input for channel AIN_1A
J-3
AIN_2A
Analog input for channel AIN_2A
J-4
AIN_3A
Analog input for channel AIN_3A
J-5
AIN_4A
Analog input for channel AIN_4A
J-6
AIN_5A
Analog input for channel AIN_5A
J-7
AIN_6A
Analog input for channel AIN_6A
J-8
AIN_7A
Analog input for channel AIN_7A
Table 3. SMA Analog Interface ADC-B Connections
6
SMA Connector
Signal
J-9
AIN_0B
Analog input for channel AIN_0B
Description
J-10
AIN_1B
Analog input for channel AIN_1B
J-11
AIN_2B
Analog input for channel AIN_2B
J-12
AIN_3B
Analog input for channel AIN_3B
J-13
AIN_4B
Analog input for channel AIN_4B
J-14
AIN_5B
Analog input for channel AIN_5B
J-15
AIN_6B
Analog input for channel AIN_6B
J-16
AIN_7B
Analog input for channel AIN_7B
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
SBAU319 – November 2019
Submit Documentation Feedback
EVM Analog Interface
www.ti.com
2.1
ADS8686S Internal Reference and EVM Onboard Reference
The ADS8686S device incorporates an internal 2.5-V reference. Alternatively, the user can select the
onboard 2.5-V reference, REF5025 (U4). The reference voltage source is determined by setting REFSEL
(pin 35) of the ADS8686S device. By default, the evaluation module is set up with the ADS8686S internal
reference source, with a shunt jumper installed on JP6 (REFSEL). If the onboard REF5025 2.5-V
reference is desired, the shunt jumper must be removed from JP6 and placed on JP8 (REFIN/OUT). For
more information, see Section 5.1. The output of the REF5025 is filtered through a passive RC filter and
connected to the REFINOUT pin (pin 33) of the ADS8686S using jumper JP8 (REFIN/OUT). Figure 2
shows a schematic for the reference circuit.
10k
JP8
ADS8686S
REFINOUT
(Pin 33)
VOUT
0.22
10
U4
REF5025
0.1µF
TRIM/NR
1µF
10µF
Figure 2. REF5025 2.5-V External Reference Source
3
Digital Interfaces
As noted in Section 1, the EVM interfaces with the PHI that, in turn, communicates with the computer over
the USB. There are two devices on the EVM with which the PHI communicates: the ADS8686S ADC (over
a single or dual SDO serial interface or parallel interface) and the EEPROM (over I2C). The EEPROM
comes preprogrammed with the information required to configure and initialize the ADS8686SEVM-PDK
platform. The EEPROM is initially programmed to communicate with the ADS8686S, but can be
reprogrammed for any of the supported devices in the ADS8686X device family through their respective
GUI software. See Section 5.2 for more information and instructions. After the hardware is initialized, the
EEPROM is no longer used.
3.1
ADS8686S Digital Interface
The ADS8686SEVM-PDK supports parallel, parallel byte, and serial digital interface as detailed in the
ADS8686S data sheet. The PHI controller is configured to operate at a 3.3-V logic level and is directly
connected to the digital I/O lines of the ADC. The digital interface configuration can be easily selected by
navigating within the ADS8686SEVM GUI to Device Configuration tab. For more information, see
Section 6.1.
Socket strip connector J17 provides the digital I/O connections between the ADS8686SEVM board and
the PHI controller. Table 4 summarizes the pin outs for connector J17.
Table 4. Digital I/O Connections for Connector J17
Pin Number
Signal
Description
Parallel data output connections OR oversampling mode control
pins
J17.6, J17.8, J17.10
DB15/OS2, DB14/OS1, DB13/OS0
J17.12, J17.14,
DB12/SDOA, DB11/SDOB
J17.16,
DB10/SDI
J17.18
DB9/BYTESEL
J17.20
DB8/FLTEN
Parallel data output connections
J17.22,J17.24
DB7, DB6
Parallel data output connections
J17.26
DB5/CRCEN
Parallel data output connections OR enable CRC word
J17.28
DB4/SER1W
Parallel data output connections OR serial data output wire select
SBAU319 – November 2019
Submit Documentation Feedback
Parallel data output connections OR serial data output
connections
Parallel data output connections OR serial data input connections
Parallel data output connections OR enable parallel byte
interface
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
7
Power Supplies
www.ti.com
Table 4. Digital I/O Connections for Connector J17 (continued)
Pin Number
Signal
J17.30
DB3
Parallel data output connections
Description
J17.32, J17.34
CSn
CS select, active low
J17.36
SCLK/RD
J17.38, J17.40, J17.42
DB2, DB1, DB0
Clock input pin in serial interface mode OR active-low ready input
pin in parallel and parallel byte interface
Parallel data output connections
J17.44
CONVST
J17.46, J17.48
HW_RNGSEL1,0
J17.50
DVDD
3.3-V digital supply from the PHI controller board
2
I2C bus; used only to read the EEPROM (U5) in the EVM board
J17.56, J17.58
I C Bus
J17.3, J17.60
GND
J1721
WR/BURST
Active high logic input to control start of conversion
Pins used to select input range of device (±10 V, ±5 V, or ±2.5 V)
Ground connections
Write register configuration in parallel and parallel byte modes
OR enable burst mode
J17.23
BUSY
J17.31
SEQEN
Active high digital input enabling channel sequencer
J17.33
RESET
Active low logic input to reset the device
J17.39
SER/BYTE/PAR
Logic input pin to select between serial, parallel byte, or parallel
interface mode
J17.41, J17.43, J17.45
CHSEL0,1,2
Logic input pin to select channel for hardware mode sequencer
J17.59
ID_POWER
Power supply used only to power the EEPROM (U3) in the EVM
board
4
Power Supplies
4.1
Device Power Supplies
Active high digital output indicating ongoing conversion
The ADS8686S ADC analog supply (AVDD) is provided by a low-noise linear regulator (TPS7A4700). The
regulator uses a 5.5-V external supply provided through terminal block T1 (PWR) connected in position 3
(5.5V), and position 4 (GND). This (TBD this what?) is connected to JP7 set to position EXT (pins 2 and
3). The switching regulator (U2) is not populated, and the EVM does not support setting JP7 in position
INT (pins 1 and 2). The 3.3-V supply to the digital supply of the ADS8686S is provided directly by an LDO
on the PHI controller. The power supply for each active component on the EVM is bypassed with a
ceramic capacitor placed close to that component. Additionally, the EVM layout uses thick traces or large
copper filled areas where possible between bypass capacitors and their loads to minimize inductance
along the load current path.
CAUTION
When using the ADS8686SEVM in conjunction with the PHI controller, install a
shunt between JP7 pins 2-3 as shown in Figure 4 The PHI controller supplies
the DVDD power supply. Do not use the JP7 internal setting or the device can
be damaged.
CAUTION
When using the ADS8686SEVM as a stand-alone board, install a shunt
between JP7 (pins 2 and 3) and connect the analog supply (AVDD) on the
terminal block T1 (position 3 or 4). For the digital supply (DVDD), remove R28
and supply DVDD on the terminal block T1 (position 1 or 2). Make sure that the
AVDD voltage is in the range between 5.5 V to 6 V, and that DVDD is in the
range of 2.3 V < DVDD < AVDD for proper device operation. Do not exceed the
absolute maximum ratings for the ADS8686S device, or damage may occur.
8
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
SBAU319 – November 2019
Submit Documentation Feedback
Power Supplies
www.ti.com
4.2
High-Voltage Power Supplies
As shown in Figure 3, the ADS8686SEVM is equipped with two input driving amplifiers for two ADS8686S
analog inputs. The device input AIN_0B can be driven by U6, the OPA192 (a precision rail-to-rail
operational amplifier) in a buffer configuration. Input AIN_B1 can be driven by a difference amplifier, U7
(INA149). Each of these amplifiers require positive and negative power rails over the expected maximum
and minimum input levels, and the recommended supply is ±15 V. Connect an external power supply to
terminal block T6 (HV PWR) to provide the high-voltage power supplies. See the respective device data
sheet for more information.
By default, each of the amplifiers are bypassed. To include the OPA192 in the input driving circuit to
channel AIN_0B, remove the 0-Ω resister, R127, and populate R129 and R128 with 0-Ω resisters. The
input can be connected through either terminal block T4 (position 3 or4) or by the BNC connector J10. To
include the INA149 in the input driving circuit to channel AIN_1B, remove the 0-Ω resistors, R130 and
R133, and populate R134, R135, and R131. Inputs can be connected through either terminal block T4
(position 5 or 6) or by the BNC connector J11. To use a different value other than ground for input
AIN_1BGND, use terminal block T4, position 6.
T6
+15V
1
2
3
-15V
GND
+15V
+15V
BIN1J+
-
R129
100k
OPA192
+
BIN1+
INA149
+
BIN2+
GND
+
-15V
-15V
R132
10k
+
-
BIN2J+
GND
Figure 3. High-Voltage Power Supply for Amplifiers
NOTE:
The high-voltage power supplies connected to terminal block T6 only provide power to U6
and U7, the input driving amplifiers. The high-voltage power supplies are not connected to
any other device on the board.
CAUTION
Terminal T6 (HV PWR) on the ADS8686SEVM is intended for high-voltage
supplies and does not have a protection scheme or regulation circuitry onboard.
When connecting an external power supply to T6 use a clean and precise
supply, otherwise damage can occur to the driving amplifiers U6 and U7.
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
9
Initial Setup
5
www.ti.com
Initial Setup
This section explains the initial hardware and software setup procedure that must be completed for the
proper operation of the ADS8686SEVM-PDK.
5.1
Default Jumper Settings
Install a shunt at JP6 to select the internal reference. Install a shunt between JP7 (pins 2 and 3) as shown
in Figure 4 to connect the onboard regulated AVDD 5.0-V supply. Figure 4 details the default jumper
settings. Table 5 explains the configuration for these jumpers. When the EVM is paired with the PHI
board, the jumper selections on JP1 thru JP5 have no effect in either hardware or software mode. The
GUI provides user-selectable options to control these settings and overrides the jumper selection. When
the EVM is used standalone, the jumper settings take effect in the device settings.
Figure 4. ADS8686SEVM Default Jumper Settings
Table 5. Default Jumper Configuration
Jumper
Function
Default Position
JP1, JP3, JP5
CHSEL0,
CHSEL1,
CHSEL2
Open
1-2 logic high, 2-3 logic low. Programs the channel sequencer.
JP2, JP4
HW_RNGSEL0,
HW_RNGSEL1
Open
1-2 logic high, 2-3 logic low. Selects the analog input range.
JP6
REFSEL
Closed
AVDD Ext
Closed between
pins 2 and 3
JP7
10
Description
Open selects the external reference; closed selects the internal reference
2-3 external source regulated with the onboard LDO to the AVDD 5.0-V supply
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
SBAU319 – November 2019
Submit Documentation Feedback
Initial Setup
www.ti.com
Table 5. Default Jumper Configuration (continued)
Jumper
JP8
5.2
Function
REFIN/OUT
Default Position
Description
Open
Open when using the internal reference; closed connects the external onboard
reference
EVM Graphical User Interface (GUI) Software Installation
NOTE: Manually disable any antivirus software running on the computer before downloading the
EVM GUI installer onto the local hard disk. Otherwise, depending on the antivirus settings,
an error message may appear or the installer.exe file may be deleted.
The following steps list the directions to install the software using the ADS8686S as an example.
Download and install the ADS8686SEVM software GUI from he ADS8686SEVM-PDK product folder.
Administrator privileges are required on the PC to install the EVM software.
Accept the license agreements and follow the on-screen instructions to complete the installation, as shown
in Figure 5, after downloading and starting the GUI installer.
Figure 5. Software Installation Prompts
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
11
Initial Setup
www.ti.com
A prompt with a Device Driver Installation appears on the screen, as shown in Figure 6, as part of the
ADS8686S EVM GUI installation. Click Next to proceed.
Figure 6. ADS8686S Device Driver Installation Wizard Prompts
NOTE: A notice may appear on the screen stating that Widows cannot verify the publisher of this
driver software. Select Install this driver software anyway.
TheADS8686SEVM-PDK requires the LabVIEW™ Run-Time Engine. A prompt appears for the installation
of this software, as shown in Figure 7, if not already installed.
Figure 7. LabVIEW Run-Time Engine Installation
12
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
SBAU319 – November 2019
Submit Documentation Feedback
Initial Setup
www.ti.com
The installation is now complete. The prompts shown in Figure 8 confirm that the software is installed.
Figure 8. Software Installation Complete Prompts
Verify that the contents of C:\Program Files (x86)\Texas Instruments\ADS8686 EVM is as shown in
Figure 9 after installation.
Figure 9. ADS8686S EVM Folder Post-Installation
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
13
Operation
6
www.ti.com
Operation
The following instructions are a step-by-step guide to connecting the ADS8686S to the computer and
evaluating the performance of the ADS8686S:
1. Connect the ADS8686SEVM to the PHI. Install the two screws as indicated in Figure 10.
2. Use the USB cable provided to connect the PHI to the computer.
a. LED D5 on the PHI lights up, indicating that the PHI is powered up.
b. LEDs D1 and D2 on the PHI starts blinking to indicate that the PHI is booted up and
communicating with the PC. Figure 10 shows the resulting LED indicators.
Figure 10. ADS8686SEVM-PDK Hardware Setup and LED Indicators
14
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
SBAU319 – November 2019
Submit Documentation Feedback
Operation
www.ti.com
3. As shown in Figure 11, double click the ADS8686EVM.exe file to launch the EVM GUI.
Figure 11. Launch the ADS8686SEVM GUI Software
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
15
Operation
6.1
www.ti.com
EVM GUI Global Settings for ADC Control
Although the EVM GUI does not allow direct access to the voltage levels and timing configuration of the
ADC digital interface, the EVM GUI provides high-level control over the ADS8686S interface modes and
RD/SCLK clock frequency. In addition, the EVM GUI provides control to device configuration settings such
as sampling rate and number of samples to be captured, as well as register mapping such as input range
selection, oversampling setting, and channel sequence selection.
Figure 12 shows the Interface Configuration pane at the left, through which timing functions of the
ADS8686S are exercised. These are global settings and persist across the different GUI Pages listed in
the top left pane. TheSCLK Frequency (Hz) and Sampling Rate (sps) can be selected on this pane,
depending on the selected interface and OSR settings. Enter the targeted values for these two
parameters, and the GUI considers the timing constraints of the selected interface and computes the best
values that can be achieved. Enter a Target value in the SCLK Frequency (Hz) field, and the GUI matches
this frequency as closely as possible by changing the PHI PLL settings, and then displaying the
Achievable frequency that may differ from the entered Target value. Similarly, adjust the ADC Sampling
Rate (sps) by entering a Target value (Hz = sps). The Achievable ADC sampling rate can differ from the
Target value, depending on the applied RD/SCLK frequency and selected Interface. The closest
achievable match is then displayed. Therefore, this pane allows the various settings available on the
ADS8686S to be tested in an iterative fashion until the best settings for the corresponding test scenario
are achieved.
Displayed above this (TBD this what?) are the Full Reset and Partial Reset buttons. Each of these buttons
initiates its respective reset type through software. A hardware reset can be initiated by pressing S1 RST
on the EVM. When a master reset, either through software or hardware occurs the device resets to the
default register settings. The GUI automatically generates a reset pulse when required to execute device
configurations; there is no need to press the Full Reset button. At the bottom left, the Current Device
Mode pane displays the operational mode the device is currently in, which also persists across the GUI
tools and pages.
Figure 12. EVM GUI Global Input Parameters
16
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
SBAU319 – November 2019
Submit Documentation Feedback
Operation
www.ti.com
6.2
Register Map Configurations
The Register Map Config page (Figure 13) provides access to the device register mapping. Within the
page, the user registers listed can be easily changed through a drop down provided under the Field View
on the right. When a register is selected, the options available are listed, when an option is selected, that
option is reflected in the Value column. When a register configuration is made, that configuration persists
through all GUI pages. See the device data sheet for more information on device registers.
Figure 13. Register Map Configuration Display
6.3
Device Configuration
The device configuration page provides a user-friendly interface to the most common configuration
options. When a setting is changed, that setting persists through all GUI pages and is also reflected in the
Current Device Mode box if listed. When making a change that requires a reset pulse to the device, the
GUI provides the pulse when the setting is changed; there is no need to press the Full Reset button.
At the top of the page are drop-down menu options for the Interface Mode, Device Mode, and Serial
Output Mode. The Interface Mode field allows the choice of three interface options: serial, parallel, or
parallel byte. Serial interface communication occurs through either single or dual serial output:
DB12/SDOA and DB11/SDOB that can be selected in the Serial Output Mode field. Parallel interface
communication occurs through the DB[15:0] parallel bus, parallel byte through the DB[7:0] parallel bus.
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
17
Operation
6.3.1
www.ti.com
Software Mode
The page displays the setting options as shown in Figure 14 when in software mode. The setting are
displayed in three sections, Configuration, Individual Range Selections, and Sequencer Configuration.
In the left-most section, Configuration, channel selection options for each ADC is provided. In software
mode the device allows the ADC channels sampled not to correspond with each other (for example,
channel AIN_0A can be sampled with channel AIN_2B). The device also supports sequencer mode that
can be enabled in this section. When this mode is disabled, the Burst Mode option is grayed out because
burst mode is only available with the Sequencer Mode option enabled. To use burst mode, first enable
Sequencer Mode, then enable Burst Mode. The ADS8686S supports an oversampling mode of operation
using an on-chip averaging digital filter, as explained in the device data sheet. The oversampling ratio
(OSR) settings drop-down menu in this section provides selectable oversampling ratios of 2x, 4x, 8x, 16x,
32x, 64x, and 128x. The Filter Settings drop down provides a drop-down field to select the cutoff
frequency of the internal second-order, low-pass filter: 15 kHz, 39 kHz, or 300 kHz.
The middle section, Individual Range Selection, is used to select the input range of each input channel of
the device: ±10 V, ±5 V, or ±2.5 V. Each channel can also support an input range increase of 20% of the
selected input range by checking the Over Range option. More information on the overrange setting is
available in the device data sheet.
The right most section, Sequencer Configuration, provides a user-friendly interface to set the channel
stack setting in sequencer mode. The device supports up to 32 stack options, navigating through the
Jump to Page buttons displays these options. The stack length is selected by checking the Last Layer box
of the final stack desired. Each stack can support non-corresponding input channels between ADC A and
ADC B.
Figure 14. Device Configuration in Software Mode
18
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
SBAU319 – November 2019
Submit Documentation Feedback
Operation
www.ti.com
6.3.2
Hardware Mode
When in hardware mode, Figure 15 shows the setting options for the Device Configuration page. The
device has limited configuration options in hardware mode, whcih are disabled in the GUI. The Register
Map Config page is also not accessible in hardware mode.
In hardware mode, simultaneous sampling is restricted to the corresponding ADC A and ADC B channel,
that is, channel AIN_0A is always sampled with channel AIN_0B. The diagnostic channels can not be
sampled in the hardware mode of operation. All input channels are configured to the same input range in
hardware more. Sequencer mode is supported in hardware mode. When sequencer mode is disabled, the
Burst Mode option is grayed out because burst mode is only available with sequencer mode enabled. The
oversampling setting is also available in hardware mode, and can be selected using the drop-down field.
The Float Detection option is displayed as a drop-down field in the Device Configurations page because
the Register Map Config page is inaccessible in hardware mode.
Figure 15. Device Configuration Display in Hardware Mode
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
19
Operation
6.4
www.ti.com
Time Domain Display Tool
The Time Domain Display tool (Figure 16) allows visualization of the time domain conversion results given
a set of analog input signals.
The GUI Time Domain Display shows two time domain voltage plots: the top time domain plot shows the
conversion results ADC A and the bottom display shows conversion results for ADC B. The sample
indices are on the x-axis and there are two y-axes showing the corresponding converted analog voltages.
Any combination of desired channels can be selected using the Analog CH AINx selection buttons at the
top-right side of the display.
When the Capture button is pressed, the software captures a contingent number of samples that are
selected in the Samples field. In addition, the bottom-right side of the GUI provides information about the
converted signals, such as the selected channel maximum and minimum code, maximum and minimum
voltage, and the calculated RMS voltage value for the captured signal on each channel.
Figure 16. Time Domain Display
20
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
SBAU319 – November 2019
Submit Documentation Feedback
Operation
www.ti.com
6.5
Spectral Analysis Tool
The spectral analysis tool is intended to evaluate the dynamic performance (SNR, THD, SFDR, SINAD,
and ENOB) of the ADS8686S SAR ADC through a single-tone sinusoidal signal FFT analysis using the 7term Blackman-Harris window setting.
For dynamic performance evaluation, the external differential source must have better specifications than
the ADS8686S device in order to make sure that the measured system performance is not limited by the
performance of the signal source. Therefore, the external reference source must meet the source
requirements mentioned in Table 6.
Table 6. External Source Requirements for Evaluation of the ADS8686S
Specification Description
Specification Value
Signal frequency
1 kHz (OSR = 0)
External source type
Single ended
External source common-mode
0V
Maximum noise
35 µVRMS
Maximum SNR
100 dB
Maximum THD
–110 dB
For 1-kHz SNR and ENOB evaluation at a maximum throughput of 200 kSPS, the optimal number of
samples is 32768. More samples brings the noise floor so low that the external source phase noise can
dominate the SNR and ENOB calculations. Figure 17 shows the spectral analysis tool.
Figure 17. Spectral Analysis Tool
Finally, the FFT tool includes windowing options that are required to mitigate the effects of non-coherent
sampling (a discussion that is beyond the scope of this document). The 7-Term Blackman Harris window
is the default option and has sufficient dynamic range to resolve the frequency components of up to a 24bit ADC. The None option corresponds to not using a window (or using a rectangular window), and is not
recommended.
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
21
Operation
6.6
www.ti.com
Histogram Analysis Tool
Noise degrades ADC resolution and the histogram tool can be used to estimate effective resolution, which
is an indicator of the number of bits of ADC resolution losses resulting from noise generated by the
various sources connected to the ADC when measuring a DC signal. The cumulative effect of noise
coupling to the ADC output from sources such as the input drive circuits, the reference drive circuit, the
ADC power supply, and the ADC, is reflected in the standard deviation of the ADC output code histogram
that is obtained by performing multiple conversions of a dc input applied to a given channel.
As shown in Figure 18, the histogram corresponding to a dc input is displayed on clicking on the Capture
button.
Figure 18. Histogram Analysis Tool
22
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
SBAU319 – November 2019
Submit Documentation Feedback
Operation
www.ti.com
6.7
Linearity Analysis Tool
The linearity analysis tool measures and generates the performance DNL and INL plots over code for the
ADS8686S. A 1-kHz sinusoidal input signal is required, which is slightly saturated (100 mV to 200 mV
outside the full-scale range) at each input with very low distortion. The external source linearity must be
better than the ADC linearity. The measured system performance must reflect the linearity errors of the
ADC and must not be limited by the performance of the signal source. To make sure that the DNL and INL
of the ADC are correctly measured, the requirements in Table 7 must be met by the external source.
Table 7. External Source Requirements for ADS8686S Evaluation
Specification Description
Specification Value
Signal frequency
1 kHz
External source type
Single ended, referred to GND
External source common mode
0V
Signal Amplitude
10.2 Vp (TBD VPP?) for ±10-V range;
5.1 Vp (TBD VPP?) for ±5-V range;
2.55 Vp (TBD VPP?) for ±2.5-V range;
Maximum noise
35 µVRMS
Maximum SNR
100 dB
Maximum THD
–110 dB
The number-of-hits setting depends on the external noise source. For a 100-dB SNR external source with
approximately 30 µVrms of noise, the total number of hits must be 256. Figure 19 shows the linearity
analysis tool.
NOTE: This analysis can take a couple of minutes to run; therefore, the evaluation board must
remain undisturbed during the complete duration of the analysis.
Figure 19. Linearity Analysis Tool
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
23
Bill of Materials, PCB Layout, and Schematics
7
www.ti.com
Bill of Materials, PCB Layout, and Schematics
This section contains the ADS8686S EVM bill of materials (BOM), printed circuit board (PCB) layout, and the EVM schematics.
7.1
Bill of Materials
Table 8 lists the ADS8686SEVM BOM.
Table 8. ADS8686S EVM Bill of Materials
Manufacturer Part Number
Qty
Reference Designators
Manufacturer
Description
DC029
1
N/A
Any
Printed Circuit Board for Evaluation of ADS8686S
PHI-EVM-CONTROLLER
(Edge# 6591636 rev. B)
1
N/A
Texas Instruments
USB Controller Board for ADC EVMs (Kit Item)
GRM188R60J106ME84
10
C1, C3, C5, C7, C9, C11,
C15, C17, C18, C21
MuRata
CAP, CERM, 10 uF, 6.3 V, +/- 20%, X5R, 0603
550L104KCAT
14
C2, C4, C6, C8, C10, C12,
C16, C44, C45, C46, C47,
C48, C50, C51
AT Ceramics
CAP, CERM, 0.1 uF, 16 V, +/- 10%, 0402
C0805C104K4RACTU
1
C13
Kemet
CAP, CERM, 0.1 uF, 16 V, +/- 10%, X7R, 0805
C0805C106K8PACTU
3
C14, C26, C43
Kemet
CAP, CERM, 10 uF, 10 V, +/- 10%, X5R, 0805
GRM31CR61A226ME19L
1
C19
MuRata
CAP, CERM, 22 uF, 10 V, +/- 20%, X5R, 1206
GRM188R71E105KA12D
5
C23, C24, C25, C49, C52
MuRata
CAP, CERM, 1 uF, 25 V, +/- 10%, X7R, 0603
GRM1885C1H102FA01J
16
C27, C28, C29, C30, C31,
C32, C33, C34, C35, C36,
C37, C38, C39, C40, C41,
C42
MuRata
CAP, CERM, 1000 pF, 50 V, +/- 1%, C0G/NP0, 0603
PMSSS 440 0025 PH
4
H1, H2, H3, H4
B&F Fastener Supply
Machine Screw Pan PHILLIPS 4-40
1891
4
H5, H6, H7, H8
Keystone
Hex Standoff, #4-40, Aluminum, 1/4"
9774050360R
2
H9, H10
Wurth Elektronik
ROUND STANDOFF M3 STEEL 5MM
RM3X4MM 2701
2
H11, H12
APM HEXSEAL
Machine Screw Pan PHILLIPS M3
1803633
4
H13, H14, H15, H16
Phoenix Contact
Terminal Block Plug, 8 Pos, 3.81mm
5-1814832-1
4
J1, J2, J9, J10
TE Connectivity
SMA Straight PCB Socket Die Cast, 50 Ohm, TH
QTH-030-01-L-D-A
1
J17
Samtec
Header(Shrouded), 19.7mil, 30x2, Gold, SMT
TSW-116-07-G-D
1
J18
Samtec
Header, 100mil, 16x2, Gold, TH
Header, 100mil, 3x1, Gold, TH
PBC03SAAN
6
JP1, JP2, JP3, JP4, JP5, JP7
Sullins Connector
Solutions
5-146261-1
3
JP6, JP8, JP9
TE Connectivity
Header, 100mil, 2x1, Gold, TH
CRCW040210K0FKED
5
R2, R27, R122, R126, R132
Vishay-Dale
RES, 10.0 k, 1%, 0.063 W, 0402
19
R5, R6, R7, R8, R9, R10,
R11, R12, R17, R18, R19,
R20, R21, R22, R23, R24,
R25, R26, R124
Vishay-Dale
RES, 100 k, 1%, 0.063 W, 0402
CRCW0402100KFKED
24
ADS8686SEVM-PDK Evaluation Module
SBAU319 – November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Bill of Materials, PCB Layout, and Schematics
www.ti.com
Table 8. ADS8686S EVM Bill of Materials (continued)
Manufacturer Part Number
Qty
Reference Designators
Manufacturer
Description
CRCW12060000Z0EA
17
R28, R34, R36, R44, R46,
R54, R56, R64, R66, R74,
R76, R84, R86, R94, R96,
R104, R106
RT0603BRD0710KL
1
R31
Yageo America
RES, 10.0 k, 0.1%, 0.1 W, 0603
ERJ-3RQFR22V
1
R32
Panasonic
RES, 0.22, 1%, 0.1 W, 0603
CRCW04022K70JNED
2
R33, R125
Vishay-Dale
RES, 2.7 k, 5%, 0.063 W, 0402
RG1608P-102-B-T5
32
R35, R37, R40, R41, R45,
R47, R50, R51, R55, R57,
R60, R61, R65, R67, R70,
R71, R75, R77, R80, R81,
R85, R87, R90, R91, R95,
R97, R100, R101, R105,
R107, R110, R111
Susumu Co Ltd
RES, 1.00 k, 0.1%, 0.1 W, 0603
CRCW06030000Z0EA
18
R42, R43, R52, R53, R62,
R63, R72, R73, R82, R83,
R92, R93, R102, R103, R112,
R113, R130, R133
Vishay-Dale
RES, 0, 5%, 0.1 W, 0603
CRCW040249R9FKED
9
R114, R115, R116, R117,
R118, R119, R120, R121,
R123
Vishay-Dale
RES, 49.9, 1%, 0.063 W, 0402
RC0402JR-070RL
1
R127
Yageo America
RES, 0, 5%, 0.063 W, 0402
EVQPNF04M
1
S1
Panasonic
Switch, Tactile, SPST-NO, 0.05A, 12V, SMD
382811-6
7
SH-J1, SH-J2, SH-J3, SH-J4,
SH-J5, SH-J6, SH-J7
AMP
Shunt, 100mil, Gold plated, Black
ED555/4DS
1
T1
On-Shore Technology
Terminal Block, 3.5mm Pitch, 4x1, TH
1803332
4
T2, T3, T4, T5
Phoenix Contact
Header(shrouded), 3.81mm, 8x1, Tin, R/A, TH
ED555/3DS
1
T6
On-Shore Technology
Terminal Block, 3.5mm Pitch, 3x1, TH
5001
2
TP1, TP2
Keystone
Test Point, Miniature, Black, TH
5002
3
TP3, TP4, TP5
Keystone
Test Point, Miniature, White, TH
ADS8686-PZA
1
U1
Texas Instruments
16-Channel DAS with 16-Bit, Bipolar Input, Dual Simultaneous Sampling ADC, PZA0080A (LQFP-80)
TPS7A4700RGWR
1
U3
Texas Instruments
36-V, 1-A, 4.17-uVRMS, RF LDO Voltage Regulator, RGW0020A (VQFN-20)
REF5025AIDGKT
1
U4
Texas Instruments
Low Noise, Very Low Drift, Precision Voltage Reference, -40 to 125 degC, 8-pin MSOP(DGK), Green (RoHS & no
Sb/Br)
BR24G32FVT-3AGE2
1
U5
Rohm
I2C BUS EEPROM (2-Wire), TSSOP-B8
OPA192IDBVT
1
U6
Texas Instruments
Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp with E-trim, 4.5 to 36 V,
-40 to 125 degC, 8-Pin SOT-23 (DBV), Green (RoHS & no Sb/Br), Tape and Reel
INA149AID
1
U7
Texas Instruments
High Common Mode Voltage Difference Amplifier, -40 to 125 degC, 8-pin SOIC (D8), Green (RoHS & no Sb/Br)
GRM188R60J106ME84
0
C20, C22
MuRata
CAP, CERM, 10 uF, 6.3 V, +/- 20%, X5R, 0603
0
D4, D5, D6, D7, D8, D9, D10,
D11, D12, D13, D14, D15,
D16, D17, D18, D19
Littelfuse
Diode, TVS, Bi, 14 V, SMB
SMBJ14CA
Vishay-Dale
RES, 0, 5%, 0.25 W, 1206
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
25
Bill of Materials, PCB Layout, and Schematics
www.ti.com
Table 8. ADS8686S EVM Bill of Materials (continued)
Manufacturer Part Number
Qty
Reference Designators
Manufacturer
Description
5-1814832-1
0
J3, J4, J5, J6, J7, J8, J11,
J12, J13, J14, J15, J16
1269AS-H-4R7M=P2
0
L1
MuRata Toko
Inductor, Shielded, Metal Composite, 4.7 uH, 1.2 A, 0.25 ohm, SMD
CRCW040210K0FKED
0
R1
Vishay-Dale
RES, 10.0 k, 1%, 0.063 W, 0402
CRCW0402100KFKED
0
R3, R4, R13, R14, R15, R16,
R30, R129
Vishay-Dale
RES, 100 k, 1%, 0.063 W, 0402
CRCW04021M00JNED
0
R29
Vishay-Dale
RES, 0, 5%, 0.1 W, 0603
CRCW06030000Z0EA
0
R38, R39, R48, R49, R58,
R59, R68, R69, R78, R79,
R88, R89, R98, R99, R108,
R109, R131, R134, R135
Vishay-Dale
RES, 0, 5%, 0.1 W, 0603
RC0402JR-070RL
0
R128
Yageo America
RES, 0, 5%, 0.063 W, 0402
TPS61220DCKR
0
U2
Texas Instruments
Low Input Voltage, 0.7V Boost Converter with 5.5uA Quiescent Current, DCK0006A (SOT-SC70-6)
26
TE Connectivity
SMA Straight PCB Socket Die Cast, 50 Ohm, TH
ADS8686SEVM-PDK Evaluation Module
SBAU319 – November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Bill of Materials, PCB Layout, and Schematics
www.ti.com
7.2
PCB Layout
Figure 21 through Figure 25 illustrate the EVM PCB layout.
Figure 20. ADS8686S EVM PCB: Top Overlay
Figure 21. ADS8686S EVM PCB Layer 1: Top Layer
Figure 22. ADS8686S EVM PCB Layer 2: GND Plane
Figure 23. ADS8686S EVM PCB Layer 3: Power Planes
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
27
Bill of Materials, PCB Layout, and Schematics
Figure 24. ADS8686S EVM PCB Layer 4: Bottom Layer
28
www.ti.com
Figure 25. ADS8686S EVM PCB: Bottom Overlay
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
SBAU319 – November 2019
Submit Documentation Feedback
Bill of Materials, PCB Layout, and Schematics
www.ti.com
7.3
Schematics
Figure 26 through Figure 26 illustrate the EVM schematics.
DVDD
C1
10uF
C2
0.1uF
DVDD
AVDD
R1
DNP
10.0k
U1
GND
49
C3
10uF
C4
0.1uF
C5
10uF
C6
0.1uF
C7
10uF
C8
0.1uF
C9
10uF
C10
0.1uF
6
15
30
71
VCC
VCC
VCC
VCC
28
27
26
25
24
23
22
21
19
20
17
18
14
13
12
11
V0A
V0AGND
V1A
V1AGND
V2A
V2AGND
V3A
V3AGND
V4A
V4AGND
V5A
V5AGND
V6A
V6AGND
V7A
V7AGND
GND
Place pair of decoupling caps near each AVDD device pin
AIN0
AIN0GND
AIN1
AIN1GND
AIN2
AIN2GND
AIN3
AIN3GND
AIN4
AIN4GND
AIN5
AIN5GND
AIN6
AIN6GND
AIN7
AIN7GND
73
74
75
76
77
78
79
80
2
1
4
3
7
8
9
10
BIN0
BIN0GND
BIN1
BIN1GND
BIN2
BIN2GND
BIN3
BIN3GND
BIN4
BIN4GND
BIN5
BIN5GND
BIN6
BIN6GND
BIN7
BIN7GND
70
C11
10uF
C12
0.1uF
33
REFINOUT
C13
0.1uF
GND
GND
SCLK/RD
CS
SER/PAR
V0B
V0BGND
V1B
V1BGND
V2B
V2BGND
V3B
V3BGND
V4B
V4BGND
V5B
V5BGND
V6B
V6BGND
V7B
V7BGND
RESET
WR/BURST
SEQEN
HW_RNGSEL0
HW_RNGSEL1
CHSEL0
CHSEL1
CHSEL2
BUSY
CONVST
36
61
37
39
38
64
65
66
67
68
SER/PAR/BYTE
R2
10.0k
DB0
DB1
DB2
DB3
GND
DB6
DB7
DB8/FLTEN
DB9/BYTESEL
DB10/SDI
DB11/SDOB
DB12/SDOA
DB13/OS0
DB14/OS1
DB15/OS2
R7
100k
R8
100k
R9
100k
R10
100k
R11
100k
DB4/SER1W
DB5/CRCEN
R5
100k
R6
100k
R12
100k
GND
GND
RESET
WR/BURST
DVDD
SEQEN
D_HW_RNGSEL0
D_HW_RNGSEL1
D_CHSEL0
D_CHSEL1
D_CHSEL2
BUSY
CONVST
DVDD
R3
R4
DNP
100kDNP
100k
R17
100k
R13
DNP
100k
DVDD
R18
100k
R14
DNP
100k
DVDD
R15
R16
DNP
100kDNP
100k
DB8/FLTEN
DB9/BYTESEL
REGGNDD
REFGND
REGGND
REGCAP
REGCAPD
DGND
ADS8686-PZA
C16
0.1uF
GND
R20
100k
R21
100k
GND
5
16
29
72
AGND
AGND
AGND
AGND
GND
69
34
REFCAP
R19
100k
51
32
REFINOUTGND
REFINOUT
REFSEL
52
SCLK/RD
CS
40
41
42
43
44
45
46
47
48
53
54
55
56
57
58
59
60
31
C15
10uF
62
63
DB0
DB1
DB2
DB3
DB4/SER1W
DB5/CRCEN
DB6
DB7
DB8
DB9
DB10/SDI
DB11/SDOB
DB12/SDOA
DB13/OS0
DB14/OS1
DB15/OS2
REFSEL 35
C14
10uF
GND
VDRIVE
GND
ZZ5
Assembly Note
On JP1 through JP5 place jumper short on pin2-3
50
DVDD
JP1
GND
1
2
3
CHSEL0
R22
100k
DVDD
D_CHSEL0
JP2
GND
1
2
3
HW_RNGSEL0
R23
100k
GND
D_HW_RNGSEL0
JP3
DVDD
1
2
3
CHSEL1
R24
100k
GND
JP4
DVDD
INT
REFSEL
EXT
HW_RNGSEL1
DVDD
1
2
3
R25
100k
JP6
GND
JP5
D_HW_RNGSEL1
CHSEL2
1
2
REFSEL
ZZ6
Assembly Note
On JP6 place jumper short
D_CHSEL1
DVDD
1
2
3
R26
100k
D_CHSEL2
GND
GND
R27
10.0k
GND
Figure 26. ADS8686SEVM-PDK Schematic
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
29
Bill of Materials, PCB Layout, and Schematics
www.ti.com
AIN0+
J1
R34
R35
0
1.00k
R36
AIN4+
2
3
4
5
AIN4
1.00k
D5
DNP SMBJ14CA
14V
R38
DNP
0
R37
0
D4
DNP SMBJ14CA
1 AIN0+
AIN0
AIN0
14V
R39
DNP
0
C27
1000pF
C28
1000pF
AIN0_GND
GND
GND
R40
AIN0_GND
AIN0GND
1.00k
J2
R41
AIN4_GND
R43
0
2
3
4
5
1 AIN1+
AIN4GND
1.00k
R42
0
AIN1
AIN1_GND
GND
GND
J3
1 AIN2+
R44
AIN1+
DNP
2
3
4
5
AIN2
R45
0
AIN2_GND
R48
DNP
0
J4
T2
R49
DNP
0
AIN3
AIN1GND
1.00k
J5
C30
1000pF
R51
AIN5_GND
AIN5GND
1.00k
R52
0
AIN3_GND
AIN5
1.00k
D7
DNP SMBJ14CA
14V
GND
R50
AIN1_GND
DNP
R47
0
GND
2
3
4
5
AIN0_GND
AIN0+
AIN1_GND
AIN1+
AIN2_GND
AIN2+
AIN3_GND
AIN3+
R46
AIN5+
C29
1000pF
1 AIN3+
8
7
6
5
4
3
2
1
AIN1
1.00k
D6
DNP SMBJ14CA
14V
R53
0
GND
GND
1 AIN4+
H13
MECH
1803633
2
3
4
5
DNP
AIN4
AIN4_GND
R54
AIN2+
R55
0
T3
AIN7+
AIN7_GND
AIN6+
AIN6_GND
AIN5+
AIN5_GND
AIN4+
AIN4_GND
R58
DNP
0
J6
1 AIN5+
AIN5
R56
AIN6+
R59
DNP
0
GND
AIN5_GND
AIN2GND
1.00k
C32
1000pF
R61
AIN6_GND
AIN6GND
1.00k
R62
0
R63
0
J7
1 AIN6+
DNP
2
3
4
5
H14
MECH
1803633
AIN6
1.00k
D9
DNP SMBJ14CA
14V
GND
R60
AIN2_GND
R57
0
C31
1000pF
DNP
2
3
4
5
1
2
3
4
5
6
7
8
AIN2
1.00k
D8
DNP SMBJ14CA
14V
AIN6
GND
R64
AIN3+
R65
0
J8
1 AIN7+
DNP
R68
DNP
0
2
3
4
5
AIN7
GND
AIN6_GND
AIN3
1.00k
D10
DNP SMBJ14CA
14V
R66
AIN7+
R69
DNP
0
C33
1000pF
R67
0
AIN7
1.00k
D11
DNP SMBJ14CA
14V
C34
1000pF
AIN7_GND
GND
GND
R70
AIN3_GND
1.00k
AIN3GND
R72
0
GND
R71
AIN7_GND
1.00k
AIN7GND
R73
0
GND
Figure 27. ADS8686SEVM-PDK Schematic
30
ADS8686SEVM-PDK Evaluation Module
SBAU319 – November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Bill of Materials, PCB Layout, and Schematics
www.ti.com
BIN0+
R74
R75
0
1.00k
2
3
4
5
GND
C36
1000pF
R127
0
J10
C47
0.1uF
4
R128
DNP
0
1 GND
R129
DNP
100k
3
U6
OPA192IDBVT
R132 -15V
10.0k
1 BIN1J+
GND
R80
BIN0_GND
BIN1+
BIN0GND
1.00k
R81
BIN4_GND
BIN4GND
1.00k
R82
0
R83
0
2
BIN0_GND
2
3
4
5
C48
0.1uF GND
GND
BIN1
14V
R79
DNP
0
BIN1+
5
BIN0
BIN4
1.00k
D13
DNP SMBJ14CA
C35
1000pF
+15V
R77
0
14V
R78
DNP
0
1 BIN0+
GND
GND
BIN1_GND
J11
1 BIN2J+
R130
+15V
BIN2
BIN2_GND
J12
1 BIN3+
T4
C50
0.1uF
R88
DNP
0
7
0
BIN2J_GND
R134
DNP
0 R135
DNP
0
U7
INA149AID
2
6
3
8
1
5
-15V
GND
R131
DNP
0
2
3
4
5
GND
BIN1
1.00k
R87
0
R89
DNP
0
C37
1000pF
GND
BIN5
1.00k
D15
DNP SMBJ14CA
14V
C38
1000pF
GND
R90
BIN1_GND
BIN1GND
1.00k
C51
0.1uF
R86
BIN5+
D14
DNP SMBJ14CA
14V
BIN2+
DNP
BIN3
R85
0
C49
1uF
4
2
3
4
5
R133
R84
BIN1+
BIN2+
0
DNP
BIN0+
BIN0_GND
BIN1J+
BIN1_GND
BIN2J+
BIN2J_GND
BIN3+
BIN3_GND
R76
BIN4+
D12
DNP SMBJ14CA
J9
1
2
3
4
5
6
7
8
BIN0
R91
BIN5_GND
C52
1uF
BIN5GND
1.00k
R92
0
R93
0
BIN3_GND
GND
GND
GND
J13
1 BIN4+
H15
MECH
1803633
2
3
4
5
DNP
BIN4
T5
BIN4+
BIN4_GND
BIN5+
BIN5_GND
BIN6+
BIN6_GND
BIN7+
BIN7_GND
R94
R95
0
1.00k
BIN2
R96
BIN6+
BIN6
1.00k
D17
DNP SMBJ14CA
14V
R98
DNP
0
14V
R99
DNP
0
C39
1000pF
J14
R97
0
D16
DNP SMBJ14CA
C40
1000pF
1 BIN5+
GND
DNP
2
3
4
5
1
2
3
4
5
6
7
8
BIN2+
BIN4_GND
BIN5
GND
R100
BIN2_GND
BIN2GND
1.00k
BIN5_GND
R101
BIN6_GND
BIN6GND
1.00k
R102
0
H16
MECH
1803633
R103
0
J15
1 BIN6+
GND
GND
2
3
4
5
DNP
BIN6
BIN6_GND
BIN3+
R104
R105
0
J16
1 BIN7+
R108
DNP
0
R106
BIN7+
R109
DNP
0
C41
1000pF
R107
0
BIN7
1.00k
D19
DNP SMBJ14CA
14V
C42
1000pF
2
3
4
5
DNP
BIN3
1.00k
D18
DNP SMBJ14CA
14V
BIN7
GND
BIN7_GND
GND
R110
BIN3_GND
1.00k
R112
0
GND
BIN3GND
R111
BIN7_GND
1.00k
BIN7GND
R113
0
GND
Figure 28. ADS8686SEVM-PDK Schematic
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
31
Bill of Materials, PCB Layout, and Schematics
T1
www.ti.com
Power for 5.5V to AVDD
DVDD
1
2
3
4
5V
EXT5V5
C17
10uF
AVDD
D1
INT
5.5V
GND
PWR
EVM_DVDD
EXT
DVDD
GND
External Power - High Voltage
JP7
1
2
3
TLV_5V5
5V5
EXT5V5
+15V
T6
1
2
3
R28
C18 GND
10uF
D2
-15V
HV PWR
0
GND
ZZ7
Assembly Note
on JP7 place jumper short on pin 2-3
For External DVDD 3.3V, remove resistor R28
GND
L1
DNP
5V
4.7uH
5V5
U2
RAW_5V
5
1
6
DNPC20
6.3V
10uF
IN
IN
13
EN
4
5
6
8
9
10
11
12
6P4V2
6P4V1
3P2V
1P6V
0P8V
0P4V
0P2V
0P1V
TLV_5V5
L
VIN
U3
15
16
VOUT
4
FB
2
DNP
EN
GND
R29
DNP
1.0M
3
C21
6.3V
10uF
DNPC22
6.3V
10uF
TPS61220DCKR
R30
DNP
100k
GND
GND
GND
OUT
OUT
SENSE
NR
1
20
C19
10V
22uF
3
14
GND
NC
NC
NC
NC
19
18
17
2
GND
PAD
7
21
C23
25V
1uF
TPS7A4700RGWR
GND
GND
TP1
GND
AVDD
TP2
GND
R33
2.7k
AVDD
TP3
5V5
TP4
AVDD
U4A
TP5
DVDD
2
C24
5V5
AVDD
DVDD
1uF
1
3
VIN
VOUT
TRIM/NR
TEMP
GND
GND
JP8
R31
6
5
R32
0.22
4
1
2
10.0k
REFINOUT
REFINOUT
REF5025AIDGKT
C25
GND
2
GND
GND
C26
10uF
1uF
D3
150080VS75000
Bright Green
GND
GND
Figure 29. ADS8686SEVM-PDK Schematic
32
ADS8686SEVM-PDK Evaluation Module
SBAU319 – November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Bill of Materials, PCB Layout, and Schematics
www.ti.com
RAW_5V
C43
10uF
GND
EVM_DVDD
J17
R114
R115
R116
R117
R118
R119
DB15/OS2
DB14/OS1
DB13/OS0
DB12/SDOA
DB11/SDOB
DB10/SDI
DB9/BYTESEL
DB8/FLTEN
DB7
DB6
DB5/CRCEN
DB4/SER1W
DB3
CS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
49.9
49.9
49.9
49.9
49.9
49.9
R121 49.9
R123 49.9
SCLK/RD
DB2
DB1
DB0
CONVST
D_HW_RNGSEL1
D_HW_RNGSEL0
EVM_ID_SDA
EVM_ID_SCL
MP1
MP2
REG_5V5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
GND
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
GND
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
GND
WR/BURST
BUSY
R120 49.9
R122
SEQEN
RESET
10.0k
SER/PAR/BYTE
D_CHSEL0
D_CHSEL1
D_CHSEL2
ID_PWR
DVDD
MP3
MP4
R124
100k
GND
GND
1
RESET
2
S1
R125
2.7k
C44
0.1uF
GND
J18
CONVST
D_CHSEL2
D_CHSEL0
SCLK/RD
DB15/OS2
DB13/OS0
DB11/SDOB
DB9/BYTESEL
DB7
DB5/CRCEN
DB3
DB1
SER/PAR/BYTE
D_HW_RNGSEL1
SEQEN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
BUSY
D_CHSEL1
CS
WR/BURST
DB14/OS1
DB12/SDOA
DB10/SDI
DB8/FLTEN
DB6
DB4/SER1W
DB2
DB0
ID_PWR
U5
D_HW_RNGSEL0
GND
GND
ID_PWR
C45
GND
16V
0.1uF
1
A0
VCC
8
2
A1
WP
7
3
A2
SCL
6
EVM_ID_SCL
VSS
SDA
5
EVM_ID_SDA
4
R126
10.0k
GND
JP9
1
2
C46
16V
0.1uF
5-146261-1
GND
BR24G32FVT-3AGE2
GND
GND
Figure 30. ADS8686SEVM-PDK Schematic
SBAU319 – November 2019
Submit Documentation Feedback
ADS8686SEVM-PDK Evaluation Module
Copyright © 2019, Texas Instruments Incorporated
33
Bill of Materials, PCB Layout, and Schematics
www.ti.com
H5
1891
H6
H7
H8
1891
1891
1891
H9
H10
9774050360R
9774050360R
H1
H2
H3
PMSSS 440 0025 PH
PMSSS 440 0025 PH PMSSS 440 0025 PH PMSSS 440 0025 PH
H12
H11
RM3X4MM 2701
RM3X4MM 2701
H4
SH-J1
FID1
FID2
FID3
382811-6
DNP
DNP
DNP
Fiducial
Fiducial
Fiducial
SH-J2
382811-6
SH-J3
PCB Number: DC029
PCB Rev: E1
PCB
LOGO
PCB
LOGO
Texas Instruments
FCC disclaimer
LOGO2
382811-6
SH-J4
Logo4
PCB
LOGO
CE Mark
382811-6
SH-J5
WEEE logo
382811-6
SH-J6
382811-6
SH-J7
LBL1
001
ADS8686SEVM-PDK
PCB Label
THT-14-423-10
Size: 0.65" x 0.20 "
382811-6
ZZ1
Assembly Note
This Assembly Note is for PCB labels only
ZZ2
Assembly Note
These assemblies are ESD sensitive, ESD precautions shall be observed.
ZZ3
Assembly Note
These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
ZZ4
Assembly Note
These assemblies must comply with workmanship standards IPC-A-610 Class 2, unless otherwise specified.
Figure 31. ADS8686SEVM-PDK Schematic
34
ADS8686SEVM-PDK Evaluation Module
SBAU319 – November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.
www.ti.com
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
2
www.ti.com
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
3
www.ti.com
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
4
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
www.ti.com
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
5
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising