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Texas Instruments ADS131M04 Evaluation Module (Rev. A) User guides
User's Guide
SBAU332A – March 2019 – Revised June 2019
ADS131M04 Evaluation Module
This user's guide describes the characteristics, operation, and use of the ADS131M04 evaluation module
(EVM). This kit is an evaluation platform for the ADS131M04, which is a 4-channel, simultaneouslysampling, 24-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC). The ADS131M04 offers wide
dynamic range and internal calibration features, making the device excellent for energy metering, power
quality, protection relay, and circuit breaker applications.
The ADS131M04EVM eases the evaluation of the device with hardware, software, and computer
connectivity through the universal serial bus (USB) interface. This user's guide includes complete circuit
descriptions, schematic diagrams, and a bill of materials. Throughout this document, the abbreviation EVM
and the term evaluation module are synonymous with the ADS131M04EVM. The following related
documents are available through the Texas Instruments web site at www.ti.com.
Table 1. Related Documentation
Device
Literature Number
ADS131M04
SBAS890
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1
2
3
4
5
6
7
Contents
EVM Overview ............................................................................................................... 4
EVM Analog Interface ....................................................................................................... 5
Digital Interface .............................................................................................................. 8
Power Supplies ............................................................................................................. 10
ADS131M04EVM Initial Setup ............................................................................................ 11
ADS131M04EVM Operation .............................................................................................. 14
ADS131M04EVM Bill of Materials, PCB Layout, and Schematic .................................................... 21
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
........................................................................................ 4
Input Terminal Blocks and Headers (Schematic) ........................................................................ 5
Input Terminal Blocks and Headers (PCB) ............................................................................... 6
CLKIN External Clock (PCB) ............................................................................................... 7
ADS131M04EVM Jumper Default Settings ............................................................................. 11
ADS131M04 Software Installation Prompts ............................................................................ 12
Device Driver Installation Wizard Prompts .............................................................................. 12
LabVIEW Run-Time Engine Installation ................................................................................. 13
ADS131M04EVM GUI Folder Post-Installation......................................................................... 14
ADS131M04EVM Hardware Setup and LED Indicators .............................................................. 14
Launch the EVM GUI Software........................................................................................... 15
EVM GUI Global Input Parameters ...................................................................................... 16
Register Map Configuration ............................................................................................... 17
Time Domain Display Tool Options ...................................................................................... 18
Spectral Analysis Tool ..................................................................................................... 19
Histogram Analysis Tool .................................................................................................. 20
Top Silkscreen .............................................................................................................. 24
Top Layer ................................................................................................................... 24
Ground Layer 1 ............................................................................................................. 24
Ground Layer 2 ............................................................................................................. 25
Bottom Layer................................................................................................................ 25
Bottom Silkscreen .......................................................................................................... 25
ADS131M04EVM Hardware Schematic ................................................................................. 26
ADS131M04EVM Main Schematic....................................................................................... 27
System Connection for Evaluation
List of Tables
2
1
Related Documentation ..................................................................................................... 1
2
Analog Input Terminal Blocks, J1–J4 ..................................................................................... 6
3
Analog Input Jumper Connection, JP1–JP4
4
CLKIN External Clock Options ............................................................................................. 7
5
PHI Connector Pin Functions .............................................................................................. 8
6
Digital Header Pins .......................................................................................................... 9
7
LaunchPad™ Pin Functions ................................................................................................ 9
8
Default Settings............................................................................................................. 11
9
ADS131M04EVM Bill of Materials
.............................................................................
.......................................................................................
ADS131M04 Evaluation Module
7
21
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Trademarks
LaunchPad, BoosterPack are trademarks of Texas Instruments.
Windows is a registered trademark of Microsoft.
LabVIEW is a trademark of National Instruments.
All other trademarks are the property of their respective owners.
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EVM Overview
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EVM Overview
The ADS131M04EVM is a platform for evaluating the performance of the ADS131M04, which is a 4channel, simultaneously-sampling, 24-bit, ΔΣ ADC. The evaluation kit includes the ADS131M04EVM
board and the precision host interface (PHI) controller board that enables the accompanying computer
software to communicate with the ADC over the USB for data capture and analysis.
The ADS131M04EVM board includes the ADS131M04 ADC and all the peripheral analog circuits and
components required to extract optimum performance from the ADC.
The PHI board primarily serves three functions:
• Provides a communication interface from the EVM to the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS131M04
• Supplies power to all active circuitry on the ADS131M04EVM board
1.1
ADS131M04EVM Kit
The ADS131M04 evaluation module kit includes the following features:
•
•
•
•
•
Hardware and software required for diagnostic testing as well as accurate performance evaluation of
the ADS131M04 ADC
USB powered—no external power supply is required
The PHI controller that provides a convenient communication interface to the ADS131M04 ADC over
USB 2.0 (or higher) for power delivery as well as digital input and output
Easy-to-use evaluation software for 64-bit Microsoft Windows® 7, Windows 8, and Windows 10
operating systems
The software suite includes graphical tools for data capture, histogram analysis, and spectral analysis.
This suite also has a provision for exporting data to a text file for post-processing.
Figure 1 illustrates an example system setup for evaluation.
ADS131M04EVM
PHI Board
A-to-Micro-B USB
Cable
ADS131M04
EVM GUI
Signal
Source
Included in kit
Figure 1. System Connection for Evaluation
1.2
ADS131M04EVM Board
The ADS131M04EVM board includes the following features:
• External signal source from differential pair headers
• Options to use external analog and digital power supplies
• Serial interface header for easy connection to the PHI controller
• Pin connections to monitor digital signals with a logic analyzer
• Onboard ultra-low noise low-dropout (LDO) regulator for excellent 3.3-V, single-supply regulation of all
analog circuits
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EVM Analog Interface
The ADS131M04EVM is designed for easy interfacing with analog sources. This section covers the details
of the front-end circuit including jumper configuration for different input test signals and board connectors
for signal sources.
2.1
ADC Analog Input Signal Path
Analog inputs to the EVM can be connected to either the terminal blocks or to the header pins associated
with each ADC channel. The 3x2 100-mil headers for each channel allow the user to configure the inputs
differentially depending on the signal to be measured. The screw terminal blocks can interface directly
with the leads of an external sensor input. Figure 2 shows the signal chain used for all four input channels
on the EVM and is used to describe the supported input options in Figure 3, Table 2, and Table 3.
External voltage inputs can be applied to J1 pins 1 and 3. For single-ended inputs, install a jumper on
either JP1[1-2] or JP1[5-6] to connect an input to the EVM ground. If the external voltage is applied
through a series resistor, R1 or R2 can be used to form a resistor divider by installing JP1[3-4] to support
higher voltage measurements. Input jumper connections are described in Table 2. Similarly, R17 and R18
can be installed to form a resistor divider with the series 49.9-Ω resistors on each input. An input must not
be applied such that the voltage on the input pins of the ADS131M04 exceeds the absolute maximum
ratings. See the ADS131M04 data sheet for details.
R1 and R2 also present a 2-kΩ differential load when all jumpers on JP1 are uninstalled. This load acts as
a burden resistor for a current transformer (CT) input. For single-ended measurements, the unused end of
the transformer secondary side can be tied to ground by installing the appropriate jumper on JP1.
R9, R10, and C9 form a differential low-pass filter with a –3-dB cutoff frequency of 1.594 MHz. The series
impedance is kept relatively low in order to maintain adequate total harmonic distortion (THD)
performance.
Figure 2. Input Terminal Blocks and Headers (Schematic)
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Pin 1
J1
Pin 2
Pin 3
Pin 1
J2
Pin 2
Pin 3
Pin 1
J3
Pin 2
Pin 3
Pin 1
J4
Pin 2
Pin 3
Figure 3. Input Terminal Blocks and Headers (PCB)
Table 2. Analog Input Terminal Blocks, J1–J4
Terminal Block
J1
J2
J3
J4
6
Pin
Function
ADS131M04 Input Pin
1
Channel 0 positive input
AIN0P
2
EVM ground
AGND and DGND
3
Channel 0 negative input
AIN0N
1
Channel 1 positive input
AIN1P
2
EVM ground
AGND and DGND
3
Channel 1 negative input
AIN1N
1
Channel 2 positive input
AIN2P
2
EVM ground
AGND and DGND
3
Channel 2 negative input
AIN2N
1
Channel 3 positive input
AIN3P
2
EVM ground
AGND and DGND
3
Channel 3 negative input
AIN3N
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Table 3. Analog Input Jumper Connection, JP1–JP4
Jumper
Position
Description
Connection for channel 0 analog inputs
JP1
[1-2]
Short positive input to ground
[3-4]
Connect both inputs to ground via 1-kΩ resistors (default)
[5-6]
Short negative input to ground
Connection for channel 1 analog inputs
JP2
[1-2]
Short positive input to ground
[3-4]
Connect both inputs to ground via 1-kΩ resistors (default)
[5-6]
Short negative input to ground
Connection for channel 2 analog inputs
JP3
[1-2]
Short positive input to ground
[3-4]
Connect both inputs to ground via 1-kΩ resistors (default)
[5-6]
Short negative input to ground
Connection for channel 3 analog inputs
JP4
2.2
[1-2]
Short positive input to ground
[3-4]
Connect both inputs to ground via 1-kΩ resistors (default)
[5-6]
Short negative input to ground
ADC External Clock (CLKIN) Options
The ADS131M04 requires a continuous, free-running external master clock at the CLKIN pin for normal
operation. The onboard complementary metal oxide semiconductor (CMOS) crystal oscillator (Y1)
provides the nominal 8.192-MHz clock frequency used in the high-resolution (HR) mode of the device.
Two D flip-flops (U3) divide the Y1 clock output to produce clock frequencies of 4.096 MHz and 2.048
MHz to support the low-power (LP) mode and very-low-power (VLP) mode, respectively.
Install a jumper in the appropriate position on the JP6 header shown in Figure 4 to provide selectable
clock frequency options. An external clock frequency can also be provided to any even-numbered pin on
JP6 when the jumper is uninstalled. TI also recommends powering down Y1 by installing JP5 when
providing an external clock. When using an external clock, ground must be shared between the external
clock source and the EVM ground. The external clock must adhere to the frequency and amplitude limits
outlined in the ADS131M04 data sheet. Table 4 lists the JP6 jumper settings for the clock input selections.
In addition to jumper settings, each of the power modes requires configuration register settings outlined in
Section 6.1.
Figure 4. CLKIN External Clock (PCB)
Table 4. CLKIN External Clock Options
J13 Jumper Setting
Clock Frequency
Description
[1-2]
8.192 MHz
Nominal clock for high-resolution mode (default)
[3-4]
4.096 MHz
Nominal clock for low-power mode
[5-6]
2.048 MHz
Nominal clock for very-low-power mode
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Digital Interface
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Digital Interface
As noted in Section 1, the EVM interfaces with the PHI and communicates with the computer over the
USB. There are two devices on the EVM with which the PHI communicates: the ADS131M04 ADC (over
SPI) and the EEPROM (over I2C). The EEPROM comes pre-programmed with the information required to
configure and initialize the ADS131M04EVM platform. When the hardware is initialized, the EEPROM is
no longer used.
3.1
SPI Communication
The ADS131M04EVM supports limited interface modes as detailed in the ADS131M04 data sheet. The
ADS131M04 uses an SPI-compatible interface to configure the device and retrieve conversion data. SPI
communication on the ADS131M04 is performed in frames. Each SPI communication frame consists of
several words. The word size is configurable as either 16 bits, 24 bits (default), or 32 bits by programming
the WLENGTH[1:0] bits in the MODE register.
Additionally, the DRDY pin indicates when conversion data are available to be read by the master. The
DRDY_SEL[1:0] bits, DRDY_HIZ bit, and the DRDY_FMT bit in the MODE register control the behavior of
the DRDY pin.
For this EVM not all modes and functions for this SPI communication are supported. Functions not
supported are disabled in the EVM GUI software. For more information about the SPI communication, see
the ADS131M04 data sheet.
3.2
Connection to the PHI
The ADS131M04EVM board communicates with the PHI through a shrouded, 60-pin connector, J5. There
are two round standoffs next to J5 with Phillips-head screws. To connect the PHI to the EVM, remove the
screws, attach the PHI to the EVM, and replace the screws into the standoffs. The screws secure the
EVM to the PHI and ensures the connection between the boards.
Table 5 lists the different PHI connection and their functions.
Table 5. PHI Connector Pin Functions
8
PHI Connector Pin Name
PHI Connector Pin
Function
EVM_RAW_5V
J5[2]
Power-supply source for the analog section of the EVM
GND
J5[3]
Ground
SYNC/RESET
J5[10]
Conversion synchronization or system reset for the
ADS131M04; active low
DIN
J5[18]
Serial data input for the ADS131M04
CLK
J5[20]
Master clock input for the ADS131M04
CS
J5[22]
Chip select for the ADS131M04; active low
SCLK
J5[24]
Serial data clock for the ADS131M04
SCLK
J5[28]
Serial data clock for the ADS131M04
DRDY
J5[30]
Data ready for the ADS131M04; active low
DOUT
J5[36]
Serial data output for the ADS131M04
EVM_DVDD
J5[50]
Power-supply source for the digital section of the EVM
SDA
J5[56]
I2C serial data for the EEPROM used to identify the EVM
SCL
J5[58]
I2C serial clock for the EEPROM used to identify the EVM
EVM_ID_PWR
J5[59]
Power-supply source for the EEPROM used to identify the EVM
GND
J5[60]
Ground
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3.3
Digital Header
In addition to the PHI, the EVM has a header connected to the digital lines that can be used to connect a
logic analyzer or oscilloscope. This placement allows for easy access to the digital communications.
Header J6 is connected to the digital lines between the ADS131M04 and the PHI connector. Table 6
describes the digital header pins.
Table 6. Digital Header Pins
3.4
ADS131M04 Pin Name
Digital Header Pin
SYNC/RESET
J6[1]
DIN
J6[2]
CLK
J6[3]
CS
J6[4]
SCLK
J6[5]
DRDY
J6[6]
DOUT
J6[7]
GND
J6[8]
LaunchPad™ Connectors
On the bottom side of the ADS131M04EVM board is a set of unpopulated surface-mount connectors (J7
and J8). When populated, these devices can be used to connect to a TI LaunchPad™ directly as a typical
BoosterPack™ plug-in module.
Connectors J7 and J8 are a set of 10x2, 100 mil connectors. As shown in Table 7, the pin numbers for J7
and J8 map to the pin numbers for a standard 40-pin LaunchPad™ connector.
Table 7. LaunchPad™ Pin Functions
ADS131M04EVM Connection
ADS131M04EVM (J7, J8)
LaunchPad™ Connection
+3.3V
J8[1]
Pin 1
SCLK
J8[7]
Pin 7
DOUT
J7[14]
Pin 14
DIN
J7[12]
Pin 15
GND
J7[2]
Pin 20
+5V
J8[2]
Pin 21
GND
J8[4]
Pin 22
DRDY
J7[7]
Pin 37
CS
J7[5]
Pin 38
SYNC/RESET
J7[3]
Pin 39
CLK
J7[1]
Pin 40
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Power Supplies
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Power Supplies
The PHI provides multiple power-supply options for the EVM, derived from the USB supply of the
computer.
The EEPROM on the ADS131M04EVM uses a 3.3-V power supply generated directly by the PHI. The
analog supply of the ADC is powered by the LP5907 onboard the EVM, which is a low-noise linear
regulator that uses the 5-V supply on the PHI to generate a cleaner 3.3-V output. The 3.3-V supply to the
digital section of the ADC is provided directly by an LDO on the PHI.
The power supply for each active component on the EVM is bypassed with a ceramic capacitor placed
close to that component. Additionally, the EVM layout uses thick traces or large copper fill areas, where
possible, between bypass capacitors and their loads to minimize inductance along the load current path.
As mentioned previously in Section 1, power to the EVM is supplied by the PHI through connector J5. For
information about PHI pins and the power connections, see Table 5.
With modifications, the user may use external supplies for either AVDD or DVDD. AVDD can be driven
externally by moving the jumper on JP9 to the left. This placement disconnects 3V3_LDO from AVDD.
Power can then be applied through the AVDD test point at TP2 or through 3V3_LP if connector J8 is
installed. DVDD can be driven externally from the DVDD test point at TP1 if R45 is removed from the
EVM.
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5
ADS131M04EVM Initial Setup
This section explains the initial hardware and software setup procedure that must be completed for
properly operating the ADS131M04EVM.
5.1
Default Jumper Settings
After unpacking, the EVM is already configured with the default jumper settings. Figure 5 shows the
locations for the default jumpers.
Figure 5. ADS131M04EVM Jumper Default Settings
The default position of the JP6 jumper is across [1-2] at the top. JP6 sets the onboard oscillator frequency
to 8.192 MHz, used for the ADS131M04 in high-resolution mode. The default connection for JP9 is to the
left, so that the linear regulator is powering the system using 5 V from the PHI controller.
The default settings, as listed in Table 8, includes no jumpers installed at JP5, JP7, and JP8. When
installed, JP5 disables the onboard oscillator, JP7 enables the EEPROM for write, and JP8 disables the
linear regulator.
Table 8. Default Settings
Jumper
5.2
Position
Function
JP1, JP2, JP3, JP4
[3-4]
JP5
Not installed
Sets common-mode to ground for device inputs
JP6
[1-2]
Oscillator frequency select, 8.192MHz
JP7
Open
Disables write for EEPROM
JP8
Not installed
JP9
[1-2]
Disables on-board oscillator
Disables linear regulator power
Selects device power from linear regulator
EVM Graphical User Interface (GUI) Software Installation
Download the latest version of the EVM GUI installer from the Tools and Software folder of the
ADS131M04EVM and run the GUI installer to install the EVM GUI software on your computer.
CAUTION
Manually disable any antivirus software running on the computer before
downloading the EVM GUI installer onto the local hard disk. Depending on the
antivirus settings, an error message may appear or the installer. The exe file
can be deleted.
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Accept the license agreements and follow the on-screen instructions shown in Figure 6 to complete the
installation.
Figure 6. ADS131M04 Software Installation Prompts
As a part of the ADS131M04EVM GUI installation, a prompt with a Device Driver Installation (as shown in
Figure 7) appears on the screen. Click Next to proceed.
Figure 7. Device Driver Installation Wizard Prompts
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NOTE: A notice may appear on the screen stating that Windows cannot verify the publisher of this
driver software. Select Install this driver software anyway.
The ADS131M04EVM requires the LabVIEW™ run-time engine and may prompt for the installation of this
software, as shown in Figure 8, if not already installed.
Figure 8. LabVIEW Run-Time Engine Installation
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Verify that C:\Program Files (x86)\Texas Instruments\ADS131M04EVM is as shown in Figure 9 after these
installations.
Figure 9. ADS131M04EVM GUI Folder Post-Installation
6
ADS131M04EVM Operation
The following instructions are a step-by-step guide to connecting the ADS131M04EVM to the computer
and evaluating the performance of the ADS131M04:
1. Connect the ADS131M04EVM to the PHI. Install the two screws as indicated in Figure 10.
2. Use the provided USB cable to connect the PHI to the computer.
• LED D5 on the PHI lights up, indicating that the PHI is powered up
• LEDs D1 and D2 on the PHI start blinking to indicate that the PHI is booted up and communicating
with the PC; Figure 10 shows the resulting LED indicators
INSTALL
D5
D2
D1
Figure 10. ADS131M04EVM Hardware Setup and LED Indicators
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3. Figure 11 shows how to launch the ADS131M04EVM GUI software.
Figure 11. Launch the EVM GUI Software
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6.1
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EVM GUI Global Settings for ADC Control
Although the EVM GUI does not allow direct access to the levels and timing configuration of the ADC
digital interface, the EVM GUI does give users high-level control over virtually all functions of the
ADS131M04 including interface modes, sampling rate, and number of samples to be captured. Figure 12
identifies the input parameters of the GUI (as well as their default values) through which the various
functions of the ADS131M04 can be exercised.
1. Information Area
2. Pages
3. Single
Commands
4. Interface
Configuration
5. Clock and
Sampling Rate
Figure 12. EVM GUI Global Input Parameters
There are four pages available in the ADS131M04EVM GUI. The information area displays the results of
each of the pages. Each of these pages display a different control or measurement of the device. The
Register Map Config page is used to read and write to the registers of the device. The Time Domain
Display page is used to collect a set of data from the device and display the result. The Spectral Analysis
page can determine the FFT of the collected data, and the Histogram Analysis page shows a histogram of
the collected data and displays basic statistics of the result.
The Single Commands section allows for direct control of the device for three basic functions. First the
Reset button sends a signal to the SYNC/RESET pin to reset the device. The Standby button puts the
device into a low-power state in which all channels are disabled, and the reference and other nonessential circuitry are powered down. The Wakeup button exits the standby mode.
The Interface Configuration options in this pane allows the user to choose from different frame word sizes
available on the ADS131M04. This section also sets the data rate by setting the oversampling ratio (OSR)
in the ADC. Finally, this section may used to set the power modes in the registers. The ADS131M04 can
be set to high-resolution, low power, and very-low power modes in conjunction with the jumper settings of
JP6 for the CLKIN pin, as outlined in Table 4. This information is also discussed in Section 2.2.
The Clock and Sampling Rate section allows the user to specify a target SCLK frequency (in Hz) and the
GUI tries to match this frequency as closely as possible by changing the PHI PLL settings, but the
achievable frequency may differ from the target value entered. This section also displays the sampling
rate of the ADC as controlled by the OCR.
The GUI is switched between hardware mode and simulation mode by checking and unchecking the
Connected to Hardware box in the top right area of the screen at any time.
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6.2
Register Map Configuration Tool
The register map configuration tool allows the user to view and modify the registers of the ADS131M04.
This tool can be selected, as indicated in Figure 13, by clicking on the Register Map Config radio button at
the Pages section of the left pane. On power-up, the values on this page correspond to the Host
Configuration Settings that enable ADC sampling at the maximum sampling rate specified for the ADC.
The register values can be edited by double-clicking the corresponding value field. If interface mode
settings are affected by the change in register values, this change reflects on the left pane immediately.
The changes in the register value reflect on the AD131M04 device on the ADS131M04EVM based on the
Update Mode selection, as described in Section 6.1.
Figure 13. Register Map Configuration
Section 6.3 through Section 6.5 describe the data collection and analysis features of the ADS131M04EVM
GUI.
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6.3
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Time Domain Display Tool
The time domain display tool allows visualization of the ADC response to a given input signal. This tool is
useful for both studying the behavior and debugging any gross problems with the ADC or drive circuits.
The user can trigger a capture of the data of the selected number of samples from the ADS131M04EVM,
as per the current interface mode settings indicated in Figure 14 by using the Capture button. The sample
indices are on the x-axis and there are two y-axes showing the corresponding output codes as well as the
equivalent analog voltages based on the specified reference voltage. Switching pages to any of the
Analysis tools described in the subsequent sections causes calculations to be performed on the same set
of data.
Figure 14. Time Domain Display Tool Options
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6.4
Spectral Analysis Tool
The spectral analysis tool, shown in Figure 15, is intended to evaluate the dynamic performance (SNR,
THD, SFDR, SINAD, and ENOB) of the ADS131M04 ADC through single-tone sinusoidal signal FFT
analysis using the 7-term Blackman-Harris window setting.
Figure 15. Spectral Analysis Tool
The FFT tool includes windowing options that are required to mitigate the effects of non-coherent
sampling (this discussion is beyond the scope of this document). The 7-Term Blackman Harris window is
the default option and has sufficient dynamic range to resolve the frequency components of up to a 24-bit
ADC. The None option corresponds to not using a window (or using a rectangular window) and is not
recommended.
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ADS131M04EVM Operation
6.5
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Histogram Tool
Noise degrades ADC resolution and the histogram tool can be used to estimate effective resolution, which
is an indicator of the number of bits of ADC resolution losses resulting from noise generated by the
various sources connected to the ADC when measuring a DC signal. The cumulative effect of noise
coupling to the ADC output from sources such as the input drive circuits, the reference drive circuit, the
ADC power supply, and the ADC itself is reflected in the standard deviation of the ADC output code
histogram that is obtained by performing multiple conversions of a DC input applied to a given channel.
As shown in Figure 16, the histogram corresponding to a DC input is displayed on clicking the Capture
button.
Figure 16. Histogram Analysis Tool
20
ADS131M04 Evaluation Module
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ADS131M04EVM Bill of Materials, PCB Layout, and Schematic
www.ti.com
7
ADS131M04EVM Bill of Materials, PCB Layout, and Schematic
7.1
Bill of Materials
Table 9 lists the ADS131M04EVM bill of materials.
Table 9. ADS131M04EVM Bill of Materials
Designator
Quantity
Value
Description
Package
Reference
Part Number
Manufacturer
C9, C10, C11,
C12
4
1000pF
CAP, CERM, 1000 pF, 25 V, +/- 5%, C0G/NP0,
0603
0603
GRM1885C1E102JA01D
MuRata
C13, C14,
C16, C17
4
1uF
CAP, CERM, 1 uF, 25 V, +/- 10%, X7R, 0603
0603
C0603C105K3RACTU
Kemet
C15, C18,
C19, C21,
7
C22, C27, C28
0.1uF
CAP, CERM, 0.1 uF, 25 V, +/- 5%, X7R, 0603
0603
C0603C104J3RAC
Kemet
C20
1
10pF
CAP, CERM, 10 pF, 50 V, +/- 5%, C0G/NP0,
0603
0603
C0603C100J5GACTU
Kemet
C23, C24
2
10uF
CAP, CERM, 10 uF, 25 V, +/- 10%, X7R,
1206_190
1206_190
C1206C106K3RACTU
Kemet
H1, H2
2
Machine Screw Pan PHILLIPS M3
RM3X4MM 2701
APM HEXSEAL
H3, H4
2
ROUND STANDOFF M3 STEEL 5MM
9774050360R
Wurth Elektronik
SJ-5303 (CLEAR)
3M
102-1092-BL-00100
CnC Tech
Transparent
Bumpon
H5, H6, H7, H8 4
Bumpon, Hemisphere, 0.44 X 0.20, Clear
H9
1
Cable, USB-A to micro USB-B, 1 m - Kitting item
H10
1
PHI-EVM Controller Kitting item Edge# 6591636
PA007
Texas Instruments
J1, J2, J3, J4
4
Terminal Block, 3.5mm Pitch, 3x1, TH
10.5x8.2x6.5mm
ED555/3DS
On-Shore Technology
QTH-030-01-L-D-A
Samtec
J5
1
Header(Shrouded), 19.7mil, 30x2, Gold, SMT
Header
(Shrouded),
19.7mil, 30x2,
SMT
J6
1
Header, 100mil, 8x1, Gold, TH
8x1 Header
TSW-108-07-G-S
Samtec
JP1, JP2, JP3,
JP4, JP6
5
Header, 100mil, 3x2, Gold, TH
3x2 Header
TSW-103-07-G-D
Samtec
JP7
1
Header, 100mil, 2x1, Gold, TH
2x1 Header
TSW-102-07-G-S
Samtec
JP9
1
Header, 100mil, 3x1, Gold, TH
3x1 Header
TSW-103-07-G-S
Samtec
R1, R2, R3,
R4, R5, R6,
R7, R8
8
1.00k
RES, 1.00 k, 1%, 0.1 W, AEC-Q200 Grade 0,
0603
0603
CRCW06031K00FKEA
Vishay-Dale
49.9
RES, 49.9, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 0603
CRCW060349R9FKEA
Vishay-Dale
R9, R10, R11,
R12, R13,
8
R14, R15, R16
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Table 9. ADS131M04EVM Bill of Materials (continued)
Designator
Quantity
Value
Package
Reference
Description
Part Number
Manufacturer
R25, R26,
R34, R35
4
100k
RES, 100 k, 1%, 0.1 W, AEC-Q200 Grade 0,
0603
0603
CRCW0603100KFKEA
Vishay-Dale
R27
1
10.0
RES, 10.0, 1%, 0.25 W, AEC-Q200 Grade 0,
0603
0603
CRCW060310R0FKEAHP
Vishay-Dale
0
RES, 0, 5%, 0.1 W, 0603
0603
RC0603JR-070RL
Yageo
R28,
R30,
R32,
R38,
R43,
R29,
R31,
R33,
11
R39,
R45, R46
R36, R37
2
0.1
RES, 0.1, 1%, 0.1 W, AEC-Q200 Grade 1, 0603
0603
ERJ-L03KF10CV
Panasonic
R40
1
10k
RES, 10 k, 5%, 0.1 W, 0603
0603
RC1608J103CS
Samsung Electro-Mechanics
SH-J1, SH-J2,
SH-J3, SH-J4,
SH-J5, SH-J6
6
1x2
Shunt, 100mil, Flash Gold, Black
Closed Top 100mil
SPC02SYAN
Shunt
Sullins Connector Solutions
TP1, TP2
2
Test Point, Miniature, SMT
Testpoint
Keystone
Miniature
5015
Keystone
TP3, TP4,
TP5, TP6
4
Terminal, Turret, TH, Double
Keystone1573-2
1573-2
Keystone
U1
1
250-mA Ultra-Low-Noise, Low-IQ LDO,
DBV0005A (SOT-23-5)
DBV0005A
LP5907MFX-3.3/NOPB
Texas Instruments
U2
1
4-Channel, 24-Bit, Simultaneously-Sampling,
Delta-Sigma ADC, PW0020A (TSSOP-20)
PW0020A
ADS131M04IPWT
Texas Instruments
U3
1
Low-Power Dual Positive-Edge-Triggered D-Type
DCU0008A
Flip-Flop, DCU0008A (VSSOP-8)
SN74AUP2G80DCUR
Texas Instruments
U4
1
I2C BUS EEPROM (2-Wire), TSSOP-B8
TSSOP-8
BR24G32FVT-3AGE2
Rohm
Y1
1
Oscillator, 8.192 MHz, 15 pF, AEC-Q200 Grade
1, SMD
3.2x2.5mm
SIT8924BA-22-33E-8.192000G
SiTime
C1, C2, C3,
C4, C5, C6,
C7, C8
0
0.01uF
CAP, CERM, 0.01 uF, 25 V, +/- 5%, C0G/NP0,
0603
0603
C0603H103J3GACTU
Kemet
C25, C26
0
10uF
CAP, CERM, 10 uF, 25 V, +/- 10%, X7R,
1206_190
1206_190
C1206C106K3RACTU
Kemet
FID1, FID2,
FID3
0
Fiducial mark. There is nothing to buy or mount.
N/A
N/A
N/A
J7, J8
0
Connector, Receptacle, 100mil, 10x2, Gold
plated, SMD
10x2 Receptacle
SSW-110-22-F-D-VS-K
Samtec
JP5, JP8
0
Header, 100mil, 2x1, Gold, TH
2x1 Header
TSW-102-07-G-S
Samtec
22
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Table 9. ADS131M04EVM Bill of Materials (continued)
Designator
R17,
R19,
R21,
R23,
R18,
R20,
R22,
R24
Quantity
0
R41, R42, R44 0
TP7, TP8,
TP9, TP10
Value
Description
Package
Reference
Part Number
Manufacturer
1.00k
RES, 1.00 k, 1%, 0.1 W, AEC-Q200 Grade 0,
0603
0603
CRCW06031K00FKEA
Vishay-Dale
0
RES, 0, 5%, 0.1 W, 0603
0603
RC0603JR-070RL
Yageo
Terminal, Turret, TH, Double
Keystone1573-2
1573-2
Keystone
0
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ADS131M04EVM Bill of Materials, PCB Layout, and Schematic
7.2
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PCB Layout
Figure 17 through Figure 22 illustrate the ADS131M04EVM PCB layout.
Figure 17. Top Silkscreen
Figure 18. Top Layer
Figure 19. Ground Layer 1
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ADS131M04EVM Bill of Materials, PCB Layout, and Schematic
Figure 20. Ground Layer 2
Figure 21. Bottom Layer
Figure 22. Bottom Silkscreen
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ADS131M04EVM Bill of Materials, PCB Layout, and Schematic
7.3
www.ti.com
Schematic
Figure 23 and Figure 24 illustrate the ADS131M04EVM schematics.
Figure 23. ADS131M04EVM Hardware Schematic
26
ADS131M04 Evaluation Module
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Clock Tree
5V -> 3V3 Analog LDO
DVDD
3V3_LDO
AVDD
Y1
C22
0.1uF JP5
R26
100k
4
1
DNP2
1
CLOCK OUT
VDD
OE
GND
EVM_DVDD
3
2
R43
0
8.192MHz
GND
GND
/OSC_EN
GND
8
GND
VCC
R44
DNP
0
8.192MHz
C21
0.1uF
4
5
6
GND
U3C
DVDD
TP1
R46
0
0
1
C16
1uF
1
2D
2Q
3
4.096MHz
1Q
7
2.048MHz
3
R1
1.00k
GND
JP1
1
3
5
2
4
6
1D
LP5907MFX-3.3/NOPB
J5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
ADC_DIGITAL.SYNC/RESET
R2
1.00k
GND
R10
R18
GND
DN1.00k
P
DNPC2
0.01uF
R3
1.00k
1
2
3
GND
49.9
JP2
1
3
5
2
4
6
R4
1.00k
C14
1uF
R19 DNPC3
DN1.00k
P
0.01uF
C15
0.1uF
2
C10
1000pF
GND
3
4
R20
GND
DN1.00k
P
DNPC4
R12
0.01uF
DNP TP10
D-
U2
1
R11
GND
AVDD
DVDD
AGND
DGND
AIN0P
AIN0N
VCAP
CLKIN
5
6
49.9
AIN1N
AIN1P
DIN
DOUT
R13
R5
1.00k
J3
1
2
3
GND
49.9
JP3
1
3
5
2
4
6
R6
1.00k
7
8
R21 DNPC5
DN1.00k
P
0.01uF
AIN2P
AIN2N
SCLK
DRDY
C11
1000pF
9
10
GND R22
GND
DN1.00k
P
DNPC6
R14
0.01uF
AIN3N
AIN3P
CS
SYNC/RESET
R7
1.00k
GND
R8
1.00k
49.9
JP4
1
3
5
2
4
6
C18
0.1uF
C17
1uF
GND
C19
0.1uF
ADC_DIGITAL.DIN
ADC_DIGITAL.CLK
ADC_DIGITAL.CS
ADC_DIGITAL.SCLK
ADC_DIGITAL.DRDY
ADC_DIGITAL.DOUT
GND
C20
10pF
19
18
GND
17
16
15
14
13
12
11
R28
EVM_DVDD
R38
0
DIN
0
R29
R30
0
C23
10uF
DOUT
SCLK
0
R31
R32
0
0
R33
ADC_DIGITAL
DRDY
EVM_ID_SDA
EVM_ID_SCL
GND
MP1
MP2
SYNC/RESET
R16
EVM_ID_PWR
R39
0
MP3
MP4
C24
10uF
GND
EVM_ID_PWR
U4
TP3 TP4 TP5 TP6
1
2
GND
DNPC8
0.01uF
GND
GND
EVM_ID_PWR
R24
DN1.00k
P
GND
GND
GND
C12
1000pF
GND
GND
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
R35
100k
DVDD
R23 DNPC7
DN1.00k
P
0.01uF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
CS
R34
100k
R15
1
2
3
R27
10.0
1
2
3
4
5
6
7
8
20
0
ADS131M04IPWT
49.9
J4
ADC_DIGITAL.SYNC/RESET
ADC_DIGITAL.DIN
ADC_DIGITAL.CLK
ADC_DIGITAL.CS
ADC_DIGITAL.SCLK
ADC_DIGITAL.DRDY
ADC_DIGITAL.DOUT
DNP TP9
D+
R37
0.1
ADS131M04
DNP TP8
A-
49.9
J2
DVDD
DNP TP7
A+
R36
0.1
C9
1000pF
GND
EVM_RAW_5V
J6
AVDD
R17 DNPC1
DN1.00k
P
0.01uF
C13
1uF
Digital Interface
R9
1
2
3
2
1CLK
Analog Inputs
J1
GND
GND
U3A
49.9
JP9
1
2
3
GND
2
4
6
U3B
2
5
N/C
GND
1
VOUT
EN
4
/LDO_EN
1
3
5
VIN
DNP2
JP6
2CLK
R25
100k
JP8
ADC_DIGITAL.CLK
3V3_LP
TP2
U1
EVM_RAW_5V
R45
3
GND
4
49.9
EVM_ID_PWR
C27
R40
A0
VCC
A1
WP
A2
SCL
VSS
SDA
8
GND
7
6
5
10k
0.1uF
EEPROM_EN
1
2
EVM_ID_SCL
EVM_ID_SDA
C28
0.1uF
JP7
GND
BR24G32FVT-3AGE2
GND
EVM_DVDD
R41
DNP
0
3V3_LP
5V_LP
J8
DNPC25
10uF
GND
ADC_DIGITAL.SCLK
1
3
5
7
9
11
13
15
17
19
DNP
2
4
6
8
10
12
14
16
18
20
DNPC26
10uF
GND
EVM_RAW_5V
R42
DNP
0
GND
J7
ADC_DIGITAL.CLK
ADC_DIGITAL.SYNC/RESET
ADC_DIGITAL.CS
ADC_DIGITAL.DRDY
1
3
5
7
9
11
13
15
17
19
DNP
2
4
6
8
10
12
14
16
18
20
GND
ADC_DIGITAL.DIN
ADC_DIGITAL.DOUT
Figure 24. ADS131M04EVM Main Schematic
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Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2019) to A Revision ....................................................................................................... Page
•
28
Changed document to align with new evaluation module
...........................................................................
Revision History
1
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Copyright © 2019, Texas Instruments Incorporated
STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.
www.ti.com
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
2
www.ti.com
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
3
www.ti.com
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
4
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
www.ti.com
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
5
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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