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Texas Instruments ADS9224REVM-PDK (Rev. A) User guides
User's Guide
SBAU315A – July 2018 – Revised June 2019
ADS9224REVM-PDK
This user's guide describes the characteristics, operation, and use of the ADS9224R evaluation module
(EVM) performance demonstration kit (PDK). The EVM-PDK eases the evaluation of the ADS9224R
device with hardware, software, and computer connectivity through a universal serial bus (USB) interface.
Throughout this document, the terms evaluation board, evaluation module, and EVM are synonymous with
the ADS9224REVM-PDK. This user's guide includes complete circuit descriptions, schematic diagrams,
and a bill of materials.
The following related documents are available through the Texas Instruments web site at www.ti.com.
Related Documentation
Device
Literature Number
ADS9224R
SBAS876
THS4551
SBOS778
REF5025
SBOS410
TPS7A4700
SBVS204
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Contents
Overview ...................................................................................................................... 4
1.1
ADS9224REVM-PDK Features ................................................................................... 4
1.2
ADS9224REVM Features ......................................................................................... 4
Analog Interface.............................................................................................................. 5
2.1
Connectors for Signal Source ..................................................................................... 5
2.2
ADC Differential Input Signal Driver .............................................................................. 5
2.3
ADS9224R Internal Reference ................................................................................... 7
Digital Interfaces ............................................................................................................. 7
3.1
multiSPI™ for ADC Digital IO ..................................................................................... 7
Power Supplies .............................................................................................................. 8
Setup .......................................................................................................................... 9
5.1
Default Jumper Settings ........................................................................................... 9
5.2
EVM Graphical User Interface (GUI) Software Installation .................................................. 10
Operation .................................................................................................................... 13
6.1
EVM GUI Global Settings for ADC Control .................................................................... 14
6.2
Register Map Configuration Tool ................................................................................ 15
6.3
Time Domain Display Tool ....................................................................................... 16
6.4
Spectral Analysis Tool ............................................................................................ 17
6.5
Histogram Tool .................................................................................................... 18
ADS9224REVM Bill of Materials, PCB Layout, and Schematics .................................................... 19
7.1
Bill of Materials .................................................................................................... 19
7.2
PCB Layout ........................................................................................................ 23
7.3
Schematics ......................................................................................................... 26
List of Figures
................................................................................. 6
............................................................................. 6
ADS9224REVM-PDK Jumper Locations ................................................................................. 9
ADS9224R Software Installation Prompts .............................................................................. 10
Device Driver Installation Wizard Prompts .............................................................................. 10
LabVIEW Run-Time Engine Installation ................................................................................. 11
ADS9224REVM-PDK Folder Post-Installation.......................................................................... 12
EVM-PDK Hardware Setup and LED Indicators ....................................................................... 13
Launch the EVM GUI Software........................................................................................... 13
EVM GUI Global Input Parameters ...................................................................................... 14
Register Map Configuration ............................................................................................... 15
Time Domain Display Tool Options ...................................................................................... 16
Spectral Analysis Tool ..................................................................................................... 17
Histogram Analysis Tool .................................................................................................. 18
ADS9224REVM PCB Top Overlay ...................................................................................... 23
ADS9224REVM PCB Layer 1: Top Layer .............................................................................. 23
ADS9224REVM PCB Layer 2: GND Plane ............................................................................. 24
ADS9224REVM PCB Layer 3: Power Planes .......................................................................... 24
ADS9224REVM PCB Layer 4: Bottom Layer .......................................................................... 25
ADS9224REVM Schematic Diagram 1 .................................................................................. 26
ADS9224REVM Schematic Diagram 2 .................................................................................. 27
1
THS4551 Differential Input Driving Path
2
THS4551 Fully-Differential Amplifier Driver
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4
5
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7
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14
15
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17
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21
List of Tables
2
1
J2 to J5 SMA Analog Interface Connections ............................................................................. 5
2
JP1 to JP4 Header Descriptions ........................................................................................... 5
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3
4
5
6
7
.............................................................................................................. 7
Power-Supply Test Points .................................................................................................. 8
Default Jumper Configurations ............................................................................................. 9
External Source Requirements for Evaluation of the ADS9224R.................................................... 17
ADS9224REVM Bill of Materials ......................................................................................... 19
SPI Test Points
Trademarks
multiSPI is a trademark of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation.
LabVIEW is a trademark of National Instruments.
All other trademarks are the property of their respective owners.
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Overview
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Overview
The ADS9224REVM-PDK is an evaluation platform for the ADS9224R, a dual, simultaneous-sampling, 16bit, 3-MSPS, fully-differential input successive approximation register (SAR) analog-to-digital converter
(ADC). The ADS9224R features an enhanced serial multiSPI™ digital interface. The evaluation kit
includes the ADS9224REVM board and the Precision Host Interface (PHI) controller board that enables
the accompanying computer software to communicate with the ADC using a USB interface for data
capture and analysis.
The ADS9224REVM board includes the ADS9224R SAR ADC, all the peripheral analog circuits, and
components required to extract optimum performance from the ADC.
The PHI board primarily serves three functions:
• Provides a communication interface from the EVM to the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS9224R
• Supplies power to all active circuitry on the ADS9224REVM-PDK board
Along with the ADS9224REVM and PHI controller board, this evaluation kit includes an A-to-micro-B USB
cable to connect to a computer.
1.1
ADS9224REVM-PDK Features
The ADS9224REVM-PDK includes the following features:
• Hardware and software required for diagnostic testing as well as accurate performance evaluation of
the ADS9224R ADC
• USB powered—no external power supply is required
• A PHI controller that provides a convenient communication interface to the ADS9224R ADC over USB
2.0 (or higher) for power delivery as well as digital input and output
• Easy-to-use evaluation software for Windows® 7, 8, and 10, 64-bit operating systems
• The software suite includes graphical tools for data capture, histogram analysis, spectral analysis,
linearity analysis, and reference settling analysis. This suite also has a provision for exporting data to a
text file for post-processing.
1.2
ADS9224REVM Features
The ADS9224REVM includes the following features:
• Onboard low-noise and low distortion ADC fully-differential amplifier input drivers optimized to meet
ADC performance
• Onboard ultra-low-noise, low-dropout (LDO) regulator for excellent, 5-V single-supply regulation of the
voltage reference and all the fully-differential amplifier input drivers
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2
Analog Interface
The ADS9224R is a dual-channel, simultaneous-sampling ADC that supports fully-differential inputs. Each
channel of the ADS9224R uses a THS4551 fully-differential amplifier (FDA) to drive the differential inputs
of the ADC. This section covers driver details and board connections for a differential signal source.
2.1
Connectors for Signal Source
The ADS9224REVM is designed for easy interfacing to multiple analog sources. SMA connectors allow
the EVM to have input signals connected through coaxial cables. In addition, header connectors JP1
through JP4 provide a convenient way to connect input signals. All analog inputs are buffered by the
THS4551 high-speed FDA in order to properly drive the ADS9224R ADC inputs.
Table 1. J2 to J5 SMA Analog Interface Connections
Pin Number
Signal
Description
J2
AIN-_A
CHA negative differential input. This SMA connector can be grounded by
installing a shunt on JP1 for single-ended signals.
1-kΩ input impedance
J3
AIN+_A
CHA positive differential input or input for single-ended signals.
1-kΩ input impedance
J4
AIN+_B
CHB positive differential input or input for single-ended signals.
1-kΩ input impedance
J5
AIN-_B
CHB negative differential input. This SMA connector can be grounded by
installing a shunt on JP4 for single-ended signals.
1-kΩ input impedance
Table 2. JP1 to JP4 Header Descriptions
Pin Number
2.2
Signal
Description
JP1.1
AIN-_A
CHA negative differential input. This SMA connector can be grounded by
installing a shunt on JP1 for single-ended signals.
1-kΩ input impedance.
JP2.1
AIN+_A
CHA positive differential input or input for single-ended signals.
1-kΩ input impedance.
JP3.1
AIN+_B
CHB positive differential input or input for single-ended signals.
1-kΩ input impedance.
JP4.1
AIN-_B
CHB negative differential input. This SMA connector can be grounded by
installing a shunt on JP4 for single-ended signals.
1-kΩ input impedance.
ADC Differential Input Signal Driver
The analog inputs of the ADS9224R SAR ADC are not high-impedance but rather present a dynamic load
as the sample-and-hold switches open and close. The current demand of the SAR ADC input increases as
a function of the sampling rate. Thus, the evaluation board provides the THS4551 FDA driver that
maintains ADC performance with maximum loading at the full device throughput of 3 MSPS.
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Analog Interface
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Input Signal Path
Figure 1 shows the signal path for the differential signal applied at the board inputs. The board input
impedance is 1 kΩ. The overall signal-path bandwidth is limited to 1.5-MHz by the 1-kΩ resistor and 100pF capacitor at the FDA feedback. The two THS4551 FDAs drive the ADS9224R differential inputs
through an RC charge-kickback filter. These drivers provide a low dynamic impedance source at the ADC
inputs at the full throughput of 3 MSPS.
AIN-_A
SMA J2 (IN-)
THS4551: Fully-Differential Amplifier
100 pF
ADS9224x
4.32 Ÿ
1 NŸ
Header JP1.1
5V
+
-
AIN+_A
SMA J3 (IN+)
AINP_A (Pin 1)
1 NŸ
+
3300pF
1 NŸ
1 NŸ
AINM_A (Pin 2)
4.32 Ÿ
100 pF
Header JP2.1
SMA J4 (IN+)
AIN+_B
THS4551: Fully-Differential Amplifier
100 pF
4.32 Ÿ
1 NŸ
Header JP3.1
5V
+
AIN-_B
-
SMA J5 (IN-)
1 NŸ
1 NŸ
AINM_B (Pin 7)
+
3300pF
1 NŸ
AINP_B (Pin 8)
4.32 Ÿ
100 pF
Header JP4.1
Figure 1. THS4551 Differential Input Driving Path
The ADS92x4REVM incorporates two THS4551 FDAs to drive the ADC inputs. The FDAs shift the signal
to the appropriate common-mode voltage level. Figure 2 shows the fully-differential amplifier circuit. A
differential input signal with a common-mode voltage of 0 V is applied to the inputs of the THS4551. The
FDA establishes a fixed common-mode voltage at the ADC inputs using the FDA VOCM input pin. The
ADS9224R incorporates a REF / 2 buffer output pin for setting the common-mode voltage. The
ADS9224R REF / 2 output is connected to each THS4551 VOCM input pin. The THS4551 shifts the signal
to the required common-mode voltage of REF / 2. Because of the THS4551 output swing specification to
GND, either the input signals must be limited to a differential voltage of ±3.876 V amplitude in order to
avoid saturating the amplifier output, or the negative supply must be driven below GND (in other words,
–200 mV) to extend the output range.
100 pF
1k
+1.828 V
A0(-) 0 V
-1.828 V
+1.828 V
A0(+) 0 V
-1.828 V
1k
1k
4.32
0.22 V
AINP
5V
+
VOCM = REF/2
2.048V
3.876 V
2.048 V
10
+
3300 pF
THS4551
-
10
4.32
1k
100 pF
+3.876 V
0V
-3.876
V
AINN
3.876 V
2.048 V
0.22 V
FSR_ADC
±VREF =
±4.096V
Figure 2. THS4551 Fully-Differential Amplifier Driver
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2.3
ADS9224R Internal Reference
The ADS9224R device incorporates an internal 2.5-V band-gap reference and independently matched
reference buffers for each ADC. The internal reference output pin (REFOUT) is decoupled with a 1-µF
capacitor and can be probed at test point TP8. The internally matched reference buffers provide a gain of
1.6384 V/V. These reference buffers generate a high-precision, 4.096-V reference voltage for each ADC
channel at pins REFP_A and REFP_B. These pins are decoupled with 10-µF decoupling capacitors.
Additionally, a mid-reference output (REFby2) is available at test point TP5. This internal REFby2 buffer
provides a common-mode voltage for input amplifiers driving the ADC inputs.
3
Digital Interfaces
As noted in Section 1, the EVM interfaces with the PHI that, in turn, communicates with the computer
using the USB interface. There are two devices on the EVM that communicate with the PHI: the
ADS9224R ADC (over SPI or multiSPI) and the EEPROM (over I2C). The EEPROM comes
preprogrammed with the information required to configure and initialize the ADS9224REVM-PDK platform.
After the hardware is initialized, the EEPROM is no longer used.
3.1
multiSPI™ for ADC Digital IO
The ADS9224REVM-PDK supports several interface modes, as detailed in the ADS9224R data sheet. In
addition to the standard SPI modes (single-, dual-, and quad-SDO lines), the multiSPI modes support
single- and dual-data output rates. The PHI is capable of operating at a 3.3-V logic level and is directly
connected to the digital I/O lines of the ADC. Table 3 lists the test points available for probing the SPI pins
in both SPI and parallel byte mode.
Table 3. SPI Test Points
Designator
Signal
TP1
RST
Description
TP2
READY/STR
TP3
SDO-0/0A
TP4
SDO-1/1A
TP6
SDO-2/2A
TP7
SDO-3/3A
TP9
SDO-4/0B
TP10
SDO-5/1B
TP11
SDO-6/2B
TP12
SDO-7/3B
TP13
SCLK
TP14
SDI
Serial data input pin.
TP15
CS
Chip-select input pin; active low.
TP16
CONVST
Asynchronous reset; active low.
Indicates data-ready or strobe output for data capture.
SPI mode: data output 0 for channel A.
Parallel byte mode: least significant bit (LSB) from the data byte.
SPI mode: data output 1 for channel A.
Parallel byte mode: LSB+1 from the data byte.
SPI mode: data output 2 for channel A.
Parallel byte mode: LSB+2 from the data byte.
SPI mode: data output 3 for channel A.
Parallel byte mode: LSB+3 from the data byte.
SPI mode: data output 4 for channel A.
Parallel byte mode: LSB+4 from the data byte.
SPI mode: data output 5 for channel A.
Parallel byte mode: LSB+5 from the data byte.
SPI mode: data output 6 for channel A.
Parallel byte mode: LSB+6 from the data byte.
SPI mode: data output 7 for channel A.
Parallel byte mode: MSB from the data byte.
Clock input pin for the serial interface.
Conversion start input pin.
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Power Supplies
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Power Supplies
The PHI controller provides multiple power-supply options for the EVM, derived from the USB supply of
the computer.
The EEPROM on the ADS9224REVM use a 3.3-V power supply generated directly by the PHI. The ADC
and analog input drive circuits are powered by the TPS7A4700 onboard the EVM. The TPS7A4700 is a
low-noise linear regulator that uses the 5.5-V supply out of a switching regulator on the PHI to generate a
much cleaner 5.0-V output. The 3.3-V supply to the digital section of the ADC is provided directly by an
LDO regulator on the PHI.
The power supply for each active component on the EVM is bypassed with a ceramic capacitor placed
close to that component. Additionally, the EVM layout uses thick traces or large copper fill areas, where
possible, between bypass capacitors and their loads in order to minimize inductance along the load
current path.
The LM7705 outputs a –230-mV option to drive the negative supply (VS–) of the fully-differential input
amplifiers. This option allows the amplifier outputs to swing all the way to ground and achieve a full-scale
differential signal at the ADC input. Configure JP8 in the [1-2] position to use the –230-mV supply for VS–.
If the entire full-scale range is not required, VS– can be connected to GND by configuring JP8 in the [2-3]
position. U8 can be disabled by uninstalling the jumper on JP7. Table 4 lists the relevant power supply
test points on the EVM.
Table 4. Power-Supply Test Points
Designator
8
Signal
Description
TP17
GND
TP18
LDO_IN_5V5
EVM ground
TP19
VA
5-V analog supply
TP20
DVDD
3.3-V digital supply
TP21
VS–
5.5-V supply from PHI EVM controller
Negative supply for fully-differential input amplifiers
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5
Setup
This section explains the initial hardware and software setup procedures that must be completed for the
proper operation of the ADS9224xEVM-PDK.
5.1
Default Jumper Settings
JP1-JP2 and JP3-JP4 are used to connect differential analog sources to channel A and channel B inputs,
respectively. In addition, shunts can be used on jumpers JP1 and JP4 to ground the negative inputs and
support single-ended signals, as described in Section 2.1.
. Figure 3 shows the default factory jumper locations and settings.
Figure 3. ADS9224REVM-PDK Jumper Locations
Table 5 explains the functionality of each of these jumpers and their default configurations.
Table 5. Default Jumper Configurations
Designator
Default Configuration
Description
JP1
Open
CHA negative differential input. This pin can be grounded by shunting JP1 pin
1 and JP1 pin 2 for single-ended signals.
JP2
Open
CHA positive differential input or input for single-ended signals.
JP3
Open
CHB negative differential input. This pin can be grounded by shunting JP1 pin
1 and JP1 pin 2 for single-ended signals.
JP4
Open
CHB positive differential input or input for single-ended signals.
JP5
Open
EEPROM write protect function (EEPROM rewrite disabled).
JP6
Open
External CONVST is disconnected.
JP7
Installed
JP8
1-2
Shutdown pin on U8 LDO is disabled.
Negative supply for fully-differential input amplifiers is connected to –230 mV.
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Setup
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EVM Graphical User Interface (GUI) Software Installation
Download the latest version of the EVM GUI installer from the Tools and Software folder of the
ADS9224R, and run the GUI installer to install the EVM GUI software on the user’s computer.
NOTE: Manually disable any antivirus software running on the computer before downloading the
EVM GUI installer onto the local hard disk. Otherwise, depending on the antivirus settings,
an error message may appear or the installer.exe file may be deleted.
Accept the license agreements and follow the onscreen instructions to complete the installation.
Figure 4. ADS9224R Software Installation Prompts
As a part of the ADS9224REVM GUI installation, a prompt with a Device Driver Installation will appear on
the screen. Click Next to proceed.
Figure 5. Device Driver Installation Wizard Prompts
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NOTE: A notice may appear on the screen stating that Widows cannot verify the publisher of this
driver software. Select Install this driver software anyway.
The ADS9224xEVM-PDK requires LabVIEW™ Run-Time Engine, and may prompt for the installation of
this software if not already installed.
Figure 6. LabVIEW Run-Time Engine Installation
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After these installations, verify that C:\Program Files (x86)\Texas Instruments\ADS9224REVM is as shown
in Figure 7.
Figure 7. ADS9224REVM-PDK Folder Post-Installation
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6
Operation
The following instructions are a step-by-step guide to connecting the ADS9224REVM-PDK to the
computer and evaluating the performance of the ADS9224R:
1. Connect the ADS9224REVM to the PHI, and install the two screws, as indicated in Figure 8.
2. Use the provided USB cable to connect the PHI to the computer.
• LED D5 on the PHI lights up, indicating that the PHI is powered up.
• LEDs D1 and D2 on the PHI start blinking to indicate that the PHI is booted up and communicating
with the PC.
LED D5
LED D2 LED D1
Figure 8. EVM-PDK Hardware Setup and LED Indicators
3. Double-click on the ADS92x4R EVM.exe, file to launch the ADS9224REVM-PDK GUI software.
Figure 9 shows the ADS9224REVM software folder.
Figure 9. Launch the EVM GUI Software
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Operation
6.1
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EVM GUI Global Settings for ADC Control
Although the EVM GUI does not allow direct access to the levels and timing configuration of the ADC
digital interface, the EVM GUI does allow high-level control over virtually all functions of the ADS9224R.
The available functions include interface modes, sampling rate, and number of samples to be captured.
Figure 10 presents the input parameters and the default values of the GUI, through which the various
functions of the ADS9224R are exercised. These settings are global and are applied to all the pages listed
in Pages section at the top of the left pane.
Figure 10. EVM GUI Global Input Parameters
The host configuration options in this pane allow the user to choose from various SPI and multiSPI host
interface options available on the ADS9224R. The host always communicates with the ADS9224R using
the standard SPI protocol over the single SDI lane, irrespective of the mode selected for data capture.
The drop-down boxes under the Interface Configuration submenu allow the user to select the data capture
protocol. The SDO Width drop-down menu allows selection between Single-, Dual- and Quad-SDO lanes.
The SDO Mode drop-down menu allows selection between standard SPI and multiSPI modes. The
ADS9224REVM-PDK software supports maximum throughput of 3-MSPS when using Dual- and QuadSDO lanes, and a maximum throughput of 2.61-MSPS when using Single-SDO lane. For maximum
throughput of 3-MSPS, select the Dual or Quad-SDO lanes.
In SPI mode, the SDI Mode drop-down menu allows selection between the four SPI protocol combinations
for CPOL and CPHA.
In multiSPI mode, the Data Rate drop-down menu allows selection between SDR and DDR modes.
Detailed descriptions of each of these modes is available in the ADS9224R data sheet. The selected data
capture protocol is summarized in the Protocol Selected indicator box.
Select SCLK Frequency and Sampling Rate on this pane. Enter the targeted values for these two
parameters, and the GUI computes the best values that can be achieved, considering the timing
constraints of the selected device protocol.
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Specify a target SCLK frequency (in Hz), and the GUI tries to match this frequency as closely as possible
by changing the PHI PLL settings. However, the achievable frequency may differ from the target value
entered. Similarly, the sampling rate of the ADC can be adjusted by modifying the Target Sampling Rate
argument (also in Hz). The achievable ADC sampling rate can differ from the target value depending on
the applied SCLK frequency and selected Device Mode. The closest achievable match is then displayed.
Thus, this pane allows the user to test various available settings on the ADS9224R in an iterative fashion
until the best settings for the corresponding test scenario are found.
The Device Reset button functions as a master reset to both the ADS9224REVM and the GUI. When the
button is pressed, the ADC resets to the reset configuration explained in the ADS9224R data sheet. The
GUI also updates the interface configuration settings and the register map to reflect the device reset state.
6.2
Register Map Configuration Tool
Use the register map configuration tool to view and modify the registers of the ADS9224R. To select this
tool, click on the Register Map Config radio button in the Pages section at the top of the left pane, as
shown in Figure 11. At power-up, the values on this page correspond to the host configuration settings
that enable ADC sampling at the maximum sampling rate specified for the ADC. Edit the register values
by double-clicking the corresponding value field. If interface mode settings are affected by the change in
register values, this change reflects on the left pane immediately. The effect of changes in the register
value reflect on the ADS9224R device on ADS9224REVM-PDK based on the Update Mode selection, as
described in Figure 11.
Figure 11. Register Map Configuration
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Time Domain Display Tool
The time domain display tool allows visualization of the ADC response to a given input signal. This tool is
useful for both studying the behavior and debugging any gross problems with the ADC or drive circuits.
To trigger a capture of the data of the selected number of samples from the ADS9224R, as per the current
interface mode settings, use the Capture button shown on the left pane of Figure 12. The sample indices
are on the x-axis. The two y-axes show the corresponding output codes, as well as the equivalent analog
voltages based on the specified reference voltage. To display channel A (Ch A) data or channel B (Ch B)
data, select the proper channel, as shown in the top right section of Figure 12. Switching pages to any of
the analysis tools described in the subsequent sections triggers calculations that are performed on the
same set of data.
Figure 12. Time Domain Display Tool Options
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6.4
Spectral Analysis Tool
The spectral analysis tool evaluates the dynamic performance (SNR, THD, SFDR, SINAD, and ENOB) of
the ADS9224R SAR ADC. Evaluation is done through single-tone sinusoidal signal FFT analysis using the
7-term Blackman-Harris window setting. The window setting of None can be used to search for noise
spurs over frequency in dc inputs.
For dynamic performance evaluation, the external differential source must have better specifications than
the ADC. The measured system performance must not be limited by the performance of the signal source.
Therefore, the external reference source must meet the source requirements mentioned in Table 6.
Table 6. External Source Requirements for Evaluation of the ADS9224R
Specification Description
Specification Value
Signal frequency
Less than fS / 2
External source type
Balanced differential
External source common-mode voltage
0 V or floating
Source differential signal
(VPP amplitude for –0.5 dBFS)
±3.875 VP OR 7.75 VPP
Maximum noise
20 µVRMS
Minimum SNR
103.2 dB
Maximum THD
–120 dB
For 2-kHz SNR and ENOB evaluation at a maximum throughput of 3 MSPS, the number of samples must
be a minimum of 65536.
Figure 13. Spectral Analysis Tool
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Operation
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Finally, the FFT tool includes windowing options that are required to mitigate the effects of noncoherent
sampling (a discussion that is beyond the scope of this document). The 7-Term Blackman Harris window
is the default option and has sufficient dynamic range to resolve the frequency components of up to a 24bit ADC. The None option corresponds to not using a window (or using a rectangular window) and is not
recommended.
6.5
Histogram Tool
Noise degrades ADC resolution. The histogram tool can be used to estimate effective resolution. Effective
resolution is an indicator of the number of bits of ADC resolution losses resulting from noise generated by
the various sources connected to the ADC when measuring a dc signal. The cumulative effect of noise
coupling to the ADC output from sources (such as the input drive circuits, the reference drive circuit, the
ADC power supply, and the ADC) is reflected in the standard deviation of the ADC output code histogram
that is obtained by performing multiple conversions of a dc input applied to a given channel.
The histogram corresponding to a dc input is displayed on clicking the Capture button, as shown in
Figure 14:
Figure 14. Histogram Analysis Tool
18
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7
ADS9224REVM Bill of Materials, PCB Layout, and Schematics
This section contains the ADS9224REVM bill of materials, PCB layout, and the EVM schematics.
7.1
Bill of Materials
Table 7 lists the ADS9224REVM bill of materials.
Table 7. ADS9224REVM Bill of Materials
Designator
!PCB1
Quantity
Value
1
Description
Package
Reference
Printed Circuit Board
Part Number
Manufacturer
DC053
Any
C1, C8, C15,
C24, C27, C29, 9
C37, C39, C40
0.1uF
CAP, CERM, 0.1 uF, 16 V, +/- 10%, X7R, 0603
0603
885012206046
Wurth Elektronik
C2, C28, C38,
C41
4
0.01uF
CAP, CERM, 0.01 uF, 10 V, +/- 10%, X7R, 0603
0603
0603ZC103KAT2A
AVX
C3, C12, C17,
C26
4
100pF
CAP, CERM, 100 pF, 50 V, +/- 1%, C0G/NP0,
0603
0603
06035A101FAT2A
AVX
C4, C5, C14,
C16, C23, C31, 7
C48
1uF
CAP, 1uF, 25V, ±10%, X7R, 0603
0603
CL10B105KA8NNNC
Samsung
C6, C13, C18,
C25
4
330pF
CAP, CERM, 330 pF, 50 V, +/- 5%, C0G/NP0,
0603
0603
C0603C331J5GACTU
Kemet
C7, C22
2
3300pF
CAP, CERM, 3300 pF, 50 V, +/- 5%, C0G/NP0,
0603
0603
GRM1885C1H332JA01D
MuRata
C9, C10, C19,
C20, C21, C30, 7
C47
10uF
CAP, CERM, 10 uF, 16 V, +/- 10%, X7R, 0805
0805
CL21B106KOQNNNE
Samsung Electro-Mechanics
C11
1
1000pF
CAP, CERM, 1000 pF, 50 V, +/- 1%, C0G/NP0,
0603
0603
GRM1885C1H102FA01J
MuRata
C33
1
47uF
CAP, CERM, 47 uF, 25 V, +/- 20%, X5R,
1206_190
1206_190
C3216X5R1E476M160AC
TDK
C35, C36, C42
3
0.1uF
CAP, CERM, 0.1 uF, 16 V, +/- 10%, X7R, 0402
0402
GRM155R71C104KA88D
MuRata
C43, C46
2
4.7uF
CAP, CERM, 4.7 µF, 16 V,+/- 10%, X5R, 0805
0805
CL21A475KOFNNNE
Samsung Electro-Mechanics
C44
1
22uF
CAP, CERM, 22 µF, 16 V,+/- 10%, X5R, 0805
0805
CL21A226KOQNNNE
Samsung Electro-Mechanics
C45
1
0.47uF
CAP, CERM, 0.47 uF, 16 V, +/- 10%, X5R, 0603
0603
GRM188R61C474KA93D
MuRata
D1
1
Green
LED, Green, SMD
LED_0805
APT2012LZGCK
Kingbright
D2, D3
2
75V
Diode, Switching, 75 V, 0.3 A, SOD-523F
SOD-523F
1N4148WT
Fairchild Semiconductor
MACHINE SCREW PAN PHILLIPS 4-40
Machine
Screw, 4-40,
1/4 inch
PMSSS 440 0025 PH
B&F Fastener Supply
H1, H2, H3, H4 4
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Table 7. ADS9224REVM Bill of Materials (continued)
Designator
Quantity
Value
Description
H6, H7, H8, H9 4
Hex Standoff, #4-40, Aluminum, 1/4"
H10, H11
2
Machine Screw Pan PHILLIPS M3
H12, H13
2
ROUND STANDOFF M3 STEEL 5MM
J1
1
J2, J3, J4, J5
Package
Reference
1/4 inch
Aluminum Hex
Standoff
Part Number
Manufacturer
1891
Keystone
RM3X4MM 2701
APM HEXSEAL
ROUND
STANDOFF
M3 STEEL
5MM
9774050360R
Wurth Elektronik
Header(Shrouded), 19.7mil, 30x2, Gold, SMT
Header
(Shrouded),
19.7mil, 30x2,
SMT
QTH-030-01-L-D-A
Samtec
4
Connector, End launch SMA, 50 ohm, SMT
End Launch
SMA
142-0701-801
Cinch Connectivity
J6
1
SMA Straight PCB Socket Die Cast, 50 Ohm, TH
SMA Straight
PCB Socket
Die Cast, TH
5-1814832-1
TE Connectivity
JP1, JP2, JP3,
JP4, JP5, JP6,
JP7
7
Header, 100mil, 2x1, Gold, TH
Header,
100mil, 2x1,
TH
HTSW-102-07-G-S
Samtec
JP8
1
Header, 100mil, 3x1, Gold, TH
Header,
100mil, 3x1,
TH
HTSW-103-07-G-S
Samtec
LBL1
1
Thermal Transfer Printable Labels, 0.650" W x
0.200" H - 10,000 per roll
PCB Label
0.650 x 0.200
inch
THT-14-423-10
Brady
R1
1
49.9
RES, 49.9, 1%, 0.25 W, 1206
1206
RC1206FR-0749R9L
Yageo America
R2, R12, R14,
R22, R26, R32, 9
R40, R48, R74
0
RES, 0, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
0603
RMCF0603ZT0R00
Stackpole Electronics Inc
R3, R4, R15,
R16, R33, R34, 8
R49, R50
1.00k
RES, 1.00 k, 0.1%, 0.1 W, 0603
0603
RT0603BRD071KL
Yageo America
R5, R10, R35,
R55, R68, R71
6
10.0k
RES, 10.0 k, 1%, 0.1 W, 0402
0402
ERJ-2RKF1002X
Panasonic
R7, R17, R36,
R47
4
4.32
RES, 4.32, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
0603
CRCW06034R32FKEA
Vishay-Dale
R8, R21, R42,
R56
4
100
RES, 100, 1%, 0.1 W, 0603
0603
RC0603FR-07100RL
Yageo America
R9, R11, R43,
R44
4
10.0
RES, 10.0, 0.1%, 0.1 W, 0603
0603
TNPW060310R0BEEA
Vishay-Dale
20
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Table 7. ADS9224REVM Bill of Materials (continued)
Designator
R13,
R23,
R28,
R39,
R51,
R18,
R24,
R29,
R41,
R53
Quantity
R20,
R27,
R31, 14
R45,
Value
Description
Package
Reference
Part Number
Manufacturer
0
RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0, 0402
0402
ERJ-2GE0R00X
Panasonic
R30
1
5.11
RES, 5.11, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
0603
CRCW06035R11FKEA
Vishay-Dale
R37
1
0
RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0, 0603
0603
ERJ-3GEY0R00V
Panasonic
R58, R72, R75
3
0
RES, 0, 5%, 0.1 W, 0603
0603
ERJ-3GEY0R00V
Panasonic
R60
1
0.1
RES, 0.1, 1%, 0.1 W, 0603
0603
ERJ-3RSFR10V
Panasonic
R62, R65
2
0
RES, 0, 5%, 0.063 W, 0402
0402
ERJ-2GE0R00X
Panasonic
R69
1
1.24k
RES, 1.24 k, 1%, 0.1 W, 0603
0603
RC0603FR-071K24L
Yageo
R70
1
1.00k
RES, 1.00 k, 1%, 0.1 W, 0603
0603
ERJ-3EKF1001V
Panasonic
SH-J1, SH-J2,
SH-J3, SH-J4,
SH-J5, SH-J6,
SH-J7, SH-J8
8
Shunt, 100mil, Gold plated, Black
Shunt 2 pos.
100 mil
881545-2
TE Connectivity
TP1, TP2, TP3,
TP4, TP5, TP6,
TP7, TP8, TP9,
TP10, TP11,
17
TP12, TP13,
TP14, TP15,
TP16, TP19
Test Point, Miniature, SMT
Testpoint_Keys
5015
tone_Miniature
Keystone
TP17, TP18,
TP20, TP21
4
Test Point, Compact, SMT
Testpoint_Keys
5016
tone_Compact
Keystone
U1
1
Dual, Low Latency, Simultaneous-Sampling SAR
ADC, RHB0032E (VQFN-32)
RHB0032E
ADS9224RRHB
Texas Instruments
U2, U3
2
Low Noise, Precision, 150MHz, Fully Differential
Amplifier, RUN0010A (WQFN-10)
RUN0010A
THS4551IRUNR
Texas Instruments
U4
1
36-V, 1-A, 4.17-uVRMS, RF LDO Voltage
Regulator, RGW0020A (VQFN-20)
RGW0020A
TPS7A4700RGWR
Texas Instruments
U6
1
I2C BUS EEPROM (2-Wire), TSSOP-B8
TSSOP-8
BR24G32FVT-3AGE2
Rohm
U7
1
Single Schmitt-Trigger Inverter, DCK0005A (SOTSC70-5)
DCK0005A
SN74LVC1G14DCKT
Texas Instruments
U8
1
Low Noise Negative Bias Generator, 8-pin Mini
SOIC, Pb-Free
DGK0008A
LM7705MM/NOPB
Texas Instruments
C32
0
1uF
CAP, CERM, 1 uF, 10 V, +/- 10%, X7R, 0805
0805
0805ZC105KAT2A
AVX
C34
0
10uF
CAP, CERM, 10 uF, 16 V, +/- 10%, X7R, 0805
0805
CL21B106KOQNNNE
Samsung Electro-Mechanics
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Table 7. ADS9224REVM Bill of Materials (continued)
Designator
Quantity
Value
Description
Package
Reference
FID1, FID2,
FID3
0
H5
0
R6, R38
0
10.0k
RES, 10.0 k, 1%, 0.1 W, 0402
0402
R19, R25, R54,
0
R57
100k
RES, 100 k, 0.1%, 0.1 W, 0603
R46, R52
0
0
R59
0
R61
0
Fiducial mark. There is nothing to buy or mount.
N/A
Part Number
Manufacturer
N/A
N/A
102-1092-BL-00100
CnC Tech
ERJ-2RKF1002X
Panasonic
0603
RT0603BRD07100KL
Yageo America
RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0, 0402
0402
ERJ-2GE0R00X
Panasonic
1.00k
RES, 1.00 k, 1%, 0.1 W, AEC-Q200 Grade 0,
0603
0603
CRCW06031K00FKEA
Vishay-Dale
Cable, USB-A to micro USB-B, 1 m
0.22
RES, 0.22, 1%, 0.1 W, 0603
0603
ERJ-3RQFR22V
Panasonic
R63, R64, R66,
0
R67
0
RES, 0, 5%, 0.063 W, 0402
0402
ERJ-2GE0R00X
Panasonic
R73
0
RES, 0, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
0603
RMCF0603ZT0R00
Stackpole Electronics Inc
3 µVpp/V Noise, 3 ppm/°C Drift Precision Series
Voltage Reference, DGK0008A (VSSOP-8)
DGK0008A
REF5025AIDGKR
Texas Instruments
U5
22
0
0
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7.2
PCB Layout
Figure 15 through Figure 19 illustrate the EVM PCB layout.
Figure 15. ADS9224REVM PCB Top Overlay
Figure 16. ADS9224REVM PCB Layer 1: Top Layer
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Figure 17. ADS9224REVM PCB Layer 2: GND Plane
Figure 18. ADS9224REVM PCB Layer 3: Power Planes
24
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Figure 19. ADS9224REVM PCB Layer 4: Bottom Layer
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ADS9224REVM Bill of Materials, PCB Layout, and Schematics
7.3
www.ti.com
Schematics
Figure 20 and Figure 21 illustrate the EVM schematics.
Connect V- bypass Cap
Connect V+ bypass Cap
C3
VA
VS-
in close proximity to V- pin 5 on U2
in close proximity to V+ pin 10 on U2
100pF
J2
R2
R3
0
1.00k
R4
1.00k
2
3
4
5
1
R6 10.0k
DNP
10.0k
10
3
4
GND
REFP/2
R8
7
100
JP1
NC
V+
V-
6
5
C8
0.1uF
NC
8
C38
0.01uF
4.32
GND
9
C37
0.1uF
R7
2
GND
GND
GND
GND
1
VOCM
C2
0.01uF
C6
330pF
R5
VA
C1
0.1uF
GND
VA
VA
Input_Neg
R9 10.0
R11 10.0
1µF
C4
VICM_1
U2
VA
C23
C7
3300pF
VA
C9
R12
VSJ3
R15
0
1.00k
GND
2
3
4
5
1
R14
R16
R17
1.00k
4.32
1µF
12
29
1µF
100pF
REFP/2
JP2
R21
GND
R25
C15
P
0.1uF DN100k
RET_CLK
SCLK
R45
SDI
TP14 0
GND
R46
DNP
0
GND
R39
R41
0
0
RST
READY/STR R13
0
DVDD
AINP_A
AINM_A
REFP_B
REFM_B
10
9
7
8
AINM_B
AINP_B
SDO-0/0A
SDO-1/1A
SDO-2/2A
SDO-3/3A
SDO-4/0B
SDO-5/1B
SDO-6/2B
SDO-7/3B
24
23
22
21
20
19
18
17
GND
GND
GND
GND
PAD
4
11
27
30
33
16
15
14
26
25
13
C17
6
GND
100pF
2
3
4
5
1
R32
R33
R34
0
1.00k
1.00k
GND
R35
VA
R38
DNP
10
3
4
GND
REFP/2
R42
7
100
JP3
NC
5
NC
2
3
4
5
R48
R49
0
1.00k
GND
0
0
0
0
0
0
0
TP6
SDO-2/2A
TP7 SDO-3/3A
TP9
SDO-4/0B
TP10 SDO-5/1B
TP11
0
TP12
SDO-6/2B
SDO-7/3B
ADS9224RRHB
0
0
GND
MP1
MP2
C20
10µF
10.0k
GND
8
C22
3300pF
R43 10.0
R44 10.0
GND
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
GND
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
C10
10µF
C11
1000pF
GND
GND
SDO-6/2B
SDO-7/3B
EVM_ID_PWR
R37
0
MP3
MP4
C19
10µF
GND
GND
QTH-030-01-L-D-A
GND
GND
DVDD
CONVST
R53
0
TP16
R26
C16
R22
1µF
C14
0
R47
THS4551IRUNR
4.32
R50
1.00k
Input_Neg
DNP
REFOUT
REFby2
R18
R20
R23
R24
R27
R28
R29
R31
4.32
VICM_2
VS-
1
TP15
R52
SDO-0/0A
SDO-1/1A
TP4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
GND
U3
J5
R51
CSz
NC
TP3
2
R10
4
10.0k
6
TP1
8
RST
10
12
14
16
SDI
18
CONVST
20
CSz
22
SCLK
24
TP13
26
RET_CLK
28
30
32
READY/STR
34
TP2
36
SDO-0/0A
38
SDO-1/1A
40
SDO-2/2A
42
SDO-3/3A
44
SDO-4/0B
46
SDO-5/1B
48
R30
50
52
5.11
DVDD
EVM_ID_SDA 54
EVM_ID_SCL
56
58
60
2
9
V-
C24
0.1uF
R36
10.0k
1
V+
VOCM
6
C18
330pF
VA
Input_Pos
VA
5
3
SCLK
SDI
CS
PD/RST
READY/STROBE
CONVST
0
C25
330pF
C26
GND
Scaled to accommodate
SMA100 CLK_SYN output
REF_IN
TP8
REFP/2
1µF
TP5
R73 0
DNP
R69
1.24k
J6
JP6
U7A
C39
1
2
0.1uF
2
3
4
5
J4
GND
31
32
1
2
VICM_1
100
AVDD
AVDD
REFP_A
REFM_A
28
GND
R19
P
DN100k
GND
GND
0
10µF
U1
DVDD
C5
C13
330pF
VA
EVM_REG_5V5
J1
R40
GND
C12
Input_Pos
DVDD
0
10µF
C21
THS4551IRUNR
CONVST
4
SN74LVC1G14DCKT
VA
100pF
Connect V+ bypass Cap
R54
P
DN100k
GND
JP4
REFP/2
R56
GND
in close proximity to V+ pin 10 on U3
VA
Connect V- bypass Cap
in close proximity to V- pin 5 on U3
R1
49.9
R70
1.00k
U7B
VSGND
DVDD
VICM_2
100
R57
C29
0.1uF DNP100k
GND
GND
C27
0.1uF
GND
C28
0.01uF
GND
C40
0.1uF
GND
C41
0.01uF
GND
1
NC
5
VCC
GND
GND
GND
C48
1µF
C42
0.1uF
SN74LVC1G14DCKT
3
GND
GND
Figure 20. ADS9224REVM Schematic Diagram 1
26
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REFERENCE (Not populated for ADS9224R variant):
Positive Supply
VA
U5A
2
EVM_REG_5V5
VIN
VOUT
DNP TRIM/NR
DNPC32
1uF
3
TEMP
R59
DNP
1.00k
6
5
Connected pg 1,
conn J1
LDO_IN_5V5
15
16
0
C30
10µF
REF5025AIDGKR
13
GND
U5B
NC
DNPDNC
DNC
DNPC34
10µF
7
1
8
GND
4
5
6
8
9
10
11
12
R62 0
0
GND
GND
R64 0
DNP
R65 0
REF5025AIDGKR
GND
IN
IN
OUT
OUT
1
20
3
EN
SENSE
R63
DNP
NR
14
NC
NC
NC
NC
19
18
17
2
GND
PAD
7
21
R60
0.1
C31
6P4V2
6P4V1
3P2V
1P6V
0P8V
0P4V
0P2V
0P1V
1µF
C33
47uF
GND
GND
TPS7A4700RGWR
R66 0
DNP
R67 0
DNP
Power
VA
U4
R58
R61
P
DN0
.22
4
GND
REF_IN
GND
COMPONENTS MARKED 'DNP' SHOULD NOT BE POPULATED.
LDO_IN_5V5
Origin Positive
Supply section
R68
10.0k
TP17
TP18
VA
DVDD
TP19
TP20
Green
Origin pg 1, conn J1
LDO_IN_5V5
D1
APT2012LZGCK
GND
EVM_REG_5V5
GND
R71
10.0k
GND
JP7
1
2
3
JP8
U8
C43
4.7µF
EEPROM
EVM_REG_5V5
R74
Origin pg 1, conn J1
EVM_ID_PWR
0
Origin pg 1, conn J1
EVM_ID_PWR
1
A0
VCC
8
A1
WP
7
3
A2
SCL
6
SDA
5
4
VSS
BR24G32FVT-3AGE2
GND
SD
VOUT
6
1
8
CF+
CF-
CRES
7
4
VDD
VSS
VSS
2
5
R72
0
C46
4.7µF
C44
22µF
C45
0.47uF
GND
LM7705MM/NOPB
EVM_ID_PWR
C35
C47
10µF
U6
2
3
0.1uF
R55
10.0k
GND
R75
GND
GND
GND
0
1N4148WT
D3
JP5
WP
WP
GND
EVM_ID_SCL
EVM_ID_SDA
C36
0.1uF
D2
GND
1N4148WT
GND
GND
Origins pg 1, conn J1
GND
FDA NEGATIVE SUPPLY
TP21
VS-
Figure 21. ADS9224REVM Schematic Diagram 2
SBAU315A – July 2018 – Revised June 2019
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ADS9224REVM-PDK
Copyright © 2018–2019, Texas Instruments Incorporated
27
Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2018) to A Revision ........................................................................................................... Page
•
•
•
•
•
•
•
•
•
•
•
28
Changed J2, J4, and J5 in J2 to J5 SMA Analog Interface Connections table ................................................... 5
Changed JP1 to JP4 Header Descriptions table ...................................................................................... 5
Changed discussion of how the input signal must be limited in Input Signal Path section ...................................... 6
Added REFby2 discussion and added test point TP8 to discussion of REFOUT in ADS9224R Internal Reference
section ...................................................................................................................................... 7
Added SPI Test Points table to multiSPI™ for ADC Digital IO section ............................................................ 7
Added last paragraph and Power-Supply Test Points table to Power Supplies section ......................................... 8
Changed shunts can be used on jumpers JP2 to shunts can be used on jumpers JP1 in Default Jumper Settings
section ...................................................................................................................................... 9
Added JP6, JP7, and JP8 rows to Default Jumper Configurations table .......................................................... 9
Changed signal frequency and source differential signal specification values in External Source Requirements for
Evaluation of the ADS9224R table .................................................................................................... 17
Changed ADS9224EVM Bill of Materials table ...................................................................................... 19
Changed Schematics figures ........................................................................................................... 26
Revision History
SBAU315A – July 2018 – Revised June 2019
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Copyright © 2018–2019, Texas Instruments Incorporated
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Limited Warranty and Related Remedies/Disclaimers:
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Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
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3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
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Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
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FCC Interference Statement for Class A EVM devices
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can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
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Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
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Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
2
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Concernant les EVMs avec antennes détachables
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3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
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http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
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If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
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(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
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Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
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1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
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実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
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3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
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3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
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product may cause radio interference in which case the user may be required to take adequate measures.
3
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4
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4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
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property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
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4.3.2
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User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
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7.
4
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
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WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
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8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
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MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
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CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
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a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
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excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
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these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
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