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Texas Instruments TSW14DL3200EVM High-Speed LVDS Data Capture and Pattern Generator User guides
User's Guide
SLAU766 – May 2018
TSW14DL3200 High-Speed LVDS Data Capture and
Pattern Generator User's Guide
This user's guide describes the characteristics, operation, and use of the TSW14DL3200EVM high-speed
data LVDS capture and pattern generator card. Throughout this user's guide, the abbreviation EVM and
the term evaluation module are synonymous with the TSW14DL3200EVM, unless otherwise noted.
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2
3
4
5
Contents
Introduction ................................................................................................................... 2
Functionality .................................................................................................................. 2
2.1
ADC EVM Data Capture .......................................................................................... 4
2.2
DAC EVM Pattern Generator ..................................................................................... 5
Hardware Configuration ..................................................................................................... 5
3.1
Power Connections ................................................................................................ 5
3.2
Switches, Jumpers, and LEDs .................................................................................... 6
3.3
LEDs ................................................................................................................. 7
Software Start-Up .......................................................................................................... 12
4.1
Installation Instructions ........................................................................................... 12
4.2
USB Interface and Drivers ....................................................................................... 13
Downloading Firmware .................................................................................................... 15
List of Figures
1
TSW14DL3200EVM ......................................................................................................... 3
2
TSW14DL3200EVM Block Diagram
3
Power Indicator LEDs
4
5
6
7
8
9
...................................................................................... 4
..................................................................................................... 13
TSW14DL3200EVM Serial Number ..................................................................................... 14
High-Speed Data Converter Pro GUI Top Level ....................................................................... 14
Hardware Device Manager ............................................................................................... 15
Select ADC Firmware to be Loaded ..................................................................................... 15
Status LEDs ................................................................................................................. 16
Download Firmware Error Message ..................................................................................... 16
List of Tables
1
Switch Description of the TSW14DL3200 Device ....................................................................... 6
2
Jumper Description of the TSW14DL3200 Device ...................................................................... 6
3
Power and Configuration LED Description of the TSW14DL3200 Device ........................................... 7
4
Connector Description of the TSW14DL3200 Device................................................................... 7
5
FMC Connector J10 Description of the TSW14DL3200 Device: Receive Data ..................................... 8
6
FMC Connector J8 Description of the TSW14DL3200 Device: Transmit Data ...................................... 9
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1
Introduction
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Trademarks
Cypress is a trademark of Cypress Semiconductor Corporation.
Microsoft, Windows are registered trademarks of Microsoft Corporation.
Samtec is a trademark of Samtec.
Xilinx, Ultra-Scale are registered trademarks of Xilinx Inc.
Vivado is a registered trademark of Xilinx, Inc.
All other trademarks are the property of their respective owners.
1
Introduction
The TI TSW14DL3200 evaluation module (EVM) is a next-generation pattern generator and data capture
card used to evaluate performances of the high-speed TI device family of high-speed low-voltage
differential signaling (LVDS) analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).
For an ADC, the TSW14DL3200 can be used to demonstrate datasheet performance specifications by
capturing the sampled data over a wide LVDS interface when using a high-quality, low-jitter clock and a
high-quality input frequency. Using Xilinx® IP cores, the TSW14DL3200 can be used to capture up to 48
pairs of high-speed LVDS signals or to provide up to 48 pairs of LVDS data. Together with the
accompanying high-speed data converter pro graphic user interface (GUI), the TSW14DL3200EVM is a
complete system that captures and evaluates data samples from ADC EVMs and generates and sends
desired test patterns to DAC EVMs.
2
Functionality
The TSW14DL3200EVM has two industry-standard FMC connectors that interfaces directly with new TI
high-speed LVDS ADC and DAC EVMs. When used with an ADC EVM, high-speed serial data are
captured and formatted by an Xilinx Ultra-Scale® XCKU060 field-programmable gate array (FPGA). The
data is then stored into internal FPGA memory, enabling the TSW14DL3200 to store up to 1M 16-bit data
samples. To acquire data on a host PC, the FPGA transmits the data on a high-speed, 16-bit parallel
interface. An onboard high-speed USB 3.0 to parallel converter bridges the FPGA interface to the host PC
and GUI.
In pattern generator mode, the TSW14DL3200 generates desired test patterns up to 1M 16-bit samples
for DAC EVMs under test. These patterns are sent from the host PC over the USB interface to the
TSW14DL3200. The FPGA stores the data received into internal memory. The data from memory is then
read by the FPGA and transmitted to a DAC EVM across the FMC interface connector. The board
contains a 100-MHz oscillator used as a reference clock for the USB3.0 controller and a 125-MHz
oscillator for the Xilinx Vivado HSSIO IPs. Figure 1 depicts the TI TSW14DL3200 evaluation module.
2
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Figure 1. TSW14DL3200EVM
The major features of the TSW14DL3200 are:
• Serial LVDS speeds up to 1.6 Gbps
• 48 routed receive LVDS pairs
• 48 routed transmit LVDS pairs
• 1M of 16-bit samples of onboard memory
• Onboard UCD90120A for power sequencing and monitoring
• Onboard Cypress™ CYUSB301X USB 3.0 device for JTAG and parallel interface to the FPGA
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Functionality
•
•
•
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Reference clocking for transceivers available through FMC port or SMAs
Supported by TI HSDC PRO software
FPGA firmware developed with Vivado® 2017.1
– IP core with support for:
• USB interface
• I/O delay
Figure 2 shows a block diagram of the TSW14DL3200EVM.
TSW14DL3200EVM
+12-VDC Input
Power Sequencer,
Monitor
USB
to
Parallel
USB 3.0
Port
32-Bit, 100-MHz
Parallel Interface
LDO, Switch Regulators
XILINX
XCKU060
(FPGA)
DATA, CLK, STROBE,
REF CLK
FMC Connector
FMC Connector
DAC EVM
ADC EVM
DATA, CLK, STROBE,
REF CLK
Figure 2. TSW14DL3200EVM Block Diagram
2.1
ADC EVM Data Capture
New TI high-speed ADCs and DACs have high-speed, wide-bus serial data interface. These devices are
generally available on an EVM that connects directly to the TSW14DL3200EVM. The common connector
between the EVMs and the TSW14DL3200EVM is a Samtec™ high-speed, high-density FMC connector
(SEAF-40-05.0-S-10-2-A-K) suitable for high-speed differential pairs up to 28 Gbps. At present, the
interface between the EVMs and the TSW14DL3200EVM has defined connections for 48 transmit LVDS
pairs, 48 receive LVDS pairs, eight single-ended CMOS signals, four TX clocks and strobes, four RX
clocks and strobes, and two LVDS FPGA clocks. The board has five spare SMA interfaces to the FPGA, a
pushbutton switch, several spare test points routed to the FPGA, and eight status LEDs.
4
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The data format for the ADCs and DACs is a 48-bit parallel format. The firmware in the FPGA on the
TSW14DL3200 only supports either a TI ADC or DAC at one time.
The GUI loads the FPGA with the appropriate firmware based on the ADC or DAC device selected in the
device drop-down window. Each ADC device that appears in this window has an associated initialization
file (.ini) . This .ini file contains information, such as maximum sample rate, number of channels, number
of bits, and other parameters. This information is loaded into the FPGA registers after the user clicks on
the capture button. After the parameters are loaded, valid data is then captured into the FPGA internal
memory. See the High-Speed Data Capture Pro GUI Software User's Guide and the ADC EVM User's
Guide for more information.
The TSW14DL3200 device can capture up to 1M 16-bit samples at a maximum data rate of 1.6 Gbps that
are stored inside the internal memory. To acquire data on a host PC, the FPGA reads the data from
memory and transmits parallel data to the onboard high-speed parallel-to-USB converter.
2.2
DAC EVM Pattern Generator
In pattern generator mode, the TSW14DL3200EVM generates desired test patterns for DAC EVMs under
test. These patterns are sent from the host PC over the USB interface to the TSW14DL3200. The FPGA
stores the data received into the internal memory. The data from the memory is then read by the FPGA,
then transmitted to a DAC EVM. The TSW14DL3200 can generate patterns up to 1M 16-bit samples at a
data rate up to 1.6 Gbps.
The GUI comes with several existing test patterns that can be download immediately. The GUI also has a
pattern generation tool that allows the user to generate a custom pattern, then download that pattern to
the memory. See the High-Speed Data Capture Pro Software User's Guide for more information. Like the
ADC capture mode, the DAC pattern generator mode uses .ini files to load predetermined interface
information to the FPGA.
3
Hardware Configuration
This section describes the various portions of the TSW14DL3200EVM hardware.
3.1
Power Connections
The TSW14DL3200EVM hardware is designed to operate from a single-supply voltage of 12 V DC. The
power input is controlled by the on and off switch, SW2. Make sure this switch is in the off position before
inserting the provided power cable. Insert the connector end of the power cable into J17 of the EVM.
Connect the positive red wire end of the power cable to the 12 V DC output of a power supply rated for at
least 3 A. Connect the negative black wire to the return or GND of the power supply. The board can also
be powered up by providing 12 V DC to the red test point, TP18, and the return to any black GND test
point. As an example, the TSW14DL3200 draws approximately 0.4 A at power-up and 0.6 A steady state
current when capturing 48 lanes of data from an ADC12DL3200EVM at a data rate of 1.6 Gpbs.
NOTE: The typical power-supply range for the TSW14DL3200EVM is between 10 V to 14 V with a
power consumption of approximately 7.2 W. TI recommends that at least a 3-A rated supply
be provided to the TSW14DL3200EVM because of the current consumption increase when
data are being captured by HSDC Pro.
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Hardware Configuration
3.2
3.2.1
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Switches, Jumpers, and LEDs
Switches and Pushbuttons
The TSW14DL3200 contains several switches and pushbuttons that enable certain functions on the board.
Table 1 describes these switches.
Table 1. Switch Description of the TSW14DL3200 Device
Component
3.2.2
Description
SW1
Spare pushbutton that is connected to a spare FPGA input
SW2
Board main power switch
SW3 (CPU reset)
FPGA hardware reset
SW4
USB reset
SW5 (UCD reset)
Power monitor U9 reset
SW6
Dip switch to set VAR adjustable step-down output voltage. Default is 1.8 V
(switches 1, 3, and 4 are off, 2 is on).
Jumpers
The TSW14DL3200 contains several jumpers (JP) that enable certain functions on the board. Table 2
describes these jumpers.
Table 2. Jumper Description of the TSW14DL3200 Device
Component
6
Description
Default
JP2
Programming mode for USB controller U8A
1 to 2
JP3
Programming mode for USB controller U8A
Open
JP4
Programming mode for USB controller U8A
2 to 3
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3.3
LEDs
3.3.1
Power and Configuration LEDs
Several LEDs are on the TSW14DL3200EVM to indicate the presence of power and the state of the
FPGA. Table 3 describes these LEDs.
Table 3. Power and Configuration LED Description of the TSW14DL3200 Device
Component
3.3.2
Description
D22
On after FPGA completes configuration
D9
On if VCCINT_0.95V_STAT are within specification
D10
On if VCCBRAM_0.95V_STAT are within specification
D11
On if USB_1.2V_STAT are within specification
D12
On if VADJ_1.8V_STAT are within specification
D13
On if MGTAVCC_1.0V_STAT are within specification
D14
On if power monitor device indicates that a power net is out of tolerance
D15
On if MGTAVTT_1.2V_STAT are within specification
D16
On if UTIL3.3V_STAT are within specification
D17
On if MGTVCCAUX_1.8V_STAT are within specification
D19
On if a 12-V board power is present
D20
On if 3.3 V is being provided for the power-supply sequencer
D21
On if VAR power is present
Status LEDs
Eight status LEDs on the TSW14DL3200EVM indicate the status of the FPGA and LVDs interface:
D1 – In ADC mode, indicates presence of rx_sync. In DAC mode, indicates the status of the
onboard_mmcm_locked signal.
D2 – In ADC mode, indicates the status of rx_rst_done. In DAC mode, indicates the status of the
dacclk_mmcm_locked signal.
D3 – In DAC mode, indicates the status of the tx_rst_done signal.
D4 – In DAC mode, indicates the status of the generate signal.
D5 – In DAC mode, indicates data are valid.
D6 – Not used
D7 – Not used
D8 – Not used
3.3.3
Connectors
3.3.3.1
SMA Connectors
The TSW14DL3200 has five SMA connectors. Table 4 defines these connectors.
Table 4. Connector Description of the TSW14DL3200 Device
Component
Connector
J3
TRIG_IN
J2
TRIG_OUT_A
Adjustable level CMOS trigger output. Default level is 1.8 V.
Adjustable level CMOS oscillator input. Default level is 1.8 V.
J6
REF_OSC
J12
CORE_CLK
J14
SYSREF1
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Description
Adjustable level CMOS trigger input. Default level is 1.8 V.
Spare CORE CLK input
Spare SYSREF input
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Hardware Configuration
3.3.3.2
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FPGA Mezzanine Card (FMC) Connector
The TSW14DL3200EVM has one connector to allow for the direct plug in of TI serial interface ADC EVMs
and one for the DAC EVMs. FMC connector J10 provides the interface between the TSW14DL3200EVM
and the ADC EVM under test. FMC connector J8 provides the interface between the TSW12DL3200EVM
and the DAC EVM under test. These 400-pin Samtec high-speed, high-density connectors (part number
SEAF-40-05.0-S-10-A-K) are suitable for high-speed differential pairs up to 28 Gbps.
In addition to the LVDS differential signals, several CMOS single-ended signals are connected between
the FMC and FPGA. Table 5 describes the connector pinout.
Table 5. FMC Connector J10 Description of the TSW14DL3200 Device: Receive Data
FMC Signal Name
8
FMC Pin
Description
LRX0_P, LRX0_N
A11 and A10
LVDS receiver data from the ADC
LRX1_P, LRX1_N
A8 and A7
LVDS receiver data from the ADC
LRX2_P, LRX2_N
A4 and A5
LVDS receiver data from the ADC
LRX3_P, LRX3_N
A1 and A2
LVDS receiver data from the ADC
LRX4_P, LRX4_N
C7 and C8
LVDS receiver data from the ADC
LRX5_P, LRX5_N
C5 and C4
LVDS receiver data from the ADC
LRX6_P, LRX6_N
C11 and C10
LVDS receiver data from the ADC
LRX7_P, LRX7_N
C20 and C19
LVDS receiver data from the ADC
LRX8_P, LRX8_N
C17 and C16
LVDS receiver data from the ADC
LRX9_P, LRX9_N
A14 and A13
LVDS receiver data from the ADC
LRX10_P, LRX10_N
C14 and C13
LVDS receiver data from the ADC
LRX11_P, LRX11_N
C1 and C2
LVDS receiver data from the ADC
LRX12_P, LRX12_N
B21 and B22
LVDS receiver data from the ADC
LRX13_P, LRX13_N
B25 and B24
LVDS receiver data from the ADC
LRX14_P, LRX14_N
B27 and B28
LVDS receiver data from the ADC
LRX15_P, LRX15_N
B31 and B30
LVDS receiver data from the ADC
LRX16_P, LRX16_N
B34 and B33
LVDS receiver data from the ADC
LRX17_P, LRX17_N
D21 and D22
LVDS receiver data from the ADC
LRX18_P, LRX18_N
D24 and D25
LVDS receiver data from the ADC
LRX19_P, LRX19_N
D27 and D28
LVDS receiver data from the ADC
LRX20_P, LRX20_N
K8 and K7
LVDS receiver data from the ADC
LRX21_P, LRX21_N
D34 and D33
LVDS receiver data from the ADC
LRX22_P, LRX22_N
D37 and D36
LVDS receiver data from the ADC
LRX23_P, LRX23_N
K17 and K16
LVDS receiver data from the ADC
LRX24_P, LRX24_N
E1 and E2
LVDS receiver data from the ADC
LRX25_P, LRX25_N
E4 and E5
LVDS receiver data from the ADC
LRX26_P, LRX26_N
E8 and E7
LVDS receiver data from the ADC
LRX27_P, LRX27_N
E11 and E10
LVDS receiver data from the ADC
LRX28_P, LRX28_N
E13 and E14
LVDS receiver data from the ADC
LRX29_P, LRX29_N
K1 and K2
LVDS receiver data from the ADC
LRX30_P, LRX30_N
G4 and G5
LVDS receiver data from the ADC
LRX31_P, LRX31_N
G7 and G8
LVDS receiver data from the ADC
LRX32_P, LRX32_N
G11 and G10
LVDS receiver data from the ADC
LRX33_P, LRX33_N
G14 and G13
LVDS receiver data from the ADC
LRX34_P, LRX34_N
G17 and G16
LVDS receiver data from the ADC
LRX35_P, LRX35_N
G20 and G19
LVDS receiver data from the ADC
LRX36_P, LRX36_N
F21 and F22
LVDS receiver data from the ADC
LRX37_P, LRX37_N
F24 and F25
LVDS receiver data from the ADC
LRX38_P, LRX38_N
F28 and F27
LVDS receiver data from the ADC
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Table 5. FMC Connector J10 Description of the TSW14DL3200 Device: Receive Data (continued)
FMC Signal Name
FMC Pin
Description
LRX39_P, LRX39_N
F31 and F30
LVDS receiver data from the ADC
LRX40_P, LRX40_N
F34 and F33
LVDS receiver data from the ADC
LRX41_P, LRX41_N
H21 and H22
LVDS receiver data from the ADC
LRX42_P, LRX42_N
H24 and H25
LVDS receiver data from the ADC
LRX43_P, LRX43_N
H28 and H27
LVDS receiver data from the ADC
LRX44_P, LRX44_N
H31 and H30
LVDS receiver data from the ADC
LRX45_P, LRX45_N
H34 and H33
LVDS receiver data from the ADC
LRX46_P, LRX46_N
H36 and H37
LVDS receiver data from the ADC
LRX47_P, LRX47_N
H39 and H40
LVDS receiver data from the ADC
RX_STROBE0_P,
RX_STROBE0_N
A16 and A17
RX_STROBE1_P,
RX_STROBE1_N
E19 and E20
RX_STROBE2_P,
RX_STROBE2_N
E16 and E17
RX_STROBE3_P,
RX_STROBE3_N
F37 and F36
RX_CLK0_P, RX_CLK0_N
K11 and K10
DDR data clock for LVDS Bus A
RX_CLK1_P, RX_CLK1_N
K14 and K13
DDR data clock for LVDS Bus B
RX_CLK2_P, RX_CLK2_N
K20 and K19
DDR data clock for LVDS Bus C
RX_CLK3_P, RX_CLK3_N
K25 and K24
DDR data clock for LVDS Bus D
CLK_ADC_REF_P,
CLK_ADC_REF_N
K38 and K39
RX_RESERVE0
J1
Spare signal
RX_RESERVE1
J2
Spare signal
RX_RESERVE2
J3
Spare signal
RX_RESERVE3
J4
Spare signal
Synchronization strobe for LVDS Bus A
Synchronization strobe for LVDS Bus B
Synchronization strobe for LVDS Bus C
Synchronization strobe for LVDS Bus D
Clock for FPGA
Table 6 describes the connector pinout.
Table 6. FMC Connector J8 Description of the TSW14DL3200 Device: Transmit Data
FMC Signal Name
FMC Pin
Description
LTX0_P, LTX0_N
A11 and A10
LVDS transmit data to the DAC
LTX1_P, LTX1_N
A8 and A7
LVDS transmit data to the DAC
LTX2_P, LTX2_N
A4 and A5
LVDS transmit data to the DAC
LTX3_P, LTX3_N
A1 and A2
LVDS transmit data to the DAC
LTX4_P, LTX4_N
C8 and C7
LVDS transmit data to the DAC
LTX5_P, LTX5_N
C4 and C5
LVDS transmit data to the DAC
LTX6_P, LTX6_N
C10 and C11
LVDS transmit data to the DAC
LTX7_P, LTX7_N
C20 and C19
LVDS transmit data to the DAC
LTX8_P, LTX8_N
C17 and C16
LVDS transmit data to the DAC
LTX9_P, LTX9_N
A14 and A13
LVDS transmit data to the DAC
LTX10_P, LTX10_N
C14 and C13
LVDS transmit data to the DAC
LTX11_P, LTX11_N
C1 and C2
LVDS transmit data to the DAC
LTX12_P, LTX12_N
B21 and B22
LVDS transmit data to the DAC
LTX13_P, LTX13_N
B24 and B25
LVDS transmit data to the DAC
LTX14_P, LTX14_N
B28 and B29
LVDS transmit data to the DAC
LTX15_P, LTX15_N
B31 and B30
LVDS transmit data to the DAC
LTX16_P, LTX16_N
B34 and B33
LVDS transmit data to the DAC
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Table 6. FMC Connector J8 Description of the TSW14DL3200 Device: Transmit Data (continued)
FMC Signal Name
10
FMC Pin
Description
LTX17_P, LTX17_N
D22 and D21
LVDS transmit data to the DAC
LTX18_P, LTX18_N
D25 and D24
LVDS transmit data to the DAC
LTX19_P, LTX19_N
D28 and D27
LVDS transmit data to the DAC
LTX20_P, LTX20_N
K8 and K7
LVDS transmit data to the DAC
LTX21_P, LTX21_N
D34 and D33
LVDS transmit data to the DAC
LTX22_P, LTX22_N
D37 and D36
LVDS transmit data to the DAC
LTX23_P, LTX23_N
K17 and K16
LVDS transmit data to the DAC
LTX24_P, LTX24_N
E1 and E2
LVDS transmit data to the DAC
LTX25_P, LTX25_N
E4 and E5
LVDS transmit data to the DAC
LTX26_P, LTX26_N
E8 and E7
LVDS transmit data to the DAC
LTX27_P, LTX27_N
E11 and E10
LVDS transmit data to the DAC
LTX28_P, LTX28_N
E13 and E14
LVDS transmit data to the DAC
LTX29_P, LTX29_N
K1 and K2
LVDS transmit data to the DAC
LTX30_P, LTX30_N
G4 and G5
LVDS transmit data to the DAC
LTX31_P, LTX31_N
G7 and G8
LVDS transmit data to the DAC
LTX32_P, LTX32_N
G11 and G10
LVDS transmit data to the DAC
LTX33_P, LTX33_N
G14 and G13
LVDS transmit data to the DAC
LTX34_P, LTX34_N
G17 and G16
LVDS transmit data to the DAC
LTX35_P, LTX35_N
G20 and G19
LVDS transmit data to the DAC
LTX36_P, LTX36_N
F21 and F22
LVDS transmit data to the DAC
LTX37_P, LTX37_N
F24 and F25
LVDS transmit data to the DAC
LTX38_P, LTX38_N
F28 and F27
LVDS transmit data to the DAC
LTX39_P, LTX39_N
F31 and F30
LVDS transmit data to the DAC
LTX40_P, LTX40_N
F34 and F33
LVDS transmit data to the DAC
LTX41_P, LTX41_N
H21 and H22
LVDS transmit data to the DAC
LTX42_P, LTX42_N
H24 and H25
LVDS transmit data to the DAC
LTX43_P, LTX43_N
H28 and H27
LVDS transmit data to the DAC
LTX44_P, LTX44_N
H31 and H30
LVDS transmit data to the DAC
LTX45_P, LTX45_N
H34 and H33
LVDS transmit data to the DAC
LTX46_P, LTX46_N
H36 and H37
LVDS transmit data to the DAC
LTX47_P, LTX47_N
H39 and H40
LVDS transmit data to the DAC
TX_STROBE0_P,
TX_STROBE0_N
A16 and A17
Synchronization strobe for LVDS bus A
TX_STROBE1_P,
TX_STROBE1_N
E19 and E20
Synchronization strobe for LVDS bus B
TX_STROBE2_P,
TX_STROBE2_N
E16 and E17
Synchronization strobe for LVDS bus C
TX_STROBE3_P,
TX_STROBE3_N
F37 and F36
Synchronization strobe for LVDS bus D
TX_CLK0_P, TX_CLK0_N
K11 and K10
Data clock for LVDS bus A
TX_CLK1_P, TX_CLK1_N
K14 and K13
Data clock for LVDS bus B
TX_CLK2_P, TX_CLK2_N
K20 and K19
Data clock for LVDS bus C
TX_CLK3_P, TX_CLK3_N
K25 and K24
Data clock for LVDS bus D
CLK_DAC_REF_P,
CLK_DAC_REF_N
K38 and K39
Clock for FPGA
TX_RESERVE0
J1
Spare signal
TX_RESERVE1
J2
Spare signal
TX_RESERVE2
J3
Spare signal
TX_RESERVE3
J4
Spare signal
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3.3.3.3
JTAG Connectors
The TSW14DL3200EVM includes nine industry-standard JTAG connectors; one that connects to the
JTAG ports of the FPGA, seven that connects to the JTAG pins of the step-down converters, and one that
connects to the programming pins of the power monitor and sequencer device. Jumpers on the
TSW14DL3200EVM allow for the FPGA to be programmed from JTAG connector J25 or the USB
interface. JTAG connectors J16, J18, J19, and J20 to J24 are for troubleshooting only. The board default
setup is with the FPGA JTAG pins connected to JTAG connector J25. The FPGA can be programmed
using this connector if the M0–M3 inputs are set to the proper logic levels. These inputs are set by
resistors R348, R349, and R350. Consult the Xilinx XCKU060 data sheet for more information regarding
JTAG programming. The FPGA also has the parallel programming inputs connected to the USB 3.0
controller. With JP2–JP4 in the default positions, the FPGA can be programmed by the HSDC Pro
software GUI. Every time the TSW14DL3200EVM is powered-down, the FPGA configuration is removed.
The user must program the FPGA through the GUI every time the board is powered-up. The Cypress
USB3.0 controller device is programmed at power-up using the factory preprogrammed flash device U7.
JTAG connector J16 is used to program the TI UCD90120A power monitor and sequencer device. This
device is preprogrammed at the factory and this interface is only to be used for troubleshooting.
3.3.3.4
USB I/O Connection
Control of the TSW14DL3200EVM is through the USB 3.0 connector J7. This control provides the
interface between the HSDC Pro GUI running on a PC using the Microsoft® Windows® operating system
and the FPGA. For the computer, the drivers needed to access the USB port are included on the HSDC
Pro GUI installation software that can be downloaded from the web. The drivers are automatically installed
during the installation process. On the TSW14DL3200EVM, the USB port is used to identify the type and
serial number of the EVM under test, load the desired FPGA configuration file, capture data from ADC
EVMs, and send test pattern data to the DAC EVMs.
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11
Software Start-Up
4
Software Start-Up
4.1
Installation Instructions
•
•
•
•
•
•
•
•
•
www.ti.com
Download the latest version (v4.9 or higher) of the HSDC Pro GUI to a local location on a host PC.
This program can be found on www.ti.com by entering high speed data converter pro GUI installer in
the search bar.
Unzipping the software package generates a folder called High Speed Data Converter Pro - Installer
vx.xx.exe, where x.xx is the version number. Run this program to start the installation.
Make sure to disconnect all USB cables from any TSW14xxx boards before installing the software.
Follow the onscreen instructions during installation.
Click on the Install button. A new window opens. Click the Next button.
Accept the license agreement. Click on the Next button to start the installation. After the installer has
finished, click the Next button one last time.
The installation is now complete. The GUI executable and associated files reside in the following
directory:
C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro.
Power-up the TSW14DL3200 under test.
To start the GUI, click on the file called High Speed Data Converter Pro.exe, located under
C:\Program Files\Texas Instruments\High Speed Data Converter Pro.
NOTE: If an older version of the GUI has already been installed, make sure to uninstall the older
version before loading a newer version. If the GUI detects that a newer version of the GUI is
available online (DATACONVERTERPRO-SW), the GUI assists the user with downloading
the latest version from the TI website. The GUI automatically interrogates the product
website for latest version every seven days but the latest version check can also be manually
invoked through use of the pulldown menu Help->Check for updates.
NOTE: When new TI high-speed data converter EVMs or interface modes become available that are
not currently supported by the latest release of the HSDC Pro GUI, the
HSDCProv_xpxx_Patch_setup executable, available on the TI website under the High Speed
Data Converter Pro Software product folder (DATACONVERTERPRO-SW), allows the user
to add these items to the GUI device list. After the patch is downloaded, follow the onscreen
instructions to run the patch. The software displays the files to be added. After running the
patch, open HSDC Pro and the new parts and modes appear in the ADC and DAC device
drop-down selection box. The patch is always specific to a core GUI version and does not
work for a GUI version for which the patch was not explicitly created.
12
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4.2
USB Interface and Drivers
•
•
•
•
Connect a USB 3.0 cable between J7 of the TSW14DL3200EVM and a host PC.
Connect an ADC EVM to be tested with the TSW14DL3200EVM.
Connect the provided power cable between the EVM and a 12-VDC source. LED D19 now turns
green.
Set SW2 to on. LEDs D22, D9-D13, D15-D17, and D19-D21, as shown in Figure 3, all turn blue now.
Figure 3. Power Indicator LEDs
NOTE: Power-up and configure the ADC EVM. This step is required to provide data to the
TSW14DL3200EVM, which is needed for I/O delay calibration, and occurs immediately after
the firmware is downloaded.
Click on the High-Speed Data Converter Pro icon that was created on the desktop panel, or go to
C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro and double click on the
executable called High Speed Data Converter Pro.exe to start the GUI.
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13
Software Start-Up
www.ti.com
The GUI first attempts to connect to the EVM USB interface. If the GUI identifies a valid board serial
number, as shown in Figure 4, a pop-up opens displaying this value. The user can connect several
TSW14DL3200EVMs to one host PC, but the GUI can only connect to one EVM at a time. When multiple
boards are connected to the PC, the pop-up displays all of the serial numbers found. The user then
selects which board to associate the GUI with.
Figure 4. TSW14DL3200EVM Serial Number
Click OK to connect the GUI to the board. The top level GUI, as shown in Figure 5, then opens.
Figure 5. High-Speed Data Converter Pro GUI Top Level
A new pop-up opens with the message No firmware. Please select a device to load firmware into the
board. Click on OK.
If the message No Board Connected opens, double check the USB cable connections and that power
switch SW2 is in the on position. Remove the USB cable from the board then re-install. Click on the
Instrument Option tab at the top left of the GUI and select Connect to the Board. If this process still does
not correct the issue, check the status of the host USB port.
14
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Downloading Firmware
www.ti.com
When the software is installed and the USB cable is connected to the TSW14DL3200EVM and the PC,
the TSW14DL3200 USB 3.0 converter must be located in the Hardware Device Manager under the
universal serial bus controllers as shown in Figure 6, labeled as Cypress FX3 USB Streamer Example
Device. When the USB 3.0 cable is removed, this driver is no longer visible in the device manager. If the
drivers are present in the device manager window and the software still does not connect, remove the
USB 3.0 cable from the board then reconnect. Attempt to connect to the board. If the problem still exists,
cycle power to the board and repeat the prior steps.
Figure 6. Hardware Device Manager
5
Downloading Firmware
The TSW14DL3200EVM has a Xilinx XCKU060 device that requires firmware to be downloaded every
time power is cycled to operate. The firmware files needed are special .bin formatted files that are
provided with the software package. The files used by the GUI currently reside in the directory called
C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14DL3200 Details\Firmware.
To load a firmware after the GUI has established connection, click the Select ADC window in the top left of
the GUI and select the device to evaluate, as shown in Figure 7 (for example,
ADC12DL3200_LDEMUX_1_DES_EN_0).
Figure 7. Select ADC Firmware to be Loaded
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15
Downloading Firmware
www.ti.com
The GUI prompts the user to update the firmware for the ADC. Click Yes. The GUI displays the message
Downloading Firmware, Please Wait. The software now loads the firmware from the PC to the FPGA, a
process that takes approximately 3 seconds. When completed, the GUI reports an interface type in the
lower right corner and LED D2 turns green. Enter an ADC output data rate in the GUI and click on the
Capture button. When data are captured LED D1 turns on. Figure 8 shows the status LEDs after both the
firmware has been loaded and data are captured,
Figure 8. Status LEDs
For more information regarding the use of the TSW14DL3200EVM with a TI ADC or DAC wide LVDS
interface EVM, consult the High-Speed Data Converter Pro GUI User's Guide and the individual EVM
User’s Guide, available on www.ti.com.
If the message appears as shown in Figure 9, verify that all jumpers are in the default position and all
power status LEDs are illuminated. If certain jumpers are not installed in the proper location, the USB 3.0
controller does not boot from flash memory. If any power status LED is off, there may be a problem with a
power supply on the board, which can prevent the firmware from downloading. Unplug and re-install the
USB connector and try to connect to the board. If this connection fails, cycle the power switch to reinitialize the power-up sequencer to try to correct this problem.
Figure 9. Download Firmware Error Message
16
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STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,
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This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.
These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation
modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
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