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Texas Instruments ADS54J54 EVM Users (Rev. A) User guides
User's Guide
SLAU616A – January 2015 – Revised January 2016
ADS54J54 Evaluation Module
This document outlines the basic steps and functions that are required to ensure the proper operation of
the Texas Instruments (TI) ADS54J54 Evaluation Module (EVM). The EVM includes an ADS54J54EVM, a
cable for connection to an external 5-VDC power supply, and a mini-USB cable. This EVM is designed to
be used with the TI TSW14J56EVM JESD204B capture card using an FMC connector interface or FPGA
development boards, such as the Xilinx KC705 or Altera Arria V. The ADS54J54EVM contains an
ADS54J54 (14-bit) four-channel, 500-MSPS ADC. The EVM also contains a TI LMK04828 clock jitter
cleaner. When used with the TSW14J56EVM, JESD204B standard output data from the EVM is captured
and sent to a host PC for analysis. This guide helps users to quickly evaluate the performance of the
ADS54J54EVM board by capturing and displaying waveforms using the TSW14J56 with the High Speed
Data Converter Pro GUI software. The EVM schematics, BOMs, and layout files are found in the design
package under the ADS54J54EVM tool folder on www.ti.com.
1
2
3
Contents
Introduction ................................................................................................................... 2
1.1
Overview ............................................................................................................. 2
1.2
Block Diagram ....................................................................................................... 2
Software Control ............................................................................................................. 4
2.1
Installation Instructions ............................................................................................. 4
2.2
Software Operation ................................................................................................. 4
Basic Test Setup ........................................................................................................... 14
3.1
Test Block Diagram ............................................................................................... 14
3.2
TSW14J56EVM Setup ............................................................................................ 15
3.3
ADS54J54EVM Quick-Start Procedure ........................................................................ 15
List of Figures
....................................................................................
1
Block Diagram of the ADS54J54EVM
2
Top-Level Block Diagram Window of the ADS54J54 GUI.............................................................. 5
3
ADS54J54 Controls Tab .................................................................................................... 6
4
JESD204B Configuration Tab .............................................................................................. 8
5
LMK04828 PLL1 Configuration Tab ....................................................................................... 9
6
LMK04828 PLL2 Configuration Tab ..................................................................................... 10
7
LMK04828 Clock Outputs Tab
8
LMK04828 SYSREF and SYNC tab ..................................................................................... 12
9
Low Level Controls Tab ................................................................................................... 13
10
Test Setup ................................................................................................................... 14
11
High Speed Data Converter Pro (HSDC Pro) Sample Capture ...................................................... 17
...........................................................................................
2
11
List of Tables
1
Input and Output Connectors and Jumper Descriptions of the ADS54J54EVM..................................... 3
2
ADS54J54 Controls Tab Descriptions
....................................................................................
6
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ADS54J54 Evaluation Module
1
Introduction
1
Introduction
1.1
Overview
www.ti.com
The ADS54J54EVM is an evaluation module (EVM) used to evaluate Texas Instruments’ ADS54J54 ADC
and the LMK04828 clock jitter cleaner devices. The ADS54J54 (14-bit) is a four-channel, 500-MSPS ADC
with buffered analog inputs and outputs featuring a JESD204B interface. The EVM has transformercoupled analog inputs accommodating a wide range of signal sources and frequencies. The LMK04828
provides an ultra-low-jitter and phase-noise sample clock along with system reference clocks and a device
sample clock for the mating FPGA capture board, for a complete JESD204B subclass 1 clocking solution.
The ADS54J54 and LMK04828 are controlled through an easy-to-use software GUI enabling quick
configuration for a variety of uses.
The TSW14J56EVM connects directly to the ADS54J54EVM. The High Speed Data Converter Pro
software GUI processes the data from the TSW14J56EVM to quickly assess the performance of the
ADS54J54. The FMC output interface connector of the EVM has also been verified to be compatible with
both the Xilinx KC705 and Altera Arria V evaluation platforms.
1.2
Block Diagram
The block diagram for the ADS54J54EVM is shown in Figure 1. The various inputs, outputs, and jumpers
of the ADS54J54EVM are described in Table 1.
SYNCAB
SYNCCD
ADS54J54
SYSREF
Dev Clock
Dev Clock
SYSREF CD
8 TX
SYSREF AB
ChA
ChB
ChC
ChD
FMC Connector (Male)
ADS54J54 EVM
LMK04828
JESD204B
Clock Generator
5-V DC
Bench
Supply
PC (Windows 7)
Figure 1. Block Diagram of the ADS54J54EVM
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Table 1. Input and Output Connectors and Jumper Descriptions of the
ADS54J54EVM
Component
Description
J1 (AINP)
Analog input for channel A, single-ended or positive side of differential.
(Negative side of differential on J11, normally not installed.)
J2 (BINP)
Analog input for channel B, single-ended or positive side of differential.
(Negative side of differential on J12, normally not installed.)
J23 (CINP)
Analog input for channel C, single-ended or positive side of differential.
(Negative side of differential on J25, normally not installed.)
J22 (DINP)
Analog input for channel D, single-ended or positive side of differential.
(Negative side of differential on J24, normally not installed.)
J19 (EXT_ADC_CLK)
Single-ended ADC clock input
J20 DCLK
Optional device clock output, single-ended transformer coupled
J8 (+5V)
Positive power connection (5 V)
J9 (GND)
Negative power connection (GND)
J13 (Main PWR)
5-V input from +5-V bench supply (cable supplied)
J14 (REF OSC_IN)
External reference option for LMK04828, REFOUT1 source on J16 and
CPLD_CLK
J16 (REFOUT1)
10-MHz CMOS level reference output or frequency of REF OSC_IN if
option selected
J6 (USB)
USB connection
J3
JESD204B FMC interface connector
J5 (TRIG_IN)
External trigger input for ADS58J89 burst mode. Not used for ADS54J54.
J26 (TRIG_OUT)
Trigger output, buffered version of ADS58J89 burst mode trigger, normally
connected to trigger input of TSW14J56 capture card. Normally not used for
ADS54J54.
J7 (LMK CLKIN1_P)
CLKIN0 input for LMK04828. Option to provide an external clock source to
the LMK in place of on-board 100-MHz VCXO.
J10 (CLKOUT6P)
DCLKOUT6p from LMK04828. Default is LVPECL at 250 MHz.
J15 (CLKOUT6N)
DCLKOUT6n from LMK04828. Default is LVPECL at 250 MHz.
J17 (CLKOUT7P)
SDCLKOUT7p from LMK04828. Default is LVPECL at 6.25 MHz.
J4 (CLKOUT7M)
SDCLKOUT7m from LMK04828. Default is LVPECL at 6.25 MHz.
J18 (PROG CPLD)
JTAG interface for CPLD U3
SW1 (ADC_RESET)
Switch to reset the ADC using the RESET input pin
SW2 (TRIGGER)
Pushbutton trigger source for ADS58J89 burst mode. Not used for
ADS54J54.
JP6 (XO_PWR)
Provides power to VCXO Y2 or oscillator Y3
SJP3 (REF_SEL)
Selects input or external reference source for LMK, J16 and CPLD. Default
is internal (on-board) 10-MHz oscillator.
JP2 (CDC_CLK)
Reference clock buffer output enable
JP5 (REF_PWR)
Power enable for 10-MHz reference oscillator
SJP1 (REF_EN)
Enable for 10-MHz reference oscillator
SJP4-SJP11
USB/FMC Interface select. Default is using USB.
JP4 (ENABLE)
U11 enable. Install jumper to disable switcher U11. Default is uninstalled.
JP1 (PWRGD)
Test point for power good output pin from U11.
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Software Control
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Software Control
This section provides installation instructions for the ADS54J54 GUI and descriptions of the various
controls.
2.1
Installation Instructions
1. Download the software from the ADS54J54EVM resource page: http://www.ti.com/tool/ads54j54evm.
2. Extract the files from the zip file named ADS54J54 EVM SPI GUI vXpY installer.zip where XpY
represents the version number.
3. Run setup.exe and follow the installation prompts.
4. Start the GUI by going to Start Menu → All Programs → Texas Instruments ADCs → ADS54J54
EVM GUI.
5. When plugging the board into the computer for the first time through the USB cable, you are prompted
to install the USB drivers.
• Microsoft® Windows® XP: If Windows XP does not automatically install the drivers, follow the
prompts on the screen to do so. Do not let Windows XP search Microsoft Update for the drivers,
but do let Windows XP install the drivers automatically.
• Windows 7: After installing the GUI, Windows 7 should automatically be able to install the drivers
for the ADS54J54EVM with no user input.
2.2
Software Operation
The software GUI allows full programming control of the ADS54J54 and LMK04828 devices. Figure 2
shows the GUI front panel which contains a block diagram of the ADS54J54. Clicking on the various tabs
of the ADS54J54 EVM SPI GUI allows configuration of the settings contained within that tab. Detailed
descriptions for each tab of the GUI are given in this section. Please refer to the ADS54J54 data sheet
(SLASE67) for more detailed explanations of the register fields.
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2.2.1
Top-Level GUI Controls
Figure 2 shows the top-level view of the GUI which contains the block diagram of the ADS54J54. Controls
for the ADS54J54 are under the ADS54J54 tab while controls for the LMK04828 are under the LMK04828
tab. The Low Level View tab allows detailed bit-level access to all SPI registers of both the ADS54J54 and
LMK04828. At all times, the status of the USB link between the PC and the EVM is indicated by an LED
indicator. A green indicator means the USB link is active. A red LED indicates the USB link must be reset.
The Reconnect FTDI button will attempt to reestablish the USB link between the PC and the EVM. For the
GUI to operate correctly, it is important that the ADS54J54 and LMK04828 each be reset by clicking on
the respective reset control. The reset control will reset all the internal SPI registers to their default poweron state, and then set the device in 4-wire SPI mode of operation. The USB interface on the EVM requires
the ADS54J54 and LMK04828 to be in 4-wire SPI mode for the SPI readback function to work. If power is
disrupted to the EVM at any time, a reset for each device is required.
Figure 2. Top-Level Block Diagram Window of the ADS54J54 GUI
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ADC Controls
Clicking on the ADS54J54 tab in Figure 2 takes the user to a bank of tabs for control of the ADS54J54,
one of which is the ADC Controls tab, as shown in Figure 3. The ADC Controls tab controls various ADC
functions such as the over-range detection, test patterns, output modes, input clocking modes, and power
down controls. Table 2 describes the controls seen in this window. The higher level tabs remain visible at
all times so that the user may quickly move to controls for the LMK04828 or to low-level register controls.
Figure 3. ADS54J54 Controls Tab
Table 2. ADS54J54 Controls Tab Descriptions
6
Control
Description
Device Reset
Resets the ADS54J54 SPI registers and sets the device in 4-wire SPI mode
VREF Voltage
Selects the reference voltage and thus, the full scale voltage
Input Clock Divider AB and CD
Selects an input divider of /1, /2, or /4 for channels A and B or channels C and D,
respectively
CLK SEL AB and CD
Selects the clock input for channels A and B or for channels C and D, respectively
CLK Phase SEL AB and CD
Selects the phase relationship of the clock input for channels A and B or for channels C
and D, respectively
CLK SW AB and CD
Used in conjunction with changing the clock phase relationship of channels A and B or
channels C and D.
Data Format
Selects offset binary or two's complement data format
Decimation Filter EN AB and CD
Enables the decimation filter for channels A and B or channels C and D
Decimation Filter AB and CD
Selects whether the decimation filter will be high-pass of low-pass
Fast OVR Length AB and CD
Selects how long the OVR output is active upon overrange detection
Fast OVR Threshold AB and CD
Sets how close to full scale the input can be before the fast overrange will detect
overrange
OVRx OUT EN
Selects the function of the fast OVR pin for each of the four channels
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Table 2. ADS54J54 Controls Tab Descriptions (continued)
Control
Description
Ch AB and CD Test Pattern
Selects an output test pattern or normal sample data for channels A and B or channels
C and D
Test Pattern
Selects the specific test pattern to be output when test pattern is selected
PRBS Select
Selects the length of the PRBS test pattern
PRBS Enable
Selects the PRBS test pattern to be output on individual serial lane outputs
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2.2.3
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JESD204B Controls
Clicking on JESD204B Configuration opens the JESD204B Configuration controls tab, shown in Figure 4.
Use the ADS54J54 data sheet (SLASE67) for reference to assist with the descriptions of these various
controls. The ADS54J54 EVM SPI GUI comes with a number of configuration files that will set the EVM
into a known and tested configuration that works with the TSW14J56 capture card. Full control of the
JESD204B configuration is possible with the use of this tab of controls. Of primary importance are the
JESD204B parameters L, M, F, and K. The parameter M refers to the number of data converters in a
JESD204B link, and since the ADS54J54 is a four channel device, then M is assumed to be 4. The
parameter L refers to the number of lanes used. The ADS54J54 may use one lane per channel when in 2x
decimation mode to output 250 Msps or use 2 lanes per channel when outputting sample data at 500
Msps. L may then be either 4 or 8. The parameter F is the number of octets (an octet is half of a sample
transmitted per lane). The parameter K is a number of 'frames' of sample data bundled into a multiframe
of length K frames, and this sets the period of the SYSREF clock signal. The TSW14J56 capture card (or
other FPGA receiving JESD204B serial sample data from the EVM) must be configured with the same
parameters as the ADS54J54.
Figure 4. JESD204B Configuration Tab
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2.2.4
LMK Controls
Click the LMK04828 tab located in the top tab bar of the GUI. The bank of LMK04828 control tabs is
selected as shown in Figure 5. There are four lower level tabs for control of the LMK04828. The
LMK04828 is a dual-PLL clock device so there is a tab for setting controls for the first PLL and a tab for
setting controls of the second PLL. There is a tab for setting controls related to the programming of the
JESD204b SYSREF and SYNC signals. There is a tab for individual control of each of the 14 clock
outputs of the LMK04828. The first PLL is represented in the PLL1 Configuration tab. The first PLL
essentially takes a low-frequency reference and multiplies this up to an internal reference frequency. The
second PLL has a very clean narrow-bandwidth VCO of either 2.5 or 3.0 GHz that is locked to the internal
reference frequency from PLL1 and from this VCO the output clocks are generated.
Figure 5. LMK04828 PLL1 Configuration Tab
2.2.4.1
PLL1 Configuration
Much of this panel is organized in block diagram format to help visualize the function of the controls. The
function of PLL1 is to take an external reference clock, such as the 10-MHz reference from an oscillator
on the EVM, and generate a clean, low-jitter intermediate-frequency clock for use by the second PLL loop.
There are numerous integer divider values that may be used to create this intermediate frequency from
the external reference. This tab also contains the reset and power down controls for the whole LMK04828
device. Consult the LMK04828 data sheet (SNAS605) and design tools for more information regarding the
proper settings for configuring PLL1, particularly for the proper settings for the PLL1 phase detector and
charge pump values.
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PLL2 Configuration
Clicking PLL2 Configuration opens the PLL2 Configuration tab as shown in Figure 6. Much of this panel is
organized in block diagram format to help visualize the function of the controls. In this tab there is the
control to select whether an external VCO is used or an internal VCO of frequency 2.5 GHz or 3.0 GHz.
Several integer divider ratios can be set to lock the VCO to the frequency from PLL1, labeled as OSCin.
After configuring PLL2 to select a VCO and locking it to the input reference resulting in the desired VCO
frequency, this VCO frequency is then used to generate 14 clock outputs which are normally used as 7
pairs of device clock and SYSREF system reference clocks. One of the device clock/SYSREF pairs is
connected to the FMC connector to source DCLK/SYSREF to the FPGA on the TSW14J56 capture card.
Another DCLK/SYSREF pair is used to clock the ADS54J54. The other 5 pairs of clocks are normally
powered down but may be configured as additional clock outputs. The block diagram at the bottom of the
PLL2 Configuration tab illustrates some of the operations that might be applied to the 7 DCLK/SYSREF
pairs, such as divider ratios or delay adjustments. The next two tabs provide the controls to select all
these available features that may be used to condition the DCLK/SYSREF pairs for a specific use. The
LMK04828 datasheet is indispensable in understanding the function of each of these many controls and
how these controls should be set for a specific use of the EVM.
Figure 6. LMK04828 PLL2 Configuration Tab
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2.2.4.3
Clock Output Controls
Clicking Clock Outputs opens the LMK04828 Clock Outputs tab, shown in Figure 7. This tab is organized
into 7 sections representing the 7 pairs of DCLK/SYSREF that the LMK04828 can generate. For each of
the 7 pairs of DCLK/SYSREF, there are a number of controls that apply to both outputs, such as the
option to power down the pair of signals completely, if not needed. For both DCLK and SYSREF, there is
an option to select what type of output driver is to be used, such as LVDS or LVPECL. There are controls
to enable things like delay or inversion. For the DCLK, there is a control to select a divider ration to divide
the PLL2 VCO clock down to the desired output frequency. For example, if the ADS54J54 EVM is to be
operated at 500 Msps, then the configuration file supplied with the GUI will select the 3.0-GHz VCO and
select a divider ratio of 6 to generate a 500-MHz DCLK. If the TSW14J56 capture card is used, the
TSW14J56 needs to see a DCLK reference that is one-twentieth the line rate of the serial data stream so
the divider ratio chosen is 12 to generate a 250-MHz DCLK to the FMC connector. These two divider
ratios can be seen in Figure 7.
Figure 7. LMK04828 Clock Outputs Tab
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SYSREF and SYNC Controls
Clicking SYSREF and SYNC opens the LMK04828 SYSREF and SYNC tab, shown in Figure 8. This tab
has controls specific to the generation of the SYSREF outputs of the LMK04828. Along the top of the tab
are controls that are common to all 7 of the SYSREF outputs, such as the SYSREF divider. Once the
JESD204B link is configured for a specific line rate and all JESD204B parameters such as L, M, F, and K
are chosen, then the SYSREF divider should be set to match the SYSREF rate to the Local MultiFrame
Clock period, or LMFC period. For the default configuration of the ADS54J54 EVM as configured by the
ADS54J54_500M_LMF881 config file, the device is set up for 2 lanes per channel, 1 octet per lane, with a
K value of 32. The resulting SYSREF divider value is 1920 as shown in Figure 8, matching the SYSREF
rate to the LMFC rate of the ADS54J54 and TSW14J56 capture card configurations. Along the bottom of
the tab are controls that are specific to each of the 7 SYSREF outputs, such as delay settings.
Figure 8. LMK04828 SYSREF and SYNC tab
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2.2.4.5
Low Level View
Clicking Low Level View opens the ADS54J54 EVM SPI GUI Low Level View tab, shown in Figure 9. This
tab allows for direct read/write access to each bit of each SPI address for both the ADS54J54 and the
LMK04828. This is also the tab used to load a previously saved configuration file or to save a new
configuration file once a specific EVM configuration is properly set up. There are several ways to
accomplish a read or write to a specific register. Highlighting a particular Register Name will cause the bits
of that register to display on the right side of the window. If there is a bit in that register that has a
datasheet definition, then that definition is shown in the GUI. In the example shown in the figure, bit 4 of
address 0x00 is the bit to choose between 3-wire SPI or 4-wire SPI for the LMK04828. To set a bit to a '1',
check the box for that bit in the W column, then click Write Register. The GUI will write that register and
then immediately read back that register. If the write was successful, then the R column should reflect
what was just written from the W column. Another way to do an SPI access is to enter the address in the
Address control at the bottom of the window and then click the Write Register or Read Register below it.
Be sure to select the correct 'Block' first. If there are more than one devices with SPI access such as on
this EVM, then there is a 'Block' for each device. The ADS54J54 EVM SPI GUI has a Block of ADS54J54
addresses and a Block of LMK04828 addresses.
Figure 9. Low Level Controls Tab
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Basic Test Setup
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Basic Test Setup
This section outlines basic testing of the ADS54J54EVM.
3.1
Test Block Diagram
The test setup for the ADS54J54EVM is shown in Figure 10. The TSW14J56 Capture Card is used to
capture data from the ADS54J54 EVM, which is then transferred to the computer for analysis in the HSDC
Pro software. The analog signal into a channel of the ADS54J54 can be from any high-quality low-jitter
analog signal source. The clock source is from the LMK04828, but the board provides an option to use an
external clock source, such as a HP8644B for the ADC sample clock. Note that a narrow bandpass filter is
recommended on the analog source, which is necessary to remove as much phase noise from the signal
source so as to achieve the best performance. The performance can be increased using external clock
mode as this allows for the use of a filter on the clock source.
Figure 10. Test Setup
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3.2
TSW14J56EVM Setup
See the TSW14J56EVM User's Guide (SLWU086) for a more detailed explanation of the TSW14J56
setup and its features. This document assumes that the HSDC Pro software and the TSW14J56 pattern
capture and generation board are both installed and functioning properly. This information can be found at
http://www.ti.com/tool/tsw14j56evm.
3.3
ADS54J54EVM Quick-Start Procedure
Connect J3 of a ADS54J54EVM into J4 of a TSW14J56 JESD204B capture card.
3.3.1
TSW14J56 Data Capture Card
1. Connect a 5-V power supply to connector J11 of the TSW14J56EVM.
2. Flip switch SW6 to the ON position.
3. Insert a USB cable into the USB port on the TSW14J56. Connect the other end to the PC.
3.3.2
ADS54J54EVM
1. Connect a bench 5-V power supply, or equivalent, to the connector J13 using the supplied power
supply cable. Alternatively, power may be supplied to the EVM by way of the red banana jack J8 for +5
V and the black banana jack J9 for ground.
2. Connect a USB cable to the USB port on the ADS54J54EVM and connect the other end to the PC.
3. Connect a signal source to an analog input SMA connector such as J1 (A_INP). For single-tone
testing, a bandpass filter should be used to achieve the best SNR and harmonic performance.
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ADS54J54 GUI
Use the following steps for setting up the ADS54J54 GUI:
1. Start the ADS54J54 EVM GUI by selecting Start Menu → Program Files → Texas Instruments
ADCs → ADS54J54 EVM GUI.
2. In the upper right-hand corner, there is either a red or green LED indicator labeled USB Status and a
button labeled RECONNECT FTDI?. If the LED button is red, then click the button until the LED
indicator turns green. This indicates that the ADS54J54EVM is connected to the computer.
3. Under the ADC Controls tab of the ADS54J54 tab, click on the Reset ADC button. The ADS54J54
EVM SPI GUI always does a read-back of every register write to verify that the desired value was
written. The ADS54J54 powers up in 3-wire SPI mode while the GUI requires 4-wire mode for the
readback function to work properly. The Reset ADC button will reset the ADC and set the device in 4wire mode so that the GUI will continue to work properly.
4. Under the PLL1 Controls tab of the LMK04828 tab, click on the Reset LMK button. The LMK04828
powers up in 3-wire SPI mode while the GUI requires 4-wire mode for the readback function to work
properly. The Reset LMK button will reset the LMK04828 and set the device in 4-wire mode so that
the GUI will continue to work properly.
5. On the low-level tab, click the Load Config button. Choose one of the configuration files available. If
choosing ADS54J54_500M_442.cfg, this configuration file will set the ADS54J54 to use four
JESD204B lanes and set up the 2x decimation filter to output 250 Msps while the LMK04828 is
configured to provide a 500-MHz device clock to the ADS54J54. If choosing
ADS54J54_500M_881.cfg, the ADS54J54 will not decimate the sample output to 250 Msps but will
output 500 Msps on 8 JESD204B lanes.
6. The two PLL's of the LMK04828 should now be locked. This is indicated on the ADS54J54 circuit
board by the illuminated LED's, D4 (PLL2 LOCKED) and D1 labeled (LMK LOCKED).
7. The TSW14J56 capture card should now be receiving a DEVICE clock and a SYSREF clock. This
causes the receiver FPGA to assert the JESD204B SYNC high, since synchronization has not been
established with the transmitter ADC. This is indicated by LED D3 (JESD_SYNC) illuminating on the
ADS54J54EVM. The SYSREF signal can be observed on either SMA J4 or J17 of the ADC EVM.
8. The TSW14J56 capture card should now be receiving valid data.
9. Since a periodic SYSREF signal acts as a sub-harmonic clock of the converter sampling clock and
may have spurious effect on the converter performance, it may be turned off during normal operation
once synchronization has been achieved. Click on the tab labeled LMK0428 Clock Outputs located at
the top of the GUI. Check the control for SDCLKout_PD in the block of controls for clocks CLKout 2
and 3. (See Figure 8) This will power down the SYSREF to the ADS54J54. The SYSREF must be
running initially in order to establish a JESD204B link between the ADS54J54 and the FPGA on the
TSW14J56 but after initialization, the SYSREF is no longer needed and may result in clock spurs
coupling into the ADS54J54, reducing performance.
NOTE: If SYSREF is turned off during normal operation, TX and RX devices must have the ability to
generate a Generate SYSREF request to the LMK04828 clock generator whenever a
synchronization request is detected at the SYNC interface.
10. If the JESD204B link does not get established, make sure the SYSREF MUX panel on the ADS54J54
GUI is set to SYSREF CONTINUOUS. If this is set to any other value, the SYSREF outputs will be
disabled from the LMK04828, thus preventing synchronization from occurring.
16
ADS54J54 Evaluation Module
SLAU616A – January 2015 – Revised January 2016
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Copyright © 2015–2016, Texas Instruments Incorporated
Revision History
www.ti.com
3.3.4
High Speed Data Converter Pro (HSDC Pro)
1. Start the HSDC Pro software tool by selecting Start Menu → All Programs → Texas Instruments
ADCs → High Speed Data Converter Pro.
2. When prompted for the serial number of the board, select the serial number that represents the
TSW14J56 that has been connected to the ADS54J54. This number is on a sticker on the TSW14J56
board.
3. In the Select ADC drop-down box, select ADS54J54_LMF442. If it asks to download the firmware,
select Yes. Multiple LEDs light up on the TSW14J56, once the firmware has finished downloading.
4. Select Single Tone from the Test Selection drop-down menu.
5. At the bottom-left corner, enter 250M in the ADC Output Data Rate box. If not using an external 10MHz syncing signal from the analog signal source, then the 500-MHz sample clock from the
LMK04828 will not be coherent with the analog signal generator. In this case, do not select Auto
Calculation of Coherent Frequencies. If the clocks are synchronized with an external 10M syncing
signal and are to be coherent, then select Auto Calculation of Coherent Frequencies.
6. If a windowing function is desired, then Blackman should be selected above the plot window. If the
clocks are synchronized with an external 10M syncing signal and coherent, select Rectangular.
7. All boards and software are now setup. Click the Capture button. A sample capture is shown in
Figure 11 for the ADS54J54 with a 250-MHz clock and 170-MHz input frequency.
Figure 11. High Speed Data Converter Pro (HSDC Pro) Sample Capture
Revision History
Changes from Original (January 2015) to A Revision .................................................................................................... Page
•
•
•
•
Changed first paragraph by removing reference to an included 5-VDC power supply to a cable for connection to an
external 5-VDC power supply. ........................................................................................................... 1
Changed Block Diagram of the ADS54J54EVM image. ............................................................................. 2
Changed the description in the Input and Output Connectors and Jumper Descriptions of the ADS54J54EVM table for J13
(Main PWR) from a provided 5-VDC power supply, to +5-V bench supply (cable supplied). ................................... 3
Changed list item one in the ADS54J54EVM section. .............................................................................. 15
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
SLAU616A – January 2015 – Revised January 2016
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Copyright © 2015–2016, Texas Instruments Incorporated
Revision History
17
STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or
documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.
Acceptance of the EVM is expressly subject to the following terms and conditions.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software
License Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment
by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any
way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or
instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as
mandated by government requirements. TI does not test all parameters of each EVM.
2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,
or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the
warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to
repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall
be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit
to determine whether to incorporate such items in a finished product and software developers to write software applications for
use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless
all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause
harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is
designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of
an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
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FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law of
Japan to follow the instructions below with respect to EVMs:
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ
い。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
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4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
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6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE
DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY
THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND
CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY
OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD
PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY
INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF
THE EVM.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION
SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY
OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS,
LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL
BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION
ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM
PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER
THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE
OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND
CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
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