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Texas Instruments DAC60096EVM User guides
User's Guide
SLAU644 – November 2015
DAC60096 Evaluation Module
This user's guide describes the characteristics, operation, and use of the DAC60096 evaluation boards
(EVMs). This user’s guide also discusses the proper setup and configuration of both software and
hardware, and reviews various aspects of program operation. A complete circuit description, schematic
diagram, and bill of materials (BOM) are also included in this document.
1
2
3
4
5
6
Contents
Overview ...................................................................................................................... 3
1.1
DAC60096EVM Kit Contents ...................................................................................... 3
1.2
Related Documentation from Texas Instruments ............................................................... 3
DAC60096EVM Hardware Setup .......................................................................................... 4
2.1
Theory of Operation for DAC60096 Hardware .................................................................. 4
2.2
Signal Definitions of J4 (20-Pin Connector) ..................................................................... 5
2.3
SDM-USB-DIG Platform Theory of Operation .................................................................. 6
DAC60096EVM Software Setup ........................................................................................... 7
3.1
Operating Systems for DAC60096EVM Software .............................................................. 7
3.2
DAC60096EVM Software Installation ............................................................................ 7
DAC60096EVM Hardware Overview ...................................................................................... 8
4.1
Electrostatic Discharge Warning .................................................................................. 8
4.2
Connecting the Hardware.......................................................................................... 9
4.3
Connecting the USB Cable to the SDM-DIG .................................................................. 10
4.4
DAC60096EVM Power Configurations ......................................................................... 10
4.5
SPI Communication Signals and Digital Inputs ............................................................... 14
4.6
External Trigger.................................................................................................... 14
DAC60096EVM Software Overview .................................................................................... 15
5.1
Starting the DAC60096EVM Software .......................................................................... 15
5.2
DAC60096EVM Software Features ............................................................................. 16
DAC60096EVM Documentation .......................................................................................... 20
6.1
DAC60096EVM Board Schematic .............................................................................. 20
6.2
DAC60096EVM PCB Components Layout .................................................................... 22
6.3
DAC60096 Test Board Bill of Materials ........................................................................ 23
List of Figures
1
DAC60096EVM Hardware Setup .......................................................................................... 4
2
DAC60096 Test Board Block Diagram .................................................................................... 4
3
SDM-USB-DIG Platform Block Diagram .................................................................................. 6
4
DAC60096EVM Installer Directory
5
DAC60096EVM Install Path ................................................................................................ 7
6
Typical Hardware Connections on the DAC60096EVM ................................................................ 9
7
Confirmation of SDM-USB-DIG Platform Driver Installation .......................................................... 10
8
DAC Output Connection Headers ........................................................................................ 11
9
DAC60096EVM GUI Location ............................................................................................ 15
10
DAC60096EVM GUI – Power On
11
12
........................................................................................
.......................................................................................
Low Level Configuration Page ............................................................................................
Low Level Configuration Page Available Options ......................................................................
7
15
16
16
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13
High Level Configuration Page ........................................................................................... 17
14
DAC Channel Write Order of Operation ................................................................................. 18
15
Write All DACs Button ..................................................................................................... 18
16
Register Control Buttons .................................................................................................. 18
17
Digital Input Buttons........................................................................................................ 19
18
DAC60096EVM Board Schematic ....................................................................................... 20
19
DAC60096EVM Board Schematic ....................................................................................... 21
20
DAC60096EVM PCB Components Layout
.............................................................................
22
List of Tables
1
Contents of DAC60096EVM Kit ............................................................................................ 3
2
Related Documentation ..................................................................................................... 3
3
J4 Signal Definition .......................................................................................................... 5
4
Default Jumper Settings
5
DAC60096EVM Power Supply Configuration
6
7
8
9
10
11
2
.................................................................................................... 8
.......................................................................... 10
DAC60096EVM DAC Signal Connections .............................................................................. 11
SPI Signal Definition ....................................................................................................... 14
External Trigger............................................................................................................. 14
Register Controls ........................................................................................................... 19
Digital Inputs ................................................................................................................ 19
DAC60096 Test Board Bill of Materials ................................................................................. 23
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Overview
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1
Overview
This EVM features the DAC60096 device, a very low-power, 96 channel, 12-bit digital-to-analog converter
(DAC). The device provides unbuffered bipolar voltage outputs up to ±10.5 V. The DAC60096 can be
programmed for simultaneous update as well as simultaneous clear. In addition, a versatile external
conversion trigger allows each DAC to operate as an amplitude-independent square-wave generator.
1.1
DAC60096EVM Kit Contents
Table 1 details the contents of the EVM kit. Contact the TI Product Information Center nearest you if any
component is missing. TI highly recommends to verify that the user has the latest versions of the related
software at the TI website, www.ti.com.
Table 1. Contents of DAC60096EVM Kit
1.2
Item
Quantity
DAC60096EVM PCB evaluation
board
1
SDM-USB-DIG platform PCB
1
USB extender cable
1
Related Documentation from Texas Instruments
The following documents provide information regarding TI's integrated circuits used in the assembly of the
DAC60096EVM. This user's guide is available from the TI web site under literature number SLAU644. Any
letter appended to the literature number corresponds to the document revision that is current at the time of
the writing of this document. Newer revisions may be available from the TI web site at http://www.ti.com/,
or call the Texas Instruments Literature Response Center at (800) 477-8924 or the Product Information
Center at (972) 644-5580. When ordering, identify the document by both title and literature number.
Table 2. Related Documentation
Document
Literature Number
DAC60096 Product Data Sheet
SBAS721
SDM-USB-DIG Platform User’s Guide
SBOU136
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DAC60096EVM Hardware Setup
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DAC60096EVM Hardware Setup
This section provides the overall system setup for the EVM. A personal computer (PC) runs software that
communicates with the SDM-USB-DIG platform, which generates the optional DVDD power and digital
signals used to communicate with the EVM board. Banana plug connectors are included on the EVM
board for external power supplies. Figure 1 displays the system setup for the DAC60096EVM.
Personal
Computer
(PC)
External Power
Source
USB Bus
from
Computer
SDM-USBDIG
20-Pin
Connector
DAC60096EVM
Figure 1. DAC60096EVM Hardware Setup
2.1
Theory of Operation for DAC60096 Hardware
A block diagram of the DAC60096EVM test board is displayed in Figure 2. The EVM board provides
banana plugs for the supplies, 4 header pins connected to the DAC60096 DAC outputs, external trigger
signal connection, optional external reference connection, and SPI input connections.
(Optional)
2.5-V Reference
External Power
(Banana Plugs)
Power
20-Pin
Conn. To
SDMUSB-DIG
SPI
DAC60096
96 CH
Output
External Trig Signal
SMA Connector
Figure 2. DAC60096 Test Board Block Diagram
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2.2
Signal Definitions of J4 (20-Pin Connector)
The DAC60096 EVM includes a 20-pin connector used to communicate between the EVM and the SDMUSB-DIG platform. Table 3 shows the pin out of the J4 connector.
Table 3. J4 Signal Definition
Pin on J4
Signal
Description
1
SCL
I2C Clock Signal (SCL)
2
DIG_GPIO2
GPIO – Control output or measure input
3
DIG_GPIO0
GPIO – Control output or measure input
4
DIG_GPIO3
GPIO – Control output or measure input
5
SDA
I2C data signal (SDA)
6
DIG_GPIO4
GPIO – Control output or measure input
7
DIG_GPIO1
GPIO – Control output or measure input
8
DIG_GPIO5
GPIO – Control output or measure input
9
MOSI
SPI data output (MOSI)
10
DIG_GPIO6
GPIO – Control output or measure input
11
VDUT
Switchable DUT power supply: 3.3 V, 5 V, Hi-Z (Disconnected). Note: When
VDUT is Hi-Z, all digital I/Os are Hi-Z as well.
12
DIG_GPIO7
GPIO – Control output or measure input
13
SCLK
SPI clock signal (SCLK)
14
DIG_GPIO8
GPIO – Control output or measure input
15
GND
Power return (GND)
16
DIG_GPIO9
GPIO – Control output or measure input
17
CS
SPI chip select signal (/CS)
18
DIG_GPIO10
GPIO – Control output or measure input
19
MISO
SPI data input (MISO)
20
DIG_GPIO11
GPIO – Control output or measure input
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DAC60096EVM Hardware Setup
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SDM-USB-DIG Platform Theory of Operation
The SDM-USB-DIG platform is a general-purpose data acquisition system that is used on several Texas
Instruments evaluation modules.
The core component of the platform is the MSP430F5528, an ultra-low power 16-bit MCU. The
microcontroller receives information from the host PC and translates it into I2C, SPI, or other digital I/O
patterns. The connected device, which in this case is the DAC60096 device, connects to the I/O interface
of the platform. During digital I/O transactions, the platform obtains information from the DAC60096 device
and sends to the host PC for interpretation. Figure 3 illustrates a block diagram of the platform..
SDM-USB-DIG
3.3 V
USB Bus
from
Computer
USB
+5.0V
MSP430F5528
uC
I2C
SPI
GPIO
Level
Translators
To Test Board
To Computer and Power Supplies
3.3-V
Regulator
Power on
Reset
USB 5.0 V
3.3 V
Power
Switching
Vdut
(Hi-Z, 3.3 V or 5 V)
Switched Power
Figure 3. SDM-USB-DIG Platform Block Diagram
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3
DAC60096EVM Software Setup
This section provides the procedure for EVM software installation.
3.1
Operating Systems for DAC60096EVM Software
The EVM software has been tested on the Microsoft® Windows® XP, and Windows 7 operating systems
with the United States and European regional settings. The software should also be compatible with other
Windows operating systems.
3.2
DAC60096EVM Software Installation
The software is available through the EVM product folder on the TI website. Once the software is
downloaded onto the PC, navigate to the DAC60096EVM folder, and run the Setup_DAC60096_EVM.exe
file, as shown in Figure 4. When the software is launched, an installation dialog opens, and prompts the
user to select an installation directory. If left unchanged, the software location defaults to C:\Program Files
(x86)\Texas Instruments\DAC60096 EVM as shown in Figure 5. The software installation automatically
copies the required drivers for the SDM-USB-DIG and DAC60096EVM to the PC. After the software is
installed, connecting the SDM-USB-DIG to a USB port may launch a driver installation dialog. Choose the
‘Install this driver software anyway’ option to continue with installation. (Note: On XP machines, choose to
have the system automatically find the driver/software.)
Figure 4. DAC60096EVM Installer Directory
Figure 5. DAC60096EVM Install Path
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DAC60096EVM Hardware Overview
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DAC60096EVM Hardware Overview
The subsequent sections provide detailed information on the EVM hardware and jumper configuration
settings. Table 4 displays the default configurations of all jumper connections on the DAC60096EVM.
Connect the USB extender cable from the SDM-USB-DIG to the PC.
Table 4. Default Jumper Settings
4.1
Jumper
Default Position
Function
JP1
Shunt on 2-3
DVDD selection:
spa• 1–2: J5 to DVDD pin
spa• 2–3: SDM-USB-DIG 5V to DVDD pin
JP2
Shunt on 1-2
2.5-V reference selection:
spa• 1–2: connects reference to onboard REF5025
spa• 2–3: connects reference to J9 Connection
Electrostatic Discharge Warning
Many of the components on the DAC60096EVM are susceptible to damage by electrostatic discharge
(ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling
the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
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4.2
Connecting the Hardware
To connect the SDM-USB-DIG to the EVM board, align and firmly connect the female and male ends of
the 20-pin connectors, Figure 6. Verify the connection is snug, as loose connections may cause
intermittent operation.
Figure 6. Typical Hardware Connections on the DAC60096EVM
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Connecting the USB Cable to the SDM-DIG
Figure 7 shows the typical response when connecting the SDM-USB-DIG platform to a USB port of a PC
for the first time. The PC usually responds with a Found New Hardware, USB Device pop-up dialog
window. The pop-up window then changes to Found New Hardware, Virtual COM Port (CDC). This popup indicates that the device is ready for use. The CDC driver is used for communication between the
SDM-USB-DIG and PC.
Figure 7. Confirmation of SDM-USB-DIG Platform Driver Installation
4.4
DAC60096EVM Power Configurations
The DAC60096EVM provides electrical connections to the device supply pins. The connectors and
optional configurations are shown in Table 5.
Table 5. DAC60096EVM Power Supply Configuration
Connector
Connection Type
Description
J1
Banana plug
External AVCC connection (12 V)
J3
Banana plug
External AVSS connection (–12 V)
J5
Banana plug
External DVDD selection:
spa• JP1 set to 1-2 connects J5 to DVDD pin
spa• JP1 set to 2-3 connects SDM-USB-DIG 5V to DVDD pin
J6
Banana plug
Digital Ground connection
J7
Banana plug
Power Ground connection
J8
Banana plug
REF (reference) GND and analog GND connection
J9
Banana plug
External REF (reference) connection:
spa• JP2 set to 1-2 connects reference to onboard REF5025
spa• JP2 set to 2-3 connects reference to J9 Connection
DVDD is supplied by the SDM-USB-DIG by default. If a different source is required, it is possible to
separate the SDM-USB-DIG and DVDD by setting the jumper JP1 to 1-2. An external supply can then
connect to J5 to power DVDD.
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The DAC60096EVM provides access to all DAC outputs through connection headers J11, J12, J13, and
J14 as shown in Figure 8, and listed in Table 6.
Figure 8. DAC Output Connection Headers
Table 6. DAC60096EVM DAC Signal Connections
Name
Connector
Description
DAC2_G3
J11-2
Un-buffered DAC output voltage
DAC1_G3
J11-4
Un-buffered DAC output voltage
DAC24_G4
J11-6
Un-buffered DAC output voltage
DAC22_G4
J11-8
Un-buffered DAC output voltage
DAC21_G4
J11-10
Un-buffered DAC output voltage
DAC20_G4
J11-12
Un-buffered DAC output voltage
DAC24_G2
J11-14
Un-buffered DAC output voltage
DAC23_G4
J11-16
Un-buffered DAC output voltage
DAC5_G3
J1-18
Un-buffered DAC output voltage
DAC19_G4
J11-20
Un-buffered DAC output voltage
DAC6_G3
J11-22
Un-buffered DAC output voltage
DAC4_G3
J11-24
Un-buffered DAC output voltage
DAC3_G3
J11-26
Un-buffered DAC output voltage
DAC14_G4
J11-28
Un-buffered DAC output voltage
DAC17_G4
J11-30
Un-buffered DAC output voltage
DAC15_G4
J11-32
Un-buffered DAC output voltage
DAC18_G4
J11-34
Un-buffered DAC output voltage
DAC16_G4
J11-36
Un-buffered DAC output voltage
DAC8_G3
J11-38
Un-buffered DAC output voltage
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Table 6. DAC60096EVM DAC Signal Connections (continued)
12
Name
Connector
Description
DAC10_G3
J11-40
Un-buffered DAC output voltage
DAC7_G3
J11-42
Un-buffered DAC output voltage
DAC9_G3
J11-44
Un-buffered DAC output voltage
DAC11_G3
J11-46
Un-buffered DAC output voltage
DAC12_G3
J11-48
Un-buffered DAC output voltage
DAC13_G3
J11-50
Un-buffered DAC output voltage
DAC3_G5
J12-1
Un-buffered DAC output voltage
DAC4_G5
J12-3
Un-buffered DAC output voltage
DAC5_G5
J12-5
Un-buffered DAC output voltage
DAC6_G5
J12-7
Un-buffered DAC output voltage
DAC7_G5
J12-9
Un-buffered DAC output voltage
DAC8_G5
J12-11
Un-buffered DAC output voltage
DAC1_G7
J12-13
Un-buffered DAC output voltage
DAC21_G6
J12-15
Un-buffered DAC output voltage
DAC22_G6
J12-17
Un-buffered DAC output voltage
DAC9_G5
J12-19
Un-buffered DAC output voltage
DAC20_G6
J12-21
Un-buffered DAC output voltage
DAC24_G6
J12-23
Un-buffered DAC output voltage
DAC23_G6
J12-25
Un-buffered DAC output voltage
DAC13_G5
J12-27
Un-buffered DAC output voltage
DAC10_G5
J12-29
Un-buffered DAC output voltage
DAC12_G5
J12-31
Un-buffered DAC output voltage
DAC19_G6
J12-33
Un-buffered DAC output voltage
DAC11_G5
J12-35
Un-buffered DAC output voltage
DAC18_G6
J12-37
Un-buffered DAC output voltage
DAC17_G6
J12-39
Un-buffered DAC output voltage
DAC5_G7
J12-41
Un-buffered DAC output voltage
DAC7_G7
J12-43
Un-buffered DAC output voltage
DAC16_G6
J12-45
Un-buffered DAC output voltage
DAC15_G6
J12-47
Un-buffered DAC output voltage
DAC14_G6
J12-49
Un-buffered DAC output voltage
DAC14_G2
J13-2
Un-buffered DAC output voltage
DAC15_G2
J13-4
Un-buffered DAC output voltage
DAC21_G2
J13-6
Un-buffered DAC output voltage
DAC20_G2
J13-8
Un-buffered DAC output voltage
DAC16_G2
J13-10
Un-buffered DAC output voltage
DAC17_G2
J13-12
Un-buffered DAC output voltage
DAC22_G2
J13-14
Un-buffered DAC output voltage
DAC10_G1
J13-16
Un-buffered DAC output voltage
DAC7_G1
J13-18
Un-buffered DAC output voltage
DAC11_G1
J13-20
Un-buffered DAC output voltage
DAC8_G1
J13-22
Un-buffered DAC output voltage
DAC12_G1
J13-24
Un-buffered DAC output voltage
DAC9_G1
J13-26
Un-buffered DAC output voltage
DAC13_G1
J13-28
Un-buffered DAC output voltage
DAC19_G2
J13-30
Un-buffered DAC output voltage
DAC18_G2
J13-32
Un-buffered DAC output voltage
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Table 6. DAC60096EVM DAC Signal Connections (continued)
Name
Connector
Description
DAC3_G1
J13-34
Un-buffered DAC output voltage
DAC23_G2
J13-36
Un-buffered DAC output voltage
DAC6_G1
J13-38
Un-buffered DAC output voltage
DAC5_G1
J13-40
Un-buffered DAC output voltage
DAC1_G1
J13-42
Un-buffered DAC output voltage
DAC4_G1
J13-44
Un-buffered DAC output voltage
DAC2_G1
J13-46
Un-buffered DAC output voltage
DAC13_G7
J14-1
Un-buffered DAC output voltage
DAC12_G7
J14-3
Un-buffered DAC output voltage
DAC4_G7
J14-5
Un-buffered DAC output voltage
DAC6_G7
J14-7
Un-buffered DAC output voltage
DAC11_G7
J14-9
Un-buffered DAC output voltage
DAC9_G7
J14-11
Un-buffered DAC output voltage
DAC3_G7
J14-13
Un-buffered DAC output voltage
DAC10_G7
J14-15
Un-buffered DAC output voltage
DAC8_G7
J14-17
Un-buffered DAC output voltage
DAC16_G8
J14-19
Un-buffered DAC output voltage
DAC17_G8
J14-21
Un-buffered DAC output voltage
DAC15_G8
J14-23
Un-buffered DAC output voltage
DAC18_G8
J14-25
Un-buffered DAC output voltage
DAC14_G8
J14-27
Un-buffered DAC output voltage
DAC21_G8
J14-29
Un-buffered DAC output voltage
DAC19_G8
J14-31
Un-buffered DAC output voltage
DAC24_G8
J14-33
Un-buffered DAC output voltage
DAC25_G8
J14-35
Un-buffered DAC output voltage
DAC20_G8
J14-37
Un-buffered DAC output voltage
DAC22_G8
J14-39
Un-buffered DAC output voltage
DAC2_G7
J14-41
Un-buffered DAC output voltage
DAC23_G8
J14-43
Un-buffered DAC output voltage
DAC26_G8
J14-45
Un-buffered DAC output voltage
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4.5
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SPI Communication Signals and Digital Inputs
The SPI signals are located on the J6 header and are described in Table 7, along with the digital input
signals of the DAC60096 device.
Table 7. SPI Signal Definition
4.6
Name
Connector
Description
SCLK
J2-5
Serial interface clock
SDI
J2-3
Serial interface data input
SDO
J2-7
Serial interface data output
/CS
J2-8
Active low serial data enable
/CLEAR
J2-6
Asynchronous clear input
/RESET
J2-10
Reset input, active low
STATS
J2-9
DAC output status indicator
/LDAC
J2-4
Synchronous DAC load control input
External Trigger
The DAC60096 device also incorporates a trigger input signal. This signal enables all DAC outputs to
toggle between the two DAC data registers associated with each DAC. This functionality enables the
device to operate as a square-wave generator. The DAC registers are prepared for square-wave operation
on a TRIGG rising edge and the outputs are toggled on each following TRIGG falling edge.
Table 8. External Trigger
14
Name
Connector
Description
Trigger
J10
Synchronous DAC load control input
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5
DAC60096EVM Software Overview
This section discusses how to use the DAC60096EVM software.
5.1
Starting the DAC60096EVM Software
Once the hardware connections are established and jumper settings configured, launch the software
located in the Texas Instruments folder of the Start → All Programs menu, and select the DAC60096 EVM
icon (see Figure 9).
Figure 9. DAC60096EVM GUI Location
If the SDM-USB-DIG is properly connected to the DAC60096EVM, the GUI should automatically power
the SDM-USB-DIG and display HARDWARE CONNECTED on the lower left of the GUI, as seen in
Figure 10.
Figure 10. DAC60096EVM GUI – Power On
If the SDM-USB-DIG has a faulty connection, or is not connected at all, the GUI will launch in DEMO
mode. If this text appears while the SDM-USB-DIG device is connected, then unplug the SDM-USB-DIG
and close the GUI. Reconnect the SDM-USB-DIG, and ensure that the connectors are correctly aligned.
After this, verify the USB extender cable is properly connected to both the SDM-USB-DIG and PC, and relaunch the GUI. This issue can also occur if the CDC driver is installed incorrectly, and so the
DAC60096EVM software may need to be reinstalled.
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5.2
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DAC60096EVM Software Features
The following subsections describe the functionality of each page of the DAC60096EVM GUI.
5.2.1
DAC60096EVM Low Level Configuration Page
The DAC60096EVM features a Register Map page that allows access to low-level communication by
directly writing to and reading from the DAC60096’s registers. Selecting a register on the Register Map list
presents a description of the values in that register, and also displays information such as the register’s
address, default value, size, and current value. The register values can be modified by either writing
directly to the value column or selecting the bit individually. This is shown in Figure 11.
Figure 11. Low Level Configuration Page
The values of the register map can also be saved by pressing the Save Configuration button under the
File menu option. Additionally, the configuration files can be accessed through the Load Configuration
button.
Other options selectable by the user are the Update Mode, Write Selected (red box), Read Selected
(orange box), Write Modified (gray box), and Read All (yellow box) buttons. All buttons are displayed in
Figure 12.
Figure 12. Low Level Configuration Page Available Options
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If Update Mode is selected to “Immediate”, all changes to register values update immediately, while
“Deferred” allows the user to modify the value of a register without taking effect until the Write Selected, or
Write Modified button is pressed.
The Read Selected button allows individual register reads, while the Read All button reads the status of all
registers located in the register map.
5.2.2
DAC60096EVM High Level Configuration Page
The High Level Configuration page provides an interface to observe and control the different data
registers, modes, and configurations available for the DAC60096 device. Figure 13 displays this page.
Figure 13. High Level Configuration Page
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To write to a DAC channel of the device, the GUI is designed with 4 interactive inputs that are highlighted
in Figure 14. The first four buttons, displayed within the red box, can be pressed to select any of the 4
quadrants of the DAC60096 device. Once the quadrant is chosen, the appropriate DAC channel is input in
the DAC Pointer field, which is displayed in the gray box. The orange box displays the digital code inputs,
Buffer A and Buffer B. Once an acceptable 12-bit code is written into the fields, the GUI updates the
internal Buffer Registers and also provides a numeric display of the code represented as a voltage.
Pressing the LDAC button issues a LDAC trigger at /CS rising edge, which enables the data to latch to the
DAC Active Registers and output the programmed voltage.
Figure 14. DAC Channel Write Order of Operation
An option to update all DAC Registers is provided with the “Write All DACs with Buff A/B” button. As the
name suggests, this will write to all the DAC registers of the DAC60096 device, and issue the LDAC
triggers for all quadrants. The Status LED keeps track of the status, once the GUI starts writing to the
channels the LED turns ON and remains ON until all channels are updated.
Figure 15. Write All DACs Button
The remaining controls allow the user to adjust the register values for DAC60096 device settings. These
controls are shown in Figure 16, and explained in Table 9.
Figure 16. Register Control Buttons
18
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Table 9. Register Controls
Name
Register, Bit
Description
SDO 1x/2x
0x4, 11:10
‘01’: 1X (default)
‘10’: 2X
STATS terminal
0x4, 9:8
‘01’: Hi-Z. STATS terminal is disabled
‘10’: CMOS Push-pull output. Should only be enabled for subsystem 1.
PHAINV
0x4, 7:6
‘01’: SCLK NegEdge
‘10’: SCLK PosEdge
CLRDAC
0x4, 5:4
‘01’: Normal operating state
‘10’: Clear DAC state
APB
0x4, 1:0
’01’: auto-populates BUFB with the negative value of BUFA after
each BUFA register write. Writing to BUFB has no auto-populate
effect.
‘10’: disable auto populate B feature.
SDIV
0x9, 2:0
STATS terminal toggling rate is controlled by SDIV register. SDIV is
valid between 0 and 6. STATS terminal toggles on every 2SDIV
trigger pulse. The SDIV setting should only be updated after a
device reset and before configuring the DAC outputs.
The High Level Configuration Page also provides a button interface to control different digital inputs, as
shown in Figure 17. The digital inputs include the /RESET, /LDAC, and /CLEAR signals. Pressing any of
the buttons creates an active low signal that asserts the functionality tied to the signal. The input signal
remains low until the button is pressed a second time, bringing it to a high state.
Figure 17. Digital Input Buttons
A brief description of the digital inputs tied to the button interface is provided in Table 10.
Table 10. Digital Inputs
Digital Input
Description
/RESET
Reset input. Logic low on this terminal causes the device to perform a hardware reset.
/LDAC
Synchronous DAC load control input. When /LDAC is low, the DAC outputs are updated
immediately after a register write. If left high during DAC register updates, a falling edge on
/LDAC causes all DAC outputs to update simultaneously.
/CLEAR
Asynchronous clear input. When /CLR is activated, all DACs are loaded with code 000h. When
/CLR is cleared, all DACs return to normal operation.
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DAC60096EVM Documentation
6
www.ti.com
DAC60096EVM Documentation
This section contains the complete bill of materials and schematic diagram for the DAC60096EVM. Documentation information for the SDM-USBDIG Platform can be found in the SDM-USB-DIG Platform User’s Guide, SBOU136, available at the TI web site at www.ti.com.
6.1
DAC60096EVM Board Schematic
Figure 18 and Figure 19 illustrate the DAC60096EVM board schematics.
TP1
AVCC
J1
C2
1µF
C1
10µF
575-4
C3
0.1µF
VDUT
J2
PWR_GND
TP2
AVSS
J3
DGND
C6
0.1µF
C11
0.1µF
C13
C15
0.1µF
0.1µF
0.1µF
DVDD
C16
0.22µF
C18
0.22µF
C22
2
C17
DGND
C21
0.1µF
0.22µF
0.22µF
B1
B6
B7
B8
B9
B14
N14
N8
N9
N6
N7
N1
F6
F9
J9
J6
AVSS_G1
AVSS_G2
AVSS_G2
AVSS_G3
AVSS_G3
AVSS_G4
AVSS_G5
AVSS_G6
AVSS_G6
AVSS_G7
AVSS_G7
AVSS_G8
AVSS_S1
AVSS_S2
AVSS_S3
AVSS_S4
VDUT
G1
REF1
AGND
0.15µF
C46
D10
E10
F1
F2
F5
F10
G2
G5
G10
H2
H10
J1
J2
J5
J10
K10
L10
DGND
DGND
DGND
DGND
DGND
PWR_GND
G12
G13
F12
E12
D11
C11
C10
B11
B10
A11
A10
A9
A8
A14
A13
A12
B13
B12
C12
C13
D13
E13
D12
F13
F14
CS
SCLK
SDI
SDO
REFGND2
RESET
REF2
H14
G6
G9
H6
H9
REF_GND
REFGND1
G14
F4
C45
0.1µF
G4
H4
H3
G3
H1
REF_GND
DAC1_G7
DAC2_G7
DAC3_G7
DAC4_G7
DAC5_G7
DAC6_G7
DAC7_G7
DAC8_G7
DAC9_G7
DAC10_G7
DAC11_G7
DAC12_G7
DAC13_G7
DAC14_G8
DAC15_G8
DAC16_G8
DAC17_G8
DAC18_G8
DAC20_G8
DAC19_G8
DAC21_G8
DAC22_G8
DAC23_G8
DAC24_G8
DAC25_G8
DAC26_G8
K11
K4
K5
L5
M10
M5
N10
N4
N5
P4
P5
P6
P7
P1
P2
P3
N3
N2
M2
M3
M4
L2
K2
L3
L4
K3
STATS
/CLEAR
/LDAC
/RESET
J12-1
J12-2
J12-5
J12-6
J12-8
J12-9
J12-13
J12-18
J12-21
J12-19
J12-17
J12-28
J12-27
J12-26
J12-23
J12-22
J12-20
J12-14
J12-11
J12-12
J12-16
J12-15
C7
1µF
SCLK
/CS
SDO
DGND
SDM Dig
AVCC
U2
2
C24
10µF
C26
0.1µF
7
8
1
PWR_GND
VIN
VOUT
TRIM/NR
NC
TEMP
DNC
DNC
GND
6
REFOUT
5
3
C28
1µF
C27
10µF
4
REF5025IDGK
REF_GND
J12-10
J14-21
J14-7
J14-3
J12-24
J14-4
J12-25
J14-9
J14-6
J14-8
J14-5
J14-2
J14-1
J14-14
J14-12
J14-10
J14-11
J14-13
J14-19
J14-16
J14-15
J14-20
J14-22
J14-17
J14-18
J14-23
TP8
J10 142-0701-201
1
R1
R2
R3
R4
R5
10.0k
10.0k
10.0k
10.0k
100k
DVDD
DGND
/CS
SCLK
SDI
SDO
C44
0.1µF
DVDD
DVDD
DVDD
DVDD
/RESET
2
G7
G8
H7
H8
0.15µF
0.22µF
C52
REFOUT
DVDD
0.22µF
J14
H13
H12
J13
K13
L13
M13
M12
N13
P12
P13
P14
P8
P9
P10
P11
N11
N12
M11
L12
L11
K12
J12
J11
H11
C53
C43
10µF
1
3
C42
0.15µF
C61
JP2
0.22µF
C51
DGND
J9
575-4
C39
0.22µF
C41
0.22µF
0.15µF
C60
PWR_GND
C40
0.15µF
C59
REF_GND AGND
0.15µF
PWR_GND
C58
DGND
TP7
0.22µF
0.15µF
C37
0.1µF
0.15µF
C35
NT2
0.1µF
VREFL_G1
VREFL_G2
VREFL_G2
VREFL_G3
VREFL_G3
VREFL_G4
VREFL_G5
VREFL_G6
VREFL_G6
VREFL_G7
VREFL_G7
VREFL_G8
NT1
C34
0.22µF
C36
0.22µF
C38
C1
C6
C7
C8
C9
C14
M14
M8
M9
M6
M7
M1
0.1µF
TP6
C50
C33
575-4
0.1µF
0.15µF
C30
0.1µF
C32
C49
TP5
0.1µF
C31
0.15µF
575-4
C29
C48
575-4
TP4
J8
0.15µF
C57
J7
0.1µF
C56
J6
0.1µF
C25
0.15µF
600 ohm
AVSS
0.15µF
PWR_GND
C23
VREFH_G1
VREFH_G2
VREFH_G2
VREFH_G3
VREFH_G3
VREFH_G4
VREFH_G5
VREFH_G6
VREFH_G6
VREFH_G7
VREFH_G7
VREFH_G8
DGND
D1
D6
D7
D8
D9
D14
L14
L8
L9
L6
L7
L1
L1
C47
C20
0.1µF
0.15µF
C55
0.15µF
C19
1µF
C54
1
3
NC
DAC3_G5
DAC4_G5
DAC5_G5
DAC6_G5
DAC7_G5
DAC8_G5
DAC9_G5
DAC10_G5
DAC11_G5
DAC12_G5
DAC13_G5
DAC14_G6
DAC15_G6
DAC16_G6
DAC17_G6
DAC18_G6
DAC19_G6
DAC20_G6
DAC21_G6
DAC22_G6
DAC23_G6
DAC24_G6
NC
NC
VDUT
5
4
3
2
0.1µF
C12
0.15µF
JP1
C10
AVCC_G1
AVCC_G2
AVCC_G2
AVCC_G3
AVCC_G3
AVCC_G4
AVCC_G5
AVCC_G6
AVCC_G6
AVCC_G7
AVCC_G7
AVCC_G8
AVCC_S1
AVCC_S2
AVCC_S3
AVCC_S4
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VDUT_EXT
E1
E6
E7
E8
E9
E14
K14
K8
K9
K6
K7
K1
F7
F8
J8
J7
SCL
GPIO0
SDA
GPIO1
SDI
LDAC
CLEAR
STATS
TRIGG
0.1µF
1
3
5
7
9
11
13
15
17
19
/LDAC
/CLEAR
STATS
0.1µF
C9
U1A
DAC60096NZHR
J4
H5
F3
J3
AVCC
C8
575-4
DAC1_G3
DAC2_G3
DAC3_G3
DAC4_G3
DAC5_G3
DAC6_G3
DAC7_G3
DAC8_G3
DAC9_G3
DAC10_G3
DAC11_G3
DAC12_G3
DAC13_G3
DAC14_G4
DAC15_G4
DAC16_G4
DAC17_G4
DAC18_G4
DAC19_G4
DAC20_G4
DAC21_G4
DAC22_G4
DAC23_G4
DAC24_G4
NC
E4
E3
D3
E2
D2
C2
B4
B3
B2
A4
A3
A2
A1
A7
A6
A5
B5
C3
C4
C5
D5
E5
D4
E11
G11
F11
VDUT_EXT
DAC1_G1
DAC2_G1
DAC3_G1
DAC4_G1
DAC5_G1
DAC6_G1
DAC7_G1
DAC8_G1
DAC9_G1
DAC10_G1
DAC11_G1
DAC12_G1
DAC13_G1
DAC14_G2
DAC15_G2
DAC16_G2
DAC17_G2
DAC18_G2
DAC19_G2
DAC20_G2
DAC21_G2
DAC22_G2
DAC23_G2
DAC24_G2
NC
NC
TP3
C14
10µF
/LDAC
/CLEAR
/CS
/RESET
J4
2
4
6
8
10
12
14
16
18
20
PWR_GND
J5
2
4
6
8
10
TSW-105-07-G-D
J11-2
J11-1
J11-16
J11-15
J11-12
J11-14
J11-24
J11-22
J11-25
J11-23
J11-26
J11-27
J11-28
J11-17
J11-19
J11-21
J11-18
J11-20
J11-13
J11-9
J11-8
J11-6
J11-11
J11-5
C5
1µF
J13-21
J13-23
J13-17
J13-22
J13-20
J13-19
J13-9
J13-11
J13-13
J13-8
J13-10
J13-12
J13-14
J13-1
J13-2
J13-5
J13-6
J13-16
J13-15
J13-4
J13-3
J13-7
J13-18
J11-10
C4
10µF
575-4
1
3
5
7
9
SDI
SCLK
SDO
STATS
PWR_GND
Figure 18. DAC60096EVM Board Schematic
20
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J11
J11-1
J11-2
J11-5
J11-6
J11-8
J11-9
J11-10
J11-11
J11-12
J11-13
J11-14
J11-15
J11-16
J11-17
J11-18
J11-19
J11-20
J11-21
J11-22
J11-23
J11-24
J11-25
J11-26
J11-27
J11-28
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
J12
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
J12-1
J12-2
J12-5
J12-6
J12-8
J12-9
J12-10
J12-11
J12-12
J12-13
J12-14
J12-15
J12-16
J12-17
J12-18
J12-19
J12-20
J12-21
J12-22
J12-23
J12-24
J12-25
J12-26
J12-27
J12-28
TSW-128-07-G-D
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
TSW-128-07-G-D
AGND
AGND
AGND
AGND
J13
J13-1
J13-2
J13-3
J13-4
J13-5
J13-6
J13-7
J13-8
J13-9
J13-10
J13-11
J13-12
J13-13
J13-14
J13-15
J13-16
J13-17
J13-18
J13-19
J13-20
J13-21
J13-22
J13-23
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
J14
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
J14-1
J14-2
J14-3
J14-4
J14-5
J14-6
J14-7
J14-8
J14-9
J14-10
J14-11
J14-12
J14-13
J14-14
J14-15
J14-16
J14-17
J14-18
J14-19
J14-20
J14-21
J14-22
J14-23
TSW-123-07-G-D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
TSW-123-07-G-D
AGND
AGND
Figure 19. DAC60096EVM Board Schematic
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DAC60096EVM Documentation
6.2
www.ti.com
DAC60096EVM PCB Components Layout
Figure 20 shows the layout of the components for the DAC60096EVM board.
Figure 20. DAC60096EVM PCB Components Layout
22
DAC60096 Evaluation Module
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6.3
DAC60096 Test Board Bill of Materials
Table 11 lists the DAC60096 test board bill of materials.
Table 11. DAC60096 Test Board Bill of Materials
Qty
Designator
Description
Part Number
Manufacturer
1
!PCB1
Printed Circuit Board
PA002
Any
5
C1, C4, C14, C24, C43
CAP, CERM, 10 µF, 50 V, +/- 10%, X5R,
1206_190
GRM31CR61H106KA12L
Murata
5
C2, C5, C7, C19, C28
CAP, CERM, 1 µF, 50 V, +/- 10%, X7R, 0805
GRM21BR71H105KA12L
Murata
22
C3, C6, C8, C9, C10, C11,
C12, C13, C15, C16, C20,
C23, C25, C26, C29, C30,
C31, C32, C33, C34, C44,
C45
CAP, CERM, 0.1 µF, 50 V, +/- 10%, X7R,
0603
06035C104KAT2A
AVX
12
C17, C18, C21, C22, C35,
C36, C37, C38, C39, C40,
C41, C42
CAP, CERM, 0.22 µF, 16 V, +/- 10%, X7R,
0402
C1005X7R1C224K050BC
TDK
1
C27
CAP, TA, 10 µF, 16 V, +/- 10%, 0.5 ohm,
SMD
TPSB106K016R0500
AVX
16
C46, C47, C48, C49, C50,
C51, C52, C53, C54, C55,
C56, C57, C58, C59, C60,
C61
CAP, CERM, 0.15 µF, 25 V, +/- 10%, X7R,
0603
C1608X7R1E154K080AA
TDK
4
H1, H2, H3, H4
Machine Screw, Round, #4-40 x 1/4, Nylon,
Philips panhead
NY PMS 440 0025 PH
B&F Fastener Supply
4
H5, H6, H7, H8
Standoff, Hex, 0.5"L #4-40 Nylon
1902C
Keystone
7
J1, J3, J5, J6, J7, J8, J9
Standard Banana Jack, Uninsulated, 5.5mm
575-4
Keystone
1
J2
Header, 100mil, 5x2, Gold, TH
TSW-105-07-G-D
Samtec
1
J4
Receptacle, 50mil 10x2, R/A, TH
853-43-020-20-001000
Mill-Max
1
J10
Connector, TH, SMA
142-0701-201
Emerson Network Power
2
J11, J12
Header, 100mil, 28x2, Gold, TH
TSW-128-07-G-D
Samtec
2
J13, J14
Header, 2.54 mm, 23x2, Gold, TH
TSW-123-07-G-D
Samtec
2
JP1, JP2
Header, 100mil, 3x1, Gold, TH
TSW-103-07-G-S
Samtec
1
L1
Ferrite Bead, 600 ohm @ 100 MHz, 0.2 A,
0603
BLM18HG601SN1D
Murata
4
R1, R2, R3, R4
RES, 10.0 k, 1%, 0.1 W, 0603
RC0603FR-0710KL
Yageo America
1
R5
RES, 100 k, 1%, 0.1 W, 0603
RC0603FR-07100KL
Yageo America
2
SH-JP1, SH-JP2
Shunt, 100mil, Gold plated, Black
969102-0000-DA
3M
1
TP1
Test Point, Miniature, White, TH
5002
Keystone
1
TP2
Test Point, Miniature, Orange, TH
5003
Keystone
1
TP3
Test Point, Miniature, Yellow, TH
5004
Keystone
3
TP4, TP5, TP6
Test Point, Miniature, Black, TH
5001
Keystone
2
TP7, TP8
Test Point, Miniature, Red, TH
5000
Keystone
1
U1
96-Channel, 12-Bit Low-Power, Serial Input,
Unbuffered, High-Voltage Output DAC with
External Conversion Trigger, NZH0196A
DAC60096NZHR
Texas Instruments
1
U2
Low-Noise, Very Low Drift, Precision
VOLTAGE REFERENCE, DGK0008A
REF5025IDGK
Texas Instruments
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STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or
documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.
Acceptance of the EVM is expressly subject to the following terms and conditions.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software
License Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment
by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any
way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or
instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as
mandated by government requirements. TI does not test all parameters of each EVM.
2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,
or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the
warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to
repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall
be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit
to determine whether to incorporate such items in a finished product and software developers to write software applications for
use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless
all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause
harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is
designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of
an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
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FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law of
Japan to follow the instructions below with respect to EVMs:
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ
い。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
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4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
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6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE
DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY
THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND
CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY
OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD
PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY
INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF
THE EVM.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION
SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY
OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS,
LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL
BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION
ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM
PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER
THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE
OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND
CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
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IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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Copyright © 2015, Texas Instruments Incorporated
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