Texas Instruments | 12-bit ADC128S102CVAL Low Power, Eight-Channel CMOS ADC | User Guides | Texas Instruments 12-bit ADC128S102CVAL Low Power, Eight-Channel CMOS ADC User guides

Texas Instruments 12-bit ADC128S102CVAL Low Power, Eight-Channel CMOS ADC User guides
November 1, 2010
Rev -2.0
Evaluation Board User's Guide
12-bit ADC128S102CVAL
50KSPS 1MSPS
Low Power, Eight-Channel CMOS Analog-to-Digital
Converter
© 2009 National Semiconductor Corporation.
1
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Table of Contents
1.0 Introduction ................................................................................................4
2.0
Board Assembly ........................................................................................5
3.0
Quick Start ................................................................................................5
4.0
3.1
Stand Alone Mode ............................................................................5
3.2
Computer Mode ................................................................................5
Functional Description .................................................................................6
4.1 The Signal Input .............................................................................6
4.2
ADC Reference Circuitry ................................................................6
4.3
ADC Clock Circuit .............................................................................6
4.4
Digital Data Output .........................................................................6
4.5 Power Supply Connections
............................................................6
5.0
Software Operation and Settings ..............................................................7
6.0
Evaluation Board Specifications ..................................................................7
7.0
Hardware Schematic ...................................................................................8
8.0
Evaluation Board Bill of Materials ................................................................9
A1.0 Summary Tables of Test Points, Jumpers, and Connectors ...................11
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1.0 Introduction
through a USB port. The WaveVision4
software
™
runs on Microsoft Windows and the latest
version can be downloaded from the web at
http://www.national.com/adc.
The ADC128S102CVAL Design Kit (consisting of
the ADC128S102WG Evaluation Board and this
User's Guide) is designed to ease evaluation and
design-in
of
National
Semiconductor‘s
eight-channel,
low-power
CMOS
Analog-to-Digital Converter ADC128S102WGWG.
This Hi-Rel ADC will be referenced throughout
this document as the ADC128S102WG.
Note: WaveVision Software version 4.2 or later is
required to evaluate this part with the WV4
Evaluation System.
The
Analog
input
signal
enters
the
Analog-to-Digital Converter through one of its
eight selectable input channels and is converted
into a digital stream of bits by U1, the
ADC128S102WG. The WV4 system captures
and displays the digitized signal on a PC monitor
in the time and frequency domains.
The evaluation board can be used in one of two
modes; Stand-alone or Computer mode.
In Stand-alone mode, suitable test equipment,
such as a function generator and logic analyzer,
can be used with the board to evaluate the
ADC128S102WG.
The software will perform an FFT on the captured
data upon command. This FFT plot shows
dynamic performance in the form of SNR, SINAD,
THD, SFDR and ENOB. A histogram of the
captured data is also available.
In the Computer mode, data capture and
evaluation is simplified by connecting this board
to National Semiconductor's Data Capture Board
(order number WAVEVSN BRD 4.0) with a 14-pin
ribbon cable (order number WV4ADCIFCABLE).
The Data Capture (WV4) Board is connected to a
personal computer running WaveVision software
J2
IN A
JP2
JP1
U1
ADC128S102WG
J1
Serial Interface
WV4 Connector
JP3
J4
IN B
D3
JP7
Clk Selection
JP8
J5
+5V In
D1
JP6
JP9
J8
External Clock
Figure 1: Component and Test Point Locations
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2.0 Board Assembly
The ADC128S102WG evaluation board comes fully
assembled and ready for use. Refer to the Bill of
Materials for a description of components, to Figure 1
for major component placement, and to Figure 3 for the
Evaluation Board schematic.
3.0 Quick Start
The ADC128S102WG evaluation board may be used in
the Stand-Alone mode to capture data with a logic
analyzer or other third-party equipment. It may also be
used in the Computer Mode with a WV4 Board. In
both cases, the captured data can be analyzed with
National Semiconductor‘s WaveVision4 software.
5.
3.1 Stand Alone Mode
3.2 Computer Mode
Refer to Figure 1 for locations of test points and major
components.
Refer to Figure 1 for locations of test points and major
components.
1. Run the WaveVision4 program. While the program
is loading, continue below.
2. Install the appropriate crystal oscillator into socket
Y2 and short pins 1 & 2 of JP7 (See Table 1).
Alternatively, connect a low-jitter square wave
generator with an amplitude between 2.5 VP-P and
5 VP-P to BNC connector J6 and short pins 2 & 3 of
JP7.
If using an external source, remove the oscillator
from Y2. If using an oscillator at Y2, remove the
signal source from J6. The presence of a second
oscillator source could add noise to the conversion
process.
3. Perform steps 1 and 2 of section 3.1.
4. Connect the 14-pin ribbon cable between J3 of the
ADC128S102WG evaluation board and J3 of the
WV4 board.
5. Connect a clean analog (not switching) +5V power
source to Power Connector J1 on the WV4 board.
6. Connect a USB cable between the WaveVision4
Data Capture Board and the PC running the
WaveVision4 program. See Section 4.5 for
detailed Power Supply Information.
7. Refer to section 5.0 on Software Operation and
Settings.
1.
Figure 2: J3 WaveVision4 Serial Interface Header
Open all the DIP switches at DIP1 and
configure the board‘s jumpers according to
Table 1 below.
Pin1
Pin2
Pin3
Pin4
JP1 (INA Coupling)
o
o
o
o
JP2 (INB Select)
o
o
o
o
JP3 (INB Coupling)
o
o
o
JP6 (5P5V Select)
o
o
o
JP8 (3P3V Select)
o
o
o
JP9 (VD Select)
o
o
o
JP7 (SCLK Select)
Table 1: Quick Start Jumper Configuration
2.
3.
4.
Connect a clean analog (not switching) +5V
power source to Power Connector J5.
Connect a single-ended source of 4.8 VP-P
amplitude from a suitable 50-Ohm source to
INB (BNC J4). This signal should be applied
through a bandpass filter to eliminate the
noise and harmonics commonly associated
with signal sources. To accurately evaluate
the performance of the ADC128S102WG, the
source must be better than 90dB THD.
Note: For a time-varying DC input signal, DC
couple the input by placing the jumper at JP3
across pins 1 & 2 instead of pins 2 & 3.
The digital inputs and outputs are available at
header J3. Refer to Figure 2 for connection
details. The source used to create signals
SCLK, CSB, and DIN must meet the digital
input characteristics in the ADC128S102QML
datasheet.
5
Finally, import the Data taken with a Logic
Analyzer or other third-party equipment into the
WaveVision4 Software. Refer to WaveVision4
Manual for data analysis techniques.
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Analog-to-Digital converter‘s eight channels. For INA,
simply close the DIP switches corresponding to the
desired ADC128S102WG input channels.
For
example, to route INA to input channels 0 and 5, close
dip switches 1 and 6. For INB, simply place jumpers
across JP2 to select input channels. For example, to
route INB to input channels 0 and 3, short pins 1 and 2
as well as pins 7 and 8 of JP2.
4.0 Functional Description
Table 2 describes the function of the various jumpers
on the ADC128S102WG evaluation board. The
Evaluation Board schematic is shown in Figure 3.
Jumper
Function
DIP1
Routes INA to each of the eight ADC
channels. E.g. Switch 1 routes INA to
channel 0 while switch 4 routes INA to
channel 3.
Pins 1 & 2
JP1
JP2
JP3
DC couple
INA
JP7
JP8
JP9
Pins 5 & 6
AC couple
INA
Ground
INA
The ADC128S102WG gets its reference voltage from
the analog supply (VA). Hence, a clean analog supply
must be used to guarantee the performance of the
ADC128S102WG.
4.3 ADC Clock Circuit
Routes INB to each of the eight ADC
channels. E.g. Pins 1 & 2 route INB to
channel 0 while pins 15 and 16 route INB
to channel 7.
Pins 1& 2
Pins 2 & 3
DC couple INB
AC couple INB
JP5
JP6
Pins 3 & 4
4.2 ADC Reference Circuitry
In Computer mode, the ADC128S102WG Evaluation
board sends a clock signal to the WV4 Data capture
board. This clock signal is used to derive the digital
signals that drive the ADC128S102WG.
The crystal-based oscillator provided on the evaluation
board is selected by shorting pins 1 & 2 of JP7. It is
best to remove any external signal generator when
using this oscillator to reduce any unnecessary noise.
Not Used
Pins 1& 2
Pins 2 & 3
5P5V_REMOTE
5P5V_LOCAL
Pins 1& 2
Pins 2 & 3
Select clock
oscillator at BNC
J6
Select on-board
clock oscillator Y2
Pins 1& 2
Pins 2 & 3
Select on-board
+3.3V
Select +3.3V from
WV4S board
Pins 1& 2
Pins 2 & 3
Not Used
Set VD=VA
This board will also accept a clock signal from an
external source by connecting that source to BNC J8
and shorting pins 2 & 3 of JP7. An ac-coupling circuit
together with a DC-biased resistive divider is provided
so the board can accept a 50 Ohm signal source in the
range of 2.5 to 5.0VP-P to drive this input. It is best to
remove the oscillator at Y2 when using an external
clock source to reduce any unnecessary noise.
If the Evaluation board is used in Stand-alone mode,
the onboard oscillator and signal applied to J6 do not
drive the SCLK pin. Rather, an external source such
as a pattern generator must supply the digital signals
(CSB, SCLK, DIN) to drive the ADC128S102WG.
These signals must be applied at J3, the Serial
Interface Header (See Figure 2).
Note: SCLK, CSB, & DIN must be driven between 0
and VA to prevent damage to the ADC.
Table 2: Jumper Functions
4.1 The Signal Input
4.4 Digital Data Output
The input signal to be digitized can be applied through
the BNC connector at J2 (INA) or J4 (INB). Two inputs
allow the user to utilize multiple channels of the
eight-channel ADC128S102WG at the same time.
The serial data output from this board may be
monitored at TP15 or J3. Note: The TP15 test points
are current limited by 1k? resistors which will cause
some slewing of the digital waveforms. For data
capture with the WaveVision4 Software, refer to section
3.2. Detailed timing diagrams can be found in the
datasheet.
Both INA and INB can be AC coupled or DC coupled.
To digitize a time-varying DC signal, place a jumper
across pins 1 and 2 of JP1 for INA, or place a jumper
across pins 1 and 2 of JP3 for INB. If the AC
component of an input signal is to be evaluated, place a
jumper across pins 3 and 4 of JP1 for INA, or place a
jumper across pins 2 and 3 of JP3 for INB. Additionally,
INA can be grounded by shorting pins 5 and 6 of JP1.
4.5 Power Supply Connections
The ADC128S102WG Evaluation Board has
three independent supplies; VA, VD, and 3P3V. VA
serves as the analog reference for the Analog to
Digital Converter and must be driven by a clean
source to maximize the performance of the
Both INA and INB of the ADC128S102WG Evaluation
board can be routed to any number of the
ADC128S102WG. The voltage applied to VA can be
6
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any value between 2.7V and 5.25V. VD sets the digital
output level of the device and can be any value
between 2.7V and the voltage applied to pin VA.
3P3V supplies power to the on-board EEPROM and is
automatically generated on the evaluation board when
pins 1 & 2 are shorted on JP8. This voltage is only
used by U2 when operating the evaluation board in
computer mode.
A plot of the selected number of samples will be
displayed. Make sure there is no clipping of data
samples. The Samples may be further analyzed by
clicking on the magnifying glass icon, then clicking and
dragging across a specific area of the plot for better
data inspection. See the WaveVision4 Board User's
Guide for details.
To view an FFT of the data captured, click on
the ”FFT‘ tab. This plot may also be zoomed in on. A
display of dynamic performance parameters in the form
of SINAD, SNR, THD, SFDR and ENOB will be
displayed at the top right hand corner of the FFT plot.
If desired, VD and VA can be tied together by placing a
jumper across pins 2 and 3 of JP9. Otherwise, VD can
be driven independently of VA by removing the jumper
at JP9 and driving pin 2 of JP9 directly. In either case,
the supply voltage for VA must be supplied to connector
J5, labeled 5P5V, or directly to TP10. A jumper must be
placed across pins 1 and 2 of JP6.
To view a Histogram of the data, click on the
—Software Histogram“ tab. This plot may be zoomed in
on like the data plot. If the input signal is clipping,
the ”zero‘ and ”full-scale‘ codes will be very abundant.
The number of missing codes will be displayed at the
top right hand corner of the plot.
5.0 Software Operation and Settings
The WaveVision4 software is included with the WV4
board and the latest version can be downloaded for free
from National's web site at http://www.national.com/adc.
WaveVision Software version 4.2 or later is required to
evaluate this part with the WV4 Evaluation System.
Acquired data may be saved to a file. Plots may also
be exported as graphics.
Please refer to the WaveVision4 Data Capture Board
User's Guide for further details.
To install this software, follow the procedure in the
WAVEVSN BRD 4 User's Guide. Once the software is
installed, set it up as follows:
1.
Follow the steps outlined in Section 3.2
—Computer Mode Quick Start“.
2.
From the WaveVision main menu, go to Settings,
then Board Settings and do the following:
3.
Select the following from the WaveVision4 main
menu:
4.
•
WaveVision 4.0 (USB)
•
# of Samples: 2K to 32K, as desired
6.0 Evaluation Board Specifications
Board Size:
Power
Requirements
Clock Frequency
Range:
Analog Input
Nominal
Voltage
Range:
Impedance:
Apply power as specified in Section 4.5, click on
the "Test" button and await the firmware to
download.
5.
Click on the "Accept" button.
6.
Click on ”Acquire‘ then ”Samples‘ from the Main
Menu (you can also press the F1 shortcut key). If
a dialog box opens, select ”Discard‘ or press the
Escape key to start collecting new updated
samples.
3.25" x 4.19" (8.25 cm x 10.65 cm)
Min: +2.7V,
Max: +5.25V,
100mA
100 mA
8MHz to
ADC128S102WG
16MHz
7
4.9VP-P
Low: +0.05V
High: (VA-0.05V)
50 Ohms
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J4
INB
1
1
R19
51
R8
51
VA
INB
C14
1uF
R13
4.99K
R9
4.75K
C8
1uF
R6
4.99K
TP6
Input_2
1
2
3
+
+
+
2
4
6
AC
DC
AGND
IN2_SEL
JP3
INPUT1
INPUT2
INB SELECT
AGND
INA SELECT
IN1_SEL
+
+
+
TP5
AGND
1
3
5
TP13
AGND
DC
AC
GND
TP11
AGND
AGND
10uF
C20
RED LED
D1
R23
510
5P5V
TP10
5P5V
JP2
IN2_CH_SEL
OPEN
DIP1
IN1_CH_SEL
CLOSED
1
2
5P5V_REMOTE
AGND
D5
3.3V Zener
J5
5P5V_REMOTE
D2
1N4001
R34
51
5P5V_REMOTE
2) Stuff a 2-pin male header in pins 2 and 3 of JP9. It w as originally designed to be a 3 pin jumper and now only requires 2 pins.
TP3
AGND
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
AGND
NS
VR2
3P3V_REMOTE
R26
-
3P3V_LOCAL
3P3V SELECTION
JP8
3P3V SELECTION
5P5V SELECTION
JP6
5P5V SELECTION
3P3V
6
5P5V_LOCAL
NS
C21
+
U3B
5
VA ADJUST
1
5P5V
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
1) Device U3 should not be stuffed. Instead, short pad 7 to pad 8 of the U3 footprint. This allow s 5P5V to be directly connected to VA.
Assembly Notes:
INB
INA
J2
INA
2
2
1
1
1
JP1
1
R4
4.75K
1
15
13
11
9
7
5
3
1
16
14
12
10
8
6
4
2
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
2
4
6
8
10
12
14
16
1
3
5
7
9
11
13
15
NS
NS
R24
C18
NS
C17
NS
IN6
CLK_IN
7
IN5
IN4
IN3
J6
CLK
0
R31
51
C28
0.1uF
VR1
NS
ADC128S102-TSSOP16
VA
NS
C19
C11
VD
R32
4.99K
R29
4.75K
2
3
NS
1
TP14
AGND
NS
NS
D4
R25
-
+
U3A
5P5V
1uF 0.1uF
C10
VD ADJUST
470pF
22
VA
C13
R14
470pF
22
TP8
VA
C12
R12
470pF
22
470pF
22
470pF
22
C1
R1
470pF
22
C2
R2
470pF
22
C3
R3
470pF
22
C4
R5
VA
1
IN7
C9
R10
C7
R7
IN2
IN1
7
INA
1
2
3
8
IN4
IN5
9
1
IN3
IN6
6
IN7
VA
1
3
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1
Figure 3: ADC128S102 Evaluation Board Schematic
1
2
3
8
4
8
4
11
DGND
12
VD
13
VA
1
10
IN2
5
IN1
4
IN0
3
AGND
VA
2
TP7
AGND
AGND
R33 0
2
1
NS
U1
VA
U4
NS
NS
4
C27
C26
OE
OE
SDA
SCLK
CSB
VA
VD = VA
3
1
8
OUT
CLK SELECT
2
JP7
CLK SELECT
0.1uF
OUT
R30 51
Y2
16MHz
1
3
NS
1
2
CLKSEND
Y1
NS
1
C25
10uF
C16
OSC ENABLE
3P3V VA
R27
0
0.1uF
R35
NS
JP5
OSC ENABLE
L1
100uH
3P3V
10uF
C15
14
13
11
9
12
7
5
3
1
8
SDA
SCL
WV4S
SCL
WV4
5P5V_LOCAL
CLKSEND 10
6
4
2
14
12
10
8
6
4
2
5P5V_LOCAL
J3
HEADER 7X2
3P3V_LOCAL
3P3V_LOCAL
DIN
C24
9
CLKSEND
DOUT
VD SELECTION
JP9
VD
7
11
DIN
13
5
DOUT
3
SCLK
J1
HEADER 7X2
1
CSB
R16 R15
1K 1K
DIN
CLKSEND
R18 R17
1K 1K
TP15
SPI TEST POINTS
DOUT
SCLK
CSB
AGND
VD SELECTION
AGND
R11 51
VD ADJUST
R20
C6
TP2
AGND
0.1uF 1uF
C5
VA
DOUT
1
DIN
14
1
CSB
SCLK
15
1
1
2
3
DIN
DOUT
SCLK
CSB
4
3
2
1
TP1
Input_1
2
14
VDD
GND
7
3P3V
8
16
5
3
4
VDD
GND
2
VA
7
3P3V
RED LED
D3
R28
200
3P3V
3P3V
3P3V
TP12
3P3V
R22
0
3P3V
R21
NS
AGND
U2
24C02
TP4
AGND
WP
1
VCC
2
A0
1
A1
6
SCL
5
SDA
A2
3
GND
4
8
1
IN0
7.0 Hardware Schematic
8.0 Evaluation Board Bill of Materials
Qty.
PCB Footprint
5
Reference
C1,C2,C3,C4,C7,
C9, C12, C13
C5,C11,C16,C26,
C28
Rating
Value
sm/c_0805
10V
470pF
sm/c_0805
10V
0.1uF
2
2
C10,C6
sm/c_1206
10V
1uF
C14,C8
sm/c_0805
10V
1uF
3
C15,C20,C25
sm/ct_3216_12
10V
10uF
1
sm/c_1206
10V
NS
5
C17
C18,C19,C21,
C24,C27
sm/c_0805
10V
NS
1
DIP1
dip.100/16/w.300/l.900
Digikey
CT2068-ND
IN1_CH_SEL
2
D3,D1
sm/led_21
Digikey
516-1440-1-ND
RED LED
1
D2
DAX2/DO41
Digikey
1N4001GICT-ND
1N4001
1
1
D4
D5
sm/sot23_123/nat
sm/SOT23
Digikey
Digikey
BAT54SLT1OSCT-ND
MMBZ5226BLT1OSCT-ND
NS
3.3V Zener
1
JP1
blkcon.100/vh/tm2oe/w.200/6
Digikey
A26529-40-ND
IN1_SEL
1
JP2
blkcon.100/vh/tm2oe/w.200/16
Digikey
A26529-40-ND
IN2_CH_SEL
1
JP3
blkcon.100/vh/tm1sq/w.100/3
Digikey
A26513-40-ND
IN2_SEL
1
JP5
blkcon.100/vh/tm1sq/w.100/2
Digikey
A26513-40-ND
OSC ENABLE
1
JP6
blkcon.100/vh/tm1sq/w.100/3
Digikey
A26513-40-ND
5P5V
SELECTION
1
JP7
blkcon.100/vh/tm1sq/w.100/3
Digikey
A26513-40-ND
CLK SELECT
A26513-40-ND
3P3V
SELECTION
8
1
JP8
Source
blkcon.100/vh/tm1sq/w.100/3
Digikey
Source Part #
1
JP9
blkcon.100/vh/tm1sq/w.100/3
Digikey
A26513-40-ND
VD
SELECTION
1
J1
blkcon/2mm/ra/tm2oe/w2mm/14
Digikey
S2200-07-ND
HEADER 7X2
1
J2
rf/bnc/r1.350_21
Digikey
ARF1177-ND
INA
1
J3
blkcon.100/vh/tm2oe/w.200/14
Digikey
A26529-40-ND
HEADER 7X2
1
J4
rf/bnc/r1.350_21
Digikey
ARF1177-ND
INB
1
J5
term_block/.200/2pos
Digikey
ED1609-ND
5P5V_REMOTE
1
J8
rf/bnc/r1.350_21
Digikey
ARF1177-ND
CLK
1
sm/l_1210
Digikey
445-1155-1-ND
100uH
8
L1
R1,R2,R3,R5,R7,
R10,R12, R14
sm/r_0805
22
3
R4,R9,R29
sm/r_0805
4.75K
3
R6,R13,R32
R8,R11,R19,R30,
R31,R34
sm/r_0805
4.99K
sm/r_0805
51
R15,R16,R17,R18
R20,R21,R25,
sm/r_0805
1K
6
4
9
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5
R26,R35
sm/r_0805
NS
4
R22,R24,R27,R33
sm/r_0805
0
1
R23
sm/r_0805
510
1
R28
sm/r_0805
200
1
blkcon.100/vh/tm1sq/w.100/1
Digikey
5011K-ND
Input_1
6
TP1
TP2,TP3,TP4,
TP5,TP7,TP11
blkcon.100/vh/tm1sq/w.100/1
Digikey
5011K-ND
AGND
2
TP13, TP14
blkcon.100/vh/tm1sq/w.100/1
Digikey
5011K-ND
1
TP6
blkcon.100/vh/tm1sq/w.100/1
Digikey
5011K-ND
Input_2
1
TP8
blkcon.100/vh/tm1sq/w.100/1
Digikey
5011K-ND
VA
1
TP10
blkcon.100/vh/tm1sq/w.100/1
Digikey
5011K-ND
5P5V
1
TP12
blkcon.100/vh/tm1sq/w.100/1
Digikey
5011K-ND
1
1
TP15
U1
blkcon.100/vh/tm1sq/w.100/4
sog.65m/16/wg6.40/l5.10
Digikey
A26513-40-ND
3P3V
SPI TEST
POINTS
ADC128S102WG
1
U2
sog.050/8/wg.244/l.200
1
U3
sog.050/8/wg.244/l.200
Digikey
LMC6492AEMX
NS
1
U4
sm/SOT23-5
Digikey
NC7SZ00M5CT-ND
NS
2
VR2,VR1
vres4
Digikey
3386F-103-ND
NS
1
Y1
SOJ.100/4/WG8.80MM/L.550
1
Y2
crystal_socket
Digikey
A400-ND
1
Y2
PCB J1
oscillator
ADC128S102WG evaluation
board
Digikey
CTX116-ND
socket
16.0MHz OSC
(thru-hole)
Digikey
S2200-07-ND
HEADER 7X2
1
AGND
24C02
NS
10
http://www.national.com
APPENDIX
A1.0 Summary Tables of Test Points, Jumpers, and Connectors Test Points on the
ADC128S102WG Evaluation Board
TP1: INA
INA test point. Located near the top left of the board.
TP2: AGND
Ground.
Located near the top left of the board.
TP3: AGND
Ground.
Located near the top of the board. Just above U1.
TP4: AGND
Ground.
Located at the right edge of the board.
TP5: AGND
Ground.
Located between the BNC connectors on the left side of the board.
TP6: INB
TP7: AGND
INB test point. Located near the middle of the board.
Ground.
TP8: VA
Located just above the oscillator socket.
VA supply test point. Located near the bottom edge of the board.
TP10: 5P5V
5P5V supply test point.
TP11: AGND
Ground.
Located near the bottom left of the board.
TP12: 3P3V
3.3V test point. Located at the right edge of the board.
TP13: AGND
Ground.
Located near the bottom edge of the board.
TP14: AGND
Ground.
Located near the center of the board.
TP15:
Warning: Do not attempt to drive the chip via these test points, they are isolated by 1k?
resistors and for probing only. Instead, use the header J3 as shown in Figure 2.
Pin 1: CSB
Chip Select test point.
Pin 2: SCLK
Serial Clock test point.
Pin 3: DOUT
Data Out test point.
Pin 4: DIN
Data In test point.
Located near the bottom left of the board.
Connectors on the ADC128S102WG Evaluation Board
J1: WV4S
WV4S 14-Pin Right-angle Header
J2: INA Input
BNC Connector
J3: WV4
WV4 14-Pin Header
J4: INB Input
BNC Connector
J5: VA_REMOTE
Two Position Power connector terminal block.
J8: External Clock
BNC Connector
Selection Jumpers on the ADC128S102WG Evaluation Board (Refer to Table 2, Section 4.0 for
configuration details)
DIP1: INA Channel Selection
Routes Input A to the ADC‘s eight input channels.
JP1: INA Coupling
Selects AC coupling, DC coupling, or simply grounds Input A
JP2: INB Channel Selection
Routes Input B to the ADC‘s eight input channels.
JP3: INB Coupling
Selects AC coupling, DC coupling, or simply grounds Input B
JP5: Oscillator Enable
Enables or disables the on-board oscillator.
JP6: 5P5V Select
Selects local or remote source of 5P5V supply.
JP6: Osc Enable
Not Used
JP7: Clock Select
Selects internal or external clock source.
JP8: 3P3V Select
Selects local or remote source of 3P3V supply.
JP9: VD Select
Sets the digital supply (VD) equal to the analog supply (VA).
11
http://www.national.com
BY USING THIS PRODUCT, YOU ARE AGREEING TO BE BOUND BY THE TERMS AND CONDITIONS OF
NATIONAL SEMICONDUCTOR'S END USER LICENSE AGREEMENT. DO NOT USE THIS PRODUCT UNTIL YOU
HAVE READ AND AGREED TO THE TERMS AND CONDITIONS OF THAT AGREEMENT. IF YOU DO NOT AGREE
WITH THEM, CONTACT THE VENDOR WITHIN TEN (10) DAYS OF RECEIPT FOR INSTRUCTIONS ON RETURN OF
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The ADC128S102WG Evaluation Board is intended for product evaluation purposes only and are not intended for resale
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National does not assume any responsibility for any circuitry described, no circuit patent licenses are implied and National reserves the
right at any time without notice to change said circuitry and specifications.
12
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