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Texas Instruments Single low power, ultra high speed CMOS A D Converter with data buffer User guides
Reference Board User’s Guide
ADC08(B)3000RB: 8-Bit, 3.0 GSPS, A/D Converter with
Xilinx Virtex 4 (XC4VLX15) FPGA
 Copyright 2007 National Semiconductor Corporation
ADC08(B)3000RB Reference Board User’s Guide
December 14, 2007
Revision 6.2
2
ADC08(B)3000RB REFERENCE BOARD USER’S GUIDE – TABLE OF CONTENTS
1.0 Introduction............................................................................................................................................................3
2.0 Board Assembly.....................................................................................................................................................3
3.0 Quick Start .............................................................................................................................................................3
4.0 Board Specifications ..............................................................................................................................................4
4.1 FPGA Specification............................................................................................................................. 4
4.2 Microcontroller .................................................................................................................................... 4
4.3 Memory Components.......................................................................................................................... 4
4.4 Power Supplies ................................................................................................................................... 5
4.5 Clocking .............................................................................................................................................. 5
4.6 Resets................................................................................................................................................. 5
4.7 Thermal Management......................................................................................................................... 5
4.8 ADC Analog Input ............................................................................................................................... 5
4.9 Status Indicators ................................................................................................................................. 5
4.10 Debug ............................................................................................................................................... 6
5.0 Functional Description...........................................................................................................................................6
5.1 Input circuitry....................................................................................................................................... 6
5.2 ADC reference .................................................................................................................................... 6
5.3 ADC clock ........................................................................................................................................... 6
5.4 Digital Data Output.............................................................................................................................. 6
5.5 Power Requirements .......................................................................................................................... 6
5.6 Power Supply Connections ................................................................................................................. 6
6.0 Obtaining Best Results...........................................................................................................................................7
6.1 Clock Jitter .......................................................................................................................................... 7
7.0 Using the WaveVision software with the ADC08(B)3000 ....................................................................................7
7.1 Getting Started.................................................................................................................................... 7
7.2 Control Panel ...................................................................................................................................... 8
7.3 Serial Control Mode ............................................................................................................................ 9
7.4 Manually downloading the FPGA firmware......................................................................................... 9
7.5 Capturing Waveforms....................................................................................................................... 10
Appendix A - Hardware Information .........................................................................................................................10
A.1 Xilinx Virtex 4 FPGA ......................................................................................................................... 10
A.2 LED functions ................................................................................................................................... 10
A.3 Expansion Header ............................................................................................................................ 11
A.4 System Block Diagram ..................................................................................................................... 12
Appendix B - Installing and running the WaveVision4 software...............................................................................13
B.1 Installing the WaveVision Software .................................................................................................. 13
B.2 Java™ Technology........................................................................................................................... 13
B.3 Automatic Device Detection and Configuration ................................................................................ 13
B.4 Windows Driver ................................................................................................................................ 13
Appendix C - Using WaveVision Plots......................................................................................................................14
C.1 The Waveform Plot .......................................................................................................................... 14
C.2 The FFT Plot .................................................................................................................................... 14
C.3 FFT Options ..................................................................................................................................... 15
C.4 Histogram Plots ................................................................................................................................ 15
C.5 Information Viewer ........................................................................................................................... 16
C.6 Data Import and Export .................................................................................................................... 16
3
1.0 Introduction
The ADC08(B)3000RB Board is designed to
allow quick evaluation and design development
of National Semiconductor’s ADC083000 and
ADC08B3000 8-bit Analog-to-Digital Converters.
These devices are specified for 3.0 GSPS
operation. This reference board is designed to
function
with
National
Semiconductor’s
WaveVision Software, for fast evaluation. It
requires only 3 connections to get started: a
power supply, a USB Interface to PC and an
analog signal source. A 1.5 GHz clock generator
is provided on-board and the system also allows
for an external clock to be used if alternate
sample rates are required.
The ADC connects to a Xilinx Virtex4 FPGA
which stores up to 4K of data from each channel
before transferring it through the USB interface
to the PC.
2.0 Board Assembly
The ADC08(B)3000RB Evaluation Board comes
as a plain board with rubber standoffs and
requires no assisted cooling due to its low power
consumption.
The
ADC083000
and
ADC08B3000 devices are configured entirely
through software and also allow for changes to
easily be made to the FPGA configuration to
enable system development.
DC
Power
Input
External
Clock
Input
Power LED
Clock
Generator
LMX2531
Power On/Off
Switch
Expansion
Header
USB
Input
FPGA
ADC08(B)3000
USB
Microcontroller
Figure 1. Input/Output Connection and Board Overview
Analog
Differential
Input
Analog S/E
Input
LED
Indicators
4
3.0 Quick Start
Refer to Figure 1 for locations of the power
connection, signal input and USB port.
NOTE: Install the WaveVision 4.3.01.5 Beta
ADC08x3000 Software before connecting this
product to the PC. See Appendix B –
Installing WaveVision.
NOTE: If other versions of WaveVision
software have previously been installed on
the PC, they must be uninstalled prior to
installing this version and the “National
Semiconductor” folder in the C:\Program
Files\ directory must be deleted. Never install
more than one version of WaveVision onto a
PC at a time.
OVR LED just turns off. This will result in a
full-scale signal.
10. From the WaveVision window pull-down
menu select Acquire and then Samples.
The system will then capture the input
waveform and display the results in the time
domain.
11. For FFT Analysis, click the FFT Tab.
4.0 Board Specifications
The following shows the board specifications for
the ADC08(B)3000, Table 1.
Board Size: 168mm x 100mm
Power Requirements: +8 to +12V, 800mA
Clock Frequency Range : 800 MHz to 1.5 GHz
For quick start operation:
1. Install WaveVision software. See Appendix
B – Installing WaveVision.
2. Connect the 12V DC power source (included
with the reference board) to the power input
(8-12V DC).
3. Push the Power Switch to the ON position
and check that the Green LED between the
switch and the power connector illuminates.
4. Connect the USB cable (included) from the
USB port to a PC. If this is the first time the
board has been connected, Windows may
install the drivers for this product at this time.
5. Obtain a stable analog source capable of
supplying the desired frequencies at up to 8
dBm. Using a band-pass filter for AC-coupled
signals or a low-pass filter for DC-coupled
signals, connect this source signal to either
the single-ended input (J2) or the differential
inputs (J9 and J10). The exact level required
from the generator will depend upon the
insertion loss of the filter used.
6. Start the WaveVision software.
7. Once started, the “Firmware Download”
progress bar should be displayed. See
Appendix B for more information.
8. Upon Firmware Download completion, the
control panel for the board should
automatically be displayed on the PC and the
CLK LED on the front panel should be on
and blinking at a 50% duty cycle indicating
that it is functioning. Refer to Appendix A for
LED identification.
9. For the ADC083000: Set the signal source
for the analog input to 8 dBm at the desired
frequency. Observe that the Out of Range,
(OVR) LED is illuminated. If this LED is not
on, increase the input signal source until it is.
Now, reduce the signal source level until the
Analog Input Range 100MHz to 1800MHz
(AC-Coupled)
Nominal Analog Input 600 mV P-P to 800 mV P-P
Voltage
(Differential, AC-coupled):
Impedance: 50 Ohms
Table 1. Reference Board Specifications
4.1 FPGA Specification
The board supports a Xilinx LX15 Virtex 4 363pin FPGA. This device is responsible for
collecting and storing the data from ADC,
measuring the clock frequency, and uploading
the data through the microcontroller to the PC.
Normally, the FPGA is configured automatically
by the WaveVision software. It is possible,
through modification of the board, to configure
the FPGA using a FLASH ROM, so that the
system may be run without the USB
microcontroller.
NOTE:
Although the reference board
provides a powerful capability for the user to
develop his own FPGA code, National does
not support such custom FPGA code
development.
4.2 Microcontroller
A
Cypress
CY7C68013A
microcontroller
manages the USB interface and general control
of the board hardware. It uses a 24 MHz crystal
oscillator.
4.3 Memory Components
One 2K EEPROM (24C02 or similar) is
2
connected to the I C Bus for Microcontroller and
USB configuration data. This EEPROM also
identifies the ADC and clock source.
5
4.4 Power Supplies
Power to the board is supplied through a singlepin power jack to allow the use of an external
brick power supply with a voltage range of 8V to
12V.
The following supplies are provided by on-board
regulators (Switching and Linear):
•
•
•
•
•
3.3V - USB Microcontroller
3.3V – FPGA (LVCMOS I/O)
2.5V - FPGA (AUX and LVDS25 I/O)
1.9V - ADC (VA and VDR)
1.2V – FPGA (CORE)
A power LED indicator is provided on the front
edge of the board along with the status LEDs.
A Rocker Switch is provided on the rear edge of
the board to allow easy cold start/re-start.
The USB Microcontroller controls the shutdown
pins of all the switching regulators to minimize
power in standby mode.
4.5 Clocking
The USB Microcontroller is clocked by its own 24
MHz crystal oscillator. The ADC is clocked by
either a National Semiconductor PLL and a VCO
device, or by an external clock source. Switching
between clock sources is done through a relay
controlled by the WaveVision software.
The PLL and VCO devices are selected to
provide a 1500 MHz very low jitter, on-board
clock. The on-board PLL is programmed over a
serial interface through the FPGA.
The FPGA utilizes two different clock sources:
1. For capturing data from the ADC, the
FPGA uses the source synchronous
ADC data clock (ADC083000), which will
operate at a rate of either Fs/2 (Single
Data Rate) or Fs/4 (Dual Data Rate) or it
uses
the
supplied
read
clock
(ADC08B3000).
2. For all other functions such as
calculating the input clock frequency, and
uploading the captured data to the USB
Microcontroller, an on-board crystal
oscillator running at 100 MHz is used.
4.6 Resets
The USB Microcontroller utilizes a simple RC
power-on-reset circuit along with local pushbutton reset. The FPGA has a RESET input
signal which is
Microcontroller.
controlled
by
the
USB
4.7 Thermal Management
A National Semiconductor LM95221 Dual
Temperature Sensor device monitors the die
temperature of the ADC and the Virtex 4 FPGA
via their temperature diodes. This temp sensor
interfaces to the USB Microcontroller over a 2
wire serial bus. The ADC’s temperature is
monitored to determine when calibration cycles
are required. The user may also initiate a
calibration cycle using the WaveVision software.
4.8 ADC Analog Input
The analog input is provided through SMA
connectors on the front edge of the board. It may
be either single-ended (J2) or differential (J9 and
J10) and AC- or DC-coupled. (However, the
differential input may be AC-coupled only.)
These options are selected via the WaveVision
software and controlled by Teledyne RF relays
on-board.
In the case of a single-ended input, single-endedto-differential signal conversion is performed by a
Mini-Circuits Balun (ADTL2-18) for the ACcoupled path.
A differential input signal is
provided directly to the ADC via coupling
capacitors.
For a single-ended input, a LMH6555 differential
op-amp is used to DC-couple the input signal (if
DC-coupling is selected).
4.9 Status Indicators
This is a brief summary of the name,
abbreviation and description of the status LEDs:
Name
Abbr.
Standby
Trigger
Overrange
STB
TRG
Clock
Power-on
CLK
PWR
Upload
UPL
Sample
FPGA
RDY/IDLE
SMP
OVR
IDL
Description
All switching regulators
powered down
Trigger input indicator
Over-range indicator
Clock active indicator
(blinks)
12V-30V power
Data is being uploaded to
PC
Data is being captured by
FPGA
FPGA is programmed and
IDLE
Table 2. Status Indicators
6
The Following Status Indicators (LEDs) are
provided on the front edge of the board, Figure 2:
Figure 2. Component placement and front panel
4.10 Debug
A Mictor Logic Analyzer Header is provided along
with test-point headers both of which are
connected to the FPGA. This allows monitoring
of captured data and critical signals during board
debug. A JTAG header is also provided to allow
further FPGA development.
5.0 Functional Description
5.1 Input circuitry
The analog input signal to be digitized should be
applied to the “Analog Single-Ended Input” or the
“Analog Differential Input” SMA connectors.
These inputs accept low-noise analog signals. To
accurately evaluate the dynamic performance of
this converter, the input analog signals must be
filtered by a high-quality bandpass or lowpass
filter (depending upon whether the signal is ACor DC- coupled) with at least 10-bit equivalent
noise and distortion characteristics.
This reference board is capable of handling
either a single-ended or a differential analog
input. The single-ended input is converted to
differential signals on-board via a balun and
provides
the
single-ended-to-differential
conversion for the ADC. The differential PCB
traces to the ADC input pins have a characteristic
differential impedance of 100 Ohms.
When the DC-coupled input path is selected, a
50Ω DC impedance to ground must exist at the
input (signal generator must be DC-coupled and
only a lowpass filter should be used). Should an
AC-coupled signal generator or a bandpass filter
be required, the AC-coupled input path should be
used. However, should the customer desire to
use an AC-coupled source or a bandpass filter
with the DC-input path selected, a 49.9Ω resistor
should be populated to the device location R24 to
ensure the 50Ω DC impedance requirement for
the amplifier is met.
No scope or other test equipment should be
connected anywhere in the signal path while
gathering data.
5.2 ADC reference
The ADC083000 and ADC08B3000 have an
internal reference which cannot be adjusted.
However, the Full-Scale (differential) Range may
be adjusted with the Software Control Panel.
Refer to Section 7.0 for more information.
5.3 ADC clock
NOTE: When using the internal clock, be sure
to physically isolate the external clock signal
(either gate the signal generator off or
remove the external clock cable).
The ADC clock is supplied on-board and is a
fixed frequency of 1.5 GHz. An external clock
signal may be applied to the ADC through the
SMA Connector labeled in Figure 1 as “External
Clock Input”. The balun-transformer (T1)
converts the single-ended clock source to a
differential signal to drive the ADC clock pins.
The ADC clock should be as low-jitter as possible
or the apparent SNR of the ADC device will be
compromised.
When switching from an external reference clock
to the internal reference clock, or vice-versa, be
sure to press the Test Communication button in
the Capture Settings window. This will reload
the firmware with the appropriate settings.
5.4 Digital Data Output
The digital output data from the ADC is
connected to a Xilinx Virtex 4 FPGA. Up to 4K
bytes of data per channel can be stored and
subsequently uploaded over the USB interface to
the WaveVision software. The FPGA logic usage
is low, allowing for further code to be written and
tested for product development.
5.5 Power Requirements
The power supply requirement for the
ADC08(B)3000RB Reference Board is 12V at
800mA.
Most of the on-board regulators are switching
regulators for increased power efficiency.
The board typically draws around 500 mA, but it
is good practice to have extra power reserve in
the power supply above the typical power
requirements.
A Universal 100-240V AC input to 12V DC Brick
Power Supply is included with the reference
board.
5.6 Power Supply Connections
Power to this board is supplied through the power
connector. It is advised that only the supplied
PSU is used with this board.
7
The ADC supply voltage has been set to 1.9V,
±50 mV using on-board regulators.
7.0 Using the WaveVision software
with the ADC08(B)3000
6.0 Obtaining Best Results
7.1 Getting Started
Obtaining the best results with any ADC requires
both good circuit techniques and a good PC
board layout. For layout information for this
product, please contact you nearest National
Semiconductor representative.
6.1 Clock Jitter
When any circuitry is added after a signal source,
some jitter is almost always added to that signal.
Jitter in a clock signal, depending upon how bad
it is, can degrade dynamic performance. The
effects of jitter may be seen in the frequency
domain (FFT) as "leakage" or "spreading" around
the input frequency, as seen in Figure 3.
Compare this with the more desirable plot of
Figure 4. Note that all dynamic performance
parameters (shown to the right of the FFT) are
improved by eliminating clock jitter.
This reference board is designed to connect to a
PC running the WaveVision Software via a USB
interface.
Ensure the board is connected to the 12V power
supply (included with the package) and that the
switch on the rear panel is pushed to the “ON”
position. The Green LED on the rear panel
should be illuminated.
Connect the USB cable between the PC which
has WaveVision software installed and the
ADC08(B)3000RB board. The USB port may be
found on the rear panel (Figure 5).
If this is the first time the board has been
connected to the PC, drivers may be required to
be installed (automatic) by the Operating System.
Follow the on-screen instructions and use the
recommended settings.
Figure 5. ADC08(B)3000RB rear panel showing location
of USB connector
Start the WaveVision software. (Start -> All
Programs -> WaveVision -> WaveVision4)
Figure 3. Jitter causes a spreading around the input
signal, as well as undesirable signal spurs.
The software may take several seconds to
initialize, but should display a welcome screen
similar to the Figure 6.
Figure 4. Eliminating or minimizing clock jitter results in a
more desirable FFT that is more representative of how
the ADC actually performs.
Figure 6. WaveVision welcome screen
If the board is connected correctly, the following
popup box should appear (Figure 7) to indicate
that the board has been recognized and the
firmware for the FPGA is being downloaded over
the USB interface.
8
Figure 7. Firmware downloading popup box
If the “Downloading firmware” box does not
appear automatically, click on the “Settings” pulldown menu and then click Capture Settings
(Figure 8).
Figure 10. Control Panel window
Figure 8. Capture Settings location
This will display the System Settings (Figure 9).
The following section describes the function of
the pull-down selection tabs in the left-hand side
of the ADC08(B)3000RB product Control Panel.
Note that some functions are device dependent.
Refer to the device datasheet for available
features.
Ø
o
Ø
Temp Sensor
This displays the die temperature of both
the FPGA and the ADC.
Hardware/Serial Control
Hardware Pin Control – The ADC is
controlled by the logic states on the
dedicated control pins. The logic on
these pins is determined by the setting of
OUTV, OUTEDGE, DDR, and FSR, as
described below.
o Serial Register Program – The ADC’s
registers are accessed through the
Extended Control Mode. In this mode,
the hardware pin control is disabled and
the programmable registers are available
for fine tuning.
o
Figure 9. System Settings window
If the board has not been detected, click the Test
button under the Communication heading. This
forces the software to download the software to
the FPGA. If the communications fail, check that
the USB drivers are installed correctly. Then,
disconnect and re-connect the USB cable.
Finally, restart the WaveVision software. See
Appendix B for more information.
7.2 Control Panel
Once the FPGA Firmware download is complete,
the reference board Control Panel will
automatically be displayed (Figure 10).
NOTE: The Following Pull-down Tabs are
available only when Hardware Pin Control is
selected.
Ø
Out V
Low Amplitude – LVDS output voltage
amplitude is set to 520 mVpk-pk.
o High Amplitude – LVDS output voltage
amplitude is set to 680 mVpk-pk.
o
Ø
OutEdge (SDR mode only, i.e. DDR
disabled)
o Falling Edge – Data outputs are
changed on the falling edge of DCLK+.
o Rising Edge – Data outputs are
changed on the rising edge of DCLK+.
9
Ø
DDR
Disable Dual Data Rate – DDR Mode is
disabled
(data
output
transitions
determined by OutEdge Setting).
o Enable Dual Data Rate – Data
transitions occur on both rising and
falling edge of DCLK+. (This is the
default mode for 1.5 GHz clock).
o
Ø
7.3 Serial Control Mode
When the Hardware/Serial Control tab is selected
as Serial Register Program, the control panel
display will enable the other bits (Figure 11).
FSR
600mV Full Scale – Sets the full-scale
range to 600 mVpk-pk.
o 800mV Full Scale – Sets the full-scale
range to 800 mVpk-pk.
o
NOTE: The Following Pull-down Tabs are
available regardless of Hardware/Serial
Control setting.
Ø
Standby
Active – Enable all on-board power
regulators.
o Standby – Board is put into standby
mode; all power is shutdown except USB
power.
o
Ø
PD
Disable Shutdown – The ADC is
powered up and active.
o Enable Shutdown – The ADC is put into
low power mode. Register Settings are
retained.
o
Ø
DC_Coup
AC Coupling – The analog input
channel is AC-coupled to the ADC’s
input.
o DC Coupling – The analog input
channel is DC-coupled to the ADC’s
input.
o
Ø
Ext Clock
Internal Clock – The ADC is clocked
using the on-board clock.
o External Clock – The ADC is clocked
from an external clock source which is
connected to the “CLOCK” input.
o
Ø
o
Ø
o
Reset FPGA
This button resets the FPGA, and also
returns all the pull-down tabs to their
default values.
Calibrate ADC
This button issues an on-command
calibration to the ADC by toggling the
ADC’s calibrate pin.
Figure 11. Serial Register Program window
In this mode, the register settings may be
changed simply by clicking on the bits. Doing so
will toggle each bit value. Any linear values such
as Full Scale Range or Offset will automatically
be updated.
The Reset Registers button at the bottom of the
Control Panel will reset and write all the values to
the power-on default settings.
NOTE: Please refer to the ADC08(B)3000
datasheet for a full description of the ADC’s
internal registers.
7.4 Manually downloading the FPGA firmware
Although the WaveVision software is designed to
automatically recognize the reference board and
download the appropriate FPGA code into it, it is
possible for the user to download a different
FPGA code (the .bit file) into the board. To
download another FPGA code into the board,
follow these instructions:
1. Place the desired .bit file (Xilinx object
code that is known to operate correctly for
the reference board you are using) in a
known directory of your choice on the C:
drive.
2. Start WaveVision with the board connected
via the USB.
3. The default FPGA will load automatically –
this will be overwritten.
4. From the main WaveVision panel, under
the Settings drop down menu, select
Capture Settings. This will bring up
another panel called System Settings.
10
5. Click the Xilinx Image Settings button
within the System Settings panel. This will
bring up another panel labeled Select
Xilinx Firmware.
6. Deselect the Select Images automatically
button.
7. Then click the Browse button and select
the location of the bit file.
8. Click the Accept button. The Select Xilinx
Firmware panel will disappear.
9. Load the FPGA image by clicking on the
Reset (or Test in some versions) button. It
may be found in the Communication subpanel of the System Settings panel.
10. FPGA bit file download may be confirmed
by observing the progress bar pop-up. If
the progress bar goes half-way and
suddenly terminates, the FPGA has not
loaded. The second half should progress at
a similar rate.
Please note that the reference board's operation
is only assured for the FPGA code provided by
National. Though the board makes it possible for
the user to develop and test his own FPGA code,
such operation is not supported by National.
7.5 Capturing Waveforms
When the ADC has been properly configured, the
selected input(s) may be sampled by clicking the
Acquire pull-down menu and selecting Samples.
Alternately, press F1 then the Escape key. See
Figure 12 for a sample waveform.
Figure 12. Waveform capture example
Appendix A - Hardware Information
Ø STB (STANDBY) - illuminates when the
board is in standby mode.
A.1 Xilinx Virtex 4 FPGA
Ø TRG (TRIGGER EVENT) - illuminates
when the Trigger Input makes low to high
transition.
The
ADC08(B)3000RB
reference
board
implements the Xilinx Virtex 4 XC4VLX1510SF363C FPGA for ADC control and data
capture. The FPGA firmware is loaded over the
USB port when the WaveVision software is
started.
The FPGA Verilog code and
supplemental documentation is available to users
upon request. Please contact your local National
Semiconductor Sales or Field Applications
Representative.
Ø OVR (ADC OVER-RANGE) - illuminates
when the analog input channel exceeds
the full-scale range of the ADC.
Ø CLK (CLOCK INPUT) - flashes with 50%
duty cycle if the ADC is receiving a clock
input.
A.2 LED functions
Ø PWR (POWER) - illuminates when the
external 12V power supply is connected
and the system is not in Standby.
The function of the LEDs on the front panel of the
board (Figure 13) is as follows:
Ø UPL (UPLOAD) - illuminates when the
FPGA is uploading sample data to the PC.
Ø SMP (SAMPLE) - illuminates when the
FPGA is sampling data and storing to the
FIFO buffers.
Ø IDL (IDLE) - illuminates when the system
is IDLE.
Figure 13. LED front panel
11
A.3 Expansion Header
A 72-pin Future Bus Expansion Header (Table 3)
is provided on the rear panel to allow easy
connection to a third-party microprocessor board
to allow for the reading and analysis of the data
captured by the FPGA.
Ø
Two 8-bit busses with LVDS differential
signaling, plus two LVDS strobes.
Ø
Four 8-bit busses with LVCMOS (3.3V
I/O) signaling plus four CMOS strobes.
All control signals on pins A1 to A15 will be at
LVCMOS 3.3V levels.
The Data busses on this header may be
configured as follows:
PIN
P1_A1
P1_A2
P1_A3
P1_A4
P1_A5
P1_A6
P2_A1
P2_A2
P2_A3
P2_A4
P2_A5
P2_A6
P3_A1
P3_A2
P3_A3
P3_A4
P3_A5
P3_A6
DESCRIPTION
I2C – SDA
I2C – SCL
SSP – SERIAL DATA
SSP – SERIAL CLOCK
FPGA RESET
READ FIFO
WRITE FIFO
FIFO FULL
FIFO EMPTY
ADC DCLK RESET
FPGA CONF DONE
FPGA JTAG – TMS
FPGA JTAG – TCK
FPGA JTAG – TDI
FPGA JTAG – TDO
Not SHUTDOWN
3.3V SUPPLY
12V SUPPLY
PIN
P1_B1
P1_B2
P1_B3
P1_B4
P1_B5
P1_B6
P2_B1
P2_B2
P2_B3
P2_B4
P2_B5
P2_B6
P3_B1
P3_B2
P3_B3
P3_B4
P3_B5
P3_B6
DESCRIPTION
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
P1_C1
P1_C2
P1_C3
P1_C4
P1_C5
P1_C6
P2_C1
P2_C2
P2_C3
P2_C4
P2_C5
P2_C6
P3_C1
P3_C2
P3_C3
P3_C4
P3_C5
P3_C6
DATA BUS A P0 (LVDS or CMOS)
P1_D1
DATA BUS A N0 (LVDS or CMOS)
DATA BUS A P1 (LVDS or CMOS)
P1_D2
DATA BUS A N1 (LVDS or CMOS)
DATA BUS A P2 (LVDS or CMOS)
P1_D3
DATA BUS A N2 (LVDS or CMOS)
DATA BUS A P3 (LVDS or CMOS)
P1_D4
DATA BUS A N3 (LVDS or CMOS)
DATA BUS A P4 (LVDS or CMOS)
P1_D5
DATA BUS A N4 (LVDS or CMOS)
DATA BUS A P5 (LVDS or CMOS)
P1_D6
DATA BUS A N5 (LVDS or CMOS)
DATA BUS A P6 (LVDS or CMOS)
P2_D1
DATA BUS A N6 (LVDS or CMOS)
DATA BUS A P7 (LVDS or CMOS)
P2_D2
DATA BUS A N7 (LVDS or CMOS)
INPUT STROBE P
P2_D3
INPUT STROBE N
DATA BUS B P0 (LVDS or CMOS)
P2_D4
DATA BUS B N0 (LVDS or CMOS)
DATA BUS B P1 (LVDS or CMOS)
P2_D5
DATA BUS B N1 (LVDS or CMOS)
DATA BUS B P2 (LVDS or CMOS)
P2_D6
DATA BUS B N2 (LVDS or CMOS)
DATA BUS B P3 (LVDS or CMOS)
P3_D1
DATA BUS B N3 (LVDS or CMOS)
DATA BUS B P4 (LVDS or CMOS)
P3_D2
DATA BUS B N4 (LVDS or CMOS)
DATA BUS B P5 (LVDS or CMOS)
P3_D3
DATA BUS B N5 (LVDS or CMOS)
DATA BUS B P6 (LVDS or CMOS)
P3_D4
DATA BUS B N6 (LVDS or CMOS)
DATA BUS B P7 (LVDS or CMOS)
P3_D5
DATA BUS B N7 (LVDS or CMOS)
OUTPUT STROBE P
P3_D6
OUTPUT STROBE N
Table 3. Future bus expansion header pins
3'
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/ RJLF $ QDO
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2 XW
( GJH ' ' 5
2 XW
9
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12
A.4 System Block Diagram
13
Appendix B - Installing and running
the WaveVision4 software
B.1 Installing the WaveVision Software
1. Insert the WaveVision CD-ROM into the
computer’s CD-ROM drive.
2. The WaveVision software requires a
Java Runtime Environment or Java
Development Kit, Version 1.4 or higher,
from Sun Microsystems, Inc. For detailed
information on WaveVision’s use of Java
technology, see Section 10.2. If the
computer does not have this software,
the WaveVision installer will instruct you
on how to install it.
3. Locate and run the WaveVision4
Setup.exe program on the CD-ROM.
4. Follow the on-screen instructions to
finish the install.
B.2 Java™ Technology
The
WaveVision
software
uses
Sun
Microsystems Java technology. The underlying
Java software must be installed on the computer
in order for the WaveVision software to run. The
software can run on top of either the Java
Runtime Environment (JRE) or the Java
Development Kit (JDK), Version 1.4 or higher. A
suitable copy of the JRE is included on the
WaveVision CD-ROM.
The WaveVision installer will first search for an
existing copy of the JRE or JDK on the computer.
If neither is found, the installer will prompt you to
first install a JRE.
To do this, run the
J2RE*.exe installer program which may be
found on the CD-ROM. Follow the on-screen
instructions to finish the install.
After a suitable JRE or JDK is installed, run the
WaveVision installer again. The installer will
detect the Java software and configure the
WaveVision software to use it.
Java technology can allow software to run on
different platforms. However, the WaveVision
software contains Windows-specific hardware
interface code and is therefore only supported
under Windows.
B.3 Automatic Device Detection and
Configuration
The WaveVision system provides automatic
hardware detection and configuration for the
device under test. The FPGA is re-programmed
automatically by the host PC when the reference
board is turned on.
Normally, the configuration process is completely
transparent to the user and requires no
intervention. However, this process can be
overridden, if required, by specifying a new Xilinx
configuration image. To do this, select the Xilinx
Image Settings button (Figure 14) within the
Capture Setting window (Settings ? Capture
Settings).
Figure 14. Selecting Xilinx image settings
B.4 Windows Driver
The WaveVision software communicates with the
WaveVision hardware through the Windows
device driver software. If you are unable to
connect to the WaveVision board after installing
the software, do the following to uninstall and
reinstall the driver:
1. Find the Windows Control Panel and
select System. If you are using Windows
2000/XP, select the Hardware tab.
2. Click on Device Manager and scroll down
to the Universal Serial Bus controllers.
3. With the WaveVision board connected, an
unknown device will be listed.
4. Right click on the unknown device and
uninstall the driver.
5. Unplug the USB cable from the board.
6. Plug in USB cable to the board again to
reinstall the driver.
14
Appendix C - Using WaveVision Plots
Ø
Magnifying glass tool: This tool allows
you to zoom in and out to see fine details in
the plot. Click and drag a box from upperleft to lower-right to zoom in on the region
of interest. Click and drag a box from
lower-right to upper-left to zoom out. With
the magnifying glass tool selected, click
the right mouse button to return to a full
view.
Ø
Arrow Tool: The arrow tool is used to
select, move, and edit annotations. To edit
an annotation, double click it with the arrow
tool. To delete an annotation, select it with
the arrow tool and press the Delete key on
your keyboard.
Ø
Line Annotation Tool: To draw lines on
the plot, select this tool. Drag to draw new
lines.
To add arrowheads or fix the
endpoints of the line, double-click the
appropriate end with the arrow tool.
Ø
Text Annotation Tool: To draw labels on
the plot, select this tool and click at the
desired location in the plot. To edit the
justification, location, or text of an
annotation, double-click it with the arrow
tool.
The WaveVision software provides several tools
to manipulate the plot view. A toolbar appears
above each plot, similar to Figure 15.
Seen from left to right, the following tools are
available:
Ø
Ø
Ø
Plot Actions: This menu contains
commands that pertain to this particular
plot. You may export the plot data to a file,
print it, save it as a graphic, or change the
plot’s colors.
Plot Options: This button opens a dialog
box with options that pertain to this
particular plot. You may turn off labels,
annotations, or other elements in this
dialog.
The WaveVision software
maintains default options for new plots.
You may edit the default options by
choosing Default Plot Options from the
Settings menu.
FFT Options: The toolbar shown in Figure
15 is from an FFT plot, and thus contains a
button to edit the options for the FFT
calculation. Depending upon the type of
plot, various options will be present on the
toolbar. Please consult the appropriate
section below for more information about
these options.
Figure 15. WaveVision plot tools
C.1 The Waveform Plot
The Waveform plot displays the raw samples
collected from the hardware.
This plot is
primarily used to verify the integrity of collected
data. The waveform is the best view in which to
diagnose a distorted signal, an irregular clock, a
low-amplitude signal, and many other common
ADC system problems.
The Waveform plot also quickly shows how much
of the ADC’s dynamic range the analog input
signal occupies.
C.2 The FFT Plot
The
WaveVision
software
automatically
computes a Fast Fourier Transform (FFT) of the
sample set, and displays the results in an FFT
plot. The resulting FFT plot is, in many respects,
the heart of the software because it shows the
frequency content of the analog input signal. It
marks the fundamental frequency, and a
selectable number of harmonics. It also labels
their order and frequencies. It shows the power
in the fundamental and harmonics. Place the
mouse cursor over a harmonic to display
information about it.
The FFT may be used to diagnose common ADC
problems such as input spectral impurity, clock
phase noise, and clock jitter. The FFT plot also
shows several statistics on the quality and purity
of the collected samples including SNR, SINAD,
THD, SFDR, and ENOB. These statistics are to
be interpreted with the following definitions
(which are repeated in every National
Semiconductor ADC datasheet):
15
Ø
Ø
Ø
Signal to Noise Plus Distortion (S/N+D
or SINAD) Is the ratio, expressed in dB, of
the RMS value of the input signal to the
RMS value of all of the other spectral
components below half the clock
frequency,
including
harmonics
but
excluding DC.
Signal to Noise Ratio (SNR) is the ratio,
expressed in dB, of the RMS value of the
input signal to the RMS value of the sum of
all other spectral components below onehalf the sampling frequency, not including
harmonics or DC.
Ø
Windowing: You may choose from one of
five different window functions.
The
window function is applied to the samples
before computing the FFT to compensate
for the fact that the sample set may not be
an integral number of wavelengths of the
input signal. In general, Flat-Top will give
the best results, but it may be easier to
compare data with other systems when the
windowing functions are the same.
Ø
dB Scale: You may select to represent
power on the FFT in dBc (decibels relative
to carrier), in which 0 dB is taken to be the
fundamental (carrier) power, or dBFS
(decibels relative to full-scale), in which 0
dB is taken to the be power contained in a
signal which uses the entire dynamic range
of the ADC.
Ø
Harmonic Calculations: You may select
the number of harmonics recognized (and
labeled) by the software. You may also
select the number of FFT bins excluded
around harmonics in, for example, SNR
calculations. The exclusion region around
each harmonic will be shown in a different
color than the rest of the data points.
Ø
IMD Calculations: The WaveVision
software is capable of performing
Intermodulation Distortion calculations.
When two fundamental frequencies within
3 dBFS are present in the waveform, the
software will automatically perform IMD
calculations. You may inhibit this behavior
by deselecting the Allow IMD calculation
checkbox. When the IMD calculation is
enabled, you may also select whether the
nd
software will include only 2 order or both
nd
rd
2 and 3 order terms.
Total Harmonic Distortion (THD) is the
ratio, expressed in dBc, of the RMS total of
the first five harmonic levels at the output
to the level of the fundamental at the
output. THD is calculated as
f 2 +L + f N
2
THD = 20 log
f1
2
2
where f1 is the RMS power of the
fundamental (output) frequency and f2
through fN are the RMS power in the first N
harmonic frequencies.
Ø
Spurious-Free Dynamic Range (SFDR)
is the difference, expressed in dB, between
the RMS values of the input signal and the
peak spurious signal, where a spurious
signal is any signal present in the output
spectrum that is not present at the input.
Ø
Effective Number of Bits (ENOB, or
Effective Bits) is another method of
specifying Signal-to-Noise and Distortion or
SINAD. ENOB is defined as
ENOB =
SINAD − 1.76
6.02
and says that the converter is equivalent to
a perfect ADC of this (ENOB) number of
bits.
C.3 FFT Options
FFT plots can be configured in many different
ways. Clicking the FFT Options button at the
top of the plot will display a dialog showing the
options for that particular plot. The software also
maintains default options for new FFT plots,
which are editable. The default FFT options may
be edited by choosing Default FFT Options from
the Settings menu. The options are:
C.4 Software Histogram
Histogram plots are created by counting the
number of times each ADC output code appears
in a dataset. Histograms may be computed by
software, or by hardware. A software histogram
is computed from a dataset which is normally
128k samples or smaller. A hardware histogram
is collected directly by the hardware, and may
include millions of counts per code. The resulting
histogram will show discontinuities between
comparators, gain or offset errors, and other
common ADC system problems.
The Histogram plot also displays the number of
codes that were never counted (missing codes),
followed by the first ten such missing codes.
16
C.5 Information Viewer
The information viewer is not a plot, but it
displays a variety of useful information about the
dataset, such as the sampling rate, and any
warnings generated by the software. You may
also store comments about the dataset here, to
be saved in a WaveVision file.
C.6 Data Import and Export
There are a variety of ways to export data from
the software:
Ø
Save the file as a normal WV4 (*.wv4) file.
WV4 files are ASCII, tab-delimited text
files. Samples are stored one per line in a
single column. You can open a WV4 file
directly into a spreadsheet program.
Ø
Save the file as a TXT (*.txt) file. You will
produce a one- or two-column tabdelimited ASCII text file of samples or
histogram information, without the header
information that is contained in a WV4 file.
Ø
You can export the contents of an
individual plot by choosing Export Data
from the plot’s Plot Actions menu. The
format of the data is always tab-delimited
ASCII text.
Ø
You can export a plot as either a GIF (*.gif)
or Encapsulated Postscript (*.eps) graphic
by choosing Export Plot as Graphic from
the plot’s Plot Actions menu. GIF files are
suitable for the web or for emails.
Encapsulated Postscript files are highresolution scalable files suitable for direct
publication.
The WaveVision software provides a variety of
means to share data with others, in both textual
and graphical formats.
The most flexible way to import data into the
software is from a tab-delimited ASCII text file.
The contents can be either a sample set or a
histogram, provided with or without time
information. The simplest example of this would
be a file with a single column of samples. You
may open tab-delimited text files by choosing
Open from the File menu; you can interleave
data from multiple columns and/or files. You can
choose Reopen to reopen the same file later with
the same settings (for example, if you update the
file with new data),
17
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