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Texas Instruments DAC5686 EVM (Rev. F) User guides
User's Guide
SLWU006F – December 2004 – Revised August 2010
DAC5686 EVM
1
2
3
4
5
Contents
Overview ..................................................................................................................... 2
DAC5686 EVM Operational Procedure .................................................................................. 3
Physical Description ........................................................................................................ 9
Circuit Description ......................................................................................................... 15
Schematic .................................................................................................................. 18
List of Figures
1
Serial Interface GUI ......................................................................................................... 4
2
DAC5686 Setup for X4 Interpolation, Single Sideband Mode and Tone at Fdac/4 ................................ 5
3
Spectrum with CLK2 = 500 MHz, X4 Interpolation, Single Sideband Mode, NCO Off
4
Spectrum with CLK2 = 320 MHz, X4 Interpolation, Single Sideband Mode and NCO Frequency =
536870912 ................................................................................................................... 7
5
Top Layer 1
6
7
8
9
10
11
12
13
............................
................................................................................................................
Layer 2, Ground Plane ....................................................................................................
Layer 3, Power Plane .....................................................................................................
Bottom Layer ...............................................................................................................
Schematic - Page 1 .......................................................................................................
Schematic - Page 2 .......................................................................................................
Schematic - Page 3 .......................................................................................................
Schematic - Page 4 .......................................................................................................
Schematic - Page 5 .......................................................................................................
6
10
11
12
13
19
20
21
22
23
List of Tables
................................................................................................
1
DAC5686 EVM Parts List
2
Input Connector J13 (Data A Bus) ...................................................................................... 15
3
Input Connector J14 (Data B Bus) ...................................................................................... 16
4
Transformer Output Configuration....................................................................................... 16
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
DAC5686 EVM
14
1
Overview
1
www.ti.com
Overview
This user's guide document gives a general overview of the DAC5686 evaluation module (EVM) and
provides a general description of the features and functions to be considered while using this module.
1.1
Purpose
The DAC5686 EVM provides a platform for evaluating the DAC5686 digital-to-analog converter (DAC)
under various signal, reference, and supply conditions. This document should be used in combination with
the EVM schematic diagram supplied.
1.2
EVM Basic Functions
Digital inputs to the DAC can be provided with CMOS level signals up to 160 MSPS through two 34-pin
headers. This enables the user to provide high-speed digital data to the DAC5686 device.
The analog outputs from the DAC are available via SMA connectors. Because of its flexible design the
analog output of the DAC5686 device can be configured to drive a doubly terminated 50-Ω cable using a
4:1 or 1:1 impedance ratio transformer, or single-ended referred to AVDD.
The EVM allows for different clock configurations. The user can input a single-ended, differential
ECL/PECL or TTL/CMOS level signal, to be used to generate a single-ended or differential clock source.
See Section 4.1 for proper configuration and operation.
Power connections to the EVM are via banana jack sockets.
In addition to the internal bandgap reference provided by the DAC5686 device, options on the EVM allow
an external reference to be provided to the DAC.
The DAC5686 EVM allows the user to program the DAC5686 internal registers with the supplied computer
parallel port cable and serial interface software. The interface allows read and write access to all registers
that define the operation mode of the DAC5686 device.
1.3
Power Requirements
The demonstration board requires a minimum of two power supplies. For non-PLL and 3.3-V I/O
operation, connect 3.3 Vdc to banana jack J7 with the return connected to J9. Connect 1.8 Vdc to banana
jack J8 and the return to J10. Jumper W2 selects the digital I/O voltage level and jumper W3 enables the
PLL.
1.3.1
Voltage Limits
Exceeding the maximum input voltages can damage EVM components. Undervoltage may cause
improper operation of some or all of the EVM components.
1.4
Software Installation
All
1.
2.
3.
4.
5.
necessary software to operate the serial interface is provided on the enclosed CD-ROM.
Insert the CD-ROM into the computer to be used to operate the serial interface.
Unzip the contents of the DAC5686SPI_Installv1p1.zip into the C:\temp directory on the PC.
Run the file called setup.exe in the C:\temp\Installer directory.
The software will install the appropriate files to the C:\Program Files\TI.fdr directory.
Once the installation is complete, the computer should be rebooted. The software is launched by
running
C:\ProgramFiles\TI.fdr\DAC5686_SPI\DAC5686_SPI.exe.
A shortcut for that program can be created and placed on the desktop or any other relevant location. See
Section 2, DAC5686 EVM Operational Procedure, for instructions on operating the serial interface
software.
2
DAC5686 EVM
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
DAC5686 EVM Operational Procedure
www.ti.com
1.5
Hardware Configuration
The DAC5686 EVM can be set up in a variety of configurations to accommodate a specific mode of
operation. Before starting evaluation, the user should decide on the configuration and make the
appropriate connections or changes. The demonstration board comes with the following factory-set
configuration:
• Differential clock mode using transformers T3 and T4. Input single-ended clocks are required at J3 and
J4.
• Transformer-coupled outputs using transformers T1 and T2.
• The converter is set to operate with internal reference. Jumper W1 is installed between pins 2 and 3.
• Full-scale output current set to 20 mA through RBIAS resistor R1.
• The DAC5686 output is enabled (sleep mode disabled).
• TXENABLE is set high to enable the DAC5686 device to process data.
• Internal PLL disabled. Jumper W3 is installed between pins 2 and 3.
• Input data level is set to +3.3VDC. Jumper W2 is installed between pins 1 and 2.
To
1.
2.
3.
prepare the DAC5686 EVM for evaluation, connect the following:
3.3 V to J7 and the return to J9.
1.8 V to J8 and the return to J10.
Provide a single-ended, 300-mVPP , 0-V offset sine-wave signal to SMA connector J3 (CLK1) if the
internal PLL is to be used. Connect this signal to SMA connector J4 (CLK2) if the PLL is disabled. A
second sine-wave source is required only for dual clock mode. In this mode, the signal on CLK1 is
used to clock data into the DAC5686 and the signal on CLK2 is used to clock the internal DAC. CLK1
and CLK2 must be phase-aligned for this option to work properly. In order to preserve the specified
performance of the DAC5686 converter, the clock sources must feature very low jitter. Using a clock
with a 50% duty cycle gives optimum dynamic performance.
4. Use a digital test pattern generator with 50-Ω outputs to provide 3.3-V CMOS logic level inputs to
connectors J13 and J14. Adjust the digital inputs to provide the proper setup and hold times at the
DAC5686 inputs. See the DAC5686 data sheet (SLWS147) for timing information.
5. Connect one end of the supplied serial interface cable to the parallel port of a PC. Connect the other
end of the cable to J1 on the EVM.
6. The DAC5686 outputs can be monitored using SMA connector J5 for IOUTA and SMA connector J19
for IOUTB.
2
DAC5686 EVM Operational Procedure
This chapter describes the serial interface GUI.
To prepare the DAC5686 EVM for operation, connect one end of the supplied serial interface cable to the
parallel port of a PC and the other end of the cable to J1 on the EVM.
2.1
Starting the Serial Interface Program
Power up the EVM. After power up, depress switch S1 to reset the DAC5686. Start the software by
running DAC5686_SPI.exe. If the EVM is powered on with the parallel port connected properly, then the
GUI shown in Figure 1 is displayed with the default settings read from the device. If there is a problem
with the communication, such as the EVM is not powered on or the parallel port cable is not connected, an
error message will be displayed instructing the user to correct the problem. Once corrected, hit the Read
All button to read the default settings of the device.
For normal operation, the user needs only to select values and switches as desired. The values are
automatically sent to the device and read back to verify their configuration.
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
DAC5686 EVM
3
DAC5686 EVM Operational Procedure
www.ti.com
Figure 1. Serial Interface GUI
4
DAC5686 EVM
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
DAC5686 EVM Operational Procedure
www.ti.com
2.2
DAC5686 EVM Initial Setup Tests
There are several initial tests with the DAC5686 that can be done without any input data. The following
setup steps are suggested to familiarize the user with the DAC5686 and EVM software and verify that the
DAC5686 is functioning properly.
1. Provide a CLK2 input and disable the internal PLL (W3 between pins 2 and 3). Do not provide parallel
input data.
2. Power up the EVM with 1.8 V DVDD and 3.3 V AVDD
3. Start the DAC5686_SPI software.
4. Turn "Full Bypass" off, change Interpolation to "x4", set Mode to "Single Sideband" and the Coarse
Gain for both DACs to 15. The GUI should now look as shown in Figure 2.
Figure 2. DAC5686 Setup for X4 Interpolation, Single Sideband Mode and Tone at Fdac/4
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
DAC5686 EVM
5
DAC5686 EVM Operational Procedure
www.ti.com
A tone at a frequency of CLK2/4 should now be present at connectors J5 (IOUTA) and J19 (IOUTB). In
the case of CLK2 = 500 MHz, the output spectrum should be similar to Figure 3, with a tone at
125MHz.
This tone is being generated by the DAC5686 Fdac/4 Coarse Mixer as with no input data provided to
connectors J13 and J14, the Channel A and B data bus inputs will all be zeros, or a full scale negative
value in the default offset binary format.
* RBW
Ref
10 dBm
* Att
VBW
SWT
35 dB
3 kHz
10 kHz
28 s
Marke r 1 [T1 ]
4. 56 d Bm
12 5.00 00000 00 M Hz
1
10
*
A
0
1 AP
CLRWR
−10
−20
−30
−40
−50
−60
−70
−80
−90
Cent er
125 MHz
25 M Hz/
Span
250 MH z
Figure 3. Spectrum with CLK2 = 500 MHz, X4 Interpolation, Single Sideband Mode, NCO Off
6
DAC5686 EVM
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
DAC5686 EVM Operational Procedure
www.ti.com
5. Reduce the CLK2 frequency to less than 320MHz. Enable the NCO and change the NCO DDS to
536870912. Doing this will generate a tone at Fdac/8. For CLK2 = 320 MHz, the tone corresponds to
40 MHz. The output spectrum should be similar to the one in Figure 4.
* RBW
Ref
10 dBm
* Att
35 dB
VBW
SWT
3 kHz
10 kHz
18 s
Marke r 1 [T1 ]
2. 71 d Bm
4 0.00 00000 00 M Hz
10
*
1
A
0
1 AP
CLRWR
−10
−20
−30
−40
−50
−60
−70
−80
−90
Cent er
80 MHz
16 M Hz/
Span
160 MH z
Figure 4. Spectrum with CLK2 = 320 MHz, X4 Interpolation, Single Sideband Mode and NCO Frequency =
536870912
6. Changing the NCO DDS to 268435456 will now result at an output tone at 20 MHz.
2.3
DAC5686 GUI Register Descriptions
The following section provides a brief description of each control:
2.3.1
•
•
•
•
Register Controls
Load Regs: Loads register values from a saved file to the DAC5686 and updates the GUI.
Save Regs: Saves current GUI registers settings to a text file for future use.
Read All: Reads the current registers of the DAC5686. This is used to verify settings on the front
panel.
Send All: Sends the current front panel registers to the device. This is generally only used when the
EVM power has recycled or the device has been reset and the user wants to load the displayed
settings to the device.
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
DAC5686 EVM
7
DAC5686 EVM Operational Procedure
2.3.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8
www.ti.com
Configuration Controls
Full Bypass: When set, all interpolation and NCO functions are bypassed. User can only use
CLK2/CLK2C inputs in this mode.
Counter: Uses an input counter ramp as the input data to the DAC. See the DAC5686 data sheet for
more information.
2's Comp: When set, input data is interpreted as 2's complement. When cleared, input data is
interpreted as offset binary.
Sync_Phstr: Enables the PHSTR input as a sync input to the clock dividers in external single clock
mode. For example, in external single clock mode (PLLVDD = 0), with 16x interpolation, the
CLK2/CLK2C signal is divided by 16 and output on the PLLLOCK pin. If this bit is set, a rising edge on
the PHSTR pin will be sampled by the CLK2/CLK2C clock, and used to restart the divide by 16 circuit.
Dither: Enables dithering in the PLL.
Rev B Bus: When cleared, DB input data MSB to LSB order is DB(15)= MSB and DB(0)=LSB. When
set, DB input data MSB to LSB order is reversed, DB(15) = LSB and DB(0) = MSB.
qflag: Sets qflag bit. When set, the QFLAG input pin operates as a B sample indicator when
interleaved data is enabled. When cleared, the TXENABLE rising determines the A/B timing
relationship.
Rev. Spect: When asserted the sin term is negated before being used in mixing. This gives the
reverse spectrum in single sideband mode.
Interleave: When set, interleaved input data mode is enabled; both A and B data streams are input at
the DA(15:0) input pins. The TXENABLE or QFLAG pin is used to identify the I/Q sequence depending
on the value the "Qflag Interleave" bit (see the following)
Inverse Sinc: Enables inverse sinc correction filter.
Dual Clk: Only used when the PLL is disabled. When set, two differential clocks are used to input the
data to the chip; CLK1/CLK1C is used to latch the input data into the chip, and CLK2/CLK2C is used
as the DAC sample clock.
NCO: When set, enables NCO in Single Sideband or Quad Mod modes. The NCO is operational up to
350 MHz DAC update clock. When cleared, Single Sideband and Quad Mod modes use a fixed fs/4
mix frequency.
Sif: Sets sif_4pin bit. The 4 pin serial interface mode is enabled when on, 3 pin mode when off. The
DAC5686 EVM is configured for a 3 pin serial interface, so setting to a 4 bit serial interface makes
reading registers impossible with the GUI.
Single Sideband: When set, the data to DACB is inverted to generate upper side band output.
Mode: Used to select the DAC mixer mode.
– Dual DAC - runs the device in dual DAC mode; no mixing between the A and B datapaths.
– Quad Mod - runs the device as a quadrature modulator. The DACA circuit is shut off and the output
is on the DACB outputs.
– Single Sideband - The device generates a hilbert transform pair on the DACA and DACB outputs
suitable for connection to an analog quadrature modulator.
PLL Divider: Sets PLL VCO divider to div by 1, 2, 4, or 8. Only valid when the PLL is enabled by
providing +3.3 V to PLLVDD (W3 between pins 1 and 2). The VCO works best (low phase noise) when
biased in the 250 to 500 MHz range. If the device is to be run with a DAC update rate below 250 MHz,
set the PLL divider to 2. This allows the user to run the VCO at the 250 to 500 MHz range since the
output is divided by 2.
Interpolation: Sets FIR Interpolation factor: {×2, ×4, ×8, ×16}.
Gain Dig/Analog: Sets the gain of the DDS to ensure that the overall gain is less than or equal to 1
(i.e. no clipping). See the DAC5686 data sheet for more information.
PLLVCO Boost: Increases the Vtol current of the PLL VCO from nominal to 45% in 15% increments.
DAC5686 EVM
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
Physical Description
www.ti.com
2.3.3
DAC A(B) Gain
DAC Coarse Gain: Sets coarse gain of DAC A(B) full scale current. Range is 0 to 15. See the
DAC5686 data sheet for full scale gain equation.
• DAC Fine Gain: Sets fine gain of DAC A(B) full scale current. Range is -128 to 127. See the DAC5686
data sheet for full scale gain equation.
• DAC DCOffset: Sets DAC A(B) DC offset register. Range is -1024 to 1023.
• Sleep: DAC A(B) sleeps when set, operational when cleared.
•
2.3.4
2.3.5
NCO
• NCO DDS: Sets NCO DDS registers. See the DAC5686 data sheet for the formula.
• NCO Phase: Sets initial NCO phase registers. See the DAC5686 data sheet for more information.
Additional Control/Monitor Registers
Pll Port Config: Selection of this button will bring up a separate window that shows the parallel port
configuration of the software. The EVM Menu should be loaded with "DAC EVM".
• Quit: Quits the operation of the DAC5686 software.
• Version: Displays the version of the silicon. If a version of 0 is read then the communication is not
functioning and an error message will be displayed.
•
3
Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM and lists the components
used on the module.
3.1
PCB Layout
The EVM is constructed on a 4-layer, 6.5-inch x 4.7-inch, 0.055-inch thick PCB using FR-4 material.
Figure 5 through Figure 8 show the PCB layout for the EVM.
3.1.1
PCB Layout Recommendations
The DAC5686 clock is sensitive to fast transitions of input data on pins 34, 35, and 36 (DA15, DA14, and
DA13) due to coupling to DVDD pin 32. The noise-like spectral energy of the data line couples into the
DAC clock circuit power pin, resulting in increased jitter. To minimize the jitter, a 10-Ω series resistor along
with a 10-pF capacitor to ground has been added to DVDD pin 32 on the EVM. Pin 32 only draws around
2 mA of current and the 0.02-V voltage drop across the resistor is acceptable for DVDD voltages within
the MINIMUM and MAXIMUM specifications. It is also recommended that the transition rate of the data
input lines be slowed by inserting series resistors near the data source. The optimized value of the series
resistor depends on the capacitance of the trace between the series resistor and the DAC5686 input pin.
For a 2-3 inch trace, a 22-Ω to 47-Ω resistor are recommended.
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
DAC5686 EVM
9
Physical Description
www.ti.com
Figure 5. Top Layer 1
10
DAC5686 EVM
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
Physical Description
www.ti.com
Figure 6. Layer 2, Ground Plane
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
DAC5686 EVM
11
Physical Description
www.ti.com
Figure 7. Layer 3, Power Plane
12
DAC5686 EVM
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
Physical Description
www.ti.com
Figure 8. Bottom Layer
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
DAC5686 EVM
13
Physical Description
3.2
www.ti.com
Parts List
Table 1 lists the parts used in constructing the EVM.
Table 1. DAC5686 EVM Parts List
Bill Of Material For DAC5686
Value
QTY
Part Number
Vendor
Ref Des
Not Installed
CAPACITORS
47 mF, tantalum, 20%, 10 V
6
ECS-T1AD476R
Panasonic
C53–C58
10 mF, 10 V, 20% capacitor
12
ECS-T1AX106R
Panasonic
C24, C26–C28, C30–C32,
C35, C37–C39, C41
1 mF, 16 V, 10% capacitor
6
ECJ-3YB1C105K
Panasonic
C36, C42–C46
0.1 mF, 16 V, 10% capacitor
1
ECJ-2VB1C104K
Panasonic
C21
0.01 mF, 50 V, 10% capacitor
6
ECJ-2VB1H103K
Panasonic
C47-C52
120 pf, 50 V, 5% Capacitor
1
ECJ-1VC1H121J
Panasonic
C33
0.01 mF, 16 V, 10% capacitor
2
ECJ-1VB1C103K
Panasonic
C19, C20
0.1 mF, 16 V, 10% capacitor
3
ECJ-1VB1C104K
Panasonic
C25, C60, C61
0.1 mF, 16 V, +80%, -20% capacitor
21
ECJ-0EF1C104Z
Panasonic
C1, C2, C4–C13, C15–C18,
C29, C59, C84–C86
10 pF, 50 V, ±0.5 pF Capacitor
1
ECU-E1H100DCQ
Panasonic
C3
15000 pF, 16 V, 10% capacitor
1
ECJ-0EB1C153K
Panasonic
C34
0.01 mF, 25 V, 10% capacitor
1
ECJ-0EF1E103Z
Panasonic
C14
120 pF, 50 V, 5% capacitor
1
ECU-V1H121JCV
Panasonic
C33
RESISTORS
10-kΩ resistor 1/16 W, 1%
4
ERJ-6ENF1002V
Panasonic
R34–R37
10-Ω resistor 1/16 W, 1%
1
ERJ-6ENF10R0V
Panasonic
R3
R15
0-Ω resistor, 1/16 W, 1%
2
ERJ-3GEY0R00V
Panasonic
R23, R26
R24, R27–R33
49.9-Ω resistor, 1/16 W, 1%
3
ERJ-3EKF49R9V
Panasonic
R12, R13, R39
R40
127-Ω resistor, 1/16 W, 1%
1
ERJ-3EKF1270V
Panasonic
R25
200-Ω resistor, 1/16 W, 1%
2
ERJ-3EKF2000V
Panasonic
R11, R14
1-kΩ resistor, 1/16 W, 1%
2
ERJ-3EKF1001V
Panasonic
R1, R4
110-Ω resistor, 1/10 W, 1%
0
ERA-3EKF110V
Panasonic
221-Ω resistor, 1/10 W, 1%
0
ERA-3EKF221V
Panasonic
22.1-Ω resistor, 1/10 W, 1%
2
ERJ-3EKF22R1V
Panasonic
R16, R38
10-Ω resistor, 1/16 W, 1%
1
ERJ-2RFK10R0X
Panasonic
R43
100-Ω resistor, 1/10 W, 1%
4
ERA-3EKF100V
Panasonic
R5, R10, R19, R20
Surface Mount Socket strips
1
310-93-164-41105000
Mill-Max
See Note 8
51-Ω resistor pack
4
CTS
See Note 7
BOURNS
RP1–RP4
22-Ω resistor pack
4
4816P-001-220
R18
R17
R21, R22
RP5, RP6, RP9,
RP10
FERRITE BEADS, CONNECTORS, JUMPERS, JACKS, ICs, etc.
MBRB2515L
2
MBRB2515LT4
Ferrite bead
6
EXC-ML32A680U
SMA connectors
8
16F3627
Newark
J2–J6, J11, J18, J19
Black test point
4
5001K
Keystone
TP2–TP5
3POS_header
3
HTSW-150-07-L-S
Samtec
W1–W3
30-pin header
1
HTSW-110-07-L-T
Samtec
J15
34-pin header
2
TSW-117-01-S-DV- Samtec
LC
J13, J14
Red banana jacks
2
ST-351A
J7, J8
14
DAC5686 EVM
OnSemiconduct
or
D1, D2
FB1–FB6
Allied
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
Circuit Description
www.ti.com
Table 1. DAC5686 EVM Parts List (continued)
Bill Of Material For DAC5686
Value
QTY
Part Number
Vendor
Ref Des
Black banana jacks
2
ST-351B
Allied
J9, J10
DAC5686PZP
1
DAC5686IPZP
TI
U1
SN74LVC1G125DBVR
1
SN74LVC1G125D
BVR
TI
U5
SN74HC241PW
1
SN74HC241PW
TI
U4
Transformer
2
T4-1-KK8
Mini-circuit
T1, T2
Transformer
2
TCM4-1W
Mini-circuit
T3, T4
DB25F-RA
1
745536-2
AMP
J1
Mounting screws
2
J1
Nuts
2
J1
Switch
1
4
EVQ-PJX04M
Panasonic
Not Installed
S1
Circuit Description
This chapter describes the circuit functions of the DAC5686 EVM.
4.1
Input Clocks
The initial configuration of this EVM provides transformer-coupled differential clocks from single-ended
input sources. A 300-mVP-P , 0-V offset, 50% duty cycle external square wave is applied to SMA connector
J3 to be used as the data clock input. The signal is converted to a differential clock by transformer T3 and
provides the CLK1 and CLK1C inputs to the DAC5686 device. This input represents a 50-Ω load to the
source. In order to preserve the specified performance of the DAC5686 converter, the clock source should
feature very low jitter. Using a clock with a 50% duty cycle gives optimum dynamic performance.
A 300 mVPP , 0-V offset, 50% duty cycle external square wave is applied to SMA connector J4 to be used
as the DAC sample clock. The signal is converted to a differential clock by transformer T4 and provides
the CLK2 and CLK2C inputs to the DAC5686 device. This input represents a 50-Ω load to the source. In
order to preserve the specified performance of the DAC5686 converter, the clock source should feature
low jitter. Using a clock with a 50% duty cycle gives optimum dynamic performance.
4.2
Input Data
The DAC5686 EVM can accept 1.8-V or 3.3-V CMOS logic level data inputs through the 34-pin headers
J13 and J14 per Table 2 and Table 3. The board provides 50-Ω termination option to ground and series
dampening resistors to minimize digital ringing and switching noise.
Table 2. Input Connector J13 (Data A Bus)
Pin
Description
Pin
Description
1
CMOS data bit 15 (MSB)
18
GND
2
GND
19
CMOS data bit 6
3
CMOS data bit 14
20
GND
4
GND
21
CMOS data bit 5
5
CMOS data bit 13
22
GND
6
GND
23
CMOS data bit 4
7
CMOS data bit 12
24
GND
8
GND
25
CMOS data bit 3
9
CMOS data bit 11
26
GND
10
GND
27
CMOS data bit 2
11
CMOS data bit 10
28
GND
12
GND
29
CMOS data bit 1
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
DAC5686 EVM
15
Circuit Description
www.ti.com
Table 2. Input Connector J13 (Data A Bus) (continued)
Pin
Description
Pin
Description
13
CMOS data bit 9
30
GND
14
GND
31
CMOS data bit 0 (LSB)
15
CMOS data bit 8
32
GND
16
GND
33
17
CMOS data bit 7
34
GND
Table 3. Input Connector J14 (Data B Bus)
Pin
4.3
Description
Pin
Description
1
CMOS data bit 0 (LSB)
18
GND
2
GND
19
CMOS data bit 9
3
CMOS data bit 1
20
GND
4
GND
21
CMOS data bit 10
5
CMOS data bit 2
22
GND
6
GND
23
CMOS data bit 11
7
CMOS data bit 3
24
GND
8
GND
25
CMOS data bit 12
9
CMOS data bit 4
26
GND
10
GND
27
CMOS data bit 13
11
CMOS data bit 5
28
GND
12
GND
29
CMOS data bit 14
13
CMOS data bit 6
30
GND
14
GND
31
CMOS data bit 15 (MSB)
15
CMOS data bit 7
32
GND
16
GND
33
17
CMOS data bit 8
34
GND
Output Data
The DAC5686 EVM can be configured to drive a doubly terminated 50-W cable or provide unbuffered
differential outputs.
4.3.1
Transformer-Coupled Signal Output
The factory-set configuration of the demonstration board provides the user with single-ended output
signals at SMA connectors J5 and J19. The DAC5686 outputs are configured to drive a doubly terminated
50-Ω cable using a 4:1 impedance ratio transformer with the center tap of the transformers connected to
+3.3 VA as shown in Table 4. When using a 1:1 impedance ratio transformer, configure the EVM as
shown in Table 4. The common mode input voltage of T1 and T2 can be adjusted by using the resistor
divider networks.
Table 4. Transformer Output Configuration
Components Installed
1:1 Impedance ratio transformer
R5 (49.9), R10 (49.9), R19 (49.9), R20 (49.9), R21–R23, R26, R24, R27–R33
C60, C61, T1(1:1), T2 (1:1)
4:1 Impedance ratio transformer
R5, R10, R19, R20, R23, R26, C60, C61, T1, T2
(1)
16
(1)
Configuration
Components Not Installed
R21, R22, R24, R27-R33
All component values are per the schematic except where shown in parenthesis.
DAC5686 EVM
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
Circuit Description
www.ti.com
4.3.2
Unbuffered Differential Output
To provide unbuffered differential outputs, the EVM must be configured as follows: remove R21, R22, T1,
and T2; install R5 (24.9), R10 (24.9), R19 (24.9), R20 (24.9), R24, R27-R30, and R32. With a 20 mA
full-scale output current, this configuration provides a 0.5 VPP output.
4.3.3
PLL Lock
With the internal PLL enabled (W3 installed between pins 1 and 2), when the PLL is locked to the CLK1
input, PLLOCK is driven high. With the internal PLL disabled, the PLLLOCK is an output clock that can be
used by external devices to clock the input data to the DAC5686. This signal is the CLK2 signal divided
down by the interpolation rate and phase-aligned to allow the user to clock data into the DAC5686 with the
required setup and hold times.
4.4
Control Inputs
The DAC5686 device has six discrete inputs to control the operation of the device.
4.4.1
Sleep Mode
The DAC5686 EVM provides a means of placing the DAC5686 device into a power-down mode. This
mode is activated by placing a jumper between pins 5 and 6 on header J15.
4.4.2
Reset
The DAC5686 EVM provides a means of resetting the DAC5686 device. Pressing switch S1 or sending
J15 pin 29 low provides an active low reset signal to the DAC5686 device.
4.4.3
Phase Synchronization
The DAC5686 EVM provides a means to phase synchronize the DAC5686 device. Placing an active high
signal on J15 pin 8 (PHSTR) resets the internal NCO accumulator register.
4.4.4
TxENABLE
TxENABLE must be high to enable the DAC5686 process data. When low, the DAC5686 device is forced
to a constant dc output at IOUTA and IOTB. When in the interleaved mode and MEM_QFLAG bit is set to
0, TxENABLE syncronizes the data of channels A and B. When TxENABLE goes high, data present at the
next clock rising edge is treated as I data. The next valid data is then treated as Q data and so on.
TxENABLE is controlled by J15 pin 11.
4.4.5
QFLAG
QFLAG is an input used to indicate Q sample data during the interleaved mode when the QFLAG
interleave bit (3) is set in register #9, MEM_QFLAG. When QFLAG is high, input data is treated as Q data,
and when low, data is treated as I data. QFLAG is controlled by J15 pin 14.
4.4.6
PLL_ON_OFF
PLL_ON_OFF allows the user to disable the PLLLOCK output buffer. When PLL_ON_OFF is high, the
buffer is disabled. When low, the PLLLOCK output signal is present at SMA connector J2.
4.5
Internal Reference Operation
The full-scale output current is set by applying an external resistor (R1) between the BIASJ pin of the
DAC5686 device and ground. The full-scale output current can be adjusted from 20 mA down to 2 mA by
varying R1 or changing the externally applied reference voltage. The full-scale output current, IOUTFS, is
defined as follows:
ǒ
V
IOUT
FS
+ 16
EXTIO
R1
Ǔ
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
DAC5686 EVM
17
Schematic
www.ti.com
where VEXTIO is the voltage at pin EXTIO. This voltage is 1.2 V typical when using the internally provided
bandgap reference voltage source.
4.6
External Reference Operation
The internal reference can be disabled and overridden by an external reference by connecting a voltage
source to terminal TP1 (EXTI/O) and connecting EXTLO to +3.3VA with jumper W1 installed between pins
1 and 2. The specified range for external reference voltages must be observed (see the DAC5686 data
sheet (SLWS147) for details).
5
Schematic
This chapter contains the DAC5686 EVM schematic diagrams.
18
DAC5686 EVM
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
.1uF
10uF
.1uF
C2
10uF
10uF
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
NOTE 1. DO NOT INSTALL
DA(0..15)
C37
+
C39
.1uF
C84
TXENABLE
R40
49.9
+
IOVDD
(Note 1)
TXENABLE
(SH 2)
(SH 2)
.1uF
C4
SDENB
SCLK
SDIO
SDO
.1uF
.1uF
(SH 4) SDENB
(SH 4) SCLK
(SH 4) SDIO
(SH 4) SDO
C1
+
C38
+1.8VD
C29
DA4
DA3
DA2
DA1
DA0
DA7
DA6
DA5
C17
.1uF
DA12
DA11
DA10
DA9
DA8
.1uF
C6
.1uF
C59
.1uF
.1uF
DA15
DA14
DA13
.1uF
C5
C86
C85
C24
10
R43
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
+1.8VD
10uF
+
+3.3VA
W1
(2-3)
DVDD
DGND
SDENB
SCLK
SDIO
SDO
DVDD
TXENABLE
DA15
DA14
DA13
DVDD
DGND
DA12
DA11
DA10
DA9
DA8
DVDD
DGND
IOVDD
IOGND
DA7
DA6
DA5
.1uF
C7
+3.3VA
1
3
2
+3.3VA
R1
.1uF
C16
1K
DAC5687
U1
+
C41
10uF
+3.3VCLK
10pF
C3
.1uF
C13
R16
CLK1
CLK1C
CLK2
CLK2C
.01uF
C14
CLK1
CLK1C
CLK2
CLK2C
+3.3VPLL
22.1
(SH 3)
(SH 3)
.1uF
C25
+3.3VA
QFLAG
C26
221
(Note 1)
DB7
DB6
DB5
DB12
DB11
DB10
DB9
DB8
R17
PHSTR
10uF
+
C9
.1uF
DB15
DB14
DB13
S1
C10
.1uF
SW-PB
SLEEP
DB4
DB3
DB2
DB1
DB0
1K
R4
IOVDD
.033uF
C34
330pF
C33
(SH 3)
+1.8VD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
.1uF
C8
(SH 3)
93.1
R25
DVDD
DGND
QFLAG
TESTMODE
SLEEP
/RESETB
PHSTR
DGND
DB15
DB14
DB13
DVDD
DGND
DB12
DB11
DB10
DB9
DB8
DVDD
DGND
IOVDD
IOGND
DB7
DB6
DB5
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AGND
AVDD
AVDD
AGND
IOUTA1
IOUTA2
AGND
AVDD
AGND
AVDD
EXTLO
AVDD
BIASJ
AGND
EXTIO
AVDD
AGND
AVDD
AGND
IOUTB2
IOUTB1
AGND
AVDD
AVDD
AGND
DA4
DA3
DA2
DA1
DA0
DVDD
DGND
CLKGND
CLK1
CLK1C
CLKVDD
CLK2
CLK2C
CLKGND
PLLGND
LPF
PLLVDD
DVDD
DGND
PLLLOCK
DB0
DB1
DB2
DB3
DB4
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
C15
R39
49.9
4
2
6
1
U5
GND
OE
VDD/3.3V
(SH 2)
(SH 2)
1Y3
1Y2
1Y1
1Y0
(SH 2)
CDCV304
CLKIN
R18
110
(Note 1)
+3.3VA
SLEEP
PHSTR
(SH 2)
(Sh 2)
QFLAG
49.9
R13
C12
.1uF
RESET
DB(0..15)
.1uF
C18
IOVDD
R12
49.9
C11
.1uF
RESET
8
7
5
3
0
R38
22.1
R2
100
R5
TP6
100
R19
1
100
R10
+3.3VA
J2
SMA
(Note 1)
(Note 1)
(Note 1)
100
R22
100
R20
+3.3VA
100
(Note 1)
R21
2
3
4
5
0
R6
0
R9
R8
+3.3VA
0
R26
R31
0
(Note 1)
(Note 1)
0
(Note 1)
100
R41
R33
0
(Note 1)
0
(Note 1)
R7
0
R23
.1uF
C60
1
2
3
0
T2
0
(Note 1)
R30
.1uF
C40
3
2
1
T1
6
4
1
2
3
1
4
6
1
0
6
4
IOUTB
(Note 1)
R27
T1-6T-KK81
T5
1
T4-1-KK81
R28
0
(Note 1)
R32
R29
0
(Note 1)
0
(Note 1)
T4-1-KK81
R42
+3.3VA
.1uF
C61
+3.3VA
SMA
J6
J19
SMA
1
SMA
J18
1
R24
0
(Note 1)
2
3
4
5
2
3
4
5
2
3
4
5
IOUTA
J5
SMA
J11
SMA
2
3
4
5
2
3
4
5
+3.3VA
www.ti.com
Schematic
Figure 9. Schematic - Page 1
DAC5686 EVM
19
NOTE 1. DO NOT INSTALL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
34PIN_IDC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
J14
DATA PORT 2
34PIN_IDC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
J13
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RP5
Copyright © 2004–2010, Texas Instruments Incorporated
(Note 1)
RP9
51
(Note 1)
51
1
(Note 1)
51
RP6
10
9
8
7
6
5
4
3
2
10
9
8
7
6
5
4
3
2
(Note 1)
51
RP10
10
9
8
7
6
5
4
3
2
DAC5686 EVM
1
20
1
10
9
8
7
6
5
4
3
2
DATA PORT 1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RP3
22
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RP4
22
22
16
15
14
13
12
11
10
9
RP2
RP1
22
1
2
3
4
5
6
7
8
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DA15
DA14
DA13
DA12
DA11
DA10
DA9
DA8
DB(0..15)
DA(0..15)
(SH 1)
(SH 1)
2
18
21
24
27
30
16
19
22
25
28
29
26
23
20
17
14
11
8
5
9
15
13
6
12
10
3
4
7
1
RESET
QFLAG
TXENABLE
PHSTR
SLEEP
IOVDD
3 ROW 30 PIN CONNECTOR
J15
PHSTR
SLEEP
RESET
QFLAG
(SH 1)
(SH 1)
(SH 1)
(SH 1)
(SH 1, 5)
TXENABLE
Schematic
www.ti.com
Figure 10. Schematic - Page 2
SLWU006F – December 2004 – Revised August 2010
1
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
NOTES:
1. PART NOT INSTALLED
CLK2
J4
SMA
5
4
3
2
5
4
3
2
CLK1
J3
SMA
1
1
.01uF
C20
.01uF
C19
4
6
6
4
TCM4-1W
T4
TCM4-1W
T3
3
2
1
1
2
3
200
R11
200
R14
CLK2C
CLK2
CLK1C
CLK1
CLK2C
CLK2
CLK1C
CLK1
(SH 1)
(SH 1)
(SH 1)
(SH 1)
www.ti.com
Schematic
Figure 11. Schematic - Page 3
DAC5686 EVM
21
22
DAC5686 EVM
NOTE 1. DO NOT INSTALL
SDEN
SCLK
SDIO
OE_
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
J1
DB25F-RA
10K
10K
10K
R35
R36
R37
R3
10
(Note 1)
R15
10
10K
R34
7
13
11
9
5
3
1
GND
6A
5A
4A
3A
2A
1A
6Y
5Y
4Y
3Y
2Y
1Y
VCC
U2
SN74HCT14
1
1A
13
12
7
9
11
10
5
3
GND
6A
5A
4A
3A
2A
6Y
5Y
4Y
3Y
2Y
1Y
VCC
14
12
10
8
6
4
2
.1uF
.1uF
U3
SN74HCT14
C23
+3.3V_SER
C22
8
6
4
2
14
+3.3V_SER
10
17
15
13
11
8
6
4
2
1
GND
2A4
2A3
2A2
2A1
1A4
1A3
1A2
1A1
OE1_
U4
SN74HC241
2Y4
2Y3
2Y2
2Y1
1Y4
1Y3
1Y2
1Y1
OE2
VCC
3
5
7
9
12
14
16
18
19
20
+3.3V_SER
C21
SDO
SDENB
SCLK
SDIO
.1uF
SDIO
SDO
SDENB
SCLK
(Sh 1)
(Sh 1)
(Sh 1)
(Sh 1)
Schematic
www.ti.com
Figure 12. Schematic - Page 4
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
NOTES:
1. PART NOT INSTALLED
J10
BLACK
RED
MBRB2515L
VD
J8
VD
MBRB2515L
J9
BLACK
RED
VA
1
1
D1
D2
3
3
J7
10uF
+ C30
10uF
+ C27
FB3
FB1
4
4
1uF
C43
1uF
C36
0.01uF
C49
C53
47 uF
+
C55
47 uF
+
+1.8VD
0.01uF
C47
+3.3VA
TP2
BLACK
TP3
BLACK
+1.8VD
(1-2)
1
3
SLWU006F – December 2004 – Revised August 2010
Copyright © 2004–2010, Texas Instruments Incorporated
TP4
BLACK
(2-3)
W3
2
+3.3VA
W2
2
+3.3VA
1
3
VA
C44
C50
C57
47 uF
+
0.01uF
C58
47 uF
+
+3.3VCLK
0.01uF
C51
1uF
TP5
BLACK
C56
47 uF
+
+3.3VPLL
10uF
1uF
C45
0.01uF
C52
1uF
C54
47 uF
+
+3.3V_SER
0.01uF
C48
C46
FB6
FB5
FB4
1uF
C42
IOVDD
+ C35
VA
10uF
+ C32
10uF
+ C31
VA
10uF
+ C28
FB2
www.ti.com
Schematic
Figure 13. Schematic - Page 5
DAC5686 EVM
23
EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have
electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental
measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does
not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling
(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER
AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY
INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or
services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or
safety programs, please contact the TI application engineer or visit www.ti.com/esh.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio
frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are
designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may
be required to correct this interference.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2009, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 1.8 V to 3.3 V and the output voltage range of 3.3 V max.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions
concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 60°C. The EVM is designed to operate
properly with certain components above 60°C as long as the input and output ranges are maintained. These components include but are
not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified
using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2009, Texas Instruments Incorporated
IMPORTANT NOTICE
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DLP® Products
www.dlp.com
Communications and
Telecom
www.ti.com/communications
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
www.ti.com/clocks
Consumer Electronics
www.ti.com/consumer-apps
Interface
interface.ti.com
Energy
www.ti.com/energy
Logic
logic.ti.com
Industrial
www.ti.com/industrial
Power Mgmt
power.ti.com
Medical
www.ti.com/medical
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
www.ti.com/video
Wireless
www.ti.com/wireless-apps
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Copyright © 2010, Texas Instruments Incorporated
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