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Texas Instruments DAC8801/11EVM (Rev. A) User guides
User's Guide
SLAU151A – January 2005 – Revised November 2009
DAC8801/11EVM
This user guide describes the DAC8801/11 Evaluation Module. It covers the operating procedures and
characteristics of the EVM board along with the supported device. The physical printed circuit board (PCB)
layout, schematic diagram, and circuit descriptions are included.
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Contents
Information About Cautions and Warnings .............................................................................. 2
Related Documentation from Texas Instruments ....................................................................... 2
Questions About This or Other Data Converter EVMs ................................................................. 2
EVM Overview ............................................................................................................... 2
PCB Design and Performance ............................................................................................ 4
EVM Operation .............................................................................................................. 8
Jumper Setting ............................................................................................................. 11
Schematic .................................................................................................................. 12
Using the DAC8811EVM with DXP ..................................................................................... 12
Bill of Materials ............................................................................................................. 17
List of Figures
1
DAC8801/11EVM Block Diagram ......................................................................................... 4
2
Top Silkscreen............................................................................................................... 5
3
Layer 1 (Top Signal Plane) ................................................................................................ 6
4
Layer 2 (Ground Plane) .................................................................................................... 6
5
Layer 3 (Power Plane)
6
Layer 4 (Bottom Signal Plane) ............................................................................................ 7
7
Bottom Silkscreen ........................................................................................................... 7
8
INL and DNL Characterization Plot for the DAC8811 .................................................................. 8
9
DAC8801/11EVM Default Jumper Setting ............................................................................... 9
10
MMB0 with DAC8811EVM Installed
11
Loading a DAC8811EVM Configuration ................................................................................ 15
12
DAC8811EVM: Frequency/Amplitude and Update Rate Adjustments
13
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....................................................................................
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DAC Output Update Options .............................................................................................
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List of Tables
1
DAC8801/11EVM Factory Default Jumper Setting ..................................................................... 9
2
Unity Gain Output Jumper Settings ..................................................................................... 10
3
Gain of Two Output Jumper Settings ................................................................................... 10
4
Jumper Settings for a Gain of Five With Inverted Output ............................................................ 11
5
Jumper Setting Function .................................................................................................. 11
6
Output Update Features .................................................................................................. 17
7
Parts Lists .................................................................................................................. 17
TMS320 is a trademark of Texas Instruments.
Microsoft, Windows are registered trademarks of Microsoft Corporation.
LabVIEW is a registered trademark of National Instruments.
All other trademarks are the property of their respective owners.
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1
Information About Cautions and Warnings
1
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Information About Cautions and Warnings
This manual contains cautions and warnings.
CAUTION
This is an example of a CAUTION statement.
A CAUTION statement describes a situation that could potentially damage this
EVM board or your software or equipment.
WARNING
This is an example of a WARNING statement.
A WARNING statement describes a situation that could potentially
cause HARM to you.
The information in a caution or a warning is provided for your protection. Read each caution and warning
carefully.
2
Related Documentation from Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas Instruments Literature Response
Center at (800) 477-8924 or the Product Information Center (PIC) at (972) 644-5580. When ordering,
identify this manual by its title and literature number. Updated documents can also be obtained through
our website at www.ti.com.
Related Documentation
3
Data Sheets
Literature Number
DAC8801
SLAS403
DAC8811
SLAS411
OPA277/2277
SBOS079
INA105
SBOS145
REF102
SBVS022A
Questions About This or Other Data Converter EVMs
If you have questions about this or other Texas Instruments Data Converter evaluation modules, please
feel free to e-mail the Data Converter Application Team at dataconvapps@list.ti.com. Include in the
subject heading the product you have questions or concerns with.
4
EVM Overview
This section provides an overview of the DAC8801/11 evaluation module (EVM), and instructions on
setting up and using this evaluation module.
4.1
Features
This EVM features the DAC8801/11 multiplying digital-to-analog converter (MDAC). It provides a quick
and easy way to evaluate the functionality and performance of the high resolution serial input MDAC. The
EVM provides the serial interface header to easily attach to any host microprocessor or TI TMS320™ DSP
family base system for communication.
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EVM Overview
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4.2
Power Requirements
The following sections describe the power requirements of this EVM.
4.2.1
Supply Voltage
The dc power supply for the digital section (VDD) of this EVM is dedicated to 5 V via the J3-1 terminal or
J6-10 terminal and is referenced to ground through the J3-2 and J6-5 terminals respectively.
The dc power supply requirements for the analog section of this EVM are as follows; the VCC and VSS are
typically ±15 V but can range from ±4.5 V minimum to ±18 V maximum and connect through J1-3 and
J1-1 respectively, or through J6-1 and J6-2 terminals. The 5VA connects through J6-3 and the -5VA
connects through J6-4. All of the analog power supplies are referenced to analog ground through J1-2 and
J6-6 terminals.
The VCC supply sources the positive rail of the external output amplifier, U4A as well as the
current-to-voltage converter amplifier, U5. The supply for the voltage reference circuit composed of U2, U3
and U4B also uses VCC. The negative rail of U4 and U5 is supplied by VSS, though U4 can also be
selected to be connected to AGND via W5 jumper. The external output amplifier is installed as an option
to provide output signal conditioning or for other output configurations desired
CAUTION
To avoid potential damage to the EVM board, make sure that the correct cables
are connected to their respective terminals as labeled on the EVM board.
Stresses above the maximum listed voltage ratings may cause permanent
damage to the device.
4.2.2
Reference Voltage
The externally generated ±10-VDC precision voltage reference is jumper selectable via W1. Either 10 V or
–10 V can be applied to the DAC8801/11 reference input if the onboard dc source is selected. The
external reference voltage source is supplied by the REF102, which is a 2.5 ppm/°C with excellent line
regulation and stability. The -10-V reference is created by using the INA105. The ±10-VDC reference
provides the DAC8801/11 voltage output range. An external reference source of up to ±15 VAC can be
applied to the reference input via TP1 if an ac source is desired.
4.3
EVM Basic Functions
This EVM is designed primarily as a functional evaluation platform to test certain functional characteristics
of the DAC8801/11 MDAC. Functional evaluation of the installed MDAC device can be accomplished with
the use of any microprocessor, TI DSP or some sort of a signal/waveform generator.
The headers J2 and P2 are the connectors provided to allow the control signals and data required to
interface a host processor or waveform generator to the DAC8801/11EVM using a custom built cable.
The MDAC output can be monitored through the J4 header connector. In addition, the MDAC output (via
U5) can be connected to the output operational amplifier, U4A, by using a jumper across pins 5 and 6 or
pins 7 and 8 of J4 header. The output operational amplifier, U4A, is configurable through J5, W5 and W15
for any desired waveform characteristic.
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PCB Design and Performance
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A block diagram of the DAC8801/11EVM is shown in Figure 1.
VCC
VCC
GND
(J1)
VSS
VDD
VSS
(J3)
(J6)
GND
VDD
(P6)
RF102
TP7
+5VA
+VREF
+3.3VD
VCC
TP1
−VREF
INA105
W1
FSX
VREF
U5
TP6
DAC Out
Output
Buffer
Module
TP5
VDD
(J2)
W3
(J4)
IOUT
(P4)
DAC Module
SDI
(P2)
CLK
J5
RFB
AGND
CS
W15
W5
VSS
Figure 1. DAC8801/11EVM Block Diagram
5
PCB Design and Performance
This section covers the layout design of the PCB describing the physical and mechanical characteristics of
the EVM. It shows the resulting performance of the EVM, which can be compared to the device
specification listed in the data sheet.
5.1
PCB Layout
The DAC8801/11EVM is designed to demonstrate the performance quality of the installed MDAC device
under test, as specified in the data sheet. Careful analysis of the EVM physical restrictions and factors that
contributes to the EVM performance degradation is the key to a successful design implementation. The
obvious attributes that contributes to the poor performance of the EVM can be avoided during the
schematic design phase by properly selecting the right components and designing the circuit correctly.
The circuit should include adequate bypassing, identifying and managing the analog and digital signals
and knowing or understanding the components mechanical attributes.
A critical part to any design lies in the layout process. Placement of components and the proper routing of
signals can greatly improve the performance of the overall system. Bypass capacitors should be placed as
closely as possible to the pins and the analog and digital signals should be properly separated from each
other. The power and ground planes are very important and should be carefully considered in the layout
process. A solid plane is ideally preferred but sometimes impractical, so when solid planes are not
possible, a split plane will do the job. When considering a split plane design, analyze the component
placement and carefully split the board into its analog and digital sections starting from the device under
test. The ground plane plays an important role in controlling the noise and other effects that otherwise
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contributes to the error of the MDAC output. To ensure that the return currents are handled properly, route
the appropriate signals only in their respective sections, meaning the analog traces should only lay directly
above or below the analog section and the digital traces in the digital section. Minimize the length of the
traces but use the biggest possible trace width allowable in the design. These design practice discussed
can be seen in the following figures.
The DAC8801/11EVM board is constructed on a four-layer printed-circuit board using a copper-clad FR-4
laminate material. The printed-circuit board has a dimension of 43,1800 mm (1.7000 inch) × 82,5500 mm
(3.2000 inch), and the board thickness is 1,5748 mm (0.0620 inch). Figure 2 through Figure 6 show the
individual artwork layers.
Figure 2. Top Silkscreen
Figure 3. Layer 1 (Top Signal Plane)
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Figure 4. Layer 2 (Ground Plane)
Figure 5. Layer 3 (Power Plane)
6
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Figure 6. Layer 4 (Bottom Signal Plane)
Figure 7. Bottom Silkscreen
5.2
EVM Performance Results
The EVM performance test is performed using a high density DAC bench test board, an Agilent 3458A
digital multimeter and a PC running the LabVIEW® software. The EVM board is tested for all codes of the
device under test (DUT) and is allowed to settle for 1 ms before the meter is read. This process is
repeated for all codes to generate the measurements for INL and DNL results.
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EVM Operation
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The result of the DAC8801/11EVM characterization test is shown in Figure 8. Note that the DAC8811
uses the OPA277 for the I-to-V conversion.
Figure 8. INL and DNL Characterization Plot for the DAC8811
6
EVM Operation
This section covers in detail the operation of the EVM to provide guidance to the user in evaluating the
onboard MDAC and how to interface the EVM to a host processor.
See the specific MDAC data sheet, as listed in the Related Documentation from Texas Instruments
section of this user guide (Section 2), for more information about the MDAC serial interface and other
related topics.
The EVM board is factory tested and configured to operate in the bipolar output mode.
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6.1
Factory Default Setting
The EVM board is set to its default configuration from factory as described in Table 1 to operate in
unipolar voltage output operation. The default jumper settings below are shown in Figure 9.
Table 1. DAC8801/11EVM Factory Default Jumper Setting
Reference
Jumper
Position
W1
2-3
Routes +10V reference source to the MDAC VREF input.
W2
1-2
MDAC Chip Enable is driven by CS via J2-1.
W3
1-2
MDAC IOUT is connected to the I-to-V converter, U5.
Negative supply rail of U4A operational amplifier is sourced by VSS.
Function
W5
1-2
W15
OPEN
U4A operational amplifier configuration is set for 5x gain.
W25
OPEN
Chip Enable is disconnected from GND so that the control signal from W2 is allowed to drive this pin.
J4
J5
1-2
Tie RFB to MDAC VOUT .
7-8
MDAC VOUT connected to J5 header via RC filter.
1-2
MDAC VOUT is routed to the inverting input of U4A.
3-4
Noninverting input of U4A tied to AGND.
Figure 9. DAC8801/11EVM Default Jumper Setting
6.2
Host Processor Interface
The host processor drives the MDAC, so the MDACs proper operation depends on the successful
configuration between the host processor and the EVM board. In addition, a properly written code is also
required to operate the MDAC.
A custom cable can be made specific to the host interface platform. The EVM allows interface to the host
processor through J2 header connector for the serial control signals and the serial data input. The output
can be monitored through the J4 header connector.
An interface adapter card is also available for specific TI DSP starter kit as well as an MSP430 based
microprocessor as mentioned in Section 4 of this manual. Using the interface card alleviates the tedious
task of building customize cables and allows easy configuration of a simple evaluation system.
This MDAC EVM interfaces with any host processor capable of handling serial communication protocols or
the popular TI DSP. For more information regarding the serial interface of the particular MDAC installed,
refer to the specific MDAC data sheet, as listed in the Related Documentation from Texas Instruments
section (Section 2) of this user guide.
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EVM Operation
6.3
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The Output Operational Amplifiers
The EVM includes operational amplifiers for various applications. The U5 operational amplifier is used to
convert the current output of the MDAC to voltage output. Though the option of voltage output is
implemented, the current output, IOUT, can still be monitored through J4 output header, via pins 12, 14,
and 16.
The footprint of U5 is very common for most operational amplifiers; therefore, it is easy to find an
operational amplifier that suits each specific application.
The following sections describe the different configurations of the output amplifier, U4A. This additional
operational amplifier can be used to serve as buffer to unload the I-to-V circuit of the MDAC. It can also be
used for different signal conditioning and amplification purposes desired. The EVM comes configured with
the U4A operational amplifier set to a gain of five configuration. If a gain of two is desired, the inverting
input of U4A can be tied to AGND (via W15) to achieve this specific configuration. In addition, the inverting
input of U4A can also be connected to the MDAC voltage output (by shorting pins 1 and 2 of the J5
header) or to any voltage source through J5-1.
This buffering circuit may present some slight distortion because of the feedback resistor and capacitor. If
this is the case, the user can easily configure the feedback circuit to closely match their desired wave
shape by simply removing R6 and C12 and replacing it with the proper values. Additionally, C12 can be
removed altogether and R6 can be replaced with a 0-Ω resistor if desired.
6.3.1
Unity Gain Output
Table 2 shows the jumper setting for the unity gain configuration of the MDAC output buffer in unipolar or
bipolar supply mode.
Table 2. Unity Gain Output Jumper Settings
Jumper Setting
6.3.2
Reference
Unipolar
Bipolar
J5
2-3
2-3
Function
W15
OPEN
OPEN
Disconnect the inverting input of operational amplifier, U4A, from AGND.
W5
2-3
1-2
Negative rail of operational amplifier is tied to AGND or powered by VSS.
Routes the MDAC output to the noninverting terminal of the U4A.
Gain of Two Output Jumper Settings
Table 3 shows the proper jumper settings of the EVM for the 2× gain output of the MDAC.
Table 3. Gain of Two Output Jumper Settings
Jumper Setting
10
Reference
Unipolar
Bipolar
J5
2-3
2-3
W15
CLOSED
CLOSED
W5
2-3
1-2
DAC8801/11EVM
Function
Routes the MDAC output to the noninverting terminal of the U4A.
Inverting input of the output operational amplifier, U4A, is connected to AGND to set for a
gain of 2.
Supplies power, VSS, to the negative rail of operational amplifier, U4A, for bipolar supply
mode, or ties it to AGND for unipolar supply mode.
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6.4
Output Gain of Five With MDAC VOUT Inverted
Table 4 shows the proper jumper settings of the EVM to achieve a gain of five with the output of the
MDAC inverted.
Table 4. Jumper Settings for a Gain of Five With Inverted Output
Jumper Setting
7
Reference
Unipolar
Bipolar
Function
J5
1-2 and 3-4
1-2 and 3-4
Output of MDAC is inverted with a gain of 5. Watch for clipping in unipolar mode due to
operational amplifier headroom issue.
W15
OPEN
OPEN
W5
2-3
1-2
Disconnect the inverting input of operational amplifier, U4A, from AGND.
Supplies power, VSS, to the negative rail of operational amplifier, U4A, for bipolar
supply mode, or ties it to AGND for unipolar supply mode.
Jumper Setting
Table 5 shows the function of each specific jumper setting of the EVM.
Table 5. Jumper Setting Function
Reference
W1
W2
Jumper
Setting
Function
1
3
1
3
1
3
Routes the +10-V reference to MDAC VREF pin.
1
3
Chip Enable pin driven by CS pin, J2-1.
1
3
1
3
Routes the –10-V reference to MDAC VREF pin.
Disconnect the onboard external reference and use desired source of reference via TP1.
Enable chip via W25 jumper.
Chip Enable pin driven by FSX pin, J2-7.
Disconnect the IOUT from the I-to-V amplifier circuit.
W3
Routes the IOUT to the I-to-V amplifier circuit.
1
3
Negative supply rail of the output operational amplifier, U4A, is powered by VSS for bipolar
operation.
1
3
Negative supply rail of the output operational amplifier, U4A, is tied to AGND for unipolar
operation.
W5
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Schematic
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Reference
Jumper
Setting
Function
Disconnect the inverting input terminal of U4A from ground.
W15
Connect the inverting input terminal of U4A from ground.
Chip Enable pin is driven via W2 jumper with either CS pin on J2-1 or FSX pin on J2-7.
W25
Chip Enabled and is always active.
Jumper pins 1-2 or pins 3-4 together to connect the feedback resistor, RFB, to the output of U5.
J4
Jumper pins 5-6 or pins 7-8 together to connect the MDAC VOUT to J5 header via the RC filter.
MDAC VOUT is routed to the inverting input of U2.
MDAC VOUT is routed to the non-inverting input of U2.
J5
The noninverting input of U2 is tied to AGND.
MDAC VOUT is routed to the inverting input of U2 and the noninverting input of U2 is tied to
AGND.
Legend:
8
Indicates the corresponding pins that are shorted or closed.
Schematic
The schematic for the DAC8801/11EVM PCB is appended to this document.
9
Using the DAC8811EVM with DXP
The DAC8811EVM is compatible with the DAC eXerciser Program (DXP) from Texas Instruments. DXP is
a tool that can generate the necessary control signals required to output various signals and waveforms
from the device installed on the DAC8811EVM. The DAC8811EVM-PDK kit combines the DAC8811EVM
board with the DSP based modular motherboard MMB0. The kit includes the DXP software for evaluation
using any available USB port on a Microsoft® Windows® XP-based computer.
DXP is a program for controlling the digital input signals such as the clock, CS, and SDI. Wave tables are
built into the DSP software to allow sine, ramp, triangle, and square wave signals to be generated by the
DAC8811. Straight dc outputs can also be obtained.
The DAC8811EVM-PDK uses the DSP-based MMB0 to control the DAC EVM through the DXP software.
For complete information about installing and configuring DXP, see the DXP User's Guide, available for
download from the TI web site. This section covers the specific operation of the DAC8811EVM-PDK.
9.1
Hardware
The hardware consists of two primary components: the DAC8811EVM itself and a modular motherboard
called the MMB0. The MMB0 board houses a TMS320VC5507 DSP that controls the serial interface to the
device loaded on the EVM board.
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The hardware must be configured such that the DAC8811EVM is plugged onto the MMB0 aligning female
connectors J4, J2 and J6 (on the bottom side of the DAC8811EVM) with male connectors J7, J4 and J5
on the MMB0. The assembled hardware is shown in Figure 10.
CAUTION
Use caution when assembling the boards. It is possible to misalign the
connectors and damage both the EVM and the motherboard.
CAUTION
DO NOT connect the MMB0 to your PC before installing the DXP software as
described in the DXP User’s Guide. Installing the software first ensures that the
necessary drivers are properly loaded to run the hardware.
Figure 10. MMB0 with DAC8811EVM Installed
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MMB0 Power Supplies
Several power connections are required for the hardware to work properly. For the MMB0, the supplied
6-V ac/dc converter is all that is necessary. Be sure that J12 on the MMB0 board is closed before
connecting the ac/dc adapter to the DC In connector of the MMB0. This supply provides all power to the
digital portion of the DAC8811EVM as well as all necessary power for the DSP. Clean, well-regulated
analog power for the DAC8811EVM should be supplied externally via J14, a six-position screw terminal
mounted in the lower left corner of the MMB0 board.
CAUTION
When using external power supplies applied to J14 on the MMB0, please
ensure all shorting blocks from J13 are completely removed. Permanent
damage to the MMB0 may occur otherwise.
From left to right, the J14 screw terminal connections are –VA, +VA, +5VA, –5VA, +5VD, and GND. The
5V from the ac/dc adapter can be connected to the +VA or the +5VA by installing a jumper across JP13A
or JP13B. If the jumpers are not installed, the analog VSS, VCC, +5VA, and –5VA may be applied directly to
the –VA, +VA, +5VA, and –5VA screw terminals at J14 on the MMB0 (referenced to the GND
terminal).The DAC8811 board power requirements are described in Section 4.2 of this manual.
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9.3
Software: Running DXP
Install DXP on a laptop or personal computer running Windows XP as shown in the detailed instructions in
the DXP User's Guide (TI document SBAU146). Run the DXP program by clicking on the DXP icon on
your desktop, or by browsing to your installation directory.
Before you can generate signals with DXP, a DAC EVM configuration file must be loaded. To load a
configuration file, select the desired DAC from the configuration list under the DAC menu, as Figure 11
illustrates. Choose the DAC configuration file for the device installed on the EVM.
Figure 11. Loading a DAC8811EVM Configuration
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The DXP software defaults to output a 1-kHz sine wave from the DAC. Other waveform options include
square, sawtooth, triangle, and dc output options, as described in the DXP User's Guide. The frequency
and amplitude of the output waveform are controlled by sliders on the DXP software interface. The DAC
update rate can also be modified, as shown in Figure 12.
Figure 12. DAC8811EVM: Frequency/Amplitude and Update Rate Adjustments
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9.4
DAC Output Update Options
The DXP software also allows the user to choose several DAC output update options, as Figure 13
shows.
Figure 13. DAC Output Update Options
Table 6 lists the details on these options.
Table 6. Output Update Features
Options
Detailed Description
Frame Sync
The DXP software defaults to Frame Sync. The Frame Sync output of the MMB0
connects to the SYNC input of the DAC88811. The DAC output changes to the
corresponding level when the DAC latch is updated via SDI. Ensure the shunt jumper
on W6 is covering pins 2-3 (default is 1-2) to use this feature.
Latch with DSP Timer
N/A
Latch with External Timer
N/A
Update Rate
10
User input; enter the desired DAC update rate. 1MSPS is the default
Bill of Materials
Table 7. Parts Lists
(1)
(2)
(3)
Item #
Qty
Designator
1
3
C8 C9 C10
TDK
C3216COG2A103KT
0.01µF, 1206 Multilayer ceramic capacitor
2
6
C1 C2 C5 C7
C11 C13
TDK
C3216COG1E104KT
0.1µF, 1206 Multilayer ceramic capacitor
3
1
C12
TDK
C3216COG2A102KT
1 nF, 1206 Multilayer ceramic capacitor
4
2
C4 C6
TDK
C3225X7R1E106KT
10 µF, 1210 Multilayer ceramic X5R capacitor
5
1
C3
TDK
C3216X7R1E471KT
470 pF, 50V, 1206 Multilayer ceramic capacitor SMD
6
4
R1 R2 R3 R5 (1)
Panasonic
ERJ-8GEY0R00V
0 Ω, 1/4W 1206 chip resistor
7
1
R10
Panasonic
ERJ-8ENF2002V
20 kΩ, 1/4W 1206 chip resistor
8
1
R4
Panasonic
ERJ-8GEYJ101V
100 Ω, 1/4W 1206 chip resistor
9
1
R8
Panasonic
ERJ-8GEYJ202V
2 kΩ, 5%, 1/4W 1206 chip resistor
10
2
R6 R12
Panasonic
ERJ-8ENF1002V
10 kΩ, 1/4W 1206 chip resistor
11
1
R9
Bourns
3214W-1-203E
20K Potentiometer
12
1
J5
Molex
122-03-2041
4 Position jumper_0.1" spacing
13
1
J6
Samtec
TSM-105-01-T-DV
5×2×0.1 10-pin 3A isolated power socket
14
2
J2 J4
Samtec
TSM-110-01-S-DV-M
10×2×0.1, 20 Pin 0.025"sq SMT socket
15
2
J1 J3 (1)
On-Shore Technology
ED555/3DS
3-Pin terminal connector
16
1
U1 (2)
Texas Instruments
DAC8801E/DAC8811E
14-bit/16-bit, Current output, serial input MDAC
17
1
U2
Texas Instruments
REF102AU
8-SOIC(D) precision reference, +10V
18
5
TP1 TP4 TP5
TP6 TP7
Mill-max
2348-2-01-00-00-07-0
Turret terminal test point
19
2
P2 P4
Samtec
SSW-110-22-S-D-VS-P
20-PIN 0.025"sq SMT terminal strips
(3)
Manufacturer
Part Number
Description
The following parts: J1, J3, R1, R2, and R3 are not installed.
The device installed is specific to the EVM ordered.
P2, P4, and P6 parts are not shown in the schematic diagram. All the P designated parts are installed in the bottom side of the
PCB opposite the J designated counterpart. Example, J2 is installed on the topside while P2 is installed in the bottom side
opposite of J2.
SLAU151A – January 2005 – Revised November 2009
Submit Documentation Feedback
Copyright © 2005–2009, Texas Instruments Incorporated
DAC8801/11EVM
17
Bill of Materials
www.ti.com
Table 7. Parts Lists (continued)
18
Item #
Qty
20
1
P6
Designator
21
3
22
3
23
(3)
Manufacturer
Part Number
Description
Samtec
SSW-105-22-F-D-VS-K
3A Isolated 10-pin power header
W3 W15 W25
Molex
22-03-2021
2 Position jumper_ 0.1" spacing
W1 W2 W5
Molex
22-03-2031
3 Position jumper_ 0.1" spacing
1
R7
Bourns
3214W-1-104E
100K Potentiometer
24
1
U3
Texas Instruments
INA105KU
Unity gain differential amplifier, 8 SOIC
25
1
U4
Texas Instruments
OPA2277UA
Dual high precision operational amplifier, 8SOP(D)
26
1
U5
Texas Instruments
OPA277UA
High precision operational amplifier, 8SOP(D)
DAC8801/11EVM
SLAU151A – January 2005 – Revised November 2009
Submit Documentation Feedback
Copyright © 2005–2009, Texas Instruments Incorporated
1
2
3
4
5
6
Revision History
REV
ECN Number
Approved
VDD
D
C6
10µF
VCC
Note: Replace U5
amplifier with the
desired amplifier that
fits user's application
requirements.
7
3
2
J2
8
SDI
2
SCLK
1
DAC_IOUT
W3
RFB
3
IOUT
5
W2
CE
CS
FSX
7
VDD
SDI
CLK
R2
0
R3
0
CS
SCLK
CLKR
FSX
FSR
SDI
DR
TP4
RFB
IOUT
TP1
EX_VREF
6
GND
IOUT
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
(Max of ±15V AC or DC)
DAC8801/11
OPA277U
Use these terminals for
current output
+
C13
0.1µF
VSS
C
U4B
VCC
Tantalum
-
C1
+
3
10µF -
0.1µF
4
VIN
N/C
N/C
N/C
R5
6
OUT
0
GND
VCC
1
5
TRIM
R7
2
100K
U2
REF102
3
4
R9
20K
REF
NC
-IN
V+
+IN
Output
V-
Sense
8
7
0.01µF
J5
4
3
2
1
-10Vref
INA105
R10
20K
C9
C5
0.1µF
6
5
VCC
TP7
U3
TEMP
C7
0.1µF
W5
C10
DAC_VOUT
+
2K
Note: R8 and C3 are
populated with the
values as indicated.
Replace R8 with 0
ohm jumper resistor
and do not populate
C3 if filtering is not
desired.
+
-
J3
C3
470pF
1
3
5
7
9
B
10K
C12
1nF
2
4
6
8
10
3
2
1
3
VDD
J6
2
VD1
1
-5VA
0.01µF
R6
W15
VSS
VSS
TP6
VSS
VCC
100
OPA2277U
R8
+5VA
TP5
R4
1
2
4X1X.1
B
J1
U4A
3
4
2
+
+10Vref
OPA2277U
1
C4
7
6
7
8
5
+3.3VD VD2
0
W25
W1
4
VREF
R1
8
C
CE
U5
6
1
DAC_VOUT
VOUT
2
4
6
8
10
12
14
16
18
20
Note: R1, R2 and R3
are not populated.
C8
0.01µF
4
1
3
5
7
9
11
13
15
17
19
C2
0.1µF
U1
C11
0.1µF
5
J4
D
R12
10K
VSS
VCC
VDD
VD2
ti
A
A
12500 TI Boulevard. Dallas, Texas 75243
Title:
Engineer:
J. PARGUIAN
DAC8801/11
DOCUMENTCONTROL #
Drawn By:
FILE:
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DAC88x1_RevA.Sch
DATE:
10-Jan-2005
6461221
SIZE:
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REV:
SHEET:
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OF:
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It is important to operate this EVM within the input voltage range of +4.5 V to +18 V and the output voltage range of ±10 V.
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Copyright © 2009, Texas Instruments Incorporated
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