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Texas Instruments TSW3000 Demo Kit (Rev. B) User guides
TSW3000 Demo Kit
User's Guide
November 2005
SLWU013B
TSW3000 Demo Kit
User's Guide
Literature Number: SLWU013B
March 2004 – Revised November 2005
Contents
1
2
3
4
5
6
7
8
Demo Kit Configuration Options ................................................................................... 7
1.1
DAC Component .................................................................................................... 7
1.2
VComm Configuration .............................................................................................. 7
1.3
VCXO ................................................................................................................. 7
1.4
VCO
10
7
2.1
System Block Diagram ............................................................................................. 9
2.2
Demo Kit Block Diagram ........................................................................................... 9
Key Texas Instruments Components ........................................................................... 10
3.1
CDCM7005 ......................................................................................................... 10
3.2
DAC5687 ........................................................................................................... 10
3.3
TRF370x ............................................................................................................ 10
3.4
TRF3750............................................................................................................ 10
Software Installation .................................................................................................. 10
Software Operation .................................................................................................... 10
5.1
CDCM7005 Software ............................................................................................. 11
5.2
TRF3750 Software ................................................................................................ 13
5.3
DAC5687 Software ................................................................................................ 14
5.4
DAC5687 GUI Register Descriptions ........................................................................... 15
Board Setup.............................................................................................................. 17
6.1
Jumper Settings ................................................................................................... 17
6.2
Input/Output Connectors
6.3
Parallel Port ........................................................................................................ 18
6.4
DC Power Requirements ......................................................................................... 18
.........................................................................................
18
Demo Kit Test Configuration....................................................................................... 18
7.1
Test Setup Block Diagram ....................................................................................... 19
7.2
Test Equipment .................................................................................................... 19
7.3
Calibration .......................................................................................................... 19
7.4
Test Specifications ................................................................................................ 19
Basic Test Procedure ................................................................................................. 20
...................................................................................................
8.1
Initial Inspection
8.2
Engage Power Supplies .......................................................................................... 20
8.3
Program the CDCM7005 ......................................................................................... 20
8.4
Program the TRF3750 ............................................................................................ 20
8.5
DAC5687 Program ................................................................................................ 21
8.6
Carrier Suppression ............................................................................................... 21
20
............................................................................................... 23
Optional Configurations ............................................................................................. 25
9.1
External LO ........................................................................................................ 25
9.2
External Reference ................................................................................................ 25
9.3
Monitor DAC Output .............................................................................................. 25
Filter Specifications ................................................................................................... 26
10.1 Baseband Filter .................................................................................................... 26
8.7
9
..................................................................................................................
Block Diagrams .......................................................................................................... 9
Sideband Rejection
SLWU013B – March 2004 – Revised November 2005
Table of Contents
3
11
4
Layers and Schematics .............................................................................................. 26
....................................................................................................
11.1
Bill of Materials
11.2
Layers ............................................................................................................... 30
11.3
Schematics ......................................................................................................... 40
Contents
26
SLWU013B – March 2004 – Revised November 2005
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
System Block Diagram ...................................................................................................... 9
Demo Kit Block Diagram .................................................................................................... 9
TSW3000 Startup Screen ................................................................................................. 11
Default CDCM7005 SPI GUI.............................................................................................. 12
TRF3750 GUI - Main Menu ............................................................................................... 13
TRF3750 GUI - Advanced Menu ......................................................................................... 14
DAC5687 GUI .............................................................................................................. 15
Test System Block Diagram .............................................................................................. 19
Default DAC GUI With fDAC/8 Tone From NCO ........................................................................ 22
Single Sideband Spectrum Output Before DAC Offset and QMC Adjustments ................................... 23
DAC GUI With Typical Settings To Minimize LO and Sideband ..................................................... 24
Sideband and LO ........................................................................................................... 25
Top Layer.................................................................................................................... 30
Top Layer (NH) ............................................................................................................. 31
Layer 2 ....................................................................................................................... 32
Layer 3 ....................................................................................................................... 33
Layer 4 ....................................................................................................................... 34
Layer 4 (NH) ................................................................................................................ 35
Layer 5 ....................................................................................................................... 36
Bottom Layer ................................................................................................................ 37
Bottom Silkscreen .......................................................................................................... 38
Drill Drawing ................................................................................................................ 39
Schematic - Page 1 ........................................................................................................ 40
Schematic - Page 2 ........................................................................................................ 41
Schematic - Page 3 ........................................................................................................ 42
Schematic - Page 4 ........................................................................................................ 43
Schematic - Page 5 ........................................................................................................ 44
Schematic - Page 6 ........................................................................................................ 45
Schematic - Page 7 ........................................................................................................ 46
SLWU013B – March 2004 – Revised November 2005
List of Figures
5
List of Tables
1
2
3
4
5
6
7
6
Frequency Bands ............................................................................................................ 7
CDCM7005 Register Values .............................................................................................. 12
Jumper List .................................................................................................................. 17
Input/Output Connections ................................................................................................. 18
Demo Kit Specifications ................................................................................................... 19
Frequency Designations ................................................................................................... 21
Bill of Materials ............................................................................................................. 26
List of Tables
SLWU013B – March 2004 – Revised November 2005
User's Guide
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
1
Demo Kit Configuration Options
The TSW3000 Demo Kit can be configured in different ways to evaluate different components in different
frequency bands. This section outlines the various component configurations. Based on the configuration,
testing and board setup must be altered to accommodate the given components and features.
1.1
DAC Component
The TSW3000 Demo Kit is built for the DAC5687, although this Demo Kit can also support the DAC5686
since the two devices are pin compatible. The procedures outlined in this document are primarily suited for
the DAC5687, but can be modified easily for the DAC5686 if desired.
1.2
VComm Configuration
The analog quadrature modulator requires a common-mode dc voltage of approximately 3.7 V. In order to
utilize the dc-offset adjustment capabilities of the DAC568x for carrier suppression, it is imperative to
maintain a dc path from the DAC output to the modulator input. The common-mode voltage for the
modulator is maitained with a passive resistor network that is designed to provide the proper operation
point for the DAC568x and the TRF370x modulator. By design, in order to preserve the proper dc levels,
the DAC gain should be kept at maximum (15), though deviation by a few steps is generally acceptable
with no degradation in performance.
1.3
VCXO
The CDCM7005 requires a VCXO source to derive its output clock signals. The VCXO is at reference
designator U10 on the back side of the board. The frequency of the VCXO can be changed to operate the
Demo Kit with different clocking schemes for different modulation standards or for specific customer
requirements. Denote which VCXO frequency is on the board so that the CDCM7005 part can be set up
properly. The following conventions are typically used:
• WCDMA: Derivatives of 61.44 MHz (i.e., 122.88 MHz, 245.76 MHz, 491.52 MHz)
• GSM: Derivatives of 52 MHz (i.e., 104 MHz, 208 MHz)
• CDMA2K: Derivativies of 78.6432 (i.e., 157.2864 MHz, 314.5728 MHz)
1.4
VCO
The VCO outputs the RF signal used for the LO drive on the analog quadrature modulator. The RF output
frequency is contingent on the LO frequency value.
The RF frequency band of the VCO must be noted in order to know how to program the TRF3750 and
where to measure the output RF signal from the modulator. The typical bands of operation are shown in
Table 1.
Table 1. Frequency Bands
FREQUENCY
UMTS
PCS
GSM900
DCS1800
2110-2170 MHz
1930-1990 MHz
935-960 MHz
1805-1880 MHz
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TSW3000 Demo Kit
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Demo Kit Configuration Options
8
TSW3000 Demo Kit
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Block Diagrams
2
Block Diagrams
2.1
System Block Diagram
The basic radio system block diagram in Figure 1 demonstrates where the TSW3000 Demo Kit fits in the
overall transceiver. The dash-line box illustrates the components found on the TSW3000 Demo Kit board.
DAC
TX
LPA
I/Q
Modulator
0°
90°
ANT
Diplexer
I/Q
Demod
A/D
RX
LNA
Figure 1. System Block Diagram
2.2
Demo Kit Block Diagram
The basic Demo Kit block diagram is shown in Figure 2. The shaded boxes illustrate the key Texas
Instruments components found on the TSW3000 Demo Kit board.
DAC5687
TRF370x
16
I
RF
I/Q
Modulator
16
Q
LO
CLK1
CLK2
TRF3750
VCXO
VCO
PLL
CDCM7005
Ref Osc
Figure 2. Demo Kit Block Diagram
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
9
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Key Texas Instruments Components
3
Key Texas Instruments Components
3.1
CDCM7005
The CDCM7005 clock distribution chip is used to generate and synchronize the clock outputs to the
system. The device has five outputs which can be either LVPECL or LVCMOS and can be divided down
by 1, 2, 3, 4, 6, 8, and 16. The divide by 16 can be replaced with a divide by 4 or 8 with a 90 degree
phase shift.
3.2
DAC5687
The DAC5687 is a 16-bit interpolating dual digital-to-analog converter (DAC). The device incorporates a
digital modulator, independent differential offset control, and I/Q amplitude control. The device is typically
used in baseband mode or in low IF mode in conjunction with an analog quadrature modulator.
3.3
TRF370x
The TRF370x is a direct upconvert I/Q modulator. The device accepts differential input voltage at
baseband or low IF frequencies and outputs an RF signal based on the LO drive frequency.
3.4
TRF3750
The TRF3750 is a PLL chip used in the synthesizer section to generate the LO frequency required for the
I/Q modulator.
4
Software Installation
This section summarizes the installation procedures for the software required to operate the Demo Kit.
Once all of the software is loaded, it is recommended to reboot the computer.
• Extract TSW3000-Installv2p0.zip
• Execute setup.exe
5
Software Operation
The following describes the use of the software required to set the TSW3000 Demo Kit in the baseline
configuration for the CDCM7005, TRF3750, and DAC5687. The software should be configured in the
order presented below. The first step requires starting the TSW3000 software. This opens a window as
shown in Figure 3. The tabs on the left side of the window allow selection of different GUI controllers for
the DAC5687, TRF3750, and CDCM7005. The lower left portion of the screen contains links to this user's
guide as well as the data sheets for the DAC5687, TRF3750, and the CDCM7005.
10
TSW3000 Demo Kit
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Software Operation
Figure 3. TSW3000 Startup Screen
5.1
CDCM7005 Software
By using the provided CDCM7005 serial peripheral interface (SPI) software, the user can load settings to
the CDCM7005 internal registers. This must be performed every time the TSW3000 Demo Kit is powered
up, since the CDCM7005 has default settings that are loaded at power up and the settings may be slightly
different than the ones required to operate the Demo Kit. Executing the program brings up the interface
seen in Figure 4. The default settings are correct for a VCXO of 491.52 MHz and a 10 MHz reference as
on the TSW3000. The CDCM7005 GUI allows register settings to be saved and can be loaded back in
afterwards. This can be accomplished with the Save and Load Settings buttons near the right side of the
GUI.
It is recommended that any unused output clocks be tri-stated. In this case the TSW3000 only uses
OUT_MUX_1 to drive the DAC5687. OUT_MUX_0, OUT_MUX_2, OUT_MUX_3, OUT_MUX_4 should be
tri-stated unless there is a need to use the other output clocks.
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Software Operation
Figure 4. Default CDCM7005 SPI GUI
The divider parameters, M and N, are determined according to the following equation based on the
internal reference frequency and internal VCXO frequency.
FREF = (FVCXO× M)/(N × P)
The p parameter is the VCXO input divider and set through the FB_MUX value. The M and N counter
values need to be adjusted depending on the board configuration. The M and N counter registers are
determined by the reference frequency and the VCXO frequency. The OUT_MUX sets the divide ratios for
the individual output clocks. The OUTSEL determines whether the output clocks will be used as
single-ended CMOS or differential LVPECL. With a 10-MHz reference oscillator the CDCM7005 settings
are shown in Table 2 for a variety of common VCXO frequencies. For other frequencies, see to the
CDCM7005 data sheet for more details.
Table 2. CDCM7005 Register Values
12
VCXO Freq. (MHz)
491.52
245.76
122.88
61.44
Divider M
125
125
125
125
Divider N
768
768
768
768
FB_MUX
8
4
2
1
TSW3000 Demo Kit
SLWU013B – March 2004 – Revised November 2005
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Software Operation
5.2
TRF3750 Software
The TRF3750 software is used to program the PLL chip to lock the VCO oto a desired frequency output.
The main menu of the program is shown in Figure 5.
Figure 5. TRF3750 GUI - Main Menu
The options in the front panel allow the user to program the desired frequency of the VCO, the desired
frequency of the PFD, the reference frequency, and the prescaler selection. The software then displays
the actual VCO frequency, PFD frequency and the R, N, A, and B counter values to be programmed into
the TRF3750. Hitting the Send button writes these values to the TRF3750. In default mode on a default
board, only the desired VCO frequency (2100 MHz to 2200 MHz) needs to be changed. For other VCO
ranges, other parameters may need to be changed.
The Advanced Operation button will bring up another user interface as shown in Figure 6.
SLWU013B – March 2004 – Revised November 2005
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Software Operation
Figure 6. TRF3750 GUI - Advanced Menu
This menu allows control of more register settings. For details on these settings, see the TRF3750 data
sheet (SLWS146). The register of interest in this menu is the MUXOUT CONTROL which can be used to
determine the function of LED D4. This mode defaults to Digital PLL Lock Detect and causes the LED D4
to light up when the PLL successfully locks. Normally, these menu settings do not need to be changed.
5.3
DAC5687 Software
By using the provided software, the user can write and read control register information to the DAC5687.
At first startup of this software, it is imperative to select the Pll Port Config button to bring up the parallel
port configuration settings. From the menu, select the TSW3000 setting. This configures the port to be
compatible with the TSW3000. Once the Demo Kit is powered on with the parallel port configured and
connected properly, then the GUI shown in Figure 7 is displayed with the default settings read from the
device. If there is a problem with the communication, such as the Demo Kit is not powered on or the
parallel port cable is not connected, an error message will be displayed instructing the user to correct the
problem. Once corrected, hit the Read All button to read the default settings of the device.
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TSW3000 Demo Kit
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Software Operation
Figure 7. DAC5687 GUI
For normal operation, the user needs only to select values and switches as desired. The values are
automatically sent to the device and read back to verify their configuration.
5.4
DAC5687 GUI Register Descriptions
5.4.1
•
•
•
•
5.4.2
•
•
•
•
Register Controls
Load Regs– Loads register values from a saved file to the DAC5687 and updates the GUI.
Save Regs– Saves current GUI registers settings to a text file for future use.
Read All– Reads the current registers of the DAC5687. This is used to verify settings on the front
panel.
Send All– Sends the current front panel registers to the device. This is generally only used when the
Demo Kit power has recycled or the device has been reset and the user wants to load the displayed
settings to the device.
Configuration Controls
Full Bypass– When set, all filtering, QMC, and NCO functions are bypassed.
FIR Bypass– Bypass all interpolation filters. QMC INCO functional. Limited to FDAC = 250 MHz
FIFO Bypass– When set to bypass, the internal four sample FIFO is disabled. When cleared, the FIFO
is enabled.
FIR A– A side first FIR filter in high-pass mode when set, low-pass mode when cleared.
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
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Software Operation
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16
FIR B– B side first FIR filter in high-pass mode when set, low-pass mode when cleared.
Dual Clk– Only used when the PLL is disabled. When set, two differential clocks are used to input the
data to the chip; CLK1/CLK1C is used to latch the input data into the chip, and CLK2/CLK2C is used
as the DAC sample clock.
Interleave– When set, interleaved input data mode is enabled; both A and B data streams are input at
the DA(15:0) input pins.
Inverse Sinc– Enables inverse sinc filter.
Half Rate Input– Enables half rate input mode. Input data for the DAC A data path is input to the chip
at half speed using both the DA(15:0) and DB(15:0) input pins.
Sif– Sets sif_4-pin bit. A 4-pin serial interface mode is enabled when on, 3-pin mode when off. The
DAC5687 Demo Kit is configured for a 3-pin serial interface, so setting to a 4-bit serial interface makes
reading registers impossible with the GUI.
Inv. PLL Lock– Only used when PLL is disabled and dual clock mode is disabled. When cleared, input
data is latched into the chip on rising edges of the PLLLOCK output pin. When set, input data is
latched into the chip on falling edges of the PLLLOCK output pin.
PLL Freq– Sets PLL VCO center frequency to low or high center frequency.
PLL Kv– Sets PLL VCO gain to either high or low gain.
Qflag– Sets qflag bit. When set, the QFLAG input pin operates as a B sample indicator when
interleaved data is enabled. When cleared, the TXENABLE rising determines the A/B timing
relationship.
2's Comp– When set, input data is interpreted as 2's complement. When cleared, input data is
interpreted as offset binary.
Rev A Bus– When cleared, DA input data MSB to LSB order is DA(15) = MSB and DA(0) = LSB.
When set, DA input data MSB to LSB order is reversed, DA(15) = LSB and DA(0) = MSB.
Rev B Bus– When cleared, DB input data MSB to LSB order is DB(15) = MSB and DB(0) = LSB.
When set, DB input data MSB to LSB order is reversed, DB(15) = LSB and DB(0) = MSB.
USB– When set, the data to DACB is inverted to generate upper side band output.
Inv. Clk I(Q)– Inverts the DAC core sample clock when set, normal when cleared.
Sync_Phstr– When set, the internal clock divider logic is initialized with a PHSTR pin low to high
transition.
Sync_cm– When set, the coarse mixer is synchronized with a PHSTR low-to-high transition.
Sync_NCO– When set, the NCO phase accumulator is cleared with a phstr low-to-high transition.
Phstr Clk Div Select– Selects the clock used to latch the PHSTR input when restarting the internal
clock dividers. When set, the full rate CLK2 signal latches PHSTR and when cleared, the divided down
input clock signal latches PHSTR.
DAC Serial Data– When set, both DAC A and DAC B input data is replaced with fixed data loaded into
the 16-bit serial interface DAC Static Data.
– Counter Mode– Controls the internal counter that can be used as the DAC data source: {off; all
16b; 7b LSBs; 5b MIDs; 5b MSBs}.
– DAC Static Data– When DAC Serial Data is set, both DAC A and DAC B input data is replaced
with fixed data loaded with this value. Range = 0 - 65535.
Alt. PLLLOCK Output– Can be used to determine alternate outputs on the PLLLOCK pin when using
the internal PLL mode. The EXTLO pin must be open when using this mode.
NCO– When set, enables NCO.
– NCO Gain– Sets NCO gain resulting in a 2x increase in NCO output amplitude. Except for Fs/2 and
Fs/4 mixing NCO frequencies, this selection can result in saturation for full-scale inputs. Consider
using QMC gain for lower gains.
QMC– When set, enables the QMC.
– QMCA Gain– Sets QMC gain A to a range = 0 to 2047. See the data sheet for more information.
– QMC B Gain– Sets QMC gain B to a range = 0 to 2047. See the data sheet for more information.
– QMC Phase– Sets QMC phase to a range = -512 to 511. See the data sheet for more information.
Used to adjust for I/Q phase imbalance.
Mode– Used to select the coarse mixer mode. See the DAC5687 data sheet for more information.
TSW3000 Demo Kit
SLWU013B – March 2004 – Revised November 2005
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Board Setup
•
•
•
•
5.4.3
•
•
•
•
PLL Divider– Sets VCO divider to div by 1, 2, 4, or 8.
Interpolation – Sets FIR Interpolation factor: {X2, X4, X4L, X8}. X4 uses lower power than 4xL, but
Fdac = 320 MHz max when NCO or QMC are used.
Phstr Init. Phase – Adjusts the initial phase of the fs/2 and fs/4 cmix block at PHSTR.
Sync FIFO– Sync source selection mode for the FIFO. When a low to high transition is detected on
the selected sync source, the FIFO input and output pointers are initialized. See the DAC5687 data
sheet for source description.
DAC A(B) Gain
DAC Coarse Gain– Sets coarse gain of DAC A(B) full-scale current. Range is 0 to 15. See the
DAC5687 data sheet for full-scale gain equation.
DAC Fine Gain– Sets fine gain of DAC A(B) full scale current. Range is -128 to127. See the DAC5687
data sheet for full-scale gain equation. Used to adjust for I/Q amplitude imbalance.
DAC DCOffset– Sets DAC A(B) dc-offset register. Range is -4096 to 4095. Used to adjust for carrier
suppression.
Sleep– DAC A(B) sleeps when set, operational when cleared.
5.4.4
NCO
• NCO DDS– Sets NCO DDS registers. See the DAC5687 data sheet for formula.
• NCO Phase– Sets initial NCO phase registers. See the DAC5687 data sheet for more information.
• FDAC (MHz), NCO IF (MHz)– Used to calculate the required NCO DDS value.
5.4.5
Additional Control/Monitor Registers
• Version– Displays the version of the silicon. If a version of 0 is read then the communication is not
functioning and an error message will be displayed.
6
Board Setup
6.1
Jumper Settings
The TSW3000 Demo Kit has on-board jumpers that allow the user to selectively disengage devices as
desired. The unit is shipped with jumpers in place that activate all of the devices on board. Table 3
explains the functionality of the jumpers on the board.
Table 3. Jumper List
JUMPER
LABEL
W1
PLL Lock
W2
PWD
W6
LO Buffer
FUNCTION
2-pin access port for monitoring PLL lock of the
DAC5687
CONDITION
DEFAULT
Open
Installed
Power down for the TRF370x
Powered
Pin 1, 2
Disengages power to LO buffer amp
Powered
Installed
3.3 V Engaged
Pin 1, 2
W5
IOVDD
J15 pin 2
PLLVDD
Toggles 3.3 V or 1.8 V to IOVDD on the DAC5687
Toggles power to the DAC PLL
Not Powered
Pin 1, 2
J15 pin 5
SLEEP
Power down for the DAC5687
Open
Removed
J15 pin 8
EXTLO
Toggles internal reference ground
Grounded
Pin 7, 8
J15 pin 11
TXENABLE
Selects interleaved data
Powered
Pin 11, 12
J15 pin 14
TESTMODE
DO NOT POPULATE!
Open
Removed
J15 pin 17
QFLAG
Used to flag the DAC5687 channel B data in
interleave mode
Open
Removed
Removed
J15 pin 20
CDC_PD
Power down of the CDCM7005
Open
J15 pin 23
REF_SEL
Selecets reference for CDCM7005
Open
Removed
J15 pin 27
PLL_PWD
Power down the TRF3750
Powered
Pin 26, 27
SLWU013B – March 2004 – Revised November 2005
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Demo Kit Test Configuration
Table 3. Jumper List (continued)
6.2
JUMPER
LABEL
J15 pin 29
RESET
FUNCTION
CONDITION
DEFAULT
Open
Removed
Resets the DAC5687 when low
Input/Output Connectors
The input and output connections are shown in Table 4.
Table 4. Input/Output Connections
REFERENCE DESIGNATOR
CONNECTOR TYPE
DESCRIPTION
J13
34-pin header
I channel data input
J14
34-pin header
Q channel data input
J9
SMA
RF output
J10
SMA
Optional LO input
J8
SMA
Optional external reference
J2
SMA
Output clock 1 from CDCM7005
J3
SMA
Output clock 2 from CDCM7005
J5
SMA
Optional I out A from DAC5687
J19
SMA
Optional Q out B from DAC5687
J6
SMA
Input for external VCXO for CDCM7005
J7
SMA
PLL lock status on DAC5687
J4
SMA
Phase synchronization on DAC5687
RF shield covers should be in place over the synthesizer section and the RF modulator section. These
shields provide isolation of the RF sections on the board.
6.3
Parallel Port
The TSW3000 Demo Kit contains a 25-pin parallel port connector (J1) to interface to a standard computer
parallel port. Programming of the CDCM7005, DAC5687, and TRF3750 are accomplished through this
port.
6.4
DC Power Requirements
The Demo Kit requires a single dc-voltage supply that is nominally 6 V. From that supply, the 5 V, 3.3 V,
and 1.8 V required for the devices on the board are generated internally through linear voltage regulators.
It is possible to use a higher input voltage; however, care should be taken not to over dissipate the
on-board voltage regulators.
7
Demo Kit Test Configuration
18
TSW3000 Demo Kit
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Demo Kit Test Configuration
7.1
Test Setup Block Diagram
The test set up for general testing of the TSW3000 Demo Kit is shown in Figure 8.
Power
Supply
+6 V
GND
Clock
Pattern
Generator
J7
J17 J11
16
J13
TSW3000
EVM DUT
16
J14
J9
Spectrum
Analyzer
J1
25
PC Controller
Figure 8. Test System Block Diagram
7.2
Test Equipment
The following is a list of the test equipment required for testing the TSW3000 Demo Kit. Equivalent models
may be used for certain applications, but may produce different results due to limitations within the
instrument.
• Dual Power Supply: Any with current readout capability
• Spectrum Analyzer: Rhode & Schwartz FSU, Agilent PSA, or equivalent
This particular piece can measure >70-dBc ACPR with the noise cancellation option active. This
amount of dynamic range is required to accurately measure the ACPR of the Demo Kit. Another
spectrum analyzer can be substituted if it achieves as good or better dynamic range.
• Pattern Generator: Agilent 16702B
• Oscilloscope: Tektronix 650 or equivalent
Used to probe clock output signals and for debugging.
• Digital Voltmeter: Agilent 34401A or equivalent
7.3
Calibration
In order to record proper output power the insertion loss of the output cable must calibrated. Measure the
insertion loss of the cable from J9 to the spectrum analyzer; set the analyzer's reference level offset to
that value.
7.4
Test Specifications
The test specifications are outlined in Table 5.
Table 5. Demo Kit Specifications
MIN
MAX
UNITS
1.5
A
CURRENT
+6 V
CW TESTS
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
19
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Basic Test Procedure
Table 5. Demo Kit Specifications (continued)
MIN
MAX
UNITS
Carrier suppression
30
dBc
Sideband rejection
25
dBc
2nd harmonic
45
dBc
Aliased LSB (pos)
40
dBc
Output clock
40
dBc
Aliased USB
15
dBc
Aliased USB (neg)
8
dBc
Spurious Output
WCDMA ACPR
Channel power
8
-14
dBm
ACPR -Low
70
dBc
ACPR -High
70
dBc
Basic Test Procedure
This section outlines the basic test procedure to get the Demo Kit operational. Disconnect the cables at
J13 and J14 that connect to the pattern generator. Connect the power supply cable and the RF output to
the spectrum analyzer.
8.1
Initial Inspection
Inspect the board to determine which devices were used.
• Note the VCXO frequency (U10) that is on the board
• Note the VCO frequency band (Y3) that is on the board
8.2
Engage Power Supplies
Engage 6-V power supply
• Verify the current reading is between 0.8 A to 1.3 A when configured with the DAC5687
8.3
Program the CDCM7005
Use the Default Settings on the CDCM7005 GUI (See Section 5.1). This generates a 491.52-MHz clock.
• Set the OUT_MUX_0, 2, 3, 4 to tristate. Only OUT_MUX_1 is used for clocking the DAC5687
• Hit the GUI Send button
• Verify that LEDs D1, D2, and D3 are illuminated
8.4
Program the TRF3750
Use the Default Settings in the TRF3750 GUI (See Section 5.2). This places a carrier at 2.14 GHz
• Hit the GUI send button.
• Verify the LED D4 is illuminated. This indicates lock of the VCXO and TCXO reference.
• Monitor RF output from the spectrum analyzer
• Verify a single frequency tone at the default 2.14 GHz.
20
TSW3000 Demo Kit
SLWU013B – March 2004 – Revised November 2005
www.ti.com
Basic Test Procedure
Table 6. Frequency Designations
8.5
UMTS
GSM900
PCS
DCS1800
Midband (MHz)
2140
950
1960
1850
Low (MHz)
2110
935
1930
1805
High (MHz)
2170
960
1990
1880
DAC5687 Program
•
•
•
•
•
8.6
VCO BAND
Disable the PLL by removing the jumper at J15, pins 2 and 3, if not already removed.
Verify DACA and DACB Coarse Gain is set to 15
Set Mode to 0000 (No Coarse Mixing)
Ensure DAC Offsets and DAC fine gain for both A and B are set to 0
Set the spectrum analyzer as follows:
– Center Freq: 2.14 GHz
– RBW: 30 kHz, VBW: 300 kHz
– Span: 491.52 MHz
– Attn: 5 dB
– Ref Level: 10 dBm
Carrier Suppression
The carrier suppression can be tuned for better performance by adjusting the dc-offset controls on the
DAC5687. The default DAC GUI is shown below with the NCO mixer turned on to output a 61.44-MHz
tone. The output spectrum is illustrated in Figure 10.
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
21
www.ti.com
Basic Test Procedure
Figure 9. Default DAC GUI With fDAC/8 Tone From NCO
22
TSW3000 Demo Kit
SLWU013B – March 2004 – Revised November 2005
www.ti.com
Basic Test Procedure
Figure 10. Single Sideband Spectrum Output Before DAC Offset and QMC Adjustments
An iterative process is used to achieve the best performance.
• Place a normal marker at the peak upper sideband, place a delta marker at the carrier signal, and note
the initial delta value.
• Set initial DACA offset to 1000 and DACB offset to -1000
• Change DACA offset by 1000 steps and monitor the output performance change.
• If performance gets better, then repeat the process with an additional 1000 steps. If the performance
gets worse or doesn't change, then change the offset in the other direction by 1000 steps.
• Once the performance remains basically unchanged, repeat the process on DACB offset with 1000
step changes.
• Once optimized, go back to the A side and repeat the tuning process with a step size of 100.
• Continue tuning. After each complete cycle, reduce the step size down (i.e., to 10, then to 1 if desired).
• A performance greater that 65 dBc should be achievable.
8.7
Sideband Rejection
Sideband rejection is determined by the two quadrature signals to the modulator being exactly 180
degrees out of phase and exactly the same amplitude. Amplitude and phase imbalance between the two
paths yield an unwanted lower sideband. The amplitude variation between the two paths can be
compensated for by adjusting the DAC fine gain controls or by adjusting the QMC gain controls if the
device is operating with the QMC on. The phase can be compensated by using the QMC phase
adjustment. Note this is only possible when the coarse mixer is not used in the fDAC/4 mode. Coarse
mixing in the fDAC/4 mode causes the relative phase information between I and Q paths to be mixed. In the
fDAC/2 mode there are no cross terms (terms are 0) and the relative phase information is maintained
between I and Q paths.
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
23
www.ti.com
Basic Test Procedure
•
•
•
•
•
•
Place marker delta on the lower sideband
Turn on the QMC. Set the Gain of the QMC to 1024 for gain of 0 dB for I and Q paths. Other initial
settings may be needed depending on the state of the NCO gain and signal amplitude.
Change the phase of the QMC by small increments until the sideband is minimized.
Change the QMC A or B gains in increments of 1 until the sideband is minimized.
The overall performance should be greater than 60 dBc from the other sideband with amplitude and
phase corrections.
Re-optimized the dc-offset values as required to maintain carrier suppression performance as
specified.
Figure 11. DAC GUI With Typical Settings To Minimize LO and Sideband
Sideband and LO are reduced into the noise floor. Clock related spurs can be filtered out using an RF
filter.
24
TSW3000 Demo Kit
SLWU013B – March 2004 – Revised November 2005
www.ti.com
Optional Configurations
Figure 12. Sideband and LO
9
Optional Configurations
9.1
External LO
To configure the board for external LO implement the following modifications
• Remove R225
• Place R2: 0-Ω resistor, this connects the external LO on J10 to the TRF3702 modulator
• Remove W6 (disengages power to RF amplifier)
• Disable the TRF3750 PLL CE by setting J15-25, 26. This puts GND on CE of the TRF3750 and
disables the PLL.
9.2
External Reference
To configure the board for an external reference implement the following modifications.
• Remove R144, this disconnects the on board 10-MHz reference
• Place R201: 0-Ω resistor, external reference can be hooked up to J8
9.3
Monitor DAC Output
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
25
www.ti.com
Filter Specifications
9.3.1
Single Ended
To configure the board to monitor the DAC output by utilizing the transformers on board to achieve a
single-ended output, implement the following modifications.
• Remove R187, R188, R191, R190, R208, R209, R210, R211
• Place R200, R224, R222, R223: 0-Ω resistors
• Place R179, R183, R212, R213: 100-Ω resistor. This configures the DAC output as in the DAC5687
data sheet for 4:1 impedance transformer.
Monitor outputs at J5 and J19.
10
Filter Specifications
10.1
Baseband Filter
The TSW3000 Demo Kit layout provides the opportunity to place components to realize up to a 7th order
LC filter. The Demo Kit is by default populated with a 500-MHz LC low-pass filter to help eliminate DAC
images and also out of band clock spurs which may mix into RF frequencies.
10.1.1
RF Filter/Output Match
The TSW3000 Demo Kit layout also provides the opportunity to place a small 3rd order LC filter on the
output of the modulator for either filtering or impedance matching purposes. This filter has been disabled
by removing the shunt capacitive elements and replacing the series inductor element with a 0-Ω resistor.
11
Layers and Schematics
This chapter contains the layers and schematics for the TSW3000 Demo Kit.
11.1
Bill of Materials
Table 7 lists the parts used in constructing the TSW3000 Demo Kit.
Table 7. Bill of Materials
Value
QTY
Part Number
Vendor
Ref Des
TANT 47 µF, 10%, 10 V
capacitor
7
ECS-T1AD476R
Panasonic
C25, C67, C70, C74, C105,
C124, C160
TANT 10 µF, 10%, 10 V
capacitor
18
ECS-T1AX106R
Panasonic
C24, C35, C37-C41, C51,
C83, C99, C116, C117,
C121, C123, C129, C153,
C156, C161
TANT 10 µF, 10 V, 10%
capacitor
2
T491C106K010AS
Kemet
C22, C101
TANT 22 µF, 10 V, 10%
capacitor
1
T491C226K010AS
Kemet
C96
1 µF, 25 V, 10% capacitor
6
ECJ-3YB1E105K
Panasonic
C47, C50, C53, C54, C144,
C159
0.01 µF, 50 V, 10% capacitor
5
ECJ-2VB1H103K
Panasonic
C57, C60, C64, C102, C109
0.1 F, 16 V, 10% capacitor
8
ECJ-2VB1C104K
Panasonic
C20, C21, C23, C26, C27,
C75, C81, C106
1 pF, 50 V, ±0.25 pF capacitor
4
ECJ-2VC1H010C
Panasonic
C30, C32, C125, C126
2.2 pF, 50 V, ±0.25% capacitor
3
08055A2R2CAT2A
AVX
C19, C31, C68
0.0018 µF, 50 V 5% capacitor
0
ECJ-2VC1H182J
Panasonic
6.8 pF, 50 V, ±0.25% capacitor
2
08055A6R8CAT2A
AVX
47 pF, 50 V, 5% capacitor
0
ECJ-2VC1H470J
Panasonic
1 µF, 16 V, 10% capacitor
1
ECJ-1VB1C105K
Panasonic
Not Installed
CAPACITORS
26
TSW3000 Demo Kit
C66, C72
C63, C65
C93, C95
C91
SLWU013B – March 2004 – Revised November 2005
www.ti.com
Layers and Schematics
Table 7. Bill of Materials (continued)
QTY
Part Number
Vendor
Ref Des
0.1 µF, 16 V, 10% capacitor
Value
16
ECJ-1VB1C104K
Panasonic
C28, C43-C45, C48, C76,
C78-C80, C82, C87, C89,
C90, C134, C151, C152
0.01 µF, 16 V, 10% capacitor
5
ECJ-1VB1C103K
Panasonic
C46, C52, C56, C62, C130
10 pF, 50 V, ±0.5 pF, capacitor
8
ECJ-1VC1H100D
Panasonic
C61, C97, C107, C108,
C111, C127, C128, C158
22 pF, 50 V, 5%, capacitor
3
ECJ-1VC1H220J
Panasonic
C146, C148, C149
33 pF, 50 V, 5%, capacitor
0
ECJ-1VC1H330J
Panasonic
0.47 µF, 6.3 V, 10%, capacitor
1
ECJ-1VB0J474K
Panasonic
1 pF, 50 V, 5%, capacitor
0
ECJ-1VC1H010C
Panasonic
82 pF, 50 V, 5%, capacitor
1
ECJ-1VC1H820J
Panasonic
C141
100 pF, 50 V, 5%, capacitor
5
ECJ-1VC1H101J
Panasonic
C132, C133, C135-C137
330 pF, 50 V, 5%, capacitor
1
ECJ-1VC1H331J
Panasonic
C33
560 pF, 50 V, 5%, capacitor
1
ECJ-1VC1H561J
Panasonic
C110
Not Installed
C142
C92
C98
1000 pF, 50 V, 5%, capacitor
4
ECJ-1VC1H102J
Panasonic
C88, C139, C140, C147
0.1 µF, 10 V, 10% capacitor
34
ECJ-0EB1A104K
Panasonic
C1-C18, C29, C36, C49,
C58, C69, C73, C84, C85,
C86, C100, C104,
C112-C115, C120
0.01 µF, 16 V, 10% capacitor
2
ECJ-0EB1C103K
Panasonic
C71, C122
0.001 µF, 25 V, 10% capacitor
2
ECJ-0EB1E102K
Panasonic
C119, C131
0.033 µF, 10 V, 10% capacitor
1
ECJ-0EB1A333K
Panasonic
C34
2 kΩ resistor, 1/10 W, 1%
2
ECJ-0EB1C103K
Panasonic
R8, R11
10 kΩ resistor, 1/10 W, 1%
6
ERJ-6ENF1002V
Panasonic
R17, R34-37, R155
47.5 Ω resistor, 1/10 W, 1%
2
ERJ-6ENF47R5V
Panasonic
R146, R147
10 Ω resistor, 1/10 W, 1%
1
ERJ-6ENF10R0V
Panasonic
R3
0 Ω resistor, 1/10 W, 5%
16
9C06031A0R00JLHF
T
Yageo
R6, R9, R47, R110, R114,
R133, R144, R171, R172,
R178, R189, R193, R225,
R232, R247, R249
R10, R14, R48, R109, R124,
R145, R181, R182,
R200-R202, R222-R224,
R228, R229, R245, R250
1 kΩ resistor, 1/16 W, 1%
3
ERJ-3EKF1001V
Panasonic
R1, R4, R226
R7, R44
2 kΩ resistor, 1/16 W, 1%
1
ERJ-3EKF2001V
Panasonic
R227
3.92 kΩ resistor, 1/16 W, 1%
1
ERJ-3EKF3R92V
Panasonic
R135
4.75 kΩ resistor, 1/16 W, 1%
2
ERJ-3EKF4751V
Panasonic
R125, R141
10 kΩ resistor, 1/16 W, 1%
9
ERJ-3EKF1002V
Panasonic
R115, R116, R149, R151,
R195, R196, R199, R218,
R248
20 kΩ resistor, 1/16 W, 1%
1
ERJ-3EKF2002V
Panasonic
R136
100 kΩ resistor, 1/16 W, 1%
6
ERJ-3EKF1003V
Panasonic
R30, R31, R32, R113, R130,
R131
15 Ω resistor, 1/16 W, 1%
4
ERJ-3EKF15R0V
Panasonic
R187, R188, R190, R191
18.2 Ω resistor, 1/16 W, 1%
1
ERJ-3EKF18R2V
Panasonic
R122
22.1 Ω resistor, 1/16 W, 1%
4
ERJ-3EKF22R1V
Panasonic
R16, R18, R197, R237
5.62 Ω resistor, 1/10 W, 1%
3
RC0603FR-075R62L
Yageo
R137, R138, R148
49.9 Ω resistor, 1/16 W, 1%
9
ERJ-3EKF49R9V
Panasonic
R13, R39, R40, R43, R46,
R238, R239, R243, R244
82.5 Ω resistor, 1/16 W, 1%
6
ERJ-3EKF82R5V
Panasonic
R126, R127, R161, R162,
R163, R164
100 Ω resistor, 1/16 W, 1%
10
ERJ-3EKF1000V
Panasonic
R19, R20, R21, R22, R27,
R28, R29, R45, R140, R150
110 Ω resistor, 1/16 W, 1%
0
ERJ-3EKF1100V
Panasonic
130 Ω resistor, 1/16 W, 1%
6
ERJ-3EKF1300V
Panasonic
R19, R20, R21, R22, R27,
R28, R29, R45, R140, R150
150 Ω resistor, 1/16 W, 1%
2
ERJ-3EKF1500V
Panasonic
R15, R221
RESISTORS
SLWU013B – March 2004 – Revised November 2005
R12
R2, R5, R179, R183, R212,
R213
R235
R33, R38
TSW3000 Demo Kit
27
www.ti.com
Layers and Schematics
Table 7. Bill of Materials (continued)
QTY
Part Number
Vendor
Ref Des
162 Ω resistor, 1/16 W, 1%
Value
1
ERJ-3EKF1620V
Panasonic
R142
200 Ω resistor, 1/16 W, 1%
2
ERJ-3EKF2000V
Panasonic
R132, R134
221 Ω resistor, 1/16 W, 1%
4
ERJ-3EKF2210V
Panasonic
R208-R211
274 Ω resistor, 1/16 W, 1%
2
ERJ-3EKF2740V
Panasonic
R119, R121
27.4 Ω resistor, 1/16 W, 1%
1
ERJ-3EKF27R4V
Panasonic
R139
475 Ω resistor, 1/16 W, 1%
1
ERJ-3EKF4750V
Panasonic
R117
750 Ω resistor, 1/16 W, 1%
3
ERJ-3EKF7500V
Panasonic
R23, R24, R26
825 Ω resistor, 1/16 W, 1%
2
ERJ-3EKF8250V
Panasonic
R111, R112
93.1 Ω resistor, 1/16 W, 1%
1
ERJ-3EKF93R1V
Panasonic
R25
15.8 Ω resistor, 1/16 W, 1%
1
ERJ-3EKF1582V
Panasonic
R41
30.1 Ω resistor, 1/16 W, 1%
1
ERJ-3EKF3012
Panasonic
R42
10 Ω resistor, 1/16 W, 1%
1
ERJ-2RKF10R0X
Panasonic
R255
Surface Mount Socket strips
4
310-93-164-41105000
Mill-Max
RP5- RP8
51 Ω resistor pack
0
22 Ω resistor pack
4
4816P-001-220
Bourns
RP1, RP2, RP3, RP4
11
EXC-ML32A680U
Panasonic
FB1, FB3, FB6, FB,7 FB10,
FB11, FB14-FB18
5
EXC-ML20A390U
Panasonic
FB2, FB4, FB8, FB9, FB12
1
623-2773021447
Mouser
FB13
Inductor, 18 nH
4
LLQ2012-F18NG
Toko
L9, L11, L13, L14
Inductor, 2.7 nH
4
LLQ2012-F2N7J
Toko
L10, L12, L15, L16
0 Ω resistor, 1/8 W, 5%
5
9C08052A0R00JLHF
T
Yageo
L2, L4, L7, L8, L17
2.2 nH Inductor
0
LL2012-FH2N2S
Toko
22 nH Inductor
1
0805CS-220X_B_
Coilcraft
CTS
Not Installed
R236
R118, R123
RP5-RP8
INDUCTORS
Ferrite Bead
L19
L18
IC'S ETC.
DAC5687IPZP
1
DAC5687IPZP
Texas Instruments
U1
CDCM7005RGZ
1
CDCM7005RGZ
Texas Instruments
U12
CDCV304PW
1
CDCV304PW
Texas Instruments
U17
TRF3702IRHC
1
TRF3702IRHC
Texas Instruments
U11
TRF3750IPW
1
TRF3750IPW
Texas Instruments
U14
THS4221DBVR
1
THS4221DBVR
Texas Instruments
U18
TPS76750QPWP
1
TPS76750QPWP
Texas Instruments
U6
TPS76733QPWP
1
TPS76733QPWP
Texas Instruments
U7
TPS76701QPWP
1
TPS76701QPWP
Texas Instruments
U8
SN74HC241DW
1
SN74HC241DW
Texas Instruments
U4
SN74LV125AD
1
SN74LV125AD
Texas Instruments
U13
Amplifier DC-5000 MHz
1
SGA-5386
Sirenza
U15
VCO
1
ROS-2170-7
Mini-Circuits
Y3
VCXO
1
TC0-2111-491.52
Toyocom
U10
Crystal Oscillator
1
OSC3B0 at 10 MHz
Vectron
Y2
4:1 Transformer
2
T4-1-KK81
Mini-Circuits
T1, T2
Black Test Point
1
5011K
Keystone
TP12
Red Test Point
4
5000K
Keystone
E1, TP1, TP18, TP19
SMA Plug W/Stand Off
3
901-144-8RFX
AMP
J4, J5, J19
SMA connectors
7
16F3627
Newark
J2, J3, J6-J10
Switch
1
EVQ-PJX04M
Panasonic
S1
Red Banana Jack
1
ST-351A
Allied
J11
CONNECTORS, JUMPERS, ETC.
28
TSW3000 Demo Kit
SLWU013B – March 2004 – Revised November 2005
www.ti.com
Layers and Schematics
Table 7. Bill of Materials (continued)
QTY
Part Number
Vendor
Ref Des
Black Banana Jack
Value
1
ST-351B
Allied
J17
Green SM_LED_1206
4
CMD15-21VGC/TR8
Panasonic
D1, D2, D3, D4
30 Pin Header
1
HTSW-120-07-L-T
Samtec
J15
34 Pin Header
2
TSM-117-01-S-DV-LC
Samtec
J13, J14
Connectors
1
745536-2
AMP
J1
Nuts
2
Mounting screws
2
Unformed Fence 0.13 in with
0.5 in spacing no standoff
2
3POS power jack
3POS_header
2POS_header
Not Installed
J1
J1
14R-CBSU-24
Leader-Tech
N/Q
1
RAPC722
Switchcraft
J12
2
HTSW-150-07-L-S
Samtec
W2, W5
2
HTSW-150-07-L-S
Samtec
W1, W6
MECHANICAL ASSEMBLY AND REWORKS
Fence cover
1
Screws
6
Stand Off Hex (1/4 x 0.5")
6
Jumper
Leader-Tech
1
1902CK-ND
Allied
1
W1
1
W2 - Connect pins 1 and 2
1
W5 - Connect pins 1 and 2
1
W6 - Placed
1
J15 - Conn. pin 7 and 8
(ExtLO)
1
J15 - Conn. pin 1 and 2
(PLL_VDD)
1
J15 - Conn. pin 11 and 12
(TXEnable)
1
J15 - Conn. pin 23 and 24
(REF_SEL)
1
J15 - Conn. pin 26 and 27
(PLL_PWD)
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
29
www.ti.com
Layers and Schematics
11.2
Layers
The Demo Kit is constructed on a 6-layer, 6.2 inch x 8 inch, 0.062-inch thick PCB using FR-4 material.
See Figure 13 through Figure 22 show the PCB layout for the Demo Kit.
Figure 13. Top Layer
30
TSW3000 Demo Kit
SLWU013B – March 2004 – Revised November 2005
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Layers and Schematics
Figure 14. Top Layer (NH)
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
31
www.ti.com
Layers and Schematics
Figure 15. Layer 2
32
TSW3000 Demo Kit
SLWU013B – March 2004 – Revised November 2005
www.ti.com
Layers and Schematics
Figure 16. Layer 3
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
33
www.ti.com
Layers and Schematics
Figure 17. Layer 4
34
TSW3000 Demo Kit
SLWU013B – March 2004 – Revised November 2005
www.ti.com
Layers and Schematics
Figure 18. Layer 4 (NH)
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
35
www.ti.com
Layers and Schematics
Figure 19. Layer 5
36
TSW3000 Demo Kit
SLWU013B – March 2004 – Revised November 2005
www.ti.com
Layers and Schematics
Figure 20. Bottom Layer
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
37
www.ti.com
Layers and Schematics
Figure 21. Bottom Silkscreen
38
TSW3000 Demo Kit
SLWU013B – March 2004 – Revised November 2005
www.ti.com
Layers and Schematics
Figure 22. Drill Drawing
SLWU013B – March 2004 – Revised November 2005
TSW3000 Demo Kit
39
+
.1 u F
.1 u F
TXENABLE
C3 7
+
R4 0
49.9
.1 u F
.1 uF
C1 7
DA4
DA3
DA2
DA1
DA0
.1 u F
DA7
DA6
DA5
DA1 2
DA11
DA1 0
DA9
DA8
DA15
DA1 4
DA1 3
C6
.1 uF
.1 u F
C5
C86
C8 5
C24
C4 1
+
+3.3VCLK
10
R2 55
DVDD
DGND
SDENB
SCLK
SDIO
SDO
DVDD
TXENABLE
DA15
DA14
DA13
DVDD
DGND
DA12
DA11
DA10
DA9
DA8
DVDD
DGND
IOVDD
IOGND
DA7
DA6
DA5
.1 u F
C7
10u F, 1 0V
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
+1.8VD
+3.3VA
(SH 2 ) EXT_LO
10u F, 1 0 V
+
NOTES:
1. DO NOT INSTALL
2. CHANGE TO 0 OHM FOR 50 OHM LOAD
(SH 2 ) DA(0..15)
.1 u F
C4
.1 u F
C8 4
TXENABLE
10 u F, 1 0V10 u F, 1 0 V
C3 9
+
IOVDD
(SH 2 )
SDEN1
SCLK
SDIO
C2
C1
.1u F
.1 uF
(SH 5 ) SDEN1
SCLK
(SH 5)
SDIO
(SH 5)
10 u F, 10 V
C38
+1.8VD
C2 9
C1 5
EXT_LO
.1 u F
C1 6
+3.3VA
TP1
1K
R1
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
U1
DAC5687
.1 uF
C13
.1uF
C3
.1 u F
C1 4
CLK1
CLK1C
CLK2
CLK2C
10 u F, 1 0V
C4 0
+
E1
R4 5
100
93.1
R1 50
10 0
.0 1u F
C56
DB7
DB6
DB5
DB12
DB11
DB10
DB9
DB8
DB1 5
DB14
DB1 3
C1 0
.1uF
DB[0 ..1 5 ]
.1 uF
C1 8
IOVDD
R1 2
49.9
(No te 1 )
C11
.1u F
CLK1B
.01u F
CLK1CB
CLK2B
CLK2CB
IOUTA1
IOUTA2
IOUTB2
IOUTB1
CLK1B (SH 5 )
CLK1CB(SH 5)
CLK2B (SH 5)
CLK2CB(SH 5 )
W5
(1 −2 )
+1.8VD
J4
MCX
FERRITE
.1u F
C1 34
(No te 1 )
R2 36
22 1
(No te 1 )
R2 35
11 0
+3.3VA
2
3
4
5
+3.3VA FB1 5
(SH 2)
PHSTR PHSTR
DB(0..15) (SH 2)
2
+3.3VA
QFLAG(SH 2 )
TESTMODE(SH 2 )
SLEEP (SH 2)
(Note 1 )
R2 50
1
0
R1 3
R3 9
R2 49
0
49.9
49.9
C1 2
.1uF
PLL_VDD PLL_VDD (SH 2)
.01u F
C6 2
C9
.1uF
QFLAG
TESTMODE
SLEEP
DB4
DB3
DB2
DB1
DB0
C5 2
.01 u F
C46
33 0 pF
C33
R2 5
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
S1
SW−PB
RESET RESET (Sh 2 , 4)
1K
R4
+3.3VA
C3 4
.0 33 uF
+1.8VD
.1 uF
C8
DVDD
DGND
QFLAG
TESTMODE
SLEEP
/RESETB
PHSTR
DGND
DB15
DB14
DB13
DVDD
DGND
DB12
DB11
DB10
DB9
DB8
DVDD
DGND
IOVDD
IOGND
DB7
DB6
DB5
AGND
AVDD
AVDD
AGND
IOUTA2
IOUTA1
AGND
AVDD
AGND
AVDD
EXTLO
AVDD
BIASJ
AGND
EXTIO
AVDD
AGND
AVDD
AGND
IOUTB1
IOUTB2
AGND
AVDD
AVDD
AGND
DA4
DA3
DA2
DA1
DA0
DVDD
DGND
CLKGND
CLK1
CLK1C
CLKVDD
CLK2
CLK2C
CLKGND
PLLGND
LPF
PLLVDD
DVDD
DGND
PLLLOCK
DB0
DB1
DB2
DB3
DB4
TSW3000 Demo Kit
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
40
1
C1 5 3
4
2
GND
OE
VDD/3.3V
CLKIN
1Y3
1Y2
1Y1
1Y0
3)
3)
3)
3)
FILE:
Drawn By:Y.
DEWONCK
Engineer:R. HOPPENSTEIN
10u F, 10 V
+
1
6
U17
CDCV304
IOUTA1(SH
IOUTA2(SH
IOUTB2(SH
IOUTB1(SH
8
7
5
3
SIZE:
Title:
DATE:
1
24−Oc t−2005 REV: A
SHEET:1
TSW3000
ti
W1
22.1
(Note 2 )
R19 7
2
3
4
5
7
J7
SMA
OF:
12500 TI Boulevard. Dallas, Texas 75243
R2 3 7
22.1
49.9
R4 6 49.9
R4 3
11.3
3
+3.3VA
www.ti.com
Layers and Schematics
Schematics
The following figures show the schematic for the TSW3000 Demo Kit.
Figure 23. Schematic - Page 1
SLWU013B – March 2004 – Revised November 2005
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
NOTES:
1. DO NOT INSTALL
2
1
4
3
6
5
8
7
10
9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
34 33
34 PIN_ IDC
J1 4
DATA PORT 2
34 PIN_ IDC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
PHSTR
PHSTR
51
(Note 1)
RP5
(SH 1)
RP7
51
(Note 1)
51
RP6
1
(Note 1)
51
RP8
(Note 1)
10
9
8
7
6
5
4
3
2
A1 5
A1 4
A1 3
A1 2
A11
A1 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
10
9
8
7
6
5
4
3
2
1
J13
10
9
8
7
6
5
4
3
2
10
9
8
7
6
5
4
3
2
SLWU013B – March 2004 – Revised November 2005
1
1
DATA PORT 1
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
RP3
22
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
RP4
22
22
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RP2
16
15
14
13
12
11
10
9
RP1
22
1
2
3
4
5
6
7
8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DA15
DA1 4
DA1 3
DA12
DA11
DA1 0
DA9
DA8
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB(0..15)
DA(0..15)
FILE:
Drawn By:
Engineer:
(SH 1 )
(SH 1)
2
30
28
29
26
23
20
17
14
8
11
5
21
27
25
18
16
24
12
15
10
13
22
9
4
19
3
6
1
7
RESET
PLL_PWD
REF_SEL
CDC_PD
QFLAG
TESTMODE
EXT_LO
TXENABLE
SLEEP
PLL_VDD
+3.3VA
Y. DEWONCK
R. HOPPENSTEIN
DATE:
24−Oc t−2005
SIZE:
TSW3000
ti
RESET
PLL_PWD
REF_SEL
CDC_PD
QFLAG
SHEET:
2
(SH 1 )
(Sh 7 )
(Sh 4)
(SH 4 )
(SH 1)
(SH 1)
(SH 1 )
(SH 1)
(SH 1 )
OF:
REV:
A
7
(SH 1, 4 )
TESTMODE
EXT_LO
TXENABLE
SLEEP
PLL_VDD
12500 TI Boulevard. Dallas, Texas 75243
DOCUMENTCONTROL#
Title:
3 ROW 30 PIN CONNECTOR
J1 5
www.ti.com
Layers and Schematics
Figure 24. Schematic - Page 2
TSW3000 Demo Kit
41
1. DO NOT INSTALL
NOTES:
(Sh 1 ) IOUTB2 IOUTB2
(Sh 1 ) IOUTB1 IOUTB1
R2 13
22 1
22 1
R19 0
R1 93
0
49.9
1
2
4
1
IOUTB
J1 9
SMA
18 nH
L14
L8
0 nH
2.7 nH
1p F
C3 2
L7
0nH
L4
0nH
0 nH
1p F
C30
L2
L1 6
C6 5
6.8p F
2.2 pF
L1 5
2.7 nH
L1 3
2.2 p F
C68
+5VA
18 nH
FB1 6
1
C31
.1 u F
C2 3
6
T4 −1 T−KK81
T2
R2 4 4
3
6
2.7 nH
18 nH
IOUTA
J5
SMA
L1 2
6.8 p F
L11
2.2 pF
2.7 nH
18nH
C6 3
L1 0
L9
C1 9
4
T4 −1 T−KK8 1
R2 4 3
3
2
T1
49.9
VCM
+3.3VA
15
R1 9 1 15
1
49.9
+3.3VA
R1 8 9
0
R5
10 0
(No te 1) (Note 1 )
R2 2 3
0
(Note 1 )
R2 22
0
R2 11
R21 0
10 0
10 0
(No te 1 ) (No te 1)
R2 12
+3.3VA
R2
10 0
(No te 1 ) (Note 1 )
R22 4
0
R2 0 0
0
(No te 1)
22 1
22 1
R18 8 15
R2 0 9
(Sh 1)IOUTA2 IOUTA2
R2 08
R18 7 15
(Sh 1 )IOUTA1 IOUTA1
R239
49.9
E6
E5
E4
E3
47 p F
(No te 1 )
C9 5
47 p F
(No te 1 )
C9 3
2K
R11
2K
R8
ISIG
IREF
QSIG
QREF
14
15
16
IVIN
IREF
QREF
TRF37 0 2
U11
VCC
PWD
7
6
.1u F
C7 5
FILE:
Drawn By:
Y.
DEWONCK
Engineer:R. HOPPENSTEIN
.1u F 1pF
C2 0 C1 2 5
1p F
C1 26
DATE:
+5VA
24−Oc t−2005SIZE:
SHEET:3
TSW3000
ti
TP1 2
FB18
C72
1
(1 −2 )
W2
+5VA
OF:
7
REV:A
12500 TI Boulevard. Dallas, Texas 75243
.1 uF
C8 1
(No te 2)
(No te 1)
DOCUMENTCONTROL#
Title:
0
(Note 2)
L1 7
(No te 2 )
(Note 1 )
C6 6
2
LOCAL_OSC LOCAL_OSC(SH 7 )
R11 9
274
FB17 +5VA
.1uF
C2 6
R1 22
18.2
R1 21
274
RFOUT 8
1
GND
QVIN
13
R23 8
2
GND
GND
12
VCM
3
GND
GND
11
R1 7 9
R1 8 3
100
10 0
(No te 1 ) (No te 1 )
4
LO
VCC
2
3
4
5
2
3
4
5
5
GND
GND
9
10
1
TSW3000 Demo Kit
3
42
2
3
4
5
+3.3VA
J9
SMA
REFOUT
www.ti.com
Layers and Schematics
Figure 25. Schematic - Page 3
SLWU013B – March 2004 – Revised November 2005
1
2
+
4 R6
C8 9
J6
SMA END
1
56 0 p F .1u F
C11 0
TOYOCOM
211 5 −4 91 .5 2 MHZ
6
R9 0
OUT_B 5
OUT
V_CTRLVCC
EN
GND
0
C3 6
.1 u F
C4 5
82.5
R12 7
82.5
R1 26
13 0
13 0
0
(Note 1 )
R1 0
R1 2 8
+3.3VCLK
VBB
0
(No te 1 )
R14
43
42
14
33
1
37
28
J2
SMA END
1
OUT CLK1
VCXO_IN
VCXO_ INB
(Sh 1 , 2 )RESET RESET
R1 2 9
.1 u F
CDC_REF
(Sh 2)CDC_PD CDC_PD
(Sh 5 ) CTRL_CLK
29
CTRL_LE
CTRL_DATA
CTRL_CLK
(Sh 5 ) CTRL_LE
(Sh 5 )CTRL_DATA
26
36
(Sh 2 )REF_SEL
REF_SEL 35
REF_IN
+3.3VCLK
C88 10 0 0 p F
R7
1K
(Note 1 )
U1 0
VCXO1
CDC_PD
REF_OSC
1. DO NOT INSTALL
NOTES:
10 u F, 1 0V
C99
+3.3VCLK
V_CTRL
(No te 1 )
R1 24 0
3
(Sh 7 REF_OSC
)
R1 4 9
10 K
R1 5 1
10 K
J3
SMA END
1
OUT CLK2
5
4
3
2
5
4
3
2
SLWU013B – March 2004 – Revised November 2005
5
4
3
2
+3.3VCLK
/VCXO_IN
R1 8
22.1
R1 6
22.1
R20
10 0
+3.3VCLK
R19
10 0
+3.3VCLK
VCXO_IN
VBB 40
R2 2
100
R2 1
10 0
Y1A
.1 u F
C9 0
.1 u F
C8 7
Y4B
Y4A
Y3B
Y3A
Y2B
Y2A
Y1B
75 0
75 0
R2 6
R3 8
15 0
(No te 1 )
Y3
R3 3
15 0
(No te 1 )
Y4
17
16
12
24
GND
AVCC
AVCC
AVCC
AVCC
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
27
30
32
38
39
2
5
6
9
10
13
15
18
19
20
21
41
44
45
48
82.5 82.5 82.5 82.5
150 150
U12 B
CDCM7005
R1 61 R1 62 R1 63 R1 64
R2 21 R1 5
C1 01 C4 9
C2 2
.1uF
.1u F
C11 4
FERRITE
10u F
+
.1uF
FB14
10u F
C5 8
R1 71 0
8
11
CLK1B
R11 4 0
.1 uF
C7 3
.1 uF
C6 9
C1 00
C1 20
TSW3000
ti
DEWONCK
V_CTRL
24−Oct−2005SIZE:
SHEET: 4 OF:
REV:
7
A
12500 TI Boulevard. Dallas, Texas 75243
.47 uF
DATE:
Title:
.001 u F .1 u F
C11 9
+3.3VCLK
1uF
C9 2
DOCUMENTCONTROL#
.1u F
R1 4 2
162
C9 1
Drawn By:Y.
FILE:
.1uF
22u F
C9 6
C11 5
+
R1 41
4.7 5 K
Engineer:R. HOPPENSTEIN
.01u F .0 01 uF
C1 3 1
AVCC
.1 uF
C11 3
(Sh 1)
(Sh 1)
C11 2
CLK1CB
CLK1B
C1 04 C1 22
.1uF
(Sh 1)
D3
CLK2CB (Sh 1)
CLK2B
D2
.01u F .1uF
C7 1
CLK1CB
CLK2CB
R11 0 0
7
D1
4
+
CDC_REF CDC_REF (SH 7)
CP_OUT
75 0
R2 4
CDC_LCK(Sh 5 )
R2 3
CDC_LCK
R1 09
0
(No te 1 )
CLK2B
130 13 0 130 13 0
R1 5 2 R1 53 R1 5 4 R1 56
R1 7 2 0
VBB
+3.3VCLK
3
YOA 46
YOB 47
CP_OUT 31
STATUS_REF23
STATUS_VCXO22
PLL_LOCK 25
U12 A
CDCM7005
/RESET/HOLD
VCC_CP
/PD
SEC_REF
CTRL_CLK
CTRL_DATA
CTRL_LE
PRI_REF
REF_SEL
CLOCK DISTRIBUTION
www.ti.com
Layers and Schematics
Figure 26. Schematic - Page 4
TSW3000 Demo Kit
43
44
TSW3000 Demo Kit
SDEN2
SDIO
DATA
CLK
SDEN1
CDC_LCK
R2 2 8
(No te 1 )
0
PLL_DATA (SH 7 )
PLL_CLK (SH 7)
PLL_LCK (SH 7)
CDC_LCK (Sh 4 )
PLL_DATA
PLL_CLK
PLL_LCK
NOTES:
1. DO NOT INSTALL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
J1
DB25F−RA
10 K
10 K
10 K
R3 6
R3 7
R1 7
R2 47
0
10 K
10 K
R3 5
R15 5
10 K
R3 4
R3
(No te 1 )
0
R2 29
10
7
4
1
12
9
5
2
10
17
15
13
11
8
6
4
2
1
GND
2OE
1OE
3OE
4OE
4Y
3Y
4A
3A
1Y
VCC
3
5
7
9
12
14
16
18
19
20
2Y
U1 3
SN74LV12 5 AD
2Y4
2Y3
2Y2
2Y1
1Y4
1Y3
1Y2
1Y1
OE2
VCC
2A
1A
GND
2A4
2A3
2A2
2A1
1A4
1A3
1A2
1A1
OE1
U4
SN7 4HC2 41 DW
10
13
11
8
6
3
14
+3.3VA
C2 1
10 K
10 0
FILE:
Drawn By:
Engineer:
SDEN1
SCLK
SDIO
Y. DEWONCK
R. HOPPENSTEIN
DATE:
24−Oc t−2005
SIZE:
TSW3000
SHEET:
5 OF:
REV:
CTRL_LE
CTRL_DATA
CTRL_CLK
12500 TI Boulevard. Dallas, Texas 75243
ti
10p F
C1 28
CTRL_CLK
CTRL_DATA
DOCUMENTCONTROL#
Title:
(SH 7)
10p F
C1 2 7
10 p F
C6 1
100 K
R3 2
+3.3VA
(Sh 1)
(Sh 1)
(Sh 1)
PLL_LE
10 0 K
R3 1
+3.3VA
10 0
100 K
R3 0
+3.3VA
+3.3VA
10 0
PLL_LE
R2 9
R2 7
R2 8
C2 8
.1u F
+3.3VA
10 p F
C9 7
R2 48
SDEN1
SCLK
SDIO
.1 uF
(Sh 4 )
7
A
(Sh 4 )
(Sh 4)
www.ti.com
Layers and Schematics
Figure 27. Schematic - Page 5
SLWU013B – March 2004 – Revised November 2005
SLWU013B – March 2004 – Revised November 2005
3
4
GND/HSINK
GND/HSINK
GND/HSINK
19
20
9
10
NC
GND/HSINK
GND/HSINK
13
OUT
GND/HSINK 12
GND/HSINK 11
OUT
14
8
6
IN
7
5
4
3
2
GND/HSINK 20
19
GND/HSINK
GND/HSINK
18
GND
U6
NC
17
NC
NC
TPS76 7 5 0 QPWP
EN_
RESET_ 16
IN
FB/NC 15
GND/HSINK
GND/HSINK
GND/HSINK 11
13
OUT
GND/HSINK 12
18
NC
U7
17
TPS7 6 7 3 3QPWPNC
RESET_ 16
15
FB/NC
14
OUT
GND/HSINK
NC
IN
IN
EN_
NC
GND
GND/HSINK
1
10
9
8
7
6
5
NOTES:
1. DO NOT INSTALL
.1 uF
C44
+6V
.1u F
C4 3
+6V
1
2
R11 3
10 0 K
10 0 K
R1 3 0
C11 7
C5 1
10 u F, 10 V
+
10 u F, 1 0V
+
AVDD
FB1
FB6
FB7
FB10
FB3
C1 24
.0 1u F
1u F
47 u F
47u F
+ C1 60
C2 7
.01u F
C6 4
.01u F
C7 0
47 u F
+
C7 4
47 u F
+
+3.3VCLK
+5V_PLL
C6 0
1uF
C5 4
10u F, 10V .1 uF
+ C11 6
+5VA
1uF
C5 0
R1 81
0
(No te 1 )
+6V
C1 09
C1 5 9
47 uF
+
.01 uF
1u F
+
C6 7
+3.3VPLL
C57
C4 7
+3.3VA
.1uF
C4 8
+6V
3POS−POWER−JACK
J12 1
2
3
J17
FB13
BLACK
RED
J11
6V
1
10
9
FILE:
Drawn By:Y.
DEWONCK
ti
TSW3000
DATE:
24−Oc t−2005 SIZE:
SHEET:
C1 0 5
REV:
6 OF: 7
A
47u F
+
15.8 K
R4 1
.01 u F
C1 02
+6V
12500 TI Boulevard. Dallas, Texas 75243
10 u F, 10 V
+
+1.8VD
1u F
C5 3
C1 2 1
10 0K
R1 31
DOCUMENTCONTROL#
Title:
GND/HSINK 12
11
GND/HSINK
Engineer: R. HOPPENSTEIN
GND/HSINK
GND/HSINK
OUT
13
NC
8
7
6
5
17
NC TPS7 67 01 QPWP NC
EN_
RESET_ 16
15
IN
FB/NC
IN
OUT 14
GND
GND/HSINK
GND/HSINK 20
19
GND/HSINK
18
U8
NC
GND/HSINK
47u F
+ C25
FB11
4
3
2
6V
R4 2
30 .1 K
www.ti.com
Layers and Schematics
Figure 28. Schematic - Page 6
TSW3000 Demo Kit
45
J8
REF INSMA
PLL_DATA
(SH 5PLL_DATA
)
(SH 5 ) PLL_LE PLL_LE
(SH 5 )PLL_CLK PLL_CLK
0
R13 3
TCXO_OUT
REF_OSC
0
.1 u F
+
C78
.1 u F
1
4
13
LE
R1 9 6
10 K
R2 45
0
(No te 1 )
10 K
R11 6
10 K
R11 5
C82
3
2
1
FB4
IN−
4
5
10u F, 1 0V
VS+
R2 26
1K
R1 45
0
475
R11 7
10 0 pF
C1 3 2
20 K
R1 36
.1uF
C1 06
0
C1 33
C1 41
82p F
10K
R1 99
R2 18
10K
10u F, 1 0 V
+3.3VA
+ C1 5 6
+3.3VPLL
1
3
4
5
6
2
(Note 1)
2.2n H
GND
GND
GND
GND
N/C
VT
D4
(No te 1 )
R1 23 475
R11 8 47 5
(No te 1 )
+3.3VPLL
C1 4 2
33p F
(No te 1 )
Y3
ROS−2 170 −7
5.62
10u F, 1 0V
C3 5
R1 37
+
100 pF
10p F
.1 uF
C1 35
C111
C7 9
+5V_PLL
RFOUT 10
GND 16
GND 15
GND 12
GND 11
GND 13
FB2
SM_ LED_1 20 6
L19 100 pF
R2 32
E2
PLL_LCK PLL_LCK(SH 6)
(Note 1)
C1 52
.1uF
100 p F
TP1 8
4.75 K
R1 25
100 0pF
C1 37
RSET
3.92 K
R1 35
C1 40
.0 1u F
C1 30
+3.3VPLL
RFINB 5
C8 3
+
THS4 22 1
IN+
VOUT
U1 8
VS−
1
MUXOUT 14
R2 2 7
2K
CP
2
16
RFINA 6
U14
TRF37 50
VP
RSET
10 p F
.1 u F
10 0p F .1 uF
C136
LE
DATA
CLK
REFIN
CE
C1 08
10 p F
+3.3VPLL
12
11
8
10
DATA
CLK
TP1 9
R4 4
1K
(No te 1 )
C1 3 9 10 00 p F
OSC−VECTRON
Y2
+3.3VA
R1 9 5
10 K
C8 0
2
3
R1 4 4
NOTES:
1. DO NOT INSTALL
2. OPTIMIZED VALUES FOR 2 GHz OPERATION
(SH 4 ) REF_OSC
R1 8 2
0
(No te 1 )
R2 0 1
0
(No te 1)
20 0
R1 3 4
1
20 0
R1 3 2
0
C1 2 9
10u F, 1 0V
+3.3VPLL
FB9
R4 7
10p F
PLL_PWD
C10 7
C7 6
.1 u F
CDC_REF R48 0
(No te 1 )
TCXO_OUT
(SH 2 ) PLL_PWD
(SH 4 ) CDC_REF
+
10 u F, 10 V
C1 23
C1 58
C1 5 1
CPGND
3
FB8
10 u F, 1 0V
+
7
AVDD
AGND
4
+3.3VA
5
4
3
2
15
DVDD
DGND
9
14
VCC
GND
GND
GND
C1 61
100
R1 40
27.4
R1 39
R1 38
5.62
22p F
W6
1
(No te 2 )
R11 2
825
C1 48
+5V_PLL
FENCE7
FILE:
Drawn By:
Y.
DEWONCK
Engineer:R. HOPPENSTEIN
C14 9
1p F (Note 1 )
0
R1 78
FENCE6
1
R2 02
0
(No te 1 )
0
R2 25
TSW3000
ti
DATE:
J10
SMA
C14 6
22p F
24−Oc t−2005SIZE:
SHEET:
7 OF: 7
REV: A
12500 TI Boulevard. Dallas, Texas 75243
DOCUMENTCONTROL#
Title:
3
C14 4
1uF
(No te 2 )
L1 8
080 5CS−2 2 0 X_ B_
22 p F
U1 5
SGA−53 8 6 (No te 2 )
R1 47
47.5
R1 46
47.5
(SH 3)LOCAL_OSC LOCAL_OSC
C9 8
R1 48
5.62
R111
825
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
7
8
9
4
2
TSW3000 Demo Kit
2
3
4
5
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
+5V_PLL
FB12
C1 4 7
10 00 p F
www.ti.com
Layers and Schematics
Figure 29. Schematic - Page 7
SLWU013B – March 2004 – Revised November 2005
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