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Texas Instruments ADS5553 EVM User guides
ADS5553 EVM User Guide
User's Guide
February 2005
SLWU021
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Chapter 1
SLWU021 – February 2005
Overview
This User’s Guide document gives a general overview of the ADS5553 evaluation module (EVM), and
provides a general description of the features and functions to be considered while using this module.
1.1
Purpose
The ADS5553 EVM provides a platform for evaluating the ADS5553 dual 14 bit analog-to-digital converter
(ADC) under various signals, references, and supply conditions. This document should be used in
combination with the EVM schematic diagram supplied.
1.2
EVM Basic Functions
Analog inputs to the ADC are provided via external SMA connectors. The single-ended input the user
provides is converted into a differential signal at the input of the device for both channels. Both analog
input channels of the ADS5553 EVM have two independent paths. One input path uses a differential
amplifier, while the other path is transformer coupled.
The EVM provides an external SMA connector for input of the ADC clock. The single-ended input the user
provides is transformer coupled to provide a differential signal at both clock inputs of the device. The EVM
also allows the user to send a single-ended or true differential clock if desired.
Digital output from the EVM are via two 40-pin connectors. The digital outputs from the ADC are buffered
before going to the connectors.
Power connections to the EVM are via banana jack sockets. Separate sockets are provided for the ADC
analog and output driver supplies, external buffers supply, and differential amplifiers supply.
1.3
Power Requirements
The EVM can be powered directly with only a single +3.3V supply if using the module with transformer
coupled input and internal reference mode. ±5V is required if using the differential amplifier input.
Provision has also been made to allow the EVM to be powered with independent supplies to provide
higher performance.
1.3.1
Voltage Limits
Exceeding the maximum input voltages can damage EVM components. Under voltage may cause
improper operation of some or all of the EVM components.
1.4
ADS5553 EVM Operational Procedure
The ADS5553 EVM provides a flexible means of evaluating the ADS5553 in a number of modes of
operation. A basic set-up procedure that can be used as a board confidence check is as follows:
1. Verify all jumper settings against the schematic jumper list in the following tables:
SLWU021 – February 2005
Overview
3
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ADS5553 EVM Operational Procedure
Table 1-1. Two Pin Jumper List
JUMPER
FUNCTION
INSTALLED
REMOVED
DEFAULT
SJP4
N/A
SJP5
N/A
W3
Reserved
N/A
N/A
Installed
W6
Reserved
N/A
N/A
Removed
W7
Reserved
N/A
N/A
Installed
Removed
Installed
Table 1-2. Three Pin Jumper List
JUMPER
FUNCTION
LOCATION: PINS 1-2
LOCATION: PINS 2-3
DEFAULT
SJP1
Common mode voltage path
Provide Common mode voltage to CHA Differential Amplifier
Provide Common mode voltage to Transformer T1
2-3
SJP3
Common mode voltage path
Provide Common mode voltage to CHB Differential Amplifier
Provide Common mode voltage to Transformer T2
2-3
W2
Channel A output enable
Outputs enabled
Outputs disabled
1-2
W10
Channel B output enable
Outputs enabled
Outputs disabled
1-2
W8
Common mode source
Selects ADS5553 channel A
common mode source
Selects External common
mode source
1-2
W9
Common mode source
Selects ADS5553 channel B
common mode source
Selects External common
mode source
1-2
SJP6
Reset polarity select
Used with active low ADC reset
Used with active high ADC
reset
2-3
SJP8
U7 operation
Register
Buffer
2-3
SJP9
CLKOUTA path
Series resistor
Input to U7
2-3
SJP10
U10 operation
Register
Buffer
2-3
SJP11
CLKOUTB path
Series resistor
Input to U10
2-3
2. Connect supplies to the EVM as follows:
+3.3V ADC output buffer supply to J17 and return to J18.
+3.3V ADC analog supply to J11 and return to J10.
3. Switch power supplies on.
4. Use a function generator with 50-Ω output to input a 65-MHz, 0-V offset, 1-Vrms sine wave signal into
J3. The frequency of the clock must be within the specification for the device speed grade.
5. Use frequency generators with a 50-Ω output to provide a 30-MHz, 0-V offset, -1-dBFS amplitude sine
wave signals into J15 and J16. This will provide a transformer coupled differential input signal to both
channels of the ADC. A full scale input tone into channel A or channel B is 2.2Vpp and dBFS can be
calculated by using the following formula:
captured max code captured min code
dBFS 20 log
, where N is the number of bits.
2N
6. The digital patterns on output connectors J8 and J21 should now represent a 2's compliment sine
wave and can be monitored using a logic analyzer.
4
Overview
SLWU021 – February 2005
Chapter 2
SLWU021 – February 2005
Circuit Description
2.1
Schematic Diagram
The schematic diagram for the EVM is attached to the end of this document.
2.2
Circuit Function
The following paragraphs describe the function of individual circuits. Refer to the relevant data sheet for
device operating characteristics.
2.2.1
Analog Inputs
The EVM can be configured to provide the ADC with either transformer-coupled or differential amplifier
inputs from a single-ended source. The inputs are provided via SMA connectors J15 and J16 for
transformer coupled input, and J1, J2, J7 and J9 for differential amplifier input. To setup for one of these
options, the EVM must be configured as follows:
1. For a 1:1 transformer coupled input to the ADC, a single ended source is connected to J15 for channel
A and J16 for channel B. R43, R45, R49, and R61 must be removed. C107, C108, R80, and R81
provide the user with the option to add filters if desired. This is the default configuration for the EVM.
2. For single-ended inputs into the differential amplifiers, sources are connected to J2 for channel A and
J9 for channel B. R43, R45, R49, and R61 must be installed. Surface mount jumpers, SPJ1 and SPJ2
must be configured such that pins 1 and 2 are shorted. Supply power to the differential amplifiers by
connecting +5V to J14, -5V to J13 and connect the return to J12.
3. For a differential input into the amplifiers, the positive source of channel A is connected to J2 and the
negative source to J1. The positive source of channel B is connected to J9 and the negative source to
J7. R43, R45, R49, and R61 must be installed, and R74, R75, R78 and R79 removed. R19 and R22
must be replaced with 383 Ohm resistors, and R12 and R14 must be replaced with 54.9 Ohm resistors
for proper termination. Surface mount jumpers, SPJ1 and SPJ2 must be configured such that pins 1
and 2 are shorted. Supply power to the differential amplifiers by connecting +5V to J14, -5V to J13 and
connect the return to J12.
2.2.2
Clock Inputs
The EVM provides the clock inputs for both channels using a single-ended source. To provide a
transformer-coupled differential clock to both channel clock inputs, simply provide a clock source to SMA
J3.
2.2.2.1
True Differential ADC Clock
To provide a true differential ADC clock input, install J4, R11 and R25, and replace R31 with a 49.9 Ohm
resistor, and remove T3. The positive source should be connected to J3 and the negative source to J4.
2.2.3
Control Inputs
The EVM has two discrete inputs to control the operation of the device:
SLWU021 – February 2005
Circuit Description
5
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Circuit Function
2.2.3.1
Output Enables
With jumper W2 installed between pins 1 and 2, channel A of the ADC is enabled. This channel is
disabled with the jumper installed between pins 2 and 3. With jumper W10 installed between pins 1 and 2,
channel B of the ADC is enabled. This channel is disabled with the jump installed between pins 2 and 3.
2.2.3.2
IREF Control
By adjusting the resistance on R4, the user can adjust the bias current used by the ADS5553 device. The
default value for the EVM is 56.2 kΩ. Care must be taken when changing this value. See the relevant data
sheet for more information.
2.2.4
Power
Power is supplied to the EVM via banana jack sockets. A separate connection is provided for a +3.3V
analog supply (J11 and J10), +3.3V driver supply and external buffer supply (J17 and J18), and ±5V
amplifier supply (J14, J13, and J12).
2.2.5
Outputs
The data outputs from the ADC are buffered using two Texas Instrument's SN74AVC16244s. Output data
headers J8 and J21 are standard 40-pin headers on a 100-mil grid, and allow easy connection to a logic
analyzer. The connector pinout is listed in Table 2-1.
Table 2-1. Output Connector J8/J21
J8 PIN
6
DESCRIPTION
J8 PIN
DESCRIPTION
1
OUTPUT CLOCK
21
DATA BIT 6
2
GND
22
GND
3
NC
23
DATA BIT 7
4
GND
24
GND
5
NC
25
DATA BIT 8
6
GND
26
GND
7
NC
27
DATA BIT 9
8
GND
28
GND
9
DATA BIT 0 (LSB)
29
DATA BIT 10
10
GND
30
GND
11
DATA BIT 1
31
DATA BIT 11
12
GND
32
GND
13
DATA BIT 2
33
DATA BIT 12
14
GND
34
GND
15
DATA BIT 3
35
DATA BIT 13 (MSB)
16
GND
36
GND
17
DATA BIT 4
37
OVERFLOW
18
GND
38
GND
19
DATA BIT 5
39
NC
20
GND
40
GND
Circuit Description
SLWU021 – February 2005
Chapter 3
SLWU021 – February 2005
Parts List
Table 3-1 lists the parts used in constructing the EVM
Table 3-1. Bill of Materials for ADS5553
VALUE
QTY
PART NUMBER
VENDOR
REF DES
NOT INSTALLED
47 uF, tantalum, 20%, 10V
5
ECS-T1AD476R
Panasonic
C19 C21 C75 C81
C82
10 uF, 10V, 20% Capacitor
5
ECS-T1AX106R
Panasonic
C23 C27 C83 C87
C88
10 uF, 10V, 10% Capacitor
4
T491A106K010AS
KEMET
C12 C20 C22 C26
6.8pF,50V, +/- .25pF Capacitor
0
08055A6R8CAT2A
AVX
470 pF,100V, 10% Capacitor
8
ECJ-1VB2A471K
Panasonic
0.047uF,16V, 10% Capacitor
0
ECJ-1VB1C473K
Panasonic
C50 C51
10 pF, 50V, +/- .5pF Capacitor
0
ECJ-1VC1H100D
Panasonic
C102 C103
0.01uF, 50V,10% Capacitor
6
ECJ-1VB1C103K
Panasonic
C94 C95 C96 C97
C104 C105
C55
0.1uF,16V, 10% Capacitor
24
ECJ-1VB1C104K
Panasonic
C1 C13 C14 C15
C25 C30 C40 C58
C60 C62 C64 C65
C66 C70 C73 C74
C80 C84 C85 C86
C89 C91 C92 C93
C24 C29
C41-C44
C67 C113
1uF, 6.3V,10% Capacitor
4
ECJ-1VB0J105K
Panasonic
C78 C79 C114 C115
C53
2.2uF, 6.3V,+/- 80%/-20% Capacitor
0
ECJ-1VF0J225Z
Panasonic
2 pF, 25V, +/-0.25 pF Capacitor
2
ECJ-1VC1H020C
Panasonic
C16 C17
0.1uF,16V, +/- 80%/-20% Capacitor
11
ECJ-0EF1C104Z
Panasonic
C2-C11 C28
10 pF, 50V, +/- 0.5pF Capacitor
2
ECJ-0EC1H100D
Panasonic
0 Ohm resistor, 1/16 W, 1 %
2
ERJ-6ENF0R00V
Panasonic
R12 R14
54.9 Ohm resistor, 1/16 W, 1 %
2
ERJ-6ENF54R9V
Panasonic
R82 R83
383 Ohm resistor, 1/16 W, 1 %
2
ERJ-6ENF3830V
Panasonic
R28 R33
392 Ohm resistor, 1/16 W, 1 %
4
ERJ-6ENF3920V
Panasonic
R35 R36 R40 R41
412 Ohm resistor, 1/16 W, 1 %
2
ERJ-6ENF4120V
Panasonic
R19 R22
0 Ohm resistor, 1/16 W, 1 %
5
Panasonic
R31 R42 R59 R94
R102
1 Ohm resistor, 1/16 W, 5 %
4
9C0603A1 JLHFT
Panasonic
R10 R37 R55 R93
100 Ohm resistor, 1/16 W, 1%
0
ERJ-3EKF1000V
Panasonic
CAPACITORS
C46 C47
C48
C98 C99
C100 C101
C57 C59 C61 C63
C109 C110 C111
C112
C33 C34
C56
C107 C108
RESISTORS
SLWU021 – February 2005
R11 R25
R38 R39
R56 R57
R58 R65
R23 R24
Parts List
7
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Circuit Function
Table 3-1. Bill of Materials for ADS5553 (continued)
VALUE
QTY
PART NUMBER
VENDOR
REF DES
36.5 Ohm resistor, 1/16 W, 1%
4
ERJ-3EKF36R5V
Panasonic
R72 R73 R76 R77
49.9 Ohm resistor, 1/16 W, 1%
1
ERJ-3EKF49R9V
Panasonic
R30
200 Ohm resistor, 1/16 W, 1%
0
ERJ-3EKF200V
Panasonic
R32
1K Ohm resistor, 1/16 W, 1%
0
ERJ-3EKF1001V
Panasonic
R95 R96
R97 R98
10K Ohm resistor, 1/16 W, 1%
1
ERJ-3EKF1002V
Panasonic
2K Ohm resistor, 1/16 W, 1%
0
ERJ-3EKF2001V
Panasonic
49.9K Ohm resistor, 1/16 W, 1%
1
ERJ-3EKF4992V
Panasonic
4.99K Ohm resistor, 1/16 W, 1%
0
56.2K Ohm resistor, 1/16 W, 1%
1
ERJ-3EKF5622V
Panasonic
174 Ohm resistor, 1/16 W, 1 %
0
ERJ-2RFK1740X
Panasonic
R80 R81
1K VARIABLE RESISTOR
0
CT94W102
CERMET
R17 R18
0 Ohm R-Pack
4
742C163000JCT
CTS
R99
NOT INSTALLED
R7 R13
R20 R21
R60
R15 R26
R27 R29
R51
Panasonic
R50 R52
R16 R34
R4
RP7 RP8 RP9 RP10
RP1 RP2
RP3 RP6
FB1 FB2 FB3 FB5
FB6
FB4
CONNECTORS, JUMPERS, HEADERS, FERRITE BEADS, TRANSFORMERS, ICS
8
Ferrite Bead
5
EXC-ML32A680U
Transformer
2
ADT1-1W T
Mini-Circuits
T1 T2
Transformer
1
ADT4-1WT
Mini-Circuits
T3
SMA connectors
7
2262-0000-09
NEWARK
J1 J2 J3 J7 J9 J15
J16
Black test point
3
5011K-ND
Keystone
TP1 TP3 TP4
RED test point
0
5010K-ND
Keystone
2POS_header
3
TSW-150-07-L-S
Samtec
W3 W6 W7
3POS_header
4
TSW-150-07-L-S
Samtec
W2 W8 W9 W10
SWITCH
1
EVQ-PJX04M
Panasonic
S1
40 pin IDC Connector
1
TSW-120-07-L-D
Samtec
J8 J21
10 pin IDC Connector
0
TSW-120-07-L-D
Samtec
Red Banana Jacks
4
ST-351A
ALLIED
J11 J13 J14 J17
Black Banana Jacks
3
ST351B
ALLIED
J10 J12 J18
ADS5553
1
ADS5553
Texas Instruments
U1
THS4503
2
THS4503
Texas Instruments
U2 U9
OPA2227UA
0
OPA2227UA
Texas Instruments
TPS79225
0
TPS79225
Texas Instruments
SN74AVC16244
2
SN74AVC16244DGG
Texas Instruments
SCREWS
4
Plastic Stand Off Hex (1/4 x .5")
4
1902CK-ND
ALLIED
Parts List
J4 J5
TP6 TP7
J6
U3
U4
U7 U10
SLWU021 – February 2005
Chapter 4
SLWU021 – February 2005
Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM and lists the components
used on the module.
4.1
PCB Layout
The EVM is constructed on a 6-layer, 6.0-inch x 5.1-inch, 0.062-inch thick PCB using FR-4 material. The
individual layers are shown in the diagrams attached to the end of this document.
Figure 4-1. Top Layer
SLWU021 – February 2005
Physical Description
9
www.ti.com
PCB Layout
Figure 4-2. Layer 2, Ground Plane
10
Physical Description
SLWU021 – February 2005
www.ti.com
PCB Layout
Figure 4-3. Layer 3, Power Plane #1
SLWU021 – February 2005
Physical Description
11
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PCB Layout
Figure 4-4. Layer 4, Power Plane #2
12
Physical Description
SLWU021 – February 2005
www.ti.com
PCB Layout
Figure 4-5. Layer 5, Ground Plane
SLWU021 – February 2005
Physical Description
13
www.ti.com
PCB Layout
Figure 4-6. Layer 6, Bottom Layer
14
Physical Description
SLWU021 – February 2005
1
2
3
VDD
+
C22
C4
C2
C3
10uF
.1uF
.1uF
.1uF
C7
C10
C11
C8
.1uF
.1uF
.1uF
.1uF
4
5
6
VDD_OBUFFER
C9
C6
C28
C5
.1uF
.1uF
.1uF
.1uF
+
C26
10uF
D
D
OVRA
2
(Sh 2)
INMA
(Sh 2)
INPA
SJP5
OVRA
1
(INSERT)
INMA
INPA
1
(1-2)
W8
R93
REFPA
.1uF
C114
C115
1uF
1uF
1
1
VDD
R94
0
2
(Note 1)
C24
R37
REFMB
.1uF
R55
REFPB
C79
C78
1uF
1uF
CLKPA
CLKMA
(Sh 5) CLKPA
(Sh 5) CLKMA
IREF
SJP4
1
(OPEN)
1
1
CLKPB
CLKMB
(Sh 5) CLKPB
(Sh 5) CLKMB
(Sh 2)
CMB
CMB
W9
2
EXT_REFB
D4A
D3A
DRVSS
DRVDD
D2A
D1A
D0A
CLKOUTA
OEA
Reserved
Reserved
Reserved
OEB
CLKOUTB
OVRB
D13B
D12B
D11B
DRVDD
DRGND
U1
ADS5553
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
DA4
DA3
2
C
W2
(1-2)
DA2
DA1
DA0
CLKOUTA
SEN
SCLK
SDATA
CLKOUTB
OVRB
CLKOUTA
SEN
SCLK
SDATA
(Sh 3)
(Sh 6)
(Sh 6)
(Sh 6)
CLKOUTB (Sh 4)
(Sh 4)
OVRB
VDD_OBUFFER
2
W10
(1-2)
(1-2)
3
EXT_REFB
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
3
(Sh 7)
CMA
AVSS
CLKPA
CLKMA
AVSS
REFMA
REFPA
AVDD
AVDD
IREF
AVDD
AVSS
AVDD
REFMB
REFPB
AVSS
CLKPB
CLKMB
AVSS
CMB
3
R10
REFMA
(Sh 3)
1
C113
AVDD
AVSS
INMB
INPB
AVSS
AVDD
PIN CONFIGURE
D0B
D1B
D2B
D3B
D4B
DRVSS
DRVDD
D5B
D6B
D7B
D8B
D9B
D10B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
3
(Note 1)
DA[0..13]
VDD_OBUFFER
2
EXT_REFA
EXT_REFA
1
C
(Sh 7)
AVDD
AVSS
INPA
INMA
AVSS
AVDD
AVSS
AVDD
OVRA
D13A
D12A
D11A
D10A
D9A
DRVSS
DRVDD
D8A
D7A
D6A
D5A
CMA
CMA
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
DA[0..13]
(Sh 2)
(Sh 3)
DA13
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
B
B
(Sh 2)
INMB
(Sh 2)
INPB
INMB
INPB
VDD_OBUFFER
IREF
VDD_OBUFFER
R65
0
3
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
10K
S1
2
SJP6
SW-PB
R60
1
(1-2)
(Note 1)
C29
R4
R99
C30
10K
.1uF
A
56.2K
DB[0..13]
DB[0..13]
.1uF
(Note 1)
ti
12500 TI Boulevard. Dallas, Texas 75243
(Sh 4)
Title:
Note 1. Part not installed
Engineer:
Drawn By:
J. SETON
Y. DEWONCK
SIZE:
ADS5553
DATE:
17-Jan-2005
FILE:
1
2
3
4
A
5
REV:
A
1
SHEET:
6
OF:
7
1
2
3
4
5
C99
6
(Note 1)
6.8pF
R36
R82
J2
392
+VCC
54.9
AINA+
U2
THS4503
383
NC
5
4
3
2
8
CMA
CMA
VOUT+
(Sh 1)
5
4
3
2
3
1
T1
3
.1uF
R74
4
2pF
5
4
3
2
2
5
1
C80
R35
C16
C
-VCC
0
INPUT_CMLA
J15
AIN_A
INPA
24.9
(Note 1)
-VCC
412
R12
R43
4
-
R19
1
R96
1K
(Note 1)
(2-3)
24.9
VOUT-
1
J1
AINA-
INMA
VOCM
6
1
2
SJP1
(Note 1)
R45
5
C94
VDD
.01uF
1K
D
.1uF
+VCC
+
2
(Note 1)
R95
3
7
C70
R28
1
D
(Note 1)
C102
R72
R73
10pF
36.5
36.5
INMA
24.9
C107
27pF
(Note 1)
R75
6
ADT1-1WT
392
INMA (Sh 1)
C98
R80
C
174
(Note 1)
6.8pF
INPA
(Note 1)
(Sh 1)
INPA
24.9
C104
C95
.01uF
.01uF
C101
(Note 1)
6.8pF
R41
R83
J9
392
+VCC
54.9
AINB+
5
4
3
2
8
B
2
CMB
CMB
1
J7
AINB-
(Sh 1)
1
1
T2
R14
5
4
3
2
2pF
B
VOCM
R61
4
-
24.9
(Note 1)
-VCC
412
0
INPB
-VCC
C84
.1uF
R78
6
2
3
INMB
24.9
VOUT-
R40
C17
5
+
R22
1
5
4
3
2
3
1
INPUT_CMLB
J16
AIN_B
(Note 1)
R49
5
VOUT+
R98
1K
(Note 1)
(2-3)
.1uF
+VCC
6
.01uF
1K
2
SJP3
NC
C96
VDD
3
U9
THS4503
383
(Note 1)
R97
7
C85
R33
1
(Note 1)
C103
R76
R77
10pF
36.5
36.5
4
ADT1-1WT
INPB
24.9
C108
27pF
(Note 1)
R79
392
INPB
(Sh 1)
R81
174
(Note 1)
INMB
C100
6.8pF
(Note 1)
INMB (Sh 1)
ti
24.9
A
C97
.01uF
C105
.01uF
12500 TI Boulevard. Dallas, Texas 75243
Title:
Engineer:
Note 1. Part not installed
Drawn By:
FILE:
1
2
A
3
4
5
J. SETON
Y. DEWONCK
ADS5553
DOCUMENTCONTROL #
DATE:
17-Jan-2005
REV:
SIZE:
6
SHEET:
2
OF:
A
7
1
2
3
(Sh 1)
4
OVRA
OVRA
DA13
DA12
DA11
DA10
DA9
DA8
DA7
D
DA6
DA5
DA4
DA3
DA2
DA1
DA0
0
2
(2-3)
SJP9
48
CLKOUTA
CLKOUTA
DA0
47
46
45
C
DA1
44
DA2
43
42
DA3
41
DA4
40
39
DA5
38
DA6
37
DA7
36
DA8
35
34
DA9
33
DA10
32
31
DA11
30
DA12
29
28
B
(Sh 1) DA[0..13]
DA13
DA[0..13]
16
15
14
13
12
11
10
9
OVR1_O
DAO13
DAO12
DAO11
DAO10
DAO9
DAO8
DAO7
(Note 1) RP2
0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DAO6
DAO5
DAO4
DAO3
DAO2
DAO1
DAO0
6
D
CA_OUT
(Note 1)
U7
SN74AVC16244DGG
3
2
1
1
(2-3)
(Sh 1)
(Note 1) RP1
0
1
2
3
4
5
6
7
8
R39
3
SJP8
5
27
26
25
2OEB
1OEB
1A1
1Y1
1A2
1Y2
GND
GND
1A3
1Y3
1A4
1Y4
VCC
VCC
2A1
2Y1
2A2
2Y2
GND
GND
2A3
2Y3
2A4
2Y4
3A1
3Y1
3A2
3Y2
GND
GND
3A3
3Y3
3A4
3Y4
VCC
VCC
4A1
4Y1
4A2
4Y2
GND
GND
4A3
4Y3
4A4
4Y4
3OEB
4OEB
1
2
R102
3
0
CA_OUT
DAO0
4
C
5
DAO1
6
DAO2
7
8
DAO3
9
DAO4
DRVDD
10
11
DAO5
12
DAO6
13
DAO7
14
DAO8
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
15
16
DAO9
17
DAO10
18
19
DAO11
20
DAO12
21
22
DAO13
23
OVR1_O
RP7
0
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
RP8
0
24
J8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
B
40PIN_IDC
DRVDD
C57
470pF
C58
.1uF
C59
470pF
C60
.1uF
C61
470pF
C62
.1uF
C63
470pF
C64
.1uF
+
C20
10uF
ti
A
A
12500 TI Boulevard. Dallas, Texas 75243
Title:
Note 1. Part not installed
Engineer:
Drawn By:
FILE:
1
2
3
4
5
J. SETON
Y. DEWONCK
ADS5553
DOCUMENTCONTROL #
DATE:
17-Jan-2005
REV:
SIZE:
6
SHEET:
3
OF:
A
7
1
2
3
(Sh 1)
4
DB6
DB5
DB4
DB3
DB2
DB1
DB0
3
SJP11
48
CLKOUTB
47
46
45
C
DB1
44
DB2
43
42
DB3
41
DB4
40
39
DB5
38
DB6
37
DB7
36
DB8
35
34
DB9
33
DB10
32
31
DB11
30
DB12
29
28
DB[0..13]
DB13
DB[0..13]
16
15
14
13
12
11
10
9
DBO6
DBO5
DBO4
DBO3
DBO2
DBO1
DBO0
D
CB_OUT
U10
SN74AVC16244DGG
3
2
1
1
DB0
(Sh 1)
(Note 1) RP6
0
1
2
3
4
5
6
7
8
6
0 (Note 1)
(2-3)
B
OVR2_O
DBO13
DBO12
DBO11
DBO10
DBO9
DBO8
DBO7
R38
2
(2-3)
(Sh 1) CLKOUTB
16
15
14
13
12
11
10
9
DB13
DB12
DB11
DB10
DB9
DB8
DB7
D
SJP10
(Note 1)RP3
0
1
2
3
4
5
6
7
8
OVRB
OVRB
5
27
26
25
2OEB
1OEB
1A1
1Y1
1A2
1Y2
GND
GND
1A3
1Y3
1A4
1Y4
VCC
VCC
2A1
2Y1
2A2
2Y2
GND
GND
2A3
2Y3
2A4
2Y4
3A1
3Y1
3A2
3Y2
GND
GND
3A3
3Y3
3A4
3Y4
VCC
VCC
4A1
4Y1
4A2
4Y2
GND
GND
4A3
4Y3
4A4
4Y4
3OEB
4OEB
1
2
R42
3
0
CB_OUT
DBO0
4
C
5
DBO1
6
DBO2
7
8
DBO3
9
DBO4
DRVDD
10
11
DBO5
12
DBO6
13
DBO7
14
DBO8
RP9
0
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
15
16
DBO9
17
DBO10
18
19
DBO11
20
DBO12
21
22
DBO13
23
OVR2_O
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
RP10
0
24
J21
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
B
40PIN_IDC
DRVDD
C109
470pF
C86
.1uF
C110
470pF
C91
.1uF
C111
470pF
C92
.1uF
C112
470pF
C93
.1uF
+
C12
10uF
ti
A
A
12500 TI Boulevard. Dallas, Texas 75243
Title:
Note 1. Part not installed
Engineer:
Drawn By:
FILE:
1
2
3
4
5
J. SETON
Y. DEWONCK
ADS5553
DOCUMENTCONTROL #
DATE:
17-Jan-2005
REV:
SIZE:
6
SHEET:
4
OF:
A
7
1
2
3
4
5
6
D
D
1
J3
CLKB_INP
(Note 1)
R25
2
0
1
1
6
5
2
3
4
5
4
3
2
R30
C25
T3
49.9
J4
CLKB_INM
(Note 1)
R32
.1uF
200
(Note 1)
C40
CLKPA
CLKMA
ADT4-1WT
CLKPA
(Sh 1)
CLKMA
(Sh 1)
CLKPB
(Sh 1)
CLKMB
(Sh 1)
.1uF
R11
1
0
(Note 1)
5
4
3
2
R31
C1
0
R59
CLKPB
.1uF
0
C
C14
C
CLKMB
.1uF
B
B
ti
A
A
12500 TI Boulevard. Dallas, Texas 75243
Title:
Note 1. Part not installed
Engineer:
J. SETON
Drawn By:
Y. DEWONCK
FILE:
1
2
3
4
5
ADS5553
DOCUMENTCONTROL #
DATE:
17-Jan-2005
SIZE:
6
SHEET:
5
REV:
A
OF:
7
1
2
3
4
5
6
Diff Amp Positive Supply (+5.0V)
ADC Analog Supply (+3.3V)
+3.3VA-PS
VDD
D
C27
+
D
+
.1uF
C75
C65
+
C83
C66
J12
+
.1uF
.1uF
47uF
J10
47uF
10uF
BLACK
10uF
BLACK
Diff Amp Negative Supply (-5.0V)
-VCC
FB3
J13
C19
C15
+
RED
.1uF
47uF
C23
+
RED
C21
C13
RED
FB1
J11
+VCC
FB2
J14
10uF
FB4
(Note 1)
C
C
TP3
TP4
TP1
ADC Driver Supply (+3.3V)
ADC_BUFFER
VDD_OBUFFER
FB5
J17
RED
C89
C81
+
C87
C73
+
.1uF
.1uF
47uF
10uF
J18
BLACK
VDD_OBUFFER
(Note 1)
R50
(Note 1)
R51
49.9K
W3
DRVDD
(Sh 1)
FB6
C82
+
47uF
C88
J5
W7
SCLK
1
6
2
7
3
8
4
9
5
R57
SCLK
(Note 1)
R58
C74
+
10uF
(Note 1)
49.9K
W6
(Open)
Buffer Supply (+3.3V)
B
R52
49.9K
(Sh 1) SDATA
.1uF
(Sh 1)
SEN
SDATA
0
(Note 1)
B
DB9
0
R56
SEN
0
(Note 1)
ti
A
A
12500 TI Boulevard. Dallas, Texas 75243
Title:
Note 1. Part not installed
1
Engineer:
J. SETON
Drawn By:
Y. DEWONCK
FILE:
2
3
4
5
ADS5553
DOCUMENTCONTROL #
DATE:
17-Jan-2005
SIZE:
6
SHEET:
6
REV:
A
OF:
7
1
2
D
3
4
5
6
D
(Note 1)
R16
3
4.99K
R20
2
R23
5
100
10K
1K
1
+
C46
10uF
TP6
U3B
OPA2227UA
R17
R13
7
6
C41
C51
EXT_REFA
49.9
0.1%
.1uF
(Sh 1)
2K
.047uF
+VCC
R15
C
EXT_REFA
R27
C
2K
+VCC
10uF
2
2K
R18
C56
TPS79225
GND
2
2.2uF
1K
EN
BYPASS
4
C55
R21
10K
1uF
3
C43
C34
.1uF
470pF
R29
+2.5V
8
U4
5
R24
C44
C48
+
100
3
10uF
R7
1
2
-VCC
C42
C33
.1uF
470pF
R34
.01uF
4.99K
TP7
U3A
OPA2227UA
.1uF
4
+
C53
OUT
3
C47
IN
1
1
C50
EXT_REFB
49.9
0.1%
EXT_REFB (Sh 1)
R26
.047uF
2K
B
B
ti
A
A
12500 TI Boulevard. Dallas, Texas 75243
Title:
Note 1. Part not installed
1
Engineer:
J. SETON
Drawn By:
Y. DEWONCK
FILE:
2
3
4
5
ADS5553
DOCUMENTCONTROL #
DATE:
17-Jan-2005
SIZE:
6
SHEET:
7
REV:
A
OF:
7
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