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Texas Instruments DAC7631EVM User guides
User's Guide
SLAU148 – January 2005
DAC7631EVM
This user’s guide describes the DAC7631 evaluation module. It covers the operating
procedures and characteristics of the EVM board along with the device that it supports.
The physical PCB layout, schematic diagram, and circuit descriptions are included.
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Contents
Information about Cautions and Warnings ......................................................
Related Documentation from Texas Instruments...............................................
Questions about this or other Data Converter EVM's? ........................................
EVM Overview ......................................................................................
EVM Basic Functions ..............................................................................
PCB Design and Performance ....................................................................
EVM Operation......................................................................................
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List of Figures
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3
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10
DAC7631 EVM Block Diagram ................................................................... 4
Top Silkscreen ...................................................................................... 5
Layer 1 (Top Signal Plane) ........................................................................ 6
Layer 2 (Ground Plane) ............................................................................ 6
Layer 3 (Power Plane) ............................................................................. 7
Layer 4 (Bottom Signal Plane) .................................................................... 7
Bottom Silkscreen .................................................................................. 7
Drill Drawing ......................................................................................... 8
DAC7631EVM Default Jumper Setting ......................................................... 10
Digitally Programmable Current Source ....................................................... 13
List of Tables
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2
3
4
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6
7
8
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Parts List ............................................................................................. 9
DAC7631EVM Factory Default Jumper Setting ............................................... 10
DAC7631 Output Channel Mapping ............................................................ 11
Unity Gain Output Jumper Settings ............................................................. 12
Gain of Two Output Jumper Settings ........................................................... 12
Jumper Settings for a Gain of Five With Inverted Output .................................... 12
Digitally Programmable Current Source Configuration ....................................... 13
Jumper Setting Function ......................................................................... 14
DAC7631EVM
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Information about Cautions and Warnings
1
Information about Cautions and Warnings
This manual may contain cautions and warnings.
CAUTION
This is an example of a CAUTION statement.
A CAUTION statement describes a situtation that could potentially damage this
EVM board or your software or equipment.
WARNING
This is an example of a WARNING statement.
A WARNING statement describes a situtation that could potentially cause HARM
to you.
The information in a caution or a warning is provided for your protection. Read each caution and warning
carefully.
2
Related Documentation from Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas Instruments Literature Response
Center at (800) 477-8924 or the Product Information Center (PIC) at (972) 644-5580. When ordering,
identify this manual by its title and literature number. Updated documents can also be obtained through
the TI Website at http://www.ti.com.
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Data Sheets:
Literature Number:
DAC7631
SBAS122
OPA627
SBOS165
OPA2234
SBOS055
OPA703
SBOS180A
REF3025
SBVS032C
XTR115
SBOS124A
Questions about this or other Data Converter EVM's?
If you have questions about this or other Texas Instruments Data Converter evaluation modules, feel free
to E-mail the Data Converter Application Team at dataconvapps@list.ti.com. Include in the subject
heading the product you have questions or concerns with.
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SLAU148 – January 2005
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EVM Overview
4
EVM Overview
This section provides an overview of the DAC7631 evaluation module (EVM), and instructions on setting
up and using this evaluation module.
4.1
Features
This EVM features the DAC7631 digital-to-analog converter (DAC). It provides a quick and easy way to
evaluate the functionality and performance of the high-resolution serial input DAC. The EVM provides the
serial interface header to easily attach to any host microprocessor or TI DSP base system for
communication.
4.2
Power Requirements
The power requirements of the EVM are described in the following sections.
4.2.1
Supply Voltage
The dc-power supply for the digital section (VDD) of this EVM is dedicated to 5 V via the J3-1 terminal or
J6-10 terminal and is referenced to ground through the J3-2 and J6-5 terminals respectively.
The dc-power supply requirements for the analog section of this EVM are as follows; the VCC and VSS are
typically 15 V, but can range from ±4.5-V minimum to ±18-V maximum and connect through J1-3 and
J1-1, respectively, or through J6-1 and J6-2 terminals. The +5VA connects through J6-3 and the –5VA
connects through J6-4. All of the analog power supplies are referenced to analog ground through J1-2 and
J6-6 terminals.
The device under test (U1) analog power supply can be provided by ±5VA (via J6-3 and J6-4). The VCC
supply source provides the positive rail of the external output operational amplifier, U2, and the supply for
the reference buffer, U3. The negative rail of U2 can be selected between VSS and AGND via W5 jumper,
while the negative supply of U3 is permanently tied to VSS. The external output operational amplifier is
installed as an option to provide output signal conditioning or for other output configurations desired.
CAUTION
To avoid potential damage to the EVM board, ensure that the correct
cables are connected to their respective terminals as labeled on the EVM
board.
Stresses above the maximum listed voltage ratings may cause permanent
damage to the device.
4.2.2
Reference Voltage
The externally generated ±2.5-V precision voltage reference is jumper selectable via W7. The external
reference voltage source can come from the REF3125, which is a 15 ppm/°C CMOS device or through an
XTR115 current loop transmitter. The –2.5-V reference is created by inverting the selected output via the
U5 operational-amplifier circuit. These voltage references are buffered through the U3 operational
amplifier, which provides the DAC7631 voltage-output range.
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EVM Basic Functions
5
EVM Basic Functions
This EVM is designed primarily as a functional evaluation platform to test certain functional characteristics
of the DAC7631 DAC. Functional evaluation of the installed DAC device can be accomplished with the
use of any microprocessor, TMS320™ DSP family, or some sort of a signal/waveform generator.
The headers J2 and P2 are the connectors provided to allow the control signals and data required to
interface a host processor or waveform generator to the DAC7631 EVM using a custom-built cable.
A specific adapter interface card is also available for most of TI’s DSP Starter Kits (DSK) and the card
model depends on the type of the TI DSP Starter Kit to be used. To acquire the right adapter interface
card, be sure to specify the DSP that is used. In addition, there is also an MSP430-based platform
(HPA449) that uses the MSP430F449 microprocessor, with which this EVM can connect and interface.
For more details or information regarding the adapter interface card or the HPA449 platform, call Texas
Instruments, or send an e-mail to dataconvapps@list.ti.com.
The DAC output can be monitored through the selected pins of J4 header connector. The output of U1
can be switched from either pin 2 or pin 4 of the header, J4, for stacking reason. Stacking allows a total of
two DAC channels (if two DAC7631 EVMs are stacked).
In addition, the option of selecting one DAC output (from J4-2 or J4-4) to be connected to the output
operational amplifier, U2, is also possible by using a jumper across the selected pins of J4. The output
operational amplifier, U2, is configurable through J5, W5, and W15 for any desired waveform
characteristic.
A block diagram of the DAC7631 EVM is shown in Figure 1.
VCC
VCC
GND
(J1)
VSS
VSS
GND
VDD
±5VA
(J3)
VDD
±5 VA
TP2
(J6)
(P6)
+3.3VD
REF3025
TP7
Reference
Buffer
W7
Q2
RST
RSTSEL
XTR115
W6
VREF H VREFL VDD VCC/V SS
Output
Buffer
DAC Out
TP5
Module
TP6
(J2)
(P2)
(J4)
W2
(P4)
V OUT
J5
DAC Module
VOUT Sense DGND
AGND
CS
LOAD
SDI
LDAC
SCLK
SDO
TP1
W15
W8
W5
VSS
Q1
W9
125 Ω
Figure 1. DAC7631 EVM Block Diagram
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PCB Design and Performance
6
PCB Design and Performance
This section covers the layout design of the PCB, describing the physical and mechanical characteristics
of the EVM. This section also shows the resulting performance of the EVM which can be compared to the
device specification listed in the data sheet. The list of components used on the module is also included in
this section.
6.1
PCB Layout
The DAC7631 EVM is designed to demonstrate the performance quality of the installed DAC device under
test, as specified in the data sheet. Careful analysis of the EVM’s physical restrictions and factors that
contributes to the EVM’s performance degradation is the key to a successful design implementation. The
obvious attributes that contributes to the poor performance of the EVM can be avoided during the
schematic design phase by properly selecting the right components and designing the circuit correctly.
The circuit should include adequate bypassing, identifying and managing the analog and digital signals,
and knowing or understanding the components mechanical attributes.
The obscure part of the design lies particularly in the layout process. The main concern is primarily with
the placement of components and the proper routing of signals. The bypass capacitors should be placed
as close as possible to the pins and the analog and digital signals should be properly separated from each
other. The power and ground plane is important and should be carefully considered in the layout process.
A solid plane is ideally preferred but sometimes impractical, so when solid planes are not possible, a split
plane does the job as well. When considering a split plane design, analyze the component placement and
carefully split the board into its analog and digital sections starting from the device under test. The ground
plane plays an important role in controlling the noise and other effects that otherwise contributes to the
error of the DAC output. To ensure that the return currents are handled properly, route the appropriate
signals only in their respective sections, meaning the analog traces should only lay directly above or below
the analog section and the digital traces in the digital section. Minimize the length of the traces but use the
biggest possible trace width allowable in the design. These design practices can be seen in the following
figures.
The DAC7631 EVM board is constructed on a four-layer, printed-circuit board using a copper-clad FR-4
laminate material. The printed-circuit board has a dimension of 43,1800 mm (1.7000 inch) X 82,5500 mm
(3.2000 inch), and the board thickness is 1,5748 mm (0.0620 inch). Figure 3 through Figure 6 show the
individual artwork layers.
Figure 2. Top Silkscreen
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PCB Design and Performance
Figure 3. Layer 1 (Top Signal Plane)
Figure 4. Layer 2 (Ground Plane)
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PCB Design and Performance
Figure 5. Layer 3 (Power Plane)
Figure 6. Layer 4 (Bottom Signal Plane)
Figure 7. Bottom Silkscreen
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DAC7631EVM
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PCB Design and Performance
Figure 8. Drill Drawing
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EVM Operation
6.2
Bill of Materials
Table 1. Parts List
Item
#
Qty
1
2
C9 C10
TDK
C3216COG2A103KT
0.01 µF, 1206 Multilayer Ceramic Capacitor
2
8
C1 C2 C7 C8 C11
C13 C14 C15
TDK
C3216COG1E104KT
0.1 µF, 1206 Multilayer Ceramic Capacitor
3
1
C12
TDK
C3216COG2A102KT
1 nF, 1206 Multilayer Ceramic Capacitor
4
3
C4 C5 C6
TDK
C3225X7R1E106KT
10 µF, 1210 Multilayer Ceramic X5R Capacitor
5
1
C3
TDK
C3216X7R1E471KT
470 pF, 50V, 1206 Multilayer Ceramic Capacitor SMD
6
3
R7 R9 R10 (1)
Panasonic
ERJ-8GEY0R00V
0 Ω, 1/4W 1206 Chip Resistor
7
1
R1
Panasonic
ERJ-8ENF1240V
124 Ω, 1%, 1/8W 1206 Chip Resistor
8
3
R4 R11 R14
Panasonic
ERJ-8GEYJ101V
100 Ω, 1/4W 1206 Chip Resistor
9
1
R8
Panasonic
ERJ-8GEYJ202V
2 kΩ, 5%, 1/4W 1206 Chip Resistor
10
6
R2 R3 R5 R6 R12
R13
Panasonic
ERJ-8ENF1002V
10 kΩ, 1/4W 1206 Chip Resistor
11
2
Q1 Q2
Panasonic
2SC24050RL
FET Transistor NPN 35VCEO 50MA MINI-3P
12
1
J5
Molex
22-03-2041
4 Position Jumper_ 0.1" spacing
13
1
J6
Samtec
TSM-105-01-T-DV
5×2×0.1 10-pin 3A Isolated Power Socket
14
2
J2 J4
Samtec
TSM-110-01-S-DV-M
10×2×0.1, 20 Pin .025"sq SMT Socket
15
2
J1 J3
On-Shore Technology
ED555/3DS
3-Pin Terminal Connector
16
1
U1
Texas Instruments
DAC7631E
16-bit, Voltage Output, Serial Input DAC
17
1
U2
Texas Instruments
OPA627AU
8-SOP(D) Precision Op Amp
8
TP1 TP2 TP3 TP4
TP5 TP6 TP7 TP8
Mill-max
2348-2-01-00-00-07-0
Turret Terminal Test Point
18
(1)
(2)
7
Designator
(1)
P4 (2)
Manufacturer
Part Number
Description
19
2
P2
Samtec
SSW-110-22-S-D-VS-P
20 Pin 0.025" sq SMT Terminal Strips
20
1
P6 (2)
Samtec
SSW-105-22-F-D-VS-K
3A Isolated 10-pin Power Header
21
4
W8 W9 W14 W16
Molex
22-03-2021
2 Position Jumper_ 0.1" spacing
22
10
W1 W2 W3 W4 W5
W6 W7 W10 W11
W20
Molex
22-03-2031
3 Position Jumper_ 0.1" spacing
23
1
R15
Panasonic
ERJ-8ENF1242V
12.4 kΩ, 1/4 W 1206 Chip Res
24
1
R16
Panasonic
ERJ-8ENF3163V
316 kΩ, 1/4 W 1206 Chip Res
25
2
C18 C19
TDK
C3216COG2A102KT
1000 pF, NPO Ceramic 1206
26
2
C16 C17
TDK
C3216COG2J222KT
2200 pF, NPO Ceramic 1206
27
1
U3
Texas Instruments
OPA2234U
Dual Precision Op-amp 8 SOIC
28
1
U4
Texas Instruments
XTR115U
4-mA to 20-mA Transmitter, 8-SO
29
1
U5
Texas Instruments
OPA703NA
CMOS Op-amp, SOT23-5
30
1
REF1
Texas Instruments
REF3125AIDBZT
Precision 2.5V Ref, SOT23-3
The following parts: J1, J3, R7, R9, and R10 are not installed.
P2, P4, and P6 parts are not shown in the schematic diagram. All the P-designated parts are installed in the bottom side of the
pc board opposite the J-designated counterpart. For example, J2 is installed on the top side while P2 is installed in the bottom
side opposite of J2.
EVM Operation
This section covers in detail the operation of the EVM to provide guidance to the user in evaluating the
onboard DAC and how to interface the EVM to a host processor.
See the specific DAC data sheet, as listed in the Related Documentation from Texas Instruments section
of this user’s guide for more information about the DAC’s serial interface and other related topics.
The EVM board is factory tested and configured to operate in the bipolar output mode.
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DAC7631EVM
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EVM Operation
7.1
Factory Default Setting
The EVM board is set to its default configuration from the factory as described in Table 2 to operate in
bipolar ±2.5-V output operation. The default jumper settings are also shown in Table 2.
Table 2. DAC7631EVM Factory Default Jumper Setting
DAC7631EVM JUMPER DEFAULT CONFIGURATION
Reference
Jumper Positiion
Function
W1
2-3
LDAC is driven by the GPIO0 input from J2-2
W2
1-2
DAC output (VOUT) is routed to J4-2
W3
1-2
CS signal is driven from J2-1
W4
1-2
LOAD is driven by GPIO1 from J2-6
W5
1-2
Negative supply rail of U2 operational-amplifier is supplied with VSS
W6
OPEN
4-mA to 20-mA operation
W7
2-3
W8
CLOSE
External voltage reference source is supplied by REF1
VOUT sense pin is tied to VOUT pin
W9
OPEN
4-mA to 20-mA operation
W10
1-2
External reference to VREFH
W11
1-2
External reference to VREFL via U5 for inversion
W14
OPEN
Reset pin high
W15
OPEN
U2 operational amplifier configuration jumper set to unity gain
W16
OPEN
RSTSEL configuration jumper
W20
2-3
Dual supply operation (VSS = –5VA)
J5
2-3
DAC output (VOUT) is routed to the noninverting input of U2
Figure 9. DAC7631EVM Default Jumper Setting
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EVM Operation
7.2
Host Processor Interface
The host processor drives the DAC. The DAC's proper operation depends on the successful configuration
between the host processor and the EVM board. In addition, a properly written code is also required to
operate the DAC.
A custom cable can be made specific to the host interface platform. The EVM allows interface to the host
processor through J2 header connector for the serial control signals and the serial data input. The output
can be monitored through the J4 header connector.
An interface adapter card is also available for a specific TI DSP starter kit as well as an MSP430-based
microprocessor as mentioned in section 1 of this manual. Using the interface card alleviates the task of
building customize cables and allows easy configuration of a simple evaluation system.
This DAC EVM interfaces with any host processor capable of handling serial communication protocols or
the popular TI DSP. For more information regarding the serial interface of the particular DAC installed, see
the specific DAC data sheet, as listed in the Related Documentation from Texas Instruments section of
this user’s guide.
7.3
EVM Stacking
Stacking of the EVM is possible if there is a need to evaluate two DAC7631 to yield a total of two channel
outputs. A maximum of two DAC7631 EVMs are allowed because the output terminal, J4, dictates the
number of DAC channels that can be connected without the outputs colliding. Table 3 shows how the DAC
output channels are mapped into the output terminal, J4, with respect to the jumper position of W2.
Table 3. DAC7631 Output Channel Mapping
Reference
W2
7.4
Jumper Position
Function
1-2
DAC7631 output (VOUT) is routed to J4-2.
2-3
DAC7631 output (VOUT) is routed to J4-4.
The Output Operational Amplifier
The EVM includes an optional signal conditioning circuit for the DAC output through an external
operational amplifier, U2. Only one DAC output channel can be monitored at any given time for evaluation
because the odd numbered pins (J4-1 and J4-3) are tied together. The output operational amplifier is set
to unity gain configuration by default. Nevertheless, the raw outputs of the DAC can be probed through the
even pins of the output terminal J4, which also provides mechanical stability when stacking or plugging
into any interface card. In addition, it provides easy access for monitoring up to two DAC channels when
stacking two DAC7631 EVMs together; see the EVM Stacking section.
The inverting input of U2 can be tied to AGND (via W15) or the DAC output (by shorting pins 1 and 2 of
the J5 header) or to any voltage source through J5-1.
The following sections describe the different configurations of the output amplifier, U2.
7.4.1
Unity Gain Output (Default Configuration)
The buffered output configuration can be used to prevent loading the DAC though it may present some
slight distortion because of the feedback resistor and capacitor. The user can tailor the feedback circuit to
closely match their desired wave shape by simply removing R6 and C12 and replacing it with the desired
values. The user can also remove R6 and C12 and solder a 0-Ω resistor in place of R6.
Table 12 shows the jumper setting for the unity gain configuration of the DAC external output buffer in
unipolar or bipolar supply mode.
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EVM Operation
Table 4. Unity Gain Output Jumper Settings
Reference
7.4.2
Jumper Position
W15
OPEN
OPEN
W5
2-3
1-2
Function
Disconnect the inverting input of operational amplifier, U2, from AGND.
Negative rail of operational amplifier is tied to AGND or powered by VSS.
Output Gain of Two
Table 5 shows the proper jumper settings of the EVM for the 2× gain output of the DAC.
Table 5. Gain of Two Output Jumper Settings
Reference
7.4.3
Jumper Position
Function
Unipolar
Bipolar
W15
CLOSED
CLOSED
W5
2-3
1-2
Inverting input of the output operation amplifier, U2, is connected to AGND to set for a gain
of 2.
Supplies power, VSS, to the negative rail of operation amplifier, U2, for bipolar supply
mode, or ties it to AGND for unipolar supply mode.
Output Gain of Five With DAC VOUT Inverted
Table 6. Jumper Settings for a Gain of Five With Inverted Output
Reference
7.5
Jumper Position
Unipolar
Bipolar
J5
1-2 & 3-4
1-2 & 3-4
W15
OPEN
OPEN
W5
2-3
1-2
Function
Output of DAC is inverted with a gain of 5. Watch for clipping in unipolar mode due
to operational amplifier headroom issue.
Disconnect the inverting input of operational amplifier, U2, from AGND.
Supplies power, VSS, to the negative rail of operational amplifier, U2, for bipolar
supply mode, or ties it to AGND for unipolar supply mode.
Digitally Programmable Current Source Application
A digitally programmable, unidirectional current-source circuit is added for the convenience of users who
find the need for this type of application. Basically, the output of the DAC7631 can be connected to either
the base of transistor, Q1 or the current input pin of the XTR115, U4A, via jumper W6. The sense pin of
the DAC7631 should be connected to the emitter side of transistor Q1 via jumper W9, if used. If the
XTR115, U4A, is selected to do this operation, the sense pin of the DAC7631 should be tied back to the
VOUT pin via jumper W8. The jumper, W7, must be ensured in the position of 2-3 for the REF1 to drive
the reference voltage of the DAC7631. A simple configuration of this setup is shown in Figure 10.
To operate the DAC7631 for the digitally programmable, unidirectional current-source application, the
DAC7631 must be configured for the unipolar mode of operation. For a 4-mA to 20-mA operation, the
VREFL input must be set to accept 500 mV, which can be externally provided through the –REFin input
via J4-18. The jumper, W11, should be positioned to 2-3 to pass the voltage through.
The VREFH can take its input from REF1 via jumpers, W7 and W10.
See Table 7 for the setup configuration.
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EVM Operation
Table 7. Digitally Programmable Current Source Configuration
Reference
Jumper Position
Function
Q1
U4A
W2
OPEN
OPEN
W6
1-2
2-3
Routes VOUT to selected device for current operation
W7
2-3
2-3
Routes REF1 to source VREFH of DAC7631
W8
OPEN
CLOSED
Configures the DAC7631 output for proper operation
Configures the DAC7631 output for proper operation
Disconnect VOUT from J4 header
W9
CLOSED
OPEN
W10
1-2
1-2
Routes REF1 to source VREFH of DAC7631
W11
2-3
2-3
Routes –REFin to source VREFL of DAC7631
+5 VA
312.5 kW
+
6.5-Digit
Current Meter
A
TP2
Q2
TP1
V+
Iin
XTR115
B
IOUT
E
+5 VA
12.5 kW
VREF
TP8
+2.5 V
Iret
U4A
VREFH VREFL
W6
Q1
0.5 V
VOUT
W8
VCC
VSS
DAC Module
VOUTSENSE DGND
AGND
W9
125 W
Digitally Programmable 4-mA - 20-mA Current Source
Figure 10. Digitally Programmable Current Source
7.6
Jumper Setting
Table 8 shows the function of each specific jumper setting of the EVM.
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EVM Operation
Table 8. Jumper Setting Function
Reference
Jumper Setting
Function
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
Negative supply rail of the output operational amplifier, U2, is powered by VSS for bipolar
operation.
1
3
Negative supply rail of the output operational amplifier, U2, is tied to AGND for unipolar
operation.
1
3
VOUT is used for 4-mA to 20-mA operation to drive Q1.
1
3
4-mA to 20-mA application is not used.
1
3
1
3
1
3
LDAC driven by GPIO4 pin, J2-14.
W1
LDAC driven by GPIO0 pin, J2-2.
Routes DAC VOUT to J4-2.
W2
Routes DAC VOUT to J4-4.
Chip Enable pin driven by CS pin, J2-1.
W3
Chip Enable pin driven by FSX pin, J2-7.
LOAD driven by GPIO5 pin, J2-19.
W4
LOAD driven by GPIO1 pin, J2-6.
W5
W6
VOUT is used for 4-mA to 20-mA operation to drive U4A.
U4A is used to supply external voltage reference to the DAC7631 DUT.
W7
14
DAC7631EVM
REF1 is used to supply external voltage reference to the DAC7631 DUT.
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EVM Operation
Table 8. Jumper Setting Function (continued)
Reference
Jumper Setting
Function
4-mA to 20-mA operation is used with Q1 for current source.
W8
4-mA to 20-mA operation is used with U4A for current source.
4-mA to 20-mA operation is used with U4A for current source.
W9
4-mA to 20-mA operation is used with Q1 for current source.
1
3
1
3
1
3
1
3
REF1 or U4A supplies the external reference for VREFH of DAC7631.
W10
+REFin supplies the external reference for VREFH of DAC7631.
REF1 or U4A supplies the external reference for VREFL of DAC7631 via U5.
W11
–REFin supplies the external reference for VREFL of DAC7631.
RST_ is pulled up via R5 resistor.
W14
RST_ is pulled down to DGND and device is held on reset state.
Configures output operational amplifier, U2, to unity gain output.
W15
Configures the output operational amplifier, U2 with an inverting gain of two.
RSTSEL is pulled up via R13 resistor and device resets to midscale on powerup.
W16
RSTSEL is pulled down to DGND and device resets to minimumscale on powerup.
1
3
Dual-supply operation (VSS = –5VA).
1
3
Single-supply operation (VSS = AGND).
W20
SLAU148 – January 2005
DAC7631EVM
15
www.ti.com
EVM Operation
Table 8. Jumper Setting Function (continued)
Reference
Jumper Setting
Function
1
4
DAC VOUT is routed to the inverting input of U2.
1
4
DAC VOUT is routed to the noninverting input of U2.
1
4
The noninverting input of U2 is tied to AGND.
1
4
DAC VOUT is routed to the inverting input of U2 and the noninverting input of U2 is tied to AGND.
J5
Legend:
7.7
Indicates the corresponding pins that are shorted or closed.
Schematics
The schematic is located on the following page.
16
DAC7631EVM
SLAU148 – January 2005
1
2
3
4
5
6
Revision History
+5VA
C7
0.1µF
J4
D
2
4
6
8
10
12
14
16
18
20
C6
10µF
C5
10µF
C2
0.1µF
C8
0.1µF
R5
10K
R13
10K
P2
U1
20
Vout
W8
16
VoutSense
-REFin
+REFin
4
18
+
+
C1
W20
0.1µF
LDAC
VrefHSense
LOAD
VrefLSense
SDI
VSS
19
SDO
AGND
DGND
CS
SCLK
CLKR
FSX
FSR
SDI
DR
RST
RSTSEL
GPIO5
TP3
6
R7
W14
13
RST
14
RSTSEL
10
CE
9
SCLK
11
LDAC
12
LOAD
8
SDI
0
W16
CS
2
4
6
8
10
12
14
16
18
20
W9
VCC
DAC7631
3
100
Op Amp
2
1
4
+REFin
1
C
2K
0.1µF
GND
VSS
R8
C11
W10
U3A
3
2
R11
1
2
OPA2234
C13
4
W5
C10
C3
470pF
0.01µF
R6
VrefH
100
10K
C18
1000pF
C16
2200pF
C12
1nF
W15
+5VA
R16
2
+5VA
U4A
V+
Iret
B
Io
E
8
7
6
7
OPA2234
C15
VrefL
100
C17
2200pF
0.1µF
B
C19
1000pF
-5VA
R3
VrefLSense
10K
5
XTR115
TP2
+3.3VD VD2
+5VA
VCC
VSS
-5VA
VD1
VDD
J3
VCC
VDD
3
J1
2
Q2
MMBT3904_TRANS
TP8
1
4
Vreg
Iin
6
R14
3
3
Vref
OPA703
U3B
2
2
5
1
1
R12
10K
1
4
10K
312.5k
-REFin
W11
2
R2
0.1µF
U5
3
W7
VrefHSense
1
5
C14
12.5k
J6
1
3
5
7
9
A
2
4
6
8
10
VSS
ti
VD2
Title:
J. PARGUIAN
DAC7631 EVM
DOCUMENTCONTROL #
Drawn By:
FILE:
2
3
A
12500 TI Boulevard. Dallas, Texas 75243
Engineer:
1
D
TP5
R4
6
0.1µF
R15
GPIO0
JP4
GPIO1
JP8
JP10
JP12
GPIO4
JP16
JP18
JP20
U2
VSS
Vout
2
4
6
8
10
12
14
16
18
20
DAC_VOUT
REF3025
B
0
1
3
5
7
9
11
13
15
17
19
C9
TP6
VCC
8
IN
3
OUT
W6
0
CS
SCLK
CLKR
FSX
FSR
SDO
DR
RST
RSTSEL
GPIO5
0.01µF
J5
4
3
2
1
REF1
R1
125
R10
TP4
TP7
GPIO0
5
+5VA
VoutSense
R9
GPIO1
Q1
MMBT3904_TRANS
C
GPIO0
JP4
GPIO1
JP8
JP10
JP12
GPIO4
JP16
JP18
JP20
FSX
W1
SDO
7
J2
1
3
5
7
9
11
13
15
17
19
W4
LOAD
W3
GPIO4
Approved
5
C4
10µF
CLK
VrefL
2
VrefLSense
-5VA
CS
VrefH
3
VrefHSense
RST
RSTSEL
VoutSense
1
VrefL
VDD
Vout
17
VrefH
TP1
VCC
ECN Number
7
1
3
5
7
9
11
13
15
17
19
VDD
Vout
W2
DAC_VOUT
REV
4
5
DAC7631_REV A.SCH
DATE:
30-Nov-2004
6464403
SIZE:
6
REV:
SHEET:
1
OF:
A
1
EVM IMPORTANT NOTICE
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