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Texas Instruments ADS8382EVM User guides
User's Guide
SLAU143 – December 2004
ADS8382EVM
This user's guide describes the characteristics, operation, and use of the ADS8382
18-bit, 600 kHz, high speed, serial interface Analog-to-Digital converter Evaluation
Board (EVM). A complete circuit description, schematic diagram, and bill of materials
are included.
The following related documents are available on the TI web site at www.ti.com.
1
2
3
4
5
6
8
9
Data Sheets:
Literature Numbers:
ADS8382
SLAS416
REF1004C-2.5
SBVS002
SN74AHC1G125
SCLS377
THS4131
SLOS318
OPA627AU
SBOS165
Contents
EVM Overview ............................................................................................................... 2
Analog Interface.............................................................................................................. 2
Digital Interface .............................................................................................................. 4
Power Supplies .............................................................................................................. 5
Using the EVM ............................................................................................................... 6
ADS8382EVM Bill Of Materials ............................................................................................ 7
Board Layers ................................................................................................................. 9
Schematics .................................................................................................................. 11
List of Figures
1
2
3
4
5
Input Buffer Circuit ........................................................................................................... 3
Top Layer ..................................................................................................................... 9
Power Plane .................................................................................................................. 9
Ground Plane ............................................................................................................... 10
Bottom Layer ................................................................................................................ 10
List of Tables
1
2
3
4
5
7
Analog Input Connector .....................................................................................................
Jumper Setting ...............................................................................................................
Pinout for Serial Control Connector P2 ...................................................................................
Power Supply Test Points ..................................................................................................
Power Connector (J3) Pin Out .............................................................................................
ADS8382EVM Bill of Materials .............................................................................................
SLAU143 – December 2004
ADS8382EVM
2
4
5
5
5
7
1
www.ti.com
EVM Overview
1
EVM Overview
1.1
Features
•
•
•
•
2
Full-featured evaluation board for the ADS838218-bit, 600 kHz, single channel, high-speed
serial-interface analog-to-digital converter (ADC)
On board signal conditioning
On board reference
Input and output digital buffer
Analog Interface
The ADS8382EVM ships with buffer U13 configured in a unity-gain, single-ended to differential out
configuration. The common-mode voltage pin of the THS4131 is factory set to 2.0 V on the evaluation
module, and can be adjusted using potentiometer RP1. The potentiometer connects between the output of
reference buffer U3 and ground. The single-ended input signal can be applied at pin-connector P1 pin 2 or
via SMA connectors J2 (non-inverting input). The buffer circuit can be reconfigured for a fully differential
input by installing resistors R4 and R31 and removing R16. The inverting leg of the differential signal can
be connected to connector P1 pin 1 or SMA connector J1 (inverting input). See Table 1 for the pinout of
the analog connector, P1. See Section 9 for the EVM schematic diagrams.
The analog-to-digital converter accepts a pseudo-bipolar differential input. A pseudo-bipolar differentail
signal is a differential signal that has a common-mode voltage such that each leg is always equal to or
above zero volts. The common mode voltage should be half the reference voltage. The peak-to-peak
amplitude on each input leg can be as large as the reference voltage.
Table 1. Analog Input Connector
Description
Connector pin#
Signal Name
Description
–IN
P1.1
P1.2
+IN
Non-inverting Input
Reserved
N/A
P1.3
P1.4
N/A
Reserved
Reserved
N/A
P1.5
P1.6
N/A
Reserved
Reserved
N/A
P1.7
P1.8
N/A
Reserved
Pin tied to Ground
AGND
P1.9
P1.10
N/A
Reserved
Pin tied to Ground
AGND
P1.11
P1.12
N/A
Reserved
N/A
P1.13
P1.14
N/A
Reserved
Pin tied to Ground
AGND
P1.15
P1.16
N/A
Reserved
Pin tied to Ground
AGND
P1.17
P1.18
N/A
Reserved
N/A
P1.19
P1.20
REF+
Reserved
Reserved
2
Signal Name
Inverting Input
ADS8382EVM
External Reference Input
SLAU143 – December 2004
www.ti.com
Analog Interface
2.1
Signal Conditioning
It is a recommended practice to buffer the analog input to any SAR-type converter with a high-speed,
low-noise amplifier with fast settling time. The amplifier circuit shown in Figure 1 is the buffer circuit used
on the ADS8382EVM. This circuit consists of the THS4131, a high-speed, low-noise, fully differential
amplifier configured as a single-ended in to differential out, unity gain buffer. This circuit was optimized to
achieve the AC specifications (i.e., SNR, THD, SFDR, etc.) listed in the ADS8382 data sheet.
The type of input capacitors used in the signal path can make a few decibels of difference in AC
performance. Polypropylene or C0G-type capacitors are recommended for the input signal path.
Polypropylene capacitors cause the least distortion of the input signal and have excellent long-term
stability, but are expensive and bulky. C0G ceramic capacitors cost less, come in smaller packages and
perform as well as polypropylene capacitors in many applications, but are not as stable over time and
temperature. The 68 pF and 6800 pF capacitors installed on the EVM are low-cost C0G type,
manufactured by TDK Corporation.
68 pF
C0G
1 k
VCC
0.1 F
THS4131
1 F
1 k
25 VIN
+
−
_
+
(+) IN
6800 pF
C0G
2.048 V
(−) IN
1 F
1 k
25 0.1 F
−VCC
1 k
68 pF
C0G
Figure 1. Input Buffer Circuit
SLAU143 – December 2004
ADS8382EVM
3
www.ti.com
Digital Interface
2.2
Reference Voltage
The EVM allows the designer to select internal, on-board, or user-supplied reference-voltage sources. The
internal reference is a 4.096 V reference voltage generated by the ADS8382 on pin 9. The on-board
reference can be either a REF3040 (U1) or REF1004-2.5 (U14). The EVM ships with the REF1004-2.5
installed. The reference amplifier, U3, is set for a gain of 1.6, enabling it to take a 2.5 V input and output
4.1 V for use with the converter, or as part of the common-mode voltage circuit for the input buffer (U13).
The user-supplied reference voltage is applied to connector P1 pin 20, and can be routed through the
reference buffer and filtered, if desired. The EVM allows a number of configurations. Refer to Table 1 for
jumper settings, or the full schematic in Section 9 for more information. The common footprint for U14
allows users to evaluate this converter with various reference ICs.
The EVM ships with the internal reference tied directly to the reference pin of the converter.
Table 2. Jumper Setting
Reference
Designator
SJP1
Description
Buffer onboard reference (REF1004-2.5)
Buffer user supplied reference voltage applied at P1 pin 20.
SJP2
Connect external reference directly to SJP4
Connect buffered external reference to SJP4
SJP3
SJP4
2-3
Shorted (1)
Open
Open
Shorted
Shorted (1)
Open
Open
Shorted
Connect U3 negative supply to ground
Shorted
Open
Connect U3 negative supply to –VCC
Open
Shorted (1)
Connect internal reference to REFIN
Shorted (1)
Open
Connect external reference to REFIN
Open
Shorted
SJP5
Connect common-mode voltage to VOCM pin of THS4131
Shorted (1)
N/A
W1
Connect +5VD to BVDD
Shorted (1)
Open
Connect +3.3VD to BVDD
Open
Shorted
W3
Set power down signal (PD) high
Shorted
N/A
W4
Set frame sync signal (FS) high
Shorted
N/A
Set chip select signal (CS) low
Shorted (1)
N/A
W5
(1)
3
Pins/Pads
1-2
Factory Installed
Digital Interface
The ADS8382EVM is designed for easy interfacing to multiple platforms. Samtec plug and socket
connectors provide a convenient dual row header/socket combination at P1 and P2 to plug into prototype
boards or ribbon cable over to user system boards.
The digital input and output signals for the converter is available at connector P2 on the ADS8382EVM,
see Table 3 for the connector pinout.
4
ADS8382EVM
SLAU143 – December 2004
www.ti.com
Power Supplies
Table 3. Pinout for Serial Control Connector P2
Description
Signal Name
Signal Name
Description
Chip Select
CS
P2.1
P2.2
N/A
Serial Clock
SCLK
P2.3
P2.4
DGND
N/A
P2.5
P2.6
N/A
Reserved
Frame Sync
FS
P2.7
P2.8
N/A
Reserved
Reserved
N/A
P2.9
P2.10
N/A
Reserved
Reserved
N/A
P2.11
P2.12
N/A
Reserved
Serial Data Out
SDO
P2.13
P2.14
N/A
Reserved
BUSY
BUSY
P2.15
P2.16
N/A
Reserved
Convert Start
CONVST
P2.17
P2.18
DGND
Power down
PD
P2.19
P2.20
N/A
Reserved
4
Connector Pin
Reserved
Ground
Ground
Reserved
Power Supplies
The EVM accepts four power supplies
• A differential (±) dc supply for the dual-supply op amps. The maximum recommended voltage is ±15
Vdc
• A single +5.0 V dc supply for the analog section of the board (A/D + Reference).
• A single +5.0 V or +3.3 V dc supply for digital section of the board (A/D + buffers).
There are two ways to provide these voltages. The first is to connect the voltages to the test points listed
in Table 4.
Table 4. Power Supply Test Points
Test Point
Signal
Description
TP1
+VA
Connect +15.0 V dc supply for amplifier
TP2
–VA
Connect –15.0 V dc supply for amplifier
TP3
+BVDD
Apply +3.3 V dc or +5.0 V dc. See ADC data sheet for full range.
TP4
+AVCC
Apply +5.0 V dc
The second is to use the power connector J3, and derive the voltages elsewhere. Table 5 gives the pinout
for J3. If using this connector, set W1 jumper to connect +3.3VD or +5VD from J3 to +BVDD. Shunt pins
1-2 to select +5VD, or pins 2-3 to select +3.3VD as the source for the digital-buffer-voltage supply
(+BVDD).
Table 5. Power Connector (J3) Pin Out
Signal
SLAU143 – December 2004
J1 Pin
Signal
+VA(+15V)
1
2
–VA(–15 V)
+5VA
3
4
N/C
DGND
5
6
AGND
N/C
7
8
N/C
+3.3VD
9
10
+5VD
ADS8382EVM
5
www.ti.com
Using the EVM
5
Using the EVM
The ADS8382EVM serves three functions:
1. As a reference design
2. As a prototype board
3. As a software test platform
5.1
Reference Design
As a reference design, the ADS8382EVM contains the essential circuitry to showcase the analog-to-digital
converter. This essential circuitry includes the input amplifier, reference circuit, and buffers. The EVM
analog-input circuit is optimized for a 100-kHz input signal; therefore, users may need to adjust the
resistor and capacitor values to accommodate higher frequencies. In ac-type applications where signal
distortion is concern, polypropylene or C0G type capacitors are recommended for use in the signal path.
Typical fully-differential amplifiers configured for single-ended in to differential out can distort the signal in
an attempt to equalize the input pins. This distortion is specially evident when step inputs are applied.
Therefore, users who will be applying a step input to the converter should use discrete amplifiers for the
single-ended-to-differential conversion of the signal. The Differential Input, Differential Output Configuration circuit shown in the Theory of Operation section of the ADS8382 datasheet (literature number
SLAS416) can be used. In applications where the input is continuous, the single amplifier solution using
the THS4131, can effectively drive the converter inputs.
5.2
Prototype Board
As a prototype board, the buffer circuit has resistor pads for configuring the input as either single-ended or
fully differential input. The input circuit can be modified to accommodate user prototype needs, whether it
be evaluating another differential amplifier or limiting noise for best performance. The analog, power, and
digital connectors can be made to plug into a standard 0.1” breadboard or ribbon cables to interface
directly to FPGAs or processors.
5.3
Software Test Platform
As a software test platform, connectors P1 and P2 plug into the serial interface connectors of the 5-6K
interface card. The 5-6K interface card plugs into the C5000 and C6000 Digital Signal Processor starter
kits (DSK). Refer to the 5-6K Interface Card User’s Guide (SLAU104) for more information.
6
ADS8382EVM
SLAU143 – December 2004
www.ti.com
ADS8382EVM Bill Of Materials
6
ADS8382EVM Bill Of Materials
The following table contains a complete bill of materials for the ADS8382EVM. The schematic diagram is
also provided for reference. Contact the Product Information Center or email dataconvapps@list.ti.com for
questions regarding this EVM.
Table 7. ADS8382EVM Bill of Materials
Reference
Designators
Footprint
Manufacturer
Manufacturer's
Part Number
QTY
Value
Description
1
49.9
R1
603
Panasonic - ECG or
Alternate
ERJ-3EKF49R9V
RES 49.9 Ω 1/16 W 1% 0603 SMD
1
1.2 kΩ
R2
603
Yageo America or
Alternate
9C06031A1201FKHFT
RES 1.20 kΩ 1/10 W 1% 0603 SMD
4
NI
R3 R4 R5 R31
805
NOT INSTALLED
NOT INSTALLED
8
100 Ω
R6 R21 R22
R23 R24 R25
R26 R27
603
Panasonic - ECG or Alternate
ERJ-3EKF1000V
RES 100 Ω 1/16 W 1% 0603 SMD
1
100 Ω
R7
805
Panasonic - ECG or
Alternate
ERJ-6ENF1000V
RES 100 Ω 1/10 W 1% 0805 SMD
7
10 kΩ
R8 R10 R11
R12 R13 R32
R39
603
Panasonic - ECG or
Alternate
ERJ-3EKF1002V
RES 10.0K Ω 1/16 W 1% 0603 SMD
1
910 Ω
R14
805
Panasonic - ECG or
Alternate
ERJ-6GEYJ911V
RES 910 Ω 1/8 W 5% 0805 SMD
3
1 kΩ
R15 R16 R17
805
Panasonic - ECG or
Alternate
ERJ-6ENF1001V
RES 1.00 kΩ 1/10 W 1% 0805 SMD
1
768 Ω
R18
603
Panasonic - ECG or
Alternate
ERJ-3EKF7680V
RES 768 Ω 1/16 W 1% 0603 SMD
2
0Ω
R19 R36
603
Panasonic - ECG or
Alternate
ERJ-3GEY0R00V
RES ZERO Ω 1/16 W 5% 0603 SMD
2
1 kΩ
R28 R29
603
Panasonic - ECG or
Alternate
ERJ-3EKF1001V
RES 1.00 kΩ 1/16 W 1% 0603 SMD
1
NI
R30
603
NOT INSTALLED
NOT INSTALLED
2
24.9 Ω
R33 R34
805
Panasonic - ECG or
Alternate
ERJ-6ENF24R9V
RES 24.9 Ω 1/10 W 1% 0805 SMD
1
49.9 kΩ
R35
805
Panasonic - ECG or
Alternate
ERJ-6ENF4992V
RES 49.9 kΩ 1/10 W 1% 0805 SMD
2
0
R37 R38
1206
Panasonic - ECG or
Alternate
ERJ-8GEY0R00V
RES 0 Ω 1/4 W 5% 1206 SMD
1
47 µF
C1
1206
TDK Corporation or
Alternate
C3216X5R0J476M
CAP CER 47 µF 6.3 V X5R 20% 1206
5
1 µF
C2 C3 C4 C5
C45
805
TDK Corporation or
Alternate
C2012X7R1E105K
CAP CER 1.0 µF 25 V X7R 0805 T/R
3
1 µF
C6 C7 C44
603
TDK Corporation or
Alternate
C1608X5R1A105KT
CAP CER 1.0 µF 10 V X5R 10% 0603
15
0.1 µF
C8 C9 C10
C11 C12 C13
C17 C18 C19
C20 C21 C22
C23 C26 C28
603
TDK Corporation or
Alternate
C1608X7R1E104K
CAP CER 0.10 µF 25 V X7R 10% 060
5
2.2 µF
C14 C15 C24
C25 C27
603
TDK Corporation or
Alternate
C1608X5R1A225MT
CAP CER 2.2 µF 6.3 V X5R 20% 0603
C29 C42
603
NOT INSTALLED
NOT INSTALLED
C35 C36 C37
C38 C39 C40
C41 C55 C58
603
TDK Corporation or
Alternate
C1608X7R1H103KT
CAP CER 10000 pF 50 V X7R 10% 0603
5
NI
9
0.01 µF
1
10 µF
C34
3528
Kemet or Alternate
T491B106K016AS
CAPACITOR TANT 10 µF 16 V 10% SMD
1
6800 µF
C46 C43 C63
805
TDK Corporation or
Alternate
C2012C0G1H682J
CAP CER 6800 pF 50 V C0G 5% 0805
4
10 µF
C47 C48 C49
C50
1206
TDK Corporation or
Alternate
C3216X5R1C106KT
CAP CER 10 µF 16 V X5R 20% 1206
4
10 µF
C51 C52 C53
C54
6032
Pansonic - ECG or
Alternate
ECS-T1EC106R
CAP 10 µF 25 V Tantalum TE SMD
2
68 pF
C32 C33
603
TDK Corporation or
Alternate
C1608C0G1H680J
CAP CER 68 pF 50 V C0G 5% 0603
2
0.01 µF
C56 C57
1206
TDK Corporation or
Alternate
C3216X7R1H103KT
CAP 10000 pF 50 V CERAMIC X7R 1206
4
1000 pF
C59 C60 C61
C62 C64
603
TDK Corporation or
Alternate
C1608C0G1H102KT
CAP CER 1000 pF 50 V C0G 0603 T/R
2
NI
C30 C31
805
NOT INSTALLED
NOT INSTALLED
1/10 W 0805 Chip resistor
SLAU143 – December 2004
ADS8382EVM
7
www.ti.com
ADS8382EVM Bill Of Materials
Table 7. ADS8382EVM Bill of Materials (continued)
QTY
Value
1
10 kΩ
4
2
Reference
Designators
RP1
L1 L2 L3 L4
NI
U1 U2
1
U3
7
U5 U6 U7 U8
U9 U10 U11
Footprint
BOURNS_3296Y
Manufacturer's
Part Number
Description
Bourns Inc.
3296Y-1-103
POT 10 kΩ 3/8" SQ CERM SL MT
805
TDK Corporation
MMZ2012R601A
FERRITE CHIP 600 Ω 500 mA 0805
3-SOT-23
NOT INSTALLED
NOT INSTALLED
REF3040 50 ppm/°C, 50 µA in SOT23-3
CMOS voltage reference
8-SOP(D)
Texas Instruments
OPA627AU
DiFet amplifier
5-SOT(DBV)
Texas Instruments
SN74AHC1G125DBVR
Single bus buffer gate/line driver with 3-state
output
1
ADS8382
U12
28-PQFP(QFN)
Texas Instruments
ADS8382IBRHPT
ADS8382 18-bit serial 600 ksps
1
THS4131
U13
8-SOP(D)
Texas Instruments
THS4131ID
High-speed low noise, fully differential I/O
amplifiers
1
REF1004-2.5
U14
8-SOP(D)
Texas Instruments
REF1004C-2.5
2.5 V Micropower voltage reference
1
3POS_JUMPER
W1
3pos_jump
Samtec
TSW-103-07-L-S
3 Position jumper _ 0.1" spacing
3
2POS_JUMPER
W3 W4 W5
2pos_jump
Samtec
TSW-102-07-L-S
2 Position jumper _ 0.1" spacing
1
SJP2
SJP5
SJP2
NOT INSTALLED
NOT INSTALLED
Pad 2 position jumper
4
SJP3
SPJ1 SPJ2
SPJ3 SPJ4
SJP3
NOT INSTALLED
NOT INSTALLED
Pad 3 position jumper
2
SMA_PCB_MT
Johnson Components Inc.
142-0701-301
Right angle SMA connector
1
Power supply
Samtec
SSW-105-22-S-D-VS
0.025" SMT socket - bottom side of PWB
Samtec
TSM-105-01-T-D-V-P
0.025" SMT plug - top side of PWB
Samtec
SSW-110-22-S-D-VS
0.025" SMT socket - bottom side of PWB
J1 J2
J3
SMA_JACK
5x2x0.1_
SMT_SOCKET
1
2
10x2x0.1
P1 P2
10x2x0.1_
SMT_LPUG_
&_SOCKET
Samtec
TSM-110-01-T-D-V-P
0.025" SMT plug - top side of PWB
10
TP_0.025
TP1 TP2 TP3
TP4 TP5 TP6
TP7 TP8 TP11
TP12
test_point2
Keystone Electronics
5000K-ND
Test point PC MINI 0.040"D black
4
TP_0.25
TP10 TP13
TP9 TP14
test_point2
Keystone Electronics
5001K-ND
Test point PC MINI 0.040"D black
2
8
Manufacturer
ADS8382EVM
SLAU143 – December 2004
www.ti.com
Board Layers
8
Board Layers
Figure 2. Top Layer
Figure 3. Power Plane
SLAU143 – December 2004
ADS8382EVM
9
www.ti.com
Board Layers
Figure 4. Ground Plane
Figure 5. Bottom Layer
10
ADS8382EVM
SLAU143 – December 2004
www.ti.com
Schematics
9
Schematics
Schematic diagrams are appended following this page.
SLAU143 – December 2004
ADS8382EVM
11
1
2
3
4
5
6
Revision History
REV
D
ECN Number
Approved
D
J1
P1
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
+IN
-IN
J2
EXT_REF
Analog Input
P2
CS
SCLK
C
FS
TP1
+VA
+VA
B_SDO
B_BUSY
CONVST
PD
TP2
J3
+VA
+AVCC
DGND
+3.3VD
1
3
5
7
9
2
4
6
8
10
-VA
-VA
-VA
CS
SCLK
FS
B_SDO
B_BUSY
CONVST
PD
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
C
Serial Control
AGND
+5VD
TP3
Power Supply
+BVDD
W1
+BVDD
+AVCC
+AVCC
TP4
Circuits
B
B
ti
A
A
12500 TI Boulevard. Dallas, Texas 75243
TITLE:
ADS8372EVM/ADS8382EVM
Engineer:
Lijoy Philipose
Drawn By:
Lijoy Philipose
FILE:
1
2
3
4
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BlockDiagram.sch
REV:
DOCUMENT CONTROL #:
6458774
DATE:
30-Jun-2005
SIZE:
6
A
SHEET:
1
OF:
2
1
2
3
4
5
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Revision History
REV
ECN Number
Approved
+5VCC
U1
1
+VBD
IN
+VBD
3
GND
2
C17
+VCC
OUT
2
SJP1
C8
0.1uF
5
3
U3
VCC
0.1uF
R6
6
Y
2
1
OPA627
100
+5VCC
5
4
3
2.2uF
SJP3
C3
1uF
5
0.01uF
0.01uF
4
6
GND
768
TP5
5
NC
C32
REF1004-2.5
C34
10uF
C35
0.1uF
0.01uF
*
68pF
8
9
10
11
12
13
14
1k
R14
R7
+VCC
100
+5VCC
U9
10k
10k
10k
W5
Y
1
2
3
OE
A
GND
SN74AHC1G125
C24
C38
2.2uF
0.01uF
C42
+VBD
NI
R32
10K
C43 NI
R28
R29
SDO
BUSY
+VBD
R30
NI
C23
U10
1
2
3
1k
1k
5
OE
VCC
A
GND
Y
0.1uF
R26
4
B_SDO
100
SN74AHC1G125
AGND
VA
VA
AGND
AGND
BVDD
BGND
C10
0.1uF
R11
R39
10K
15
16
17
18
19
20
21
C5
1uF
28
27
26
25
24
23
22
REFIN
PD
REFOUT
FS
NC
CS
U12
IN+
CONVST
INSCLK
NC ADS8372/ADS8382 SDO
VA
BUSY
910
R3
NI
R10
C
C20
R15
+IN
1
2
3
OE
A
GND
VCC
4
100
100
100
100
100
NC
VREF
R8
7
6
5
4
3
2
1
EN
0
R18
R21
R22
R23
R24
R25
NI
NI
+VIN
3
R19
2
SJP4
NI
7
REFM
VA
AGND
AGND
+VA
AGND
AGND
C64
C63
5
B_SCLK
1
C
8
NC
PD
FS
CS
CONVST
SCLK
SN74AHC1G125
3
C29
+
NC
Y
0.1uF
49.9k
2
U8
+VBD
C22
U14
1
VCC
4
B_CONVST
R35
+5VCC
Y
0.1uF
C9
0.1uF
10k
+VBDSN74AHC1G125
C21
C36
-VCC
+5VCC
C37
1
2
3
OE
A
GND
U7
4
B_CS
2.2uF
1
VCC
0.1uF
2
R2
1.2k
10k
PD
FS
CS
CONVST
SCLK
SN74AHC1G125
+VBD
C19
+5VCC
C15
C14
R13
D
1
2
3
OE
A
GND
U6
4
B_FS
R12
SN74AHC1G125
+VBD
C18
3
EXT_REF
47uF
Y
W4
1
2
3
OE
A
GND
U5
4
B_PD
7
3
C1
VCC
2
SJP2
5
50
5
1
C2
1uF
NI
R1
W3
0.1uF
1
D
3
7
+VBD
U13
NC
0
U2
B
1
C44
2
1uF
IN
GND
8
TP6
5
+
2
OUT
+5VCC
C39
0.01uF
C25
2.2uF
1
B
TP8
MMZ2012R601A
C40
0.01uF
C26
0.1uF
+
C47
10uF
THS4131
25
C51
10uF
C11
0.01uF
1000pF
C30
NI
-VCC
C4
1uF
C12
0.1uF
TP9
TP11
R37
0
MMZ2012R601A
MMZ2012R601A
C54
C48
10uF
R31
C53
C6
10uF
1uF
C56
0.01uF
C50
10uF
C60
1000pF
+
10uF
C13
0.1uF
R17
NI
R16
C62
C58
1000pF
0.01uF
TP14
TP13
1k
1k
+VBD
+BVDD
+VA
-IN
TP7
L1
+VCC
L3
+
R5
NI
C59
C55
0.1uF
6
1
SJP5
NI
+5VCC
+AVCC
-VCC
R4
B_BUSY
100
L2
4
-
RP1
2
0.1uF
R27
4
+VBD
R33
10K
5
OE
VCC
A
GND
Y
+5VCC
6800pF
VOUT+
1uF
1
2
3
C27
2.2uF
SN74AHC1G125
NI
VOCM
C45
NI
C46 *
C31
VOUT-
3
C41
0.01uF
25
+VCC
R36
+5VCC
C28
U11
R34
TP10
*
C33
ti
A
68pF
+
C49
10uF
C52
10uF
C7
C57
0.01uF
1uF
C61
1000pF
0
L4
3
Lijoy Philipose
4
-VCC
FILE:
5
Lijoy Philipose
Circuits
REV:
DOCUMENT CONTROL #:
6458774
Drawn By:
MMZ2012R601A
2
TITLE:
Engineer:
-VA
1
12500 TI Boulevard. Dallas, Texas 75243
Circuits
TP12
R38
A
DATE:
30-Jun-2005
SIZE:
6
A
SHEET:
2
OF:
2
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