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Texas Instruments ADS8381EVM (Rev. A) User guides
ADS8381EVM
User’s Guide
September 2004
Data Acquistion
SLAU133A
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Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2004, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
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discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
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Copyright  2004, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of ±6 V and the output
voltage range of 0 V and 5.5 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
60°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
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Post Office Box 655303
Dallas, Texas 75265
Copyright  2004, Texas Instruments Incorporated
Related Documentation From Texas Instruments
Preface
Read This First
About This Manual
This users guide describes the characteristics, operation, and use of the
ADS8381 18-bit, 580-kHz, parallel interface, analog-to-digital converter
evaluation board. A complete circuit description, schematic diagram, and bill
of materials are included.
How to Use This Manual
This document contains the following chapters:
- Chapter 1 – EVM Overview
- Chapter 2 – Analog Interface
- Chapter 3 – Digital Interface
- Chapter 4 – Power Supply Requirements
- Chapter 5 – Using the EVM
- Chapter 6 − ADS8381EVM BOM, Layout, and Schematic
Related Documentation From Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas
Instruments Literature Response Center at (800) 477−8924 or the Product
Information Center (PIC) at (972) 644−5580. When ordering, identify this
booklet by its title and literature number. Updated documents can also be
obtained through our Web site at www.ti.com
Data Sheets:
ADS8381
REF3040
REF3020
SN74AHC138
SN74AHC245
SN74AHC1G04
THS4031
Literature Number:
SLAS364
SBVS032
SBVS032
SCLS258
SCLS230
SCLS318
SLOS224
iii
Contents
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
Trademarks
TMS320C5000 and TMS320C6000 DSP platforms are trademarks of
Texas Instruments Incorporated.
iv
Contents
Contents
1
EVM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
2
Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
4
Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
5
Using the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
As a Reference Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
As a Prototype Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
As a Software Test Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5-2
5-2
5-2
6
ADS8381EVM BOM, Layout, and Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
ADS8381EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
ADS8381EVM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
ADS8381EVM Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6-2
6-5
6-7
v
Contents
Figures
2−1
6−1
6−2
6−3
6−4
Input Buffer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Top Layer—Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ground Plane—Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Plane—Layer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bottom Layer—Layer 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
6-5
6-5
6-6
6-6
Tables
2−1
2−2
3−1
3−2
3−3
3−4
4−1
4−2
6−1
vi
Analog Input Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Solder Short Jumper Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinout for Parallel Control Connector P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Bus Connector P3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinout for Converter Control Connector J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Connector, J1, Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADS8381EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2-3
3-1
3-2
3-2
3-2
4-1
4-1
6-2
Chapter 1
EVM Overview
This chapter contains the features of the ADS8381EVM.
Topic
1.1
Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
EVM Overview
1-1
Features
1.1 Features
- Full-featured evaluation board for the high-speed ADS8381 18-bit, single
channel, parallel interface, SAR-type analog-to-digital converters.
- Onboard signal conditioning
- Onboard reference
- Input and output digital buffer
- Onboard decoding for stacking multiple EVMs
1-2
Chapter 2
Analog Interface
The ADS8381 analog-to-digital converter has both a positive and negative
analog input pin. Ground for the negative input is provided on the EVM (via
SJP3) close the device, or a user-furnished ground wire may be attached. The
negative input pin has a range of –200 mV up to 200 mV, and is shorted on the
EVM via SJP3. A signal for the positive input pin can be applied at connector
P1, pin 2 (shown in Table 2−1 ), or applied to the center pin of SMA connector
J2.
Table 2−1. Analog Input Connector
Description
Signal Name
Pin tied to Ground
Reserved
Reserved
Reserved
Pin tied to Ground
Pin tied to Ground
Reserved
Pin tied to Ground
Pin tied to Ground
Reserved
AGND
N/A
N/A
N/A
AGND
AGND
N/A
AGND
AGND
N/A
Connector.Pin#
P1.1
P1.3
P1.5
P1.7
P1.9
P1.11
P1.13
P1.15
P1.17
P1.19
P1.2
P1.4
P1.6
P1.8
P.10
P1.12
P1.14
P1.16
P1.18
P1.20
Signal Name
Description
+
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
REF+
Noninverting Input Channel
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
External Reference Input
Topic
Page
2.1
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Analog Interface
2-1
Signal Conditioning
2.1 Signal Conditioning
The factory recommends the analog input to any SAR-type converter be
buffered and low-pass filtered. It is important to note that the input buffer circuit
of the ADS8381EVM, shown in Figure 2−1, uses the THS4031 in an inverting
gain-of-one configuration. The amplifier is not stable in a conventional
gain-of-one configuration. The THS4031 was selected for its low noise, high
slew rate, and fast settling time. The low-pass filter resistor and capacitor
values are selected such that ADS8381EVM meets the 100-kHz AC
performance specifications listed in the data sheet. The series resistor works
with the capacitor to filter the input signal, but also isolates the amplifier from
the 6800-pF capacitive load. The capacitor to ground at the input of the A/D
works with the series resistor to filter the input signal, and acts like a charge
reservoir. This external filter capacitor works with the amplifier to charge the
internal sampling capacitor during sampling mode.
The EVM has a provision to offset the input voltage by adjusting R23, a 10-kΩ
potentiometer.
Figure 2−1. Input Buffer Circuit
1 kΩ
1 kΩ
−VCC
VI
0.1 µF
1 µF
4.096 V
−
10 Ω
THS4031
+
10 kΩ
500 Ω
(+) IN
1 µF
6800 pF
0.1 µF
0.22 µF
(−) IN
+VCC
2-2
Reference
2.2 Reference
The ADS8381EVM provides an onboard 4.096-V reference circuit.
This reference voltage can be applied directly to the VREF pin of the
converter; it does not need to be buffered. The EVM also has provision for a user-supplied external reference voltage. This voltage can
be filtered, as needed, by routing the signal through amplifier U1.
The EVM allows users to select from two reference sources. Set
SJP1 and SJP2 to select onboard reference voltage (REF3040), or
a user-supplied reference voltage via P1 pin 20. See Table 2−2 for
jumper settings. See Chapter 6 for the full schematic.
Table 2−2. Solder Short Jumper Setting
Jumper Setting
Reference
Designator
SJP1
Description
Select REF3040 output for reference voltage
1−2
Select buffered reference voltage
SJP2
Select U3, REF3040, as 4.096-V reference
Installed
Installed †
Buffer the user−supplied reference voltage
Installed
SJP3
Short (−)IN pin to ground
Installed †
SJP4
Apply offset voltage to A/D buffer
Installed †
SJP5
Set amplifier U1 negative supply to ground
Installed
Set amplifier U1 negative supply to −VCC
SJP6
Set amplifier U2 negative supply to ground
Set amplifier U2 negative supply to −VCC
†
2−3
Installed †
N/A
N/A
Installed†
Installed
Installed †
Factory-set condition
Analog Interface
2-3
2-4
Chapter 3
Digital Interface
The ADS8381EVM is designed for easy interfacing to multiple platforms.
Samtec part numbers SSW−110−22−F−D−VS−K and TSM−110−01−T−DV−P
provide a convenient dual-row-header/socket combination at P2 and P3.
Consult Samtec at www.samtec.com or 1−800−SAMTEC−9 for a variety of
mating connector options.
Table 3−1. Pinout for Parallel Control Connector P2
Connector.Pin
Signal
P2.1
DC_CS
Description
Daughtercard Board Select pin
P2.3
P2.5
P2.7
A0
Address line from processor
P2.9
A1
Address line from processor
P2.11
A2
Address line from processor
P2.13
P2.15
P2.17
P2.19
Note:
INTc
Set jumper W3 to select BUSY or inverted signal
to be applied to this pin.
All even-numbered pins of P2 are tied to DGND.
Read (RD) and conversion start (CONVST) signals to the converter can be
assigned to two different addresses in memory via jumper settings. This allows
for the stacking of up to two ADS8381EVMs into processor memory. See
Table 3−2 for jumper settings. Note, the evaluation module does not allow the
chip select (CS) line of the converter to be assigned to different memory
locations. It is therefore suggested that the CS line be grounded or wired to an
appropriate signal of the processor.
Digital Interface
3-1
Table 3−2. Jumper Settings
Jumper Settings
Reference Designator
W1
W2
W3
†
Description
1−2
2−3
Set A[2..0] = 0x1 to generate RD pulse
Installed †
Not installed
Set A[2..0] = 0x2 to generate RD pulse
Not installed
Installed
Set A[2..0] = 0x3 to generate CONVST pulse
Installed †
Not installed
Set A[2..0] = 0x4 to generate CONVST pulse
Not installed
Installed
Apply BUSY to P3 pin 19
Not installed
Installed †
Apply inverted BUSY to P3 pin 19
Installed
Not installed
Factory-set condition
The data bus is available at connector P3; see Table 3−3 for pinout
information.
Table 3−3. Data Bus Connector P3
Connector.Pin
Signal
P3.1
D0
Buffered Data Bit 0 (LSB)
P3.3
D1
Buffered Data Bit 1
P3.5
D2
Buffered Data Bit 2
P3.7
D3
Buffered Data Bit 3
Note:
Description
P3.9
D4
Buffered Data Bit 4
P3.11
D5
Buffered Data Bit 5
P3.13
D6
Buffered Data Bit 6
P3.15
D7
Buffered Data Bit 7
P3.17
D8
Buffered Data Bit 8
P3.19
D9
Buffered Data Bit 9
P3.21
D10
Buffered Data Bit 10
P3.23
D11
Buffered Data Bit 11
P3.25
D12
Buffered Data Bit 12
P3.27
D13
Buffered Data Bit 13
P3.29
D14
Buffered Data Bit 14
P3.31
D15
Buffered Data Bit 15
P3.33
D16
Buffered Data Bit 16
P3.35
D17
Buffered Data Bit 17 (MSB)
All even-numbered pins of P3 are tied to DGND.
This evaluation module provides direct access to all the analog-to-digital
converter control signals via connector J4; see Table 3−4.
Table 3−4. Pinout for Converter Control Connector J4
Connector.Pin
Signal
J4.1
CS
Chip Select pin. Active low
J4.3
RD
Read pin. Active low
J4.5
CONVST
J4.7
BYTE
J4.9
BUS 18/16
J4.11
BUSY
Note:
3-2
Description
Convert start pin. Active low
Byte select input. Used for 8-bit bus reading.
Bus size select input. Used for selecting 18-bit or 16-bit wide bus transfer.
Converter status output. High when a conversion is in progress.
All even-numbered pins of P4 are tied to DGND.
Chapter 4
Power Supply Requirements
The EVM accepts four power supplies.
- A dual ±Vs DC supply for the dual supply op amps. Recommend a ±6-VDC
supply.
- A single +5.0-VDC supply for analog section of the board (A/D + Refer-
ence).
- A single +5.0-V or +3.3-VDC supply for digital section of the board (A/D
+ address decoder + buffers).
There are two ways to provide these voltages.
1) Wire in the voltages at test points on the EVM. See Table 4−1.
Table 4−1. Power Supply Test Points
Test Point
Signal
Description
TP16
+BVDD
Apply +3.3 V or +5.0 V. See ADC data sheet for full range.
TP20
+AVCC
Apply +5.0 V.
TP14
+VA
Apply +6.0 V. Positive supply for amplifier.
TP18
−VA
Apply –6.0 V. Negative supply for amplifier.
2) Use the power connector J1, and derive the voltages elsewhere. The
pinout for this connector is shown below. If using this connector, set the
W4 jumper to connect +3.3 V or +5 V from connector to +BVDD. Short
between pins 1−2 to select +5 VD, or short between pins 2−3 to select
+3.3 VD as the source for the digital buffer voltage supply (+BVDD).
Table 4−2. Power Connector, J1, Pinout
Signal
Power Connector − J1
+VA (+6 V)
1
2
Signal
–VA (–6 V)
+5 VA
3
4
N/C
DGND
5
6
AGND
N/C
7
8
N/C
+3.3 VD
9
10
+5 VD
Power Supply Requirements
4-1
4-2
Chapter 5
Using the EVM
The ADS8381EVM serves three functions
1) As a reference design
2) As a prototype board and
3) As software test platform
Topic
Page
5.1
As a Reference Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2
As a Prototype Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3
As a Software Test Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Using the EVM
5-1
As a Reference Board
5.1 As a Reference Board
As a reference design, the ADS8381EVM contains the essential circuitry to
showcase the analog-to-digital converter. This essential circuitry includes the
input amplifier, reference circuit, and buffers. The EVM analog input circuit is
optimized for a 100-kHz sine wave; therefore, users may need to adjust the
resistor and capacitor values of the A/D input RC circuit. In AC type
applications where signal distortion is a concern, polypropylene capacitors
should be used in the signal path.
5.2 As a Prototype Board
As a prototype board, the buffer circuit consists of a standard 8-pin SOIC
footprint and resistor pads for inverting and noninverting configurations. The
ADS8381EVM can be used to evaluate both dual-supply and single-supply
amplifiers. The EVM comes installed with a dual-supply amplifier as it allows
the user to take advantage of the full input voltage range of the converter. For
applications that require single-supply operation (and a smaller input voltage
range), the THS4031 can be replaced with a single-supply amplifier like the
OPA300. Pad jumper SJP6 should be shorted between pads 1 and 2, as it
shorts the minus supply pin of the amplifier to ground. Positive supply voltage
can be applied via test point TP14 or connector J1, pin 1.
5.3 As a Software Test Platform
As a software test platform, connectors P1, P2, and P3 plug into the parallel
interface connectors of the 5−6K interface card. The 5−6K interface card sits
on the TMS320C5000 and TMS320C6000 DSP platform starter kit (DSK).
The ADS8381EVM is then mapped into the processor memory space. This
card also provides an area for signal conditioning. This area can be used to
install application circuit(s) for digitization by the ADS8381 analog-to-digital
converter. See the 5−6K interface card user’s guide (SLAU104) for more
information.
For the software engineer, the ADS8381EVM provides a simple platform for
interfacing to the converter. The EVM provides standard 0.1-inch headers and
sockets to wire into prototype boards. The user need only provide 3 address
lines (A2, A1, and A0) and address-valid line (DC_CS) to connector P2. To
choose the address combinations that generate RD and CONVST, set
jumpers as shown in Table 3−2. Recall that the chip select (CS) signal is not
memory-mapped or tied to P2; therefore, it must be controlled via a general
purpose pin or shorted to ground at J3 pin 1. If address decoding is not
required, the EVM provides direct access to converter data bus via P3 and to
control via J3.
5-2
Chapter 6
ADS8381EVM BOM, Layout, and Schematic
This chapter contains the ADS8381EVM bill of materials, the layouts, and the
schematic.
Topic
Page
6.1
ADS8381EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2
ADS8381EVM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.3
ADS8381EVM Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
ADS8381EVM BOM, Layout, and Schematic
6-1
ADS8381EVM Bill of Materials
6.1 ADS8381EVM Bill of Materials
Table 6−1 contains a complete bill of materials for the ADS8381EVM. The
schematic diagram also is provided for reference. Contact the Product
Information Center or send an e−mail to dataconvapps@list.ti.com for
questions regarding this EVM.
Table 6−1. ADS8381EVM Bill Of Materials
Reference
Designator
QTY
Value
Footprint
Mfr
Mfr’s Part Number
Description
R4, R21
2
0Ω
603
Panasonic−ECG
or Alternate
ERJ−3GEY0R00V
0 Ω 1/16 W 5% 0603
SMD
R1
1
0Ω
805
Panasonic−ECG
or Alternate
ERJ−6GEY0R00V
0.0 Ω 1/10W 5% 0805
SMD
R13
1
10 Ω
805
Panasonic−ECG
or Alternate
ERJ−6ENF10R0V
10.0 Ω 1/10W 1%
0805 SMD
R24
1
50 Ω
805
Panasonic−ECG
or Alternate
ERJ−6ENF49R9V
49.9 Ω 1/10W 1%
0805 SMD
R14, R15
2
100 Ω
603
Panasonic−ECG
or Alternate
ERJ−3EKF1000V
100 Ω 1/16W 1% 0603
SMD
R25
1
100 Ω
805
Not installed
Not installed
R2
1
NI
805
Not installed
Not installed
R6, R10
2
1k
805
Panasonic−ECG
or Alternate
ERJ−6ENF1001V
1.00 kΩ 1/10W 1%
0805 SMD
R16, R17,
R18, R19,
R20
5
10k
603
Panasonic−ECG
or Alternate
ERJ−3EKF1002V
10.0 kΩ 1/16W 1%
0603 SMD
R7
1
10k
805
Panasonic−ECG
or Alternate
ERA−S15J103V
10 kΩ 1/10W 1500
PPM 5%0805
R3
1
NI
603
Not installed
Not installed
R11
1
NI
805
Not installed
Not installed
C3, C5,
C11, C23
4
1 nF
1206
Kemet or
Alternate
C1206C102J5GACTU
1000 pF 50 V ceramic
NPO 1206
C39
1
6800 pF
TH
WIMA or
Alternate
MKP2 6800/630/5
6800 pF polypropylene
capacitor
C21, C41,
C44, C46,
C48, C53,
C56, C65,
C50
9
0.01 µF
603
Kemet or
Alternate
C0603C103J5RACTU
10000 pF 50 V
ceramic X7R 0603
C10, C20
2
0.01 µF
805
Kemet or
Alternate
C0805C103K5RACTU
10000 pF 50 V
ceramic X7R 0805
C4, C26
2
0.01 µF
1206
Kemet or
Alternate
C1206C103J5RACTU
10000 pF 50 V
ceramic X7R 1206
C25, C40,
C42, C43,
C47, C51,
C52, C54,
C55, C57,
C58, C59,
C64, C38
14
0.1 µF
603
Kemet or
Alternate
C0603C104K3RACTU
0.1 µF 25 V ceramic
X7R 0603
6-2
ADS8381EVM Bill of Materials
Reference
Designator
QTY
Value
Footprint
Mfr
Mfr’s Part Number
Description
C7, C9,
C15, C22,
C32, C34,
C36
7
0.1 µF
805
Kemet or
Alternate
C0805C104J5RACTU
Capacitor, 0.1 µF 50 V
ceramic X7R 0805
C8, C16,
C31, C37
4
1 µF
805
Panasonic −
ECG or
Alternate
ECJ−GVB1C105K
Capacitor, 1 µF 16 V
ceramic X5R 0805
C2, C28
2
1 µF
1206
Kemet or
Alternate
C1206C105K3RACTU
Capacitor, 1.0 µF 25 V
ceramic X7R 1206
C33
1
0.22 µF
805
Panasonic−ECG
or Alternate
ECJ−2VB1C224K
Capacitor, .22 µF 16 V
ceramic X7R 0805
C63
1
0.47 µF
603
Panasonic−
ECG or
Alternate
ECJ−1VF1C474Z
Capacitor .47 µF 16V
ceramic Y5V 0603
C62
1
10 µF
805
Not installed
Not installed
C1, C6,
C12, C19
4
10 µF
1206
Panasonic−ECG
or Alternate
ECJ−3YB1C106M
Capacotor, 10 µF 16 V
ceramic X5R 1206
C14, C24,
C27, C29,
C49
5
10 µF
3528
Kemet or
Alternate
T491B106K016AS
Capacitor, TANT 10 µF
16 V 10% SMT
C17
1
47 µF
1206
TDK Corporation
or Alternate
C3216X5R0J476M
Capacitor, CER 47 µF
6.3 V X5R 20% 1206
C13, C18,
C45, C60,
C61
5
NI
603
Not installed
Not installed
C30, C35,
R5
3
NI
805
Not installed
Not installed
RP1, RP3
2
1 kΩ
CTS_742
CTS Corporation
742C163102JTR
Resistor Array, 1 kΩ
16TERM 8RES SMD
RP2
1
100 Ω
CTS_742
CTS Corporation
742C163101JTR
Resistor Array, 100 Ω
16TERM 8RES SMD
RP4
1
1 kΩ
CTS_742_4R
ES
CTS Corporation
744C083102JTR
Resistor ARAY 1 kΩ
16TERM 4RES SMD
R23
1
10kΩ
BOURNS
32X4W
Bourns
3214W−1−103E
TRIMPOT, 10 kΩ 4MM
Top Adj SMD
L1, L2, L3,
L4
4
BLM21AJ60
1SN1L
1206
MURATA ERIE
BLM31PG601SN1L
Chip, Ferrite Beads−
600 Ω @ 100 MHz
U1
1
OPA627
8−SOP(D)
Texas
Instruments
OPA627AU
Amplifier
U2
1
THS4031
8−SOP(D)
Texas
Instruments
THS4031IDR
100-MHz low-noise
high-speed amplifier
U3
1
REF3040
3−SOT−23
Texas
Instruments
REF3040AIDBZT
REF3040 50 ppm/°C,
50 µA in SOT23−3
CMOS voltage
reference
U4
1
ADS8381
Socket
48QFP
Texas
Instruments
ADS8381IPFB
ADS8381 18 bit
580 KSPS
U5, U6, U7,
U8
4
SN74AHC24 20−TSSOP(P
5PWR
W)
Texas
Instruments
SN74AHC245PWR
Octal bus transceiver,
3-state
ADS8381EVM BOM, Layout, and Schematic
6-3
ADS8381EVM Bill of Materials
Reference
Designator
QTY
Value
Footprint
Mfr
Mfr’s Part Number
Description
U9
1
SOIC−8
Footprint
8−SOP(D)
Not installed
Not installed
Footprint for 8-pin
SOIC reference
operates from +5 V.
U10
1
REF3020
3−SOT−23
Not installed
Not installed
REF3020 50 ppm/°C,
50 µA in SOT23−3
CMOS voltage
reference
U11
1
SN74AHC13 16−TSSOP(P
8PWR
W)
Texas
Instruments
SN74AHC138PWR
3−Line to 8−Line
Decoder/Demultiplexer
U12
1
SN74AHC1
G04DBV
5−SOT(DBV)
Texas
Instruments
SN74AHC1G04DBVR
Single inverter gate
J1
1
5X2X.1
5X2X.1_SMT
_SOCKET
Samtec
SSW−105−22−S−D−VS
0.025” SMT socket –
bottom side of PWB
Samtec
TSM−105−01−T−D−V−P 0.025” SMT plug – top
side of PWB
J2
1
SMA_PCB_
MT
SMA_JACK
Johnson
Components Inc.
142−0701−301
Right Angle SMA
Connector
J4
1
6X2X.1
6X2X.1_SMT
_plug_&_soc
ket
Samtec
SSW−106−22−S−D−VS
0.025” SMT Socket−
bottom side of PWB
Samtec
TSM−106−01−T−D−V−P 0.025” SMT PLUG −
top side of PWB
18X2X.1_
SMT_PLUG
_&_SOCKET
18X2.1_SMT
_PLUG_&_S
OCKET
Samtec
SSW−118−22−S−D−VS
Samtec
TSM−118−01−T−D−V−P 0.025” SMT plug − top
side of PWB
10X2X.1
10X2X.1_SM
T_PLUG_&_
SOCKET
Samtec
SSW−110−22−S−D−VS
Samtec
TSM−110−01−T−D−V−P 0.025” SMT plug − top
side of PWB
P3
P1, P2
1
2
0.025” SMT socket −
bottom side of PWB
0.025” SMT socket −
bottom side of PWB
SJP3,
SJP4
2
SJP2
SJP2
Not installed
Not installed
Pad 2 position Jumper
SJP1,
SJP2,
SJP5,
SJP6
4
SJP3
SJP3
Not installed
Not installed
Pad 3 Postion Jumper
W1, W2
4
3pos_jumper 3pos_jump
Samtec
TSW−103−07−L−S
3 Position
Jumper_0.1” spacing
16
TP_0.025
Keystone
Electronics
5000K–ND
Test Point − Single
0.025” Pin
W3, W4
TP1, TP2,
TP3, TP4,
TP5, TP6,
TP7, TP8,
TP9, TP14,
TP15,
TP16,
TP17,
TP18,
TP19,
TP20
6-4
test_point2
ADS8381EVM Layout
6.2 ADS8381EVM Layout
Figure 6−1. Top Layer—Layer 1
Figure 6−2. Ground Plane—Layer 2
ADS8381EVM BOM, Layout, and Schematic
6-5
ADS8381EVM Layout
Figure 6−3. Power Plane—Layer 3
Figure 6−4. Bottom Layer—Layer 4
6-6
ADS8381EVM Schematic
6.3 ADS8381EVM Schematic
The schematic follows this page.
ADS8381EVM BOM, Layout, and Schematic
6-7
1
2
3
4
5
6
Revision History
REV
ECN Number
Approved
D
D
J2
Analog-to-Digital Converter
P1
EXT_REF
DB[17...0]
+IN
BUSY
2
4
6
8
10
12
14
16
18
20
B_CS
B_RD
B_CONVST
B_BYTE
B_BUS18/16
1
3
5
7
9
11
13
15
17
19
DB[17..0]
Analog Input
Power & Digital Buffer
C
C
+VA
+VA
TP18
2
4
6
8
10
-VA
AGND
-VA
TP19
+5VD
W4
TP16
+BVDD
A0
A1
A2
INTc
+3.3VD
1
3
5
7
9
B_DB[17...0]
DC_CS
+VA
+5VA
DGND
-VA
ADC_CS
ADC_RD
ADC_CONVST
BYTE
BUS18/16
B_BUSY
TP15
J1
DB[17...0]
+5VA
BUSY
+5VA
TP14
B_CS
B_RD
B_CONVST
B_BYTE
B_BUS18/16
TP20
B_DB[17...0]
B_DB0
B_DB1
B_DB2
B_DB3
B_DB4
B_DB5
B_DB6
B_DB7
B_DB8
B_DB9
B_DB10
B_DB11
B_DB12
B_DB13
B_DB14
B_DB15
B_DB16
B_DB17
P3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
B
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
B
ADC Data Bus
J4
2
1
4
3
6
5
8
7
10 9
12 11
ADC_CS
ADC_RD
ADC_CONVST
BYTE
BUS18/16
B_BUSY
ADC Control
P2
2
4
6
8
10
12
14
16
18
20
A
1
3
5
7
9
11
13
15
17
19
DC_CS
A0
A1
A2
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TITLE:
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BlockDiagram.sch
ADS8381/ADS8383EVM Block Diagram
DOCUMENT CONTROL #:
REV:
A
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Drawn By:
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REV
ECN Number
Approved
EXT_REF
TP9
3
D
D
R15
+VCC
1
100
+5VCC
C63
0.47uF
+5VCC
C16
1uF
U3
1
C36
0.1uF
GND
0.1uF
2
OUT
SJP1
3
47uF
2
R14
6
1
OPA627
2 4
1
2
C
C45
NI
C18
3
NI
4
NC
+VIN
EN
GND
NC
VREF
NC
IN
GND
OUT
100
R25
+VBD
2
NI
SJP5
C8
1uF
7
C43
C21
0.1uF
0.01uF
C48
C42
0.1uF
C13
1
2
3
4
5
6
7
8
9
10
11
12
0.01uF
5
NI
R21
0
+5VCC
C47
2
0.1uF
SJP4
C37
1uF
C60*
7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
C56
0.01uF
C
BUSY
C55
0.1uF +VBD
8
1
5
NI
C30
1
C52
0.1uF
0
B
*
C39
4
6800pF
*
-VCC
3
SJP6
C31
R6
1000
1uF
C7
0.1uF
1
NI
C44
0.01uF
R1
10
THS4031
R2
2
0.22uF
BUSY
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
R13*
6
2
C33
+IN
0.01uF
36
35
34
33
32
31
30
29
28
27
26
25
NI
U2
3
B
C46
0.1uF
ADS8381/ADS8383
+5VCC
0
NI
C40
C15
0.1uF
R4
R5
C41
0.01uF
U4
DB[17...0]
BUSY
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
BDGND
DB[17...0]
10k
1
REFIN
BIAS
NC
+VA
AGND
+IN
-IN
AGND
+VA
+VA
AGND
AGND
13
14
15
16
17
18
19
20
21
22
23
24
R23
+5VCC
+VCC
TP4
C65
0.01uF
+5VCC
R3
SOIC-8 Footprint
C64
0.1uF
C32
0.1uF
6
NI
C49
10uF
C62
NI
3
8
1
NI
-VCC
1
NC
3
48
47
46
45
44
43
42
41
40
39
38
37
U9
+5VCC
0.01uF
.01uF
U10
3
C17
C53
2
U1
5
49.9
B_CS
B_RD
B_CONVST
B_BYTE
B_BUS18/16
C50
7
R24
REF3040
0.1uF
C61
NI
1
IN
+
3
B_CS
B_RD
B_CONVST
B_BYTE
B_BUS18/16
+5VCC
C51
C54
REFM
REFM
+VA
AGND
AGND
+VA
CS
RD
CONVST
BYTE
BUS18/16
+VA
SJP2
+VA
AGND
AGND
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
+VBD
+5VCC
2
R11
SJP3
NI
2
R10
1000
C35*
NI
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ADS8381/ADS8383EVM Analog Circuits
DOCUMENT CONTROL #:
Analog-to-Digital Converter DATE:
REV:
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SHEET:
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TP6
+5VA
REV
+5VCC
L3
+5VA
ECN Number
Approved
BLM21AJ601SN1L
+ C14
C9
10uF
C12
10uF
C11
C10
0.1uF
0.01uF
1000nF
+VBD
TP5
D
+VBD
U8
B_RD
/OE
VCC
DIR
D
C59
0.1uF
TP8
+BVDD
A1
A2
A3
A4
A5
A6
A7
A8
+VBD
L4
+BVDD
RP4
BLM21AJ601SN1L
+ C24
C19
C22
10uF
10uF
DB0
DB1
C23
C20
0.1uF
0.01uF
1000nF
B1
B2
B3
B4
B5
B6
B7
B8
B_DB0
B_DB1
1K
GND
TP7
+VBD
U7
B_RD
TP3
+VA
+ C29
C28
10uF
C6
1uF
10uF
C4
C5
0.01uF
1000nF
DB[17...0]
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB[17...0]
TP2
TP17
VCC
C58
0.1uF
DIR
BLM21AJ601SN1L
C
/OE
+VCC
L2
+VA
SN74AHC245PWR
+VBD
RP3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
A2
A3
A4
A5
A6
A7
A8
B_DB2
B_DB3
B_DB4
B_DB5
B_DB6
B_DB7
B_DB8
B_DB9
B1
B2
B3
B4
B5
B6
B7
B8
C
1K
10uF
C1
10uF
GND
C2
+ C27
C26
1uF
C3
0.01uF
SN74AHC245PWR
1000nF
TP1
L1
-VA
-VA
BLM21AJ601SN1L
+VBD
-VCC
+VBD
B_RD
U6
/OE
B_DB[17...0]
B_DB[17...0]
C57
0.1uF
VCC
DIR
RP1
+VBD
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
+VBD
C25
0.1uF
U5
R20
10k
VCC
R19
10k
R18
10k
+VBD
DIR
B_BUSY
B_CS
B_RD
B_CONVST
B_BYTE
B_BUS18/16
1
2
3
4
5
6
7
8
B_BUSY
16
15
14
13
12
11
10
9
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
100
ADC_CS
ADC_RD
ADC_CONVST
BYTE
BUS18/16
ADC_CS
ADC_RD
ADC_CONVST
BYTE
BUS18/16
BUSY
R17
R16
10k
10k
2
3
GND
1
SN74AHC245PWR
2
+VBD
W2
B
C34
0.1uF
15
14
13
12
11
10
9
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A
B
C
G1
G2A
G2B
1
2
3
A0
A1
A2
6
4
5
A0
A1
A2
+VBD
R7
10k
+VBD
DC_CS
DC_CS
SN74AHC138PWR
3
8
C38
B_DB10
B_DB11
B_DB12
B_DB13
B_DB14
B_DB15
B_DB16
B_DB17
GND
U11
W1
B1
B2
B3
B4
B5
B6
B7
B8
SN74AHC245PWR
1
B_CS
B_RD
B_CONVST
B_BYTE
B_BUS18/16
A1
A2
A3
A4
A5
A6
A7
A8
16
RP2
16
15
14
13
12
11
10
9
1K
VCC
/OE
GND
B
1
2
3
4
5
6
7
8
0.1uF
A
ti
W3
5
INTc
4
3
2
U12
1
A
12500 TI Boulevard. Dallas, Texas 75243
TITLE:
SN74AHC1G04DBV
2
3
4
5
Engineer:
Lijoy Philipose
Drawn By:
Lijoy Philipose
FILE:
Power & Digital Buffer
Power Supply & Digital Buffer Circuits
DOCUMENT CONTROL #:
REV:
A
6448017
DATE:
23-Sep-2004
SIZE:
6
SHEET:
3
OF:
3
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