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Texas Instruments DAC7654 EVM User guides
DAC7654
Evaluation Module
User’s Guide
April 2004
Data Acquisition
SLAU130
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Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2004, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright  2004, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the supply voltage range of −5.25 V to 5.25 V and
−15 V to 15 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
100°C. The EVM is designed to operate properly with certain components above 100°C as
long as the input and output ranges are maintained. These components include but are not
limited to linear regulators, switching transistors, pass transistors, and current sense
resistors. These types of devices can be identified using the EVM schematic located in the
EVM User’s Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright  2004, Texas Instruments Incorporated
How to Use This Manual
Preface
Read This First
About This Manual
This user’s guide describes the DAC7654 evaluation module. It covers the
operating procedures and characteristics of the EVM board along with the
device that it supports. The physical PCB layout, schematic diagram, and
circuit descriptions are included.
How to Use This Manual
This document contains the following chapters:
- Chapter 1 – EVM Overview
- Chapter 2 – PCB Design and Performance
- Chapter 3 – EVM Operation
Information about Cautions and Warnings
This manual may contains cautions and warnings.
This is an example of a CAUTION statement.
A CAUTION statement describes a situation that could
potentially damage this EVM board or your software or
equipment.
This is an example of a WARNING statement.
A WARNING statement describes a situation that could
potentially cause HARM to you.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
iii
Contents
Related Documentation From Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas
Instruments Literature Response Center at (800) 477 – 8924 or the Product
Information Center (PIC) at (972) 644 – 5580. When ordering, identify this
manual by its title and literature number. Updated documents can also be
obtained through our Web site at www.ti.com.
Data Sheets:
DAC7654
OPA627
Literature Number:
SBAS263
SBOS165
If you need Assistance
If you have questions about this or other Texas Instruments Data Converter
evaluation modules, please feel free to e−mail the Data Converter Application
Team at dataconvapps@list.ti.com. Please include in the subject heading
the product you have questions or concerns with.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
Trademark
TI and the TI Logo are trademarks of Texas Instruments Incorporated.
iv
v
Contents
Contents
1
EVM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2 Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
PCB Design and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
EVM Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
3
EVM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Factory Default Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Host Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
EVM Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
The Output Operation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Unity Gain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Output Gain of Two (Default Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
Digitally Programmable Current Source Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
1-1
1-2
1-2
1-2
1-2
1-3
3-1
3-2
3-3
3-4
3-4
3-4
3-4
3-5
3-7
3-9
Contents
Figures
1−1
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−8
2−9
2−10
2−11
2−12
3−1
3−2
3−3
DAC7654 EVM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Top Silkscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Layer 1 (Top Signal Plane) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Layer 2 (Ground Plane) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Layer 3 (Power Plane) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Layer 4 (Bottom Signal Plane) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Bottom Silkscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Drill Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
DAC7654 EVM Test Parameters and Results in Bipolar Configuration . . . . . . . . . 2-7
INL and DNL Characterization Graph of DAC7654 Channel A . . . . . . . . . . . . . . . . . 2-8
INL and DNL Characterization Graph of DAC7654 Channel B . . . . . . . . . . . . . . . . . 2-9
INL and DNL Characterization Graph of DAC7654 Channel C . . . . . . . . . . . . . . . . 2-10
INL and DNL Characterization Graph of DAC7654 Channel D . . . . . . . . . . . . . . . . 2-11
DAC7654 EVM Default Jumper Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Digitally Programmable Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
DAC7654 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Tables
2−1
3−1
3−2
3−3
3−4
3−5
3−5
DAC7654 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
DAC7654 EVM Jumper Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
DAC7654 Output Channel Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Unity Gain Output Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Gain of Two Output Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Digitally Programmable Current Source Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Jumper Setting Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
vii
Chapter 1
EVM Overview
This chapter provides an overview of the DAC7654 evaluation module (EVM)
and instructions on setting up and using the EVM.
Topic
Page
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2
Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3
EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
EVM Overview
1-1
Features
1.1 Features
This EVM features the DAC7654 digital-to-analog converters (DAC). It
provides a quick and easy way to evaluate the functionality and performance
of the high-resolution serial input quad DAC. The EVM provides the serial
interface header to easily attach to any host microprocessor or TI DSP base
system for communication.
1.2 Power Requirements
The following sections describe the power requirements of this EVM.
1.2.1
Supply Voltage
The dc power supply for the digital section (VDD) of this EVM is dedicated to
5 V via the J3−1 terminal or J6−10 terminal and is referenced to ground through
the J3−2 and J6−5 terminals. The power for IOVDD can be selected between
3.3 V and 5 V via the W23 jumper. If the 5 V is selected for IOVDD, it is basically
the same power as VDD. The 3.3 V comes from J3−3 or J6−9 terminals and
referenced to J3−2 and J6−5, respectively.
The dc power supply requirements for the analog section of this EVM are as
follows: the VCC and VSS are typically ±15 V but can range from ±4.5 V
minimum to ±18 V maximum and connect through J1−3 and J1−1,
respectively, or through J6−1 and J6−2 terminals. The 5 VA connects through
J6−3 and the −5 VA connects through J6−4. All of the analog power supplies
are referenced to analog ground through J1−2 and J6−6 terminals.
The device under test (U1) analog power supply can be provided by ±5 VA (via
J6−3 and J6−4). The VCC supply source provides the positive rail of the
external output operational amplifier, U2. The negative rail of U2 can be
selected between VSS and AGND via the W5 jumper. The external operational
amplifier is installed as an option to provide output signal conditioning or for
other output configurations.
CAUTION
To avoid potential damage to the EVM board, make sure the correct
cables are connected to their respective terminals as labelled on
the EVM board.
Stresses above the maximum listed voltage ratings may cause
permanent damage to the device.
1.2.2
Reference Voltage
The precision voltage reference up to ±2.5 V is internally generated by the
DAC7654. This provides the DAC7654 voltage output range.
1-2
EVM Basic Functions
1.3 EVM Basic Functions
This EVM is designed primarily as a functional evaluation platform to test
certain functional characteristics of the DAC7654 DAC. Functional evaluation
of the installed DAC device can be accomplished with the use of any
microprocessor, TMS320 DSP family or some sort of a waveform generator.
The headers J2 and P2 are connectors provided to allow the control signals
and data required to interface a host processor or waveform generator with the
DAC7654 EVM using a custom-built cable.
A specific adapter interface card is available for most of TI’s DSP Starter Kit
(DSK), and the card model depends on the type of the TI DSP Starter Kit to
be used. To acquire the correct adapter interface card, be sure to specify the
DSP that is used. This EVM can connect to and interface with an MSP430
based platform (HPA449) that uses the MSP430F449 microprocessor. For
more details or information regarding the adapter interface card or the HPA449
platform, call Texas Instruments. or send email to dataconvapps@list.ti.com.
The DAC outputs are monitored through the selected pins of the J4 header
connector. The outputs of U1 can be switched from their respective jumpers
W2, W3, W4, and W10 for stacking purposes. Stacking allows a total of eight
DAC channels if two DAC7654 EVMs are stacked.
In addition, the option of selecting one DAC output (from J4−2, 4, 6, and 8 only)
to be connected to the output operational amplifier, U2, is also possible by
using a jumper across the selected pins of J4. The output operational amplifier,
U2, is configurable through J5, W5, and W15 for any desired waveform
characteristic.
A block diagram of the DAC7654 EVM is shown in Figure 1−1.
EVM Overview
1-3
EVM Basic Functions
Figure 1−1. DAC7654 EVM Block Diagram
VC C
+3.3 VA
4 CH
U2
Out put
Buf f er
M odule
DACOut
TP 5
W23
W6
W7
W8
W9
TP7
TP6
(J4)
(P4)
J5
8 CH
VD D
±5 VA
VOU T
4 CH
(J 2)
(P2)
IOVDD VCC/VSS
DACModule
VOUTS2
VOUTS1 DGND
AGND
U1
W15
W5
TP 1 / TP 2
VOUTA /
VOUTD
VSS
Q1/ Q2
W22/W24
TP 9 / TP 1 0
W11/W21
R1/R2
N OTE: a) See Sec t ion 3. 5
b) Same circuit for
V OUT A and VOUT D.
1-4
(J6)
(P6)
4 CH
OFSR 2 OFSR 1
W1
W12
W13
W20
VC C
GN D
VSS
GN D
VD D
±5VA
+3.3VD
(J1)
(J3)
VSS
RST
RSTSEL
CS
LOAD
SD I
LD AC
SC LK
SD O
Chapter 2
PCB Design and Performance
This chapter discusses the layout design of the PCB, describing the physical
and mechanical characteristics of the EVM. It shows the resulting performance of the EVM, which can be compared to the device specification listed
in the data sheet. The list of components used on the module is included in the
bill of materials (BOM).
Topic
Page
2.1
PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
EVM Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
PCB Design and Performance
2-1
PCB Layout
2.1 PCB Layout
The DAC7654 EVM is designed to demonstrate the performance quality of the
installed DAC device under test, as specified in the data sheet. Careful
analysis of the EVM’s physical restrictions and factors that contributes to the
EVM’s performance degradation is the key to a successful design
implementation. The attributes that contributes to the poor performance of the
EVM can be avoided during the schematic design phase by properly selecting
the correct components and correctly designing the circuit. The circuit should
include adequate bypassing, identifying and managing the analog and digital
signals, and knowing or understanding the components mechanical attributes.
The obscure part of the design lies particularly in the layout process. The main
concern is primarily with the placement of components and the proper routing
of signals. The bypass capacitors must be placed as close as possible to the
pins, and the analog and digital signals should be properly separated from
each other. The power and ground plane is important and should be carefully
considered in the layout process. A solid plane is ideally preferred but
sometimes impractical; so, when solid planes are not possible, a split plane
does the job. When considering a split plane design, analyze the component
placement and carefully split the board into its analog and digital sections
starting from the device under test. The ground plane plays an important role
in controlling the noise and other effects that otherwise contributes to the error
of the DAC output. To ensure that the return currents are handled properly,
route the appropriate signals only in their respective sections, meaning the
analog traces should only lay directly above or below the analog section and
the digital traces in the digital section. Minimize the length of the traces but use
the largest trace width possible in the design. These design practices
discussed are seen in the following figures.
The DAC7654 EVM board is constructed on a four-layer printed-circuit board
using a copper-clad FR−4 laminate material. The printed-circuit board has a
dimension of 43,1800 mm (1.7000 inch) X 82,5500 mm (3.2000 inch), and the
board thickness is 1,5748 mm (0.0620 inch). Figure 2−1 through Figure 2−7
show the individual artwork layers.
2-2
PCB Layout
Figure 2−1. Top Silkscreen
Figure 2−2. Layer 1 (Top Signal Plane)
PCB Design and Performance
2-3
PCB Layout
Figure 2−3. Layer 2 (Ground Plane)
Figure 2−4. Layer 3 (Power Plane)
2-4
PCB Layout
Figure 2−5. Layer 4 (Bottom Signal Plane)
Figure 2−6. Bottom Silkscreen
PCB Design and Performance
2-5
PCB Layout
Figure 2−7. Drill Drawing
2-6
EVM Performance
2.2 EVM Performance
The EVM performance test is performed using a high density DAC bench test
board, an Agilent 3458A digital multimeter, and a PC running the LABVIEW
software. The EVM board is tested for all codes of the device under test (DUT)
and is allowed to settle for 1 ms before the meter is read. This process is
repeated for all codes to generate the measurements for INL and DNL results.
The parameters and results of the DAC7654 EVM characterization test are
shown in Figure 2−8 to Figure 2−12.
Figure 2−8. DAC7654 EVM Test Parameters and Results in Bipolar Configuration
PCB Design and Performance
2-7
EVM Performance
Figure 2−9. INL and DNL Characterization Graph of DAC7654 Channel A
2-8
EVM Performance
Figure 2−10. INL and DNL Characterization Graph of DAC7654 Channel B
PCB Design and Performance
2-9
EVM Performance
Figure 2−11. INL and DNL Characterization Graph of DAC7654 Channel C
2-10
EVM Performance
Figure 2−12. INL and DNL Characterization Graph of DAC7654 Channel D
PCB Design and Performance
2-11
Bill of Materials
2.3 Bill of Materials
Table 2−1. DAC7654 Bill of Materials
Item #
2-12
Designator
Manufacturer
Part Number
Description
0.01µF, 1206 Multilayer
Ceramic Capacitor
0.1µF, 1206 Multilayer
Ceramic Capacitor
1nF, 1206 Multilayer
Ceramic Capacitor
10µF, 1210 Multilayer
Ceramic X5R Capacitor
470pF, 50V, 1206 Multilayer
Ceramic Capacitor SMD
0 Ohm, 1/4W 1206 Chip
Resistor
124 Ohms, 1%, 1/8W 1206
Chip Resistor
100 Ohms, 1/4W 1206 Chip
Resistor
2K Ohms, 5%, 1/4W 1206
Chip Resistor
10K Ohms, 1/4W 1206 Chip
Resistor
FET Transistor NPN
35VCEO 50MA MINI−3P
4 Position Jumper_ .1”
spacing
1
2
C9 C10
Panasonic
ECUV1H103KBM
2
5
C1 C2 C7 C8 C11
Panasonic
ECJ3VB1C104K
3
1
C12
Panasonic
ECUV1H102JCH
4
3
C4 C5 C6
Kemet
C1210C106K8PAC
5
1
C3
Kemet
ECU−V1H471KBM
6
3
R3 R7 R9
Panasonic
ERJ−8GEY0R00V
7
2
R1 R2
Panasonic
ERJ−8ENF1240V
8
1
R4
Panasonic
ERJ−8GEYJ101V
9
1
R8
Panasonic
ERJ−8GEYJ202V
10
4
R5 R6 R12 R13
Panasonic
ERJ−8ENF1002V
11
2
Q1 Q2
Panasonic
2SC24050RL
12
1
J5
Molex
22−03−2041
13
1
J6
Samtec
TSM−105−01−T−DV
14
2
J2 J4
Samtec
TSM−110−01−S−DV−M
15
2
J1 J3
On−Shore Technology
ED555/3DS
16
1
U1
Texas Instruments
DAC7654IDGS
16−bit, Quad Voltage Output, Serial Input DAC,
PQFP−64
17
1
U2
Texas Instruments
OPA627AU
8−SOP(D) Precision Op
Amp
18
7
TP1 TP2 TP3 TP4
Mill−Max
TP5 TP6 TP7
2348−2−01−00−00−07−0
Turret Terminal Test Point
19
2
P2 P4 (see Note)
Samtec
SSW−110−22−S−D−VS−P
20
1
P6 (see Note)
Samtec
21
9
W6 W7 W8 W9
W14 W15 W16
W22 W24
Molex
22−03−2021
2 Position Jumper_ .1”
spacing
15
W1 W2 W3 W4
W5 W10 W11
W12 W13 W20
W21 W23 W25
W26 W27
Molex
22−03−2031
3 Position Jumper_ .1”
spacing
22
Note:
Qty
5X2X0.1
10−pin 3A Isolated Power
Socket
10X2X.1, 20 Pin .025”sq
SMT Socket
3−Pin Terminal Connector
20PIN .025”sq SMT Terminal Strips
3A Isolated 10−pin Power
SSW−105−22−F−D−VS−K
Header
P2, P4 & P6 parts are not shown in the schematic diagram. All the P designated parts are installed in the
bottom side of the PC Board opposite the J designated counterpart. Example, J2 is installed on the topside
while P2 is installed in the bottom side opposite of J2. Not all parts listed in the BOM are installed in the
EVM as they are specific to the DUT installed.
Chapter 3
EVM Operation
This chapter covers in detail the operation of the EVM to provide guidance to
the user in evaluating the onboard DAC and interfacing the EVM to a host
processor.
See the specific DAC data sheet, as listed in the Related Documentation from
Texas Instruments section of this user’s guide, for more information about the
DAC serial interface and other related topics.
The EVM board is factory tested and configured to operate in the bipolar output
mode.
Topic
Page
3.1
Factory Default Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
Host Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3
EVM Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4
The Output Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.5
Digitally Programmable Current Source Application . . . . . . . . . . . . . 3-5
3.6
Jumper Setting Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.7
Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
EVM Operation
3-1
Factory Default Setting
3.1 Factory Default Setting
The EVM board is set to its default configuration from the factory as described
in Table 3−1 to operate in bipolar ±2.5-V output operation. The following
default jumper settings are shown in Figure 3−1.
Table 3−1. DAC7654 EVM Jumper Default Configuration
Reference
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W20
W21
W22
W23
W24
W25
W26
W27
TP9
TP10
J4
J5
3-2
Jumper
Position
2−3
1−2
1−2
1−2
1−2
OPEN
OPEN
OPEN
OPEN
1−2
OPEN
2−3
2−3
OPEN
CLOSED
OPEN
2−3
OPEN
OPEN
2−3
OPEN
2−3
2−3
1−2
OPEN
OPEN
1−2
2−3
Function
Dual supply operation
DAC output A (VOUTA) is routed to J4−2
DAC output B (VOUTB) is routed to J4−4
DAC output C (VOUTC) is routed to J4−6
Negative supply rail of U2 operational amplifier is supplied with VSS
Dual supply operation
Dual supply operation
Dual supply operation
Dual supply operation
DAC output D (VOUTD) is routed to J4−8
Use for digitally controlled current source application only.
Dual supply operation
Dual supply operation
Reset pin high
U2 operational-amplifier configuration jumper set to 2x gain
RSTSEL configuration jumper; RSTSEL = 1
Dual supply operation
Use for digitally controlled current source application only.
Use for digitally controlled current source application only.
IOVDD = 5 V
Use for digitally controlled current source application only.
Dual supply operation (VSS = −5 V)
GPIO0 drives LDAC signal
CS signal routed to drive CS_ line of U1
Use for digitally controlled current source application only.
Use for digitally controlled current source application only.
DAC output A (VOUTA) is routed through LPF onto J5−2 connector
Selected DAC output connected to output operational amplifier, U2
Host Processor Interface
Figure 3−1. DAC7654 EVM Default Jumper Setting
3.2 Host Processor Interface
The host processor drives the DAC; therefore, the DAC proper operation depends on the successful configuration between the host processor and the
EVM board. In addition, a properly written code is required to operate the DAC.
A custom cable can be made specific to the host interface platform. The EVM
allows interface to the host processor through J2 header connector for the serial control signals and the serial data input. The output can be monitored
through the J4 header connector.
An interface adapter card is also available for a specific TI DSP starter kit as
well as an MSP430 based microprocessor as mentioned in Chapter 1 of this
manual. Using the interface card alleviates the tedious task of building customize cables and allows easy configuration of a simple evaluation system.
This DAC EVM interfaces with any host processor capable of handling serial
communication protocols or the popular TMS320 DSP family. For more information regarding the serial interface of the particular DAC installed, see the
specific DAC data sheet, as listed in the Related Documentation from Texas
Instruments section of this user’s guide.
EVM Operation
3-3
EVM Stacking
3.3 EVM Stacking
Stacking the EVM is possible if there is a need to evaluate two DAC7654 to
yield a total of eight channel outputs. A maximum of two DAC7654 EVMs are
allowed because the output terminal, J4, dictates the number of DAC channels
that can be connected without the outputs colliding. Table 3−2 shows how the
DAC output channels are mapped into the output terminal, J4, with respect to
the jumper positions of W2, W3, W4, and W10.
Table 3−2. DAC7654 Output Channel Mapping
Reference
W2
Jumper Position
Function
1−2
DAC7654 output A (VOUTA) is routed to J4−2.
W3
W4
W10
2−3
DAC7654 output A (VOUTA) is routed to J4−10.
1−2
DAC7654 output B (VOUTB) is routed to J4−4.
2−3
DAC7654 output B (VOUTB) is routed to J4−12.
1−2
DAC7654 output C (VOUTC) is routed to J4−6.
2−3
DAC7654 output C (VOUTC) is routed to J4−14.
1−2
DAC7654 output D (VOUTD) is routed to J4−8.
2−3
DAC7654 output D (VOUTD) is routed to J4−16.
3.4 The Output Operational Amplifier
The EVM includes an optional signal-conditioning circuit for the DAC output
through an external operational amplifier, U2. Only one DAC output channel
can be monitored at any given time for evaluation because the odd-numbered
pins (J4−1 to J4−7) are tied together. The output operational amplifier is set to
unity gain configuration by default. Nevertheless, the raw outputs of the DAC
can be probed through the even pins of J4, the output terminal, which also
provides mechanical stability when stacking or plugging into any interface
card. In addition, it provides easy access for monitoring up to eight DAC
channels when stacking two DAC7654 EVMs together (see Section 3.3).
The inverting input of U2 can be tied to AGND (via W15) or the DAC output (by
shorting pins 1 and 2 of the J5 header) or to any voltage source through J5−1.
The following sections describe the different configurations of the output
amplifier, U2.
3.4.1
Unity Gain Output
The buffered output configuration is used to prevent loading the DAC, though it
may present some slight distortion because of the feedback resistor and
capacitor. The user can tailor the feedback circuit to closely match the desired
wave shape by removing R6 and C12 and replacing them with the desired
values. If desired, the user can remove R6 and C12 and solder a 0-Ω resistor in
replacement of R6.
Table 3−3 shows the jumper setting for the unity gain configuration of the
DAC external output buffer in unipolar or bipolar supply mode.
3-4
Digitally Programmable Current Source Application
Table 3−3. Unity Gain Output Jumper Settings
Reference
3.4.2
Jumper Setting
Function
Unipolar
Bipolar
W15
OPEN
OPEN
Disconnect the inverting input of operational amplifier,
U2, from AGND.
W5
2−3
1−2
Negative rail of operational amplifier is tied to AGND or
powered by VSS.
Output Gain of Two (Default Configuration)
Table 3−4 below shows the proper jumper settings of the EVM for the
2x gain output of the DAC.
Table 3−4. Gain of Two Output Jumper Settings
Reference
Jumper Setting
Unipolar
Bipolar
W15
CLOSED
CLOSED
W5
2−3
1−2
Function
Inverting input of the output operational amplifier, U2,
is connected to AGND to set for a gain of 2.
Supplies power, VSS, to the negative rail of operational
amplifier, U2, for bipolar supply mode, or ties it to
AGND for unipolar supply mode.
3.5 Digitally Programmable Current Source Application
A digitally programmable current-source circuit is added for the convenience
of the users. Any DAC channels of the DAC7654 can be selected to generate
the voltage output that can be connected to the external operational amplifier,
U2. The external operational amplifier is used to perform this operation
because of the closed-loop configuration, internal to the device, of each
DAC7654 output amplifier. Therefore, the external operational amplifier, U2,
is used to drive the transistor for this type of operation. The selected transistor
(Q1 or Q2) is placed within the loop (i.e., U2 must be configured for open-loop
gain) to implement a digitally programmable, unidirectional current source, as
shown in Figure 3−2.
To operate the DAC7654 for the digitally programmable current source
application, the DAC7654 must be configured for the unipolar mode of
operation. The DAC7654 channels A and D are the only ones shown in the
table, but any DAC channel works.
The resistor R6 and the capacitor C12 should be disconnected from the circuit
of U2 for open-loop configuration. The resistor R4 can be replaced with a 0-Ω
resistor or a jumper wire. An extra wire is needed to connect TP5 to W22−2
or W24−2, as well as the J5−1 to W11−2 or W21−2.
See Table 3−5 for the setup configuration.
EVM Operation
3-5
Digitally Programmable Current Source Application
Table 3−5. Digitally Programmable Current Source Configuration
Reference
W25
W1
W20
W6
W9
W2
W10
J4
J5
TP9
TP10
Jumper Setting
VOUTA
VOUTD
1−2
1−2
1−2
N/A
N/A
1−2
CLOSED N/A
N/A
CLOSED
1−2
N/A
N/A
1−2
1−2
7−8
2−3
2−3
CLOSED CLOSED
CLOSED CLOSED
Function
VSS is tied to AGND
VOUTS1A is feedback to VOUTA
VOUTS1D is feedback to VOUTD
DAC A is configured for unipolar mode of operation
DAC D is configured for unipolar mode of operation
DAC A is connected to J4−2
DAC A is connected to J4−8
DAC A or DAC D is connected to J5−2
DAC A or DAC D is routed to the positive input of U2
Transistor, Q1, loop is closed
Transistor, Q2, loop is closed
Figure 3−2. Digitally Programmable Current Source
+5 V
+5 V
+
A
6.5-A Digital Current Meter
−
TP 1
OFSR 2 OFSR 1
+
−
3-6
DAC Module
VOUTS2
VOUTS1 DGND
Q1
125
Ohms
VOU T
IOVDD VCC/VSS
AGND
Jumper Settings
3.6 Jumper Settings
Table 3−6 shows the function of each specific jumper setting of the EVM.
Table 3−6. Jumper Setting Function
Reference
Jumper
Setting
Function
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
Negative supply rail of the output operational amplifier, U2, is
powered by VSS for bipolar operation.
1
3
Negative supply rail of the output operational amplifier, U2, is tied
to AGND for unipolar operation.
VOUTSENSE1A is a feedback to VOUTA.
W1
VOUTSENSE2A is a feedback to VOUTA.
Routes VOUTA to J4−2.
W2
Routes VOUTA to J4−10.
Routes VOUTB to J4−4.
W3
Routes VOUTB to J4−12.
Routes VOUTC to J4−6.
W4
W5
Routes VOUTC to J4−14.
OFSR1A and OFSR2A are disconnected for bipolar output mode
W6
OFSR1A and OFSR2A are connected for unipolar output mode
OFSR1B and OFSR2B are disconnected for bipolar output mode
W7
OFSR1B and OFSR2B are connected for unipolar output mode
OFSR1C and OFSR2C are disconnected for bipolar output mode
W8
OFSR1C and OFSR2C are connected for unipolar output mode
OFSR1D and OFSR2D are disconnected for bipolar output mode
W9
OFSR1D and OFSR2D are connected for unipolar output mode
1
3
1
3
Routes VOUTD to J4−8.
W10
Routes VOUTD to J4−16.
EVM Operation
3-7
Jumper Settings
W11
1
3
1
3
1
3
1
3
1
3
1
3
1
3
VOUTSENSE1A is used for 4−20 mA drive
Digitally programmable current source application is not used
VOUTSENSE2A is used for digitally programmable current source
VOUTSENSE1B is a feedback to VOUTB
W12
VOUTSENSE2B is a feedback to VOUTB
VOUTSENSE1C is a feedback to VOUTC
W13
VOUTSENSE2C is a feedback to VOUTC
RST is pulled up via R5 resistor
W14
RST is pulled down to DGND and device is held on reset state
Configures output operational amplifier, U2, to unity gain output.
W15
Connects AGND to the inverting input of the output operational
amplifier, U2
RSTSEL is pulled up via R13 resistor and device resets to
mid-scale on power up
W16
RSTSEL is pulled down to DGND and device resets to
minimum-scale on power up
1
3
1
3
1
3
1
3
1
3
VOUTSENSE1D is a feedback to VOUTD
W20
W21
VOUTSENSE2D is a feedback to VOUTD
VOUTSENSE1D is used for digitally programmable current source
operation
Digitally programmable current source application is not used
VOUTSENSE2D is used for digitally programmable current source
VOUTA is not connected for digitally programmable current source
operation
W22
VOUTA is connected for digitally programmable current source
operation
1
3
1
3
3.3-V analog supply is selected for IOVDD of the DUT
W23
3-8
5-V analog supply is selected for IOVDD of the DUT
Schematics
VOUTD is not connected for digitally programmable current
source operation
W24
VOUTD is connected for digitally programmable current
source operation
1
3
VSS of the DUT is connected to AGND for unipolar mode of
operation
1
3
VSS of the DUT is connected to −5-V supply for bipolar mode of
operation
1
3
1
3
1
3
1
3
W25
GPIO4 is used to drive the LDAC signal of the DUT
W26
GPIO0 is used to drive the LDAC signal of the DUT
CS is used to drive the CS signal of the DUT
W27
Disconnects external load for digitally programmable current
source operation
TP9
Connects external load for digitally programmable current source
operation
TP10
Legend:
FSX is used to drive the CS signal of the DUT
Disconnects external load for digitally programmable current
source operation
Connects external load for digitally programmable current source
operation
Indicates the corresponding pins that are shorted or closed.
3.7 Schematics
Figure 3−3. DAC7654 Schematic
The EVM schematic is on the following page.
EVM Operation
3-9
1
2
3
4
5
6
Revision History
REV
P2
J4
+5VA
VoutB
W3
+3.3VD
C11
VoutC
W4
C7
0.1µF
C5
10µF
VoutD
W1
TP1
W12
Q1
NPN TRANSISTOR
W13
TP9
W11
VoutS1B
VoutB
VoutS2B
W7
VoutS1A
VoutS1C
VoutC
VoutS2C
W8
R1
125
VoutS2A
VoutS1A
VoutA
VoutS2A
W6
W22
W20
-5VA
+
C4
10µF
+
VoutS1D
VoutD
VoutS2D
W9
C1
0.1µF
W25
TP2
4
1
2
9
6
5
7
64
63
10
59
58
60
61
62
11
54
55
53
52
51
12
45
46
44
49
50
13
3
56
57
8
C6
10µF
VCC
NC
NC
NC
VoutS1A
VoutA
VoutS2A
OFSR1A
OFSR2A
NC
VoutS1B
VoutB
VoutS2B
OFSR1B
OFSR2B
NC
VoutS1C
VoutC
VoutS2C
OFSR1C
OFSR2C
NC
VoutS1D
VoutD
VoutS2D
OFSR1D
OFSR2D
NC
VSS
GNDR
GNDR
AGND
IOVDD
VDD
VDD
RST
RSTSEL
NC
NC
NC
NC
CS
SCLK
SDI
NC
LDAC
LOAD
NC
NC
NC
NC
NC
NC
SDO
NC
NC
NC
NC
NC
NC
NC
NC
DGND
DGND
19
18
29
26
27
14
48
47
43
21
22
23
42
25
24
41
40
39
38
37
36
20
35
34
33
32
31
30
16
15
28
17
C2
0.1µF
C8
0.1µF
R5
10K
0
R13
10K
LOAD
J2
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
GPIO0
JP4
GPIO1
JP8
JP10
JP12
GPIO4
JP16
JP18
JP20
TP4
R7
0
R9
0
CS
SCLK
CLKR
FSX
FSR
SDO
DR
RST
RSTSEL
GPIO5
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
GPIO0
JP4
GPIO1
JP8
JP10
JP12
GPIO4
JP16
JP18
JP20
D
LOAD_
W14
RST
RSTSEL
W16
CS
CE
SCLK
SDI
LDAC
LOAD
W27
GPIO4
FSX
W26
GPIO0
C
SDO
VCC
C9
TP7
0.01µF
J5
3
4
3
2
1
U2
TP5
R4
6
100
Op Amp
2
4X1X.1
DAC7654
4
1
5
W24
VoutD
R3
0.1µF
W10
C
TP3
W23
U1
VoutA
VDD
CS
SCLK
CLKR
FSX
FSR
SDI
DR
RST
RSTSEL
GPIO5
7
D
2
4
6
8
10
12
14
16
18
20
IOVDD
1
3
5
7
9
11
13
15
17
19
Approved
VoutA
W2
DAC_VOUT
ECN Number
Q2
NPN TRANSISTOR
TP6
VoutS1D
DAC_VOUT
2K
TP10
W21
B
VSS
R8
W5
C10
C3
470pF
R2
125
VoutS2D
0.01µF
B
R6
10K
C12
1nF
J1
VDD
1
3
5
7
9
2
4
6
8
10
VSS
VCC
VDD
R12
10K
3
VD1
2
-5VA
1
VSS
J6
3
VCC
2
+5VA
J3
1
+3.3VD VD2
W15
+3.3VD
ti
A
A
12500 TI Boulevard. Dallas, Texas 75243
Title:
Engineer:
J. PARGUIAN
DAC7654
DOCUMENTCONTROL #
Drawn By:
FILE:
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DAC7654_RevA.Sch
DATE:
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