Texas Instruments | LMH6624-MIL Single Ultra-Low-Noise Wideband Operational Amplifier | Datasheet | Texas Instruments LMH6624-MIL Single Ultra-Low-Noise Wideband Operational Amplifier Datasheet

Texas Instruments LMH6624-MIL Single Ultra-Low-Noise Wideband Operational Amplifier Datasheet
Product
Folder
Order
Now
Technical
Documents
Support &
Community
Tools &
Software
LMH6624-MIL
SNOSD63 – JUNE 2017
LMH6624-MIL Single Ultra-Low-Noise Wideband Operational Amplifier
1 Features
3 Description
•
The LMH6624-MIL device offers wide bandwidth (1.5
GHz) with very-low-input noise (0.92 nV/√Hz, 2.3
pA/√Hz) and ultra-low DC errors (100-μV VOS, ±0.1μV/°C drift) providing very precise operational
amplifiers with wide dynamic range. This enables the
user to achieve closed-loop gains of greater than 10,
in both inverting and non-inverting configurations.
1
•
•
•
•
•
•
•
•
•
•
VS = ±6 V, TA = 25°C, AV = 20 (Typical Values
Unless Specified)
Gain Bandwidth 1.5 GHz
Input Voltage Noise 0.92 nV/√Hz
Input Offset Voltage (Limit Over Temp) 700 µV
Slew Rate 350 V/μs
Slew Rate (AV = 10) 400 V/μs
HD2 at f = 10 MHz, RL = 100 Ω –63 dBc
HD3 at f = 10 MHz, RL = 100 Ω –80 dBc
Supply Voltage Range 5 V to 12 V
Improved Replacement for the CLC425
Stable for Closed Loop |AV| ≥ 10
The LMH6624-MIL traditional voltage feedback
topology provides the following benefits: balanced
inputs, low-offset voltage and offset current, very-lowoffset drift, 81-dB open loop gain, 95-dB commonmode rejection ratio, and 88-dB power supply
rejection ratio.
The LMH6624-MIL device operates from 5 V to 12 V
and is offered in SOT-23-5 and SOIC-8 packages.
2 Applications
•
•
•
•
•
•
•
Instrumentation Sense Amplifiers
Ultrasound Preamplifiers
Magnetic Tape & Disk Preamplifers
Wide Band Active Filters
Professional Audio Systems
Opto-Electronics
Medical Diagnostic Systems
Device Information(1)
PART NUMBER
LMH6624-MIL
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Voltage Noise vs. Frequency
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ±2.5 V ..............................
Electrical Characteristics ±6 V .................................
Typical Characteristics ..............................................
7.3 Device Functional Modes........................................ 21
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Feature Description................................................. 16
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
June 2017
*
Initial release.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
5 Pin Configuration and Functions
Package DBV
5-Pin SOT-23
Top View
1
Package D
8-Pin SOIC
Top View
5
OUT
V
N/C
+
-IN
V
-
2
8
-
7
+
6
N/C
V
+
2
+IN
3
-
+
+IN
1
4
3
-IN
V
-
4
5
OUT
N/C
Pin Functions
PIN
NAME
LMH6624-MIL
I/O
DESCRIPTION
DBV
D
–IN
4
2
I
Inverting input
+IN
3
3
I
Non-inverting input
N/C
—
1, 5, 8
––
No connection
OUT
1
6
O
Output
V–
2
4
I
Negative supply
V+
5
7
I
Positive supply
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
3
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VIN differential
+
–
Supply voltage (V – V )
Voltage at input pins
Junction temperature
(2)
V
13.2
V
V
±10
mA
Infrared or convection (20 s)
235
°C
Wave soldering (10 s)
260
°C
150
°C
150
°C
(2)
Storage temperature
(1)
UNIT
±1.2
V+ +0.5,
V– –0.5
Input current
Soldering information
MAX
–65
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Machine model (2)
±200
UNIT
V
Human body model, 1.5 kΩ in series with 100 pF. JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a
standard ESD control process. Manufacturing with less than 2000-V HBM is possible with the necessary precautions. Pins listed as
±2000 V may actually have higher performance.
Machine model, 0 Ω in series with 200 pF. JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard
ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
Operating temperature
(2)
Operating supply voltage (V+ – V–)
(1)
(2)
MIN
MAX
UNIT
–40
+125
°C
±2.25
±6.3
V
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
6.4 Thermal Information
LMH6624-MIL
THERMAL METRIC
RθJA
(1)
(2)
4
(1)
Junction-to-ambient thermal resistance (2)
DBV
D
5 PINS
8 PINS
265
166
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA)/ RθJA . All numbers apply for packages soldered directly onto a PC board.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
6.5 Electrical Characteristics ±2.5 V
Unless otherwise specified, all limits ensured at TA = 25°C, V+ = 2.5 V, V– = –2.5 V, VCM = 0 V, AV = +20, RF = 500 Ω,
RL = 100 Ω. See (1).
PARAMETER
TEST CONDITIONS
MIN (2)
TYP (3)
MAX (2)
UNIT
DYNAMIC PERFORMANCE
fCL
–3-dB BW
VO = 400 mVPP
90
VO = 2 VPP, AV = +20
300
VO = 2 VPP, AV = +10
360
MHz
SR
Slew rate (4)
tr
Rise time
VO = 400 mV Step, 10% to 90%
4.1
ns
tf
Fall time
VO = 400 mV Step, 10% to 90%
4.1
ns
ts
Settling time 0.1%
VO = 2 VPP (Step)
20
ns
V/μs
DISTORTION and NOISE RESPONSE
0.92
en
Input referred voltage noise
f = 1 MHz
in
Input referred current noise
f = 1 MHz
2.3
pA/√Hz
nd
nV/√Hz
1.0
HD2
2
harmonic distortion
fC = 10 MHz, VO = 1 VPP, RL 100 Ω
–60
dBc
HD3
3rd harmonic distortion
fC = 10 MHz, VO = 1 VPP, RL 100 Ω
–76
dBc
INPUT CHARACTERISTICS
VOS
IOS
IB
Input offset voltage
VCM = 0 V
Average drift (5)
VCM = 0 V
Input offset current
VCM = 0 V
Average drift (5)
VCM = 0 V
–0.95
+0.75
+0.95
±0.25
–1.5
–40°C ≤ TJ ≤ 125°C
–0.05
–2.0
μV/°C
+1.5
+2.0
2
13
mV
μA
nA/°C
+20
VCM = 0 V
Average drift (5)
VCM = 0 V
12
nA/°C
Common Mode
6.6
MΩ
Differential Mode
4.6
kΩ
Common Mode
0.9
Differential Mode
2.0
Input resistance (6)
CIN
Input capacitance (6)
CMRR
Common-mode rejection
ratio
(2)
(3)
(4)
(5)
(6)
–40°C ≤ TJ ≤ 125°C
–0.25
Input bias current
RIN
(1)
–0.75
–40°C ≤ TJ ≤ 125°C
+25
Input referred, VCM = –0.5 V to +1.9 V
87
Input referred,
VCM = –0.5 V to +1.75 V
85
–40°C ≤ TJ ≤ 125°C
μA
pF
90
dB
Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute maximum ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
All limits are specified by testing or statistical analysis.
Typical Values represent the most likely parametric norm.
Slew rate is the slowest of the rising and falling slew rates.
Average drift is determined by dividing the change in parameter at temperature extremes into the total temperature change.
Simulation results.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
5
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
Electrical Characteristics ±2.5 V (continued)
Unless otherwise specified, all limits ensured at TA = 25°C, V+ = 2.5 V, V– = –2.5 V, VCM = 0 V, AV = +20, RF = 500 Ω,
RL = 100 Ω. See (1).
PARAMETER
TEST CONDITIONS
MIN (2)
TYP (3)
75
79
MAX (2)
UNIT
TRANSFER CHARACTERISTICS
AVOL
Large signal voltage gain
RL = 100 Ω, VO = –1 V to +1 V
–40°C ≤ TJ ≤ 125°C
dB
70
OUTPUT CHARACTERISTICS
±1.1
RL = 100 Ω
VO
–40°C ≤ TJ ≤ 125°C
Output swing
±1.4
No load
RO
Output impedance
–40°C ≤ TJ ≤ 125°C
ISC
Output short circuit current
Sinking to ground
ΔVIN = –200 mV (7) (8)
IOUT
Output current
V
±1.7
±1.25
f ≤ 100 KHz
Sourcing to ground
ΔVIN = 200 mV (7) (8)
±1.5
±1.0
10
90
–40°C ≤ TJ ≤ 125°C
75
90
–40°C ≤ TJ ≤ 125°C
mΩ
145
mA
145
75
Sourcing, VO = +0.8 V
Sinking, VO = –0.8 V
100
mA
POWER SUPPLY
PSRR
Power supply rejection ratio
IS
Supply current (per channel) No load
(7)
(8)
6
VS = ±2 V to ±3 V
82
–40°C ≤ TJ ≤ 125°C
90
11.4
–40°C ≤ TJ ≤ 125°C
dB
80
16
18
mA
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
Short circuit test is a momentary test. Output short circuit duration is 1.5 ms.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
6.6 Electrical Characteristics ±6 V
Unless otherwise specified, all limits ensured at TA = 25°C, V+ = 6 V, V– = –6 V, VCM = 0 V, AV = +20, RF = 500 Ω,
RL = 100 Ω. See (1).
PARAMETER
TEST CONDITIONS
MIN (2)
TYP (3)
MAX (2)
UNIT
DYNAMIC PERFORMANCE
fCL
–3-dB BW
VO = 400 mVPP
95
VO = 2 VPP, AV = +20
350
VO = 2 VPP, AV = +10
400
MHz
SR
Slew rate (4)
tr
Rise time
VO = 400 mV Step, 10% to 90%
3.7
ns
tf
Fall time
VO = 400 mV Step, 10% to 90%
3.7
ns
ts
Settling time 0.1%
VO = 2 VPP (Step)
18
ns
V/μs
DISTORTION and NOISE RESPONSE
en
Input referred voltage noise
f = 1 MHz
0.92
nV/√Hz
in
Input referred current noise
f = 1 MHz
2.3
pA/√Hz
HD2
2nd harmonic distortion
fC = 10 MHz, VO = 1 VPP, RL = 100 Ω
–63
dBc
fC = 10 MHz, VO = 1 VPP, RL = 100 Ω
–80
dBc
HD3
rd
3 harmonic distortion
INPUT CHARACTERISTICS
VOS
IOS
IB
Input offset voltage
VCM = 0 V
Average drift (5)
VCM = 0 V
Input offset current
VCM = 0 V
Average drift (5)
VCM = 0 V
+0.7
±0.2
–1.1
–40°C ≤ TJ ≤ 125°C
0.05
–2.5
μV/°C
1.1
2.5
0.7
13
mV
μA
nA/°C
+20
Average drift (5)
VCM = 0 V
12
nA/°C
Common Mode
6.6
MΩ
Differential Mode
4.6
kΩ
Common Mode
0.9
Differential Mode
2.0
Input capacitance (6)
CMRR
Common-mode rejection
ratio
(2)
(3)
(4)
(5)
(6)
+0.5
VCM = 0 V
CIN
(1)
±0.10
–0.7
Input bias current
Input resistance (6)
RIN
–0.5
–40°C ≤ TJ ≤ 125°C
–40°C ≤ TJ ≤ 125°C
+25
Input referred, VCM = –4.5 V to +5.25 V
90
Input referred,
VCM = –4.5 V to +5 V
87
–40°C ≤ TJ ≤ 125°C
μA
pF
95
dB
Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute maximum ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
All limits are specified by testing or statistical analysis.
Typical Values represent the most likely parametric norm.
Slew rate is the slowest of the rising and falling slew rates.
Average drift is determined by dividing the change in parameter at temperature extremes into the total temperature change.
Simulation results.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
7
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
Electrical Characteristics ±6 V (continued)
Unless otherwise specified, all limits ensured at TA = 25°C, V+ = 6 V, V– = –6 V, VCM = 0 V, AV = +20, RF = 500 Ω,
RL = 100 Ω. See (1).
PARAMETER
TEST CONDITIONS
MIN (2)
TYP (3)
77
81
MAX (2)
UNIT
TRANSFER CHARACTERISTICS
AVOL
Large signal voltage gain
RL = 100 Ω, VO = –3 V to +3 V
–40°C ≤ TJ ≤ 125°C
dB
72
OUTPUT CHARACTERISTICS
±4.4
RL = 100 Ω
VO
–40°C ≤ TJ ≤ 125°C
Output swing
±4.8
No load
RO
Output impedance
–40°C ≤ TJ ≤ 125°C
ISC
Output short circuit current
Sinking to ground
ΔVIN = –200 mV (7) (8)
IOUT
Output current
V
±5.2
±4.65
f ≤ 100 KHz
Sourcing to ground
ΔVIN = 200 mV (7) (8)
±4.9
±4.3
10
100
–40°C ≤ TJ ≤ 125°C
85
100
–40°C ≤ TJ ≤ 125°C
mΩ
156
mA
156
85
Sourcing, VO = +4.3 V
Sinking, VO = –4.3 V
100
mA
POWER SUPPLY
PSRR
Power supply rejection ratio
IS
Supply current (per channel) No load
(7)
(8)
8
VS = ±5.4 V to ±6.6 V
82
–40°C ≤ TJ ≤ 125°C
88
12
–40°C ≤ TJ ≤ 125°C
dB
80
16
18
mA
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
Short circuit test is a momentary test. Output short circuit duration is 1.5 ms.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
6.7 Typical Characteristics
Figure 1. Voltage Noise vs Frequency
5
4
4
3
3
AV = -10
Normalized Gain (dB)
Normalized Gain (dB)
Figure 2. Current Noise vs Frequency
5
2
AV = -20
1
0
-1
AV = -40
-2
AV = -60
-3
AV = -80
-4
AV = -10
2
1
AV = -20
0
-1
AV = -40
-2
AV = -60
-3
AV = -80
-4
AV = -100
-5
AV = -100
-5
1k
1M
100k
10k
10M
100M
1k
1G
10k
Frequency (Hz)
1M
10M
100M
1G
Frequency (Hz)
VS = ±2.5 V
VIN = 5 mVpp
RL = 100 Ω
VS = ±6V
VIN = 5 mVpp
RL = 100 Ω
Figure 3. Inverting Frequency Response
Figure 4. Inverting Frequency Response
5
5
4
4
3
3
2
AV = +10
1
0
AV = +200
-1
AV = +100
-2
AV = +40
-3
Normalized Gain (dB)
Normalized Gain (dB)
100k
2
AV = +10
1
0
AV = +200
-1
AV = +100
-2
AV = +40
-3
AV = +30
AV = +30
-4
-4
AV = +20
AV = +20
-5
-5
1k
10k
100k
1M
10M
100M
1G
1k
Frequency (Hz)
10k
100k
1M
10M
100M
1G
Frequency (Hz)
VS = ±2.5 V
RF = 500 Ω
VO = 2 Vpp
VS = ±6 V
RF = 500 Ω
VO = 2 Vpp
Figure 5. Non-Inverting Frequency Response
Figure 6. Non-Inverting Frequency Response
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
9
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
Typical Characteristics (continued)
70
Gain (dB)
60
0
-40°C
-45
25°C
PHASE
-90
125°C
-40°C
50
-135
125°C
GAIN
40
-180
25°C
30
-225
20
-270
10
-315
0
100k
1M
10M
100M
Phase (°)
80
-360
1G
Frequency (Hz)
VS = ±2.5 V
VS = ±6V
RL = 100 Ω
Figure 7. Open Loop Frequency Response
Over Temperature
Figure 8. Open Loop Frequency Response
Over Temperature
5
5
33 pF
4
3
10 pF
2
1
5 pF
0
33 pF
4
15 pF
Normalized Gain (dB)
Normalized Gain (dB)
3
0 pF
-1
-2
1
5 pF
0
0 pF
-1
-2
-3
-3
-4
-4
-5
-5
1M
10M
1G
100M
1M
Frequency (Hz)
VS = ±2.5V
AV = +10
RF = 250 Ω
RISO = 10 Ω
RL = 1 kΩ||CL
VS = ±6V
AV = +10
RF = 250 Ω
5
4
4
5 pF
1
0
-1
10 pF
-2
RISO = 10 Ω
RL = 1 kΩ||CL
3
Normalized Gain (dB)
Normalized Gain (dB)
0 pF
2
1G
100M
Figure 10. Frequency Response with Cap. Loading
5
3
10M
Frequency (Hz)
Figure 9. Frequency Response with Cap. Loading
15 pF
-3
0 pF
2
5 pF
1
0
-1
10 pF
-2
15 pF
-3
33 pF
-4
33 pF
-4
-5
-5
1M
10M
100M
1G
1M
Frequency (Hz)
VS = ±2.5 V
AV = +10
RF = 250 Ω
10M
100M
1G
Frequency (Hz)
RISO = 100 Ω
RL = 1 kΩ||CL
VS = ±6 V
AV = +10
RF = 250 Ω
Figure 11. Frequency Response with Cap. Loading
10
15 pF
10 pF
2
RISO = 10 Ω
RL = 1 kΩ||CL
Figure 12. Frequency Response with Cap. Loading
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
Typical Characteristics (continued)
5
5
4
4
3
VIN = 20 mV
1
0
-1
-2
VIN = 200 mV
Normalized Gain (dB)
Normalized Gain (dB)
3
2
-3
2
VIN = 20 mV
1
0
-1
-2
VIN = 200 mV
-3
-4
-4
-5
-5
100k
1M
10M
100M
100k
1G
1M
Frequency (Hz)
VS = ±-2.5 V
AV = +10
RF = 500 Ω
1G
Figure 14. Non-Inverting Frequency Response Varying VIN
5
5
4
4
3
1
0
VIN = 20 mV
-1
-2
VIN = 200 mV
Normalized Gain (dB)
3
2
-3
2
1
0
-2
VIN = 200 mV
-3
-4
-4
-5
1M
VIN = 20 mV
-1
-5
100k
10M
100M
100k
1G
1M
Frequency (Hz)
10M
100M
1G
Frequency (Hz)
VS = ±2.5 V
AV = +20
RF = 500 Ω
VS = ±6 V
AV = +20
RF = 500 Ω
Figure 15. Non-Inverting Frequency Response Varying VIN
Figure 16. Non-Inverting Frequency Response Varying VIN
180
160
-40°C
-40°C
140
160
120
140
125°C
125°C
100
ISOURCE (mA)
ISOURCE (mA)
100M
VS = ±6 V
AV = +10
RF = 500 Ω
Figure 13. Non-Inverting Frequency Response Varying VIN
Normalized Gain (dB)
10M
Frequency (Hz)
25°C
80
60
40
120
25°C
100
80
60
40
20
20
0
0
0
0.5
1
0
1.5
VOUT (V)
1
2
3
VOUT (V)
4
5
VS = ±6 V
VS = ±2.5 V
Figure 17. Sourcing Current vs VOUT
Figure 18. Sourcing Current vs VOUT
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
11
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
Typical Characteristics (continued)
160
50
-40°C
140
0
125°C
120
125°C
25°C
100
ISINK (mA)
VOS (PV)
-50
25°C
-100
-150
80
60
40
-200
20
-40°C
-250
0
-300
-20
4
5
6
7
8
9
10
11
0
12
0.5
1
1.5
VOUT (V)
VSUPPLY (V)
VS = ±2.5 V
Figure 20. Sinking Current vs VOUT
Figure 19. VOS vs VSUPPLY
180
0.2
-40°C
160
0.15
140
0.1
125°C
25°C
100
80
25°C
0.05
IOS (PA)
ISINK (mA)
120
125°C
0
60
-0.05
40
-0.1
20
0
-40°C
-0.15
0
1
2
3
4
5
5
4
6
7
VOUT (V)
8
9
10
11
12
VSUPPLY (V)
VS = ±6 V
Figure 21. Sinking Current vs VOUT
0
-20
-20
-40
-60
HD2
Distortion (dBc)
Distortion (dBc)
Figure 22. IOS vs VSUPPLY
0
VS = ±6 V, VO = 2 VPP
-80
HD3
-100
-40
VS = ±6 V,
-60
-80
VS = ±2.5 V,
VO = 1 VPP
-100
-120
VS = ±2.5 V, VO = 1 VPP
-140
100k
1M
10M
HD3
-120
100k
100M
Frequency (Hz)
1M
10M
100M
Frequency (Hz)
AV = +10
RL = 100 Ω
AV = +20
RL = 100 Ω
Figure 23. Distortion vs Frequency
12
HD2
VO = 2 VPP
Submit Documentation Feedback
Figure 24. Distortion vs Frequency
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
Typical Characteristics (continued)
0
-50
HD2
VS = ±6 V
-20
VO = 2 VPP
-60
HD2
VS = ±2.5 V,
-60
Distortion (dBc)
Distortion (dBc)
-40
VO = 1 VPP
-80
-70
-80
HD3
-100
VS = ±2.5 V
-90
HD3
VO = 1 VPP
-120
VS = ±6 V, VO = 2 VPP
-100
-140
100k
1M
10M
0
100M
20
40
Frequency (Hz)
60
80
AV = +20
RL = 500 Ω
VS = ±6 V
VO = 2 Vpp
Figure 25. Distortion vs Frequency
Figure 26. Distortion vs Gain
0
0
-20
-20
HD2
fC = 10 MHz
-40
HD2
-60
-80
fC = 10 MHz
-40
Distortion (dBc)
Distortion (dBc)
100
Gain (V/V)
-60
-80
fC = 1 MHz
-100
HD3
fC = 1 MHz
-100
HD3
-120
-120
0
0.5
1
1.5
2
2.5
3
3.5
4
0
VOUT (V)
4
6
8
10
12
VOUT (VPP)
AV = +20
AV = ±2.5V
RL = 100 Ω
AV = +20
VS = ±6 V
RL = 100 Ω
Figure 28. Distortion vs VOUT Peak to Peak
200 mV/DIV
200 mV/DIV
Figure 27. Distortion vs VOUT Peak to Peak
10 ns/DIV
VS = ±2.5 V
VO = 1 Vpp
AV = +10
2
10 ns/DIV
RL = 100 Ω
VS = ±6 V
VO = 1 Vpp
AV = +20
Figure 29. Non-Inverting Large Signal Pulse Response
RL = 100 Ω
Figure 30. Non-Inverting Large Signal Pulse Response
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
13
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
50 mV/DIV
100 mV/DIV
Typical Characteristics (continued)
10 ns/DIV
VS = ±2.5 V
VO = 200 mv
AV = +10
10 ns/DIV
RL = 100 Ω
VS = ±6 V
VO = 500 mv
AV = +20
Figure 31. Non-Inverting Small Signal Pulse Response
Figure 32. Non-Inverting Small Signal Pulse Response
0
0
+PSRR, AV +10
-10
-20
-20
+PSRR, AV +20
-50
-PSRR, AV +20
PSRR (dB)
-40
-60
+PSRR, AV = +10
-40
-30
PSRR (dB)
RL = 100 Ω
-70
-60 +PSRR, AV = +20
-80
-PSRR, AV = +10
-100
-80
-120
-90
-PSRR, AV = +20
-PSRR, AV +10
-100
1k
10k
100k
1M
10M
100M
-140
1k
1G
10k
Frequency (Hz)
100M
1G
VS = ±6 V
Figure 33. PSRR vs Frequency
Figure 34. PSRR vs Frequency
0
0
-10
-10
-20
-20
-30
-30
CMRR (dB)
CMRR (dB)
10M
Frequency (Hz)
VS = ±2.5 V
-40
AV = +10
-50
-60
-40
-50
AV = +10
-60
-70
-70
AV = +20
-80
AV = +20
-80
-90
-90
1k
10k
100k
1M
10M
100M
1k
Frequency (Hz)
10k
100k
1M
10M
100M
Frequency (Hz)
VS = ±2.5V
VIN = 5 mVpp
VS = ±6 V
VIN = 5 mVpp
Figure 35. Input Referred CMRR vs Frequency
14
1M
100k
Figure 36. Input Referred CMRR vs Frequency
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
Typical Characteristics (continued)
5
Normalized Gain (dB)
3
2
5
RF = 2 k:
RF = 1.5 k:
RF = 1.5 k:
3
RF = 1 k:
RF = 750 :
1
0
-1
RF = 2 k:
4
Normalized Gain (dB)
4
RF = 511 :
-2
RF = 1 k:
2
1
RF = 750 :
0
-1
RF = 511 :
-2
-3
-3
-4
-4
-5
10M
-5
100M
1G
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
VS = ±2.5 V
AV = +10
RL = 100 Ω
VS = ±6 V
AV = +10 V
RL = 100 Ω
Figure 37. Amplifier Peaking with Varying RF
Figure 38. Amplifier Peaking with Varying RF
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
15
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
7 Detailed Description
7.1 Overview
The LMH6624-MIL device is a very-wide-gain bandwidth, ultra-low-noise voltage feedback operational amplifier.
The excellent performance of the device enables applications such as medical diagnostic ultrasound, magnetic
tape and disk storage and fiber-optics to achieve maximum high-frequency signal-to-noise ratios. The set of
characteristic plots in Typical Characteristics illustrates many of the performance trade-offs. The following
discussion will demonstrate the proper selection of external components to achieve optimum system
performance.
7.2 Feature Description
7.2.1 Bias Current Cancellation
To cancel the bias current errors of the non-inverting configuration, the parallel combination of the gain setting
(Rg) and feedback (Rf) resistors should equal the equivalent source resistance (Rseq) as defined in Figure 39.
Combining this constraint with the non-inverting gain equation also seen in Figure 39, allows both Rf and Rg to
be determined explicitly from the following equations:
Rf = AVRseq
Rg = Rf/(AV–1)
(1)
(2)
When driven from a 0-Ω source, such as the output of an op amp, the non-inverting input of the LMH6624-MIL
should be isolated with at least a 25-Ω series resistor.
As seen in Figure 40, bias current cancellation is accomplished for the inverting configuration by placing a
resistor (Rb) on the non-inverting input equal in value to the resistance seen by the inverting input (Rf||(Rg+Rs)).
Rb should to be no less than 25 Ω for optimum LMH6624-MIL performance. A shunt capacitor can minimize the
additional noise of Rb.
Figure 39. Non-Inverting Amplifier Configuration
16
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
Feature Description (continued)
Figure 40. Inverting Amplifier Configuration
7.2.2 Total Input Noise vs Source Resistance
To determine maximum signal-to-noise ratios from the LMH6624-MIL, an understanding of the interaction
between the intrinsic noise sources and the noise arising from external resistors is necessary.
Figure 41 describes the noise model for the non-inverting amplifier configuration showing all noise sources. In
addition to the intrinsic input voltage noise (en) and current noise (in = in+ = in–) source, there is also thermal
voltage noise (et = √(4KTR)) associated with each of the external resistors. Equation 3 provides the general form
for total equivalent input voltage noise density (eni). Equation 4 is a simplification of Equation 3 that assumes
Rf||Rg = Rseq for bias current cancellation. Figure 42 illustrates the equivalent noise model using this assumption.
Figure 43 is a plot of eni against equivalent source resistance (Rseq) with all of the contributing voltage noise
sources of Equation 4. This plot gives the expected eni for a given (Rseq) which assumes Rf||Rg = Rseq for bias
current cancellation. The total equivalent output voltage noise (eno) is eni*AV.
Figure 41. Non-Inverting Amplifier Noise Model
(3)
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
17
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
Feature Description (continued)
Figure 42. Noise Model with Rf||Rg = Rseq
(4)
As seen in Figure 43, eni is dominated by the intrinsic voltage noise (en) of the amplifier for equivalent source
resistances below 26 Ω. Between 26 Ω and 3.1 kΩ, eni is dominated by the thermal noise (et = √(4kT(2Rseq)) of
the equivalent source resistance Rseq. Above 3.1 kΩ, eni is dominated by the amplifier’s current noise (in = √2
inRseq). When Rseq = 283 Ω (that is, Rseq = en/√2 in) the contribution from voltage noise and current noise of
LMH6624-MIL is equal. For example, configured with a gain of +20V/V giving a –3 dB of 90 MHz and driven from
Rseq = Rf || Rg = 25 Ω (eni = 1.3 nV√Hz from Figure 43), the LMH6624-MIL produces a total output noise voltage
(eni × 20 V/V × √(1.57 × 90 MHz)) of 309 μVrms.
VOLTAGE NOISE DENSITY (nV/ Hz)
100
et
10
eni
en
1
in
0.1
10
100
1k
10k
100k
RSEQ (:)
Figure 43. Voltage Noise Density vs Source Resistance
If bias current cancellation is not a requirement, then Rf || Rg need not equal Rseq. In this case, according to
Equation 3, Rf || Rg should be as low as possible to minimize noise. Results similar to Equation 3 are obtained
for the inverting configuration of Figure 40 if Rseq is replaced by Rb and Rg is replaced by Rg + Rs. With these
substitutions, Equation 3 will yield an eni referred to the non-inverting input. Referring eni to the inverting input is
easily accomplished by multiplying eni by the ratio of non-inverting to inverting gains.
18
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
Feature Description (continued)
7.2.3 Noise Figure
Noise Figure (NF) is a measure of the noise degradation caused by an amplifier.
(5)
The Noise Figure formula is shown in Equation 5. The addition of a terminating resistor RT, reduces the external
thermal noise but increases the resulting NF. The NF is increased because RT reduces the input signal amplitude
thus reducing the input SNR.
2
2
2 2
en + in (RSeq + (Rf||Rg) ) + 4KT (RSeq + (Rf||Rg))
NF = 10 LOG
4KT (RSeq + (Rf||Rg))
(6)
The noise figure is related to the equivalent source resistance (Rseq) and the parallel combination of Rf and Rg.
To minimize "Noise Figure":
• Minimize Rf || Rg
• Choose the Optimum RS (ROPT)
ROPT is the point at which the NF curve reaches a minimum and is approximated by:
ROPT »
en
in
(7)
7.2.4 Low-Noise Integrator
The LMH6624-MIL device implements a deBoo integrator shown in Figure 44. Positive feedback maintains
integration linearity. The low-input-offset voltage of the LMH6624-MIL device and matched input allow bias
current cancellation and provide for very precise integration. Keeping RG and RS low helps maintain dynamic
stability.
VO # VIN
KO
KO = 1 +
;
sRSC
RF
RG
RB
VO
RS
+
VIN
C
R
-
50:
50:
RF
RF = RB
RG
RG = RS||R
Figure 44. Low-Noise Integrator
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
19
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
Feature Description (continued)
7.2.5 High-Gain Sallen-Key Active Filters
The LMH6624-MIL device is well suited for high-gain Sallen-Key type of active filters. Figure 45 shows the 2nd
order Sallen-Key low-pass-filter topology. Using component predistortion methods discussed in Application Note
OA-21, Component Pre-Distortion for Sallen Key Filters (SNOA369) will enable the proper selection of
components for these high-frequency filters.
C1
R1
R2
+
C2
RF
RG
Figure 45. Sallen-Key Active Filter Topology
7.2.6 Low-Noise Magnetic Media Equalizer
The LMH6624-MIL device implements a high-performance, low-noise equalizer for such applications as magnetic
tape channels as shown in Figure 46. The circuit combines an integrator with a bandpass filter to produce the
low-noise equalization. The simulated frequency response is illustrated in Figure 47.
Figure 46. Low-Noise Magnetic Media Equalizer
20
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
Feature Description (continued)
Figure 47. Equalizer Frequency Response
7.3 Device Functional Modes
7.3.1 Single Supply Operation
The LMH6624-MIL device can be operated with single power supply as shown in Figure 48. Both the input and
output are capacitively coupled to set the DC operating point.
Figure 48. Single Supply Operation
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
21
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A transimpedance amplifier is used to convert the small output current of a photodiode to a voltage, while
maintaining a near constant voltage across the photodiode to minimize non-linearity. Extracting the small signal
requires high gain and a low-noise amplifier, and therefore, the LMH6624-MIL device is ideal for such an
application in order to maximize SNR. Furthermore, because of the large gain (RF value) needed, the device
used must be high speed so that even with high-noise gain (due to the interaction of the feedback resistor and
photodiode capacitance), bandwidth is not heavily impacted.
Figure 39 implements a high-speed, single supply, low-noise transimpedance amplifier commonly used with
photo-diodes. The transimpedance gain is set by RF.
8.2 Typical Application
CF
1.1 pF
5 VDC
D1
CD = 10 pF
RF
1.2 k Ω
ID
5 VDC
–
R2
2k
5 VDC
LMH6624
+
RL
500 Ω
C1
0.1 µF
R1
3k
VOUT = 3 VDC - 1200 × I D
Figure 49. Application Schematic
22
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
Typical Application (continued)
8.2.1 Design Requirements
Figure 50 shows the Noise Gain (NG) and transfer function (I-V Gain). As with most transimpedance amplifiers, it
is required to compensate for the additional phase lag (noise gain zero at fZ) created by the total input
capacitance: CD (diode capacitance) + CCM (CM input capacitance) + CDIFF (DIFF input capacitance) looking into
RF. This is accomplished by placing CF across RF to create enough phase lead (Noise Gain pole at fP) to
stabilize the loop.
OP AMP OPEN
LOOP GAIN
GAIN (dB)
I-V GAIN (:)
NOISE GAIN (NG)
1 + sRF (CIN + CF)
1 + sRFCF
1+
CIN
CF
0 dB
FREQUENCY
fz #
1
2SRFCIN
fP =
1
GBWP
2SRFCF
Figure 50. Transimpedance Amplifier Noise Gain and Transfer Function
8.2.2 Detailed Design Procedure
The optimum value of CF is given by Equation 8 resulting in the I-V –3dB bandwidth shown in Equation 9, or
around 124 MHz in this case, assuming GBWP = 1.5 GHz, CCM (CM input capacitance) = 0.9 pF, and CDIFF
(DIFF input capacitance) = 2 pF. This CF value is a “starting point” and CF needs to be tuned for the particular
application as it is often less than 1 pF and thus is easily affected by board parasitics.
Optimum CF Value:
CF =
CIN
2S(GBWP)RF
(8)
Resulting –3dB Bandwidth:
f - 3 dB #
GBWP
2 S R F C IN
(9)
Equation 10 provides the total input current noise density (ini) equation for the basic transimpedance
configuration and is plotted against feedback resistance (RF) showing all contributing noise sources in Figure 51.
The plot indicates the expected total equivalent input current noise density (ini) for a given feedback resistance
(RF). This is depicted in the schematic of Figure 52 where total equivalent current noise density (ini) is shown at
the input of a noiseless amplifier and noiseless feedback resistor (RF). The total equivalent output voltage noise
density (eno) is ini*RF. Noise Equation for Transimpedance Amplifier:
(10)
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
23
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
Typical Application (continued)
16
Current Noise Density (pA/ Hz)
14
ini
12
10
8
it
en/RF
6
in
4
2
0
100
1k
10k
Rf (:)
Figure 51. Current Noise Density vs Feedback Resistance
+5VDC
D1
RF
(Noiseless)
CD = 10 pF
ID
ini
Noiseless Op Amp
Figure 52. Transimpedance Amplifier Equivalent Input Source Mode
From Figure 53, it is clear that with the LMH6624-MIL extremely low-noise characteristics, for RF < 3 kΩ, the
noise performance is entirely dominated by RF thermal noise. Only above this RF threshold, the input noise
current (in) of LMH6624-MIL becomes a factor and at no RF setting does the LMH6624-MIL input noise voltage
play a significant role. This noise analysis has ignored the possible noise gain increase, due to photo-diode
capacitance, at higher frequencies.
8.2.3 Application Curve
CURRENT NOISE DENSITY (pA/ Hz)
16
14
ini
12
it
10
8
en/RF
6
4
2
in
0
100
1k
10k
FEEDBACK RESISTANCE, RF (:)
Figure 53. Current Noise Density vs Feedback Resistance
24
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
9 Power Supply Recommendations
The LMH6624-MIL device can operate off a single supply or with dual supplies as long as the input CM voltage
range (CMIR) has the required headroom to either supply rail. Supplies should be decoupled with lowinductance, often ceramic, capacitors to ground less than 0.5 in from the device pins. The use of ground plane is
recommended, and as in most high-speed devices, it is advisable to remove ground plane close to device
sensitive pins such as the inputs.
10 Layout
10.1 Layout Guidelines
TI suggests the copper patterns on the evaluation boards shown in Figure 54 and Figure 55 as a guide for highfrequency layout. These boards are also useful as an aid in device testing and characterization. As is the case
with all high-speed amplifiers, accepted-practice RF design technique on the PCB layout is mandatory.
Generally, a good high-frequency layout exhibits a separation of power supply and ground traces from the
inverting input and output pins as shown in Figure 54. Parasitic capacitances between these nodes and ground
may cause frequency response peaking and possible circuit oscillations. See Application Note OA-15, Frequent
Faux Pas in Applying Wideband Current Feedback Amplifiers (SNOA367) for more information. Use high-quality
chip capacitors with values in the range of 1000 pF to 0.1 µF for power supply bypassing as shown in Figure 54.
One terminal of each chip capacitor is connected to the ground plane and the other terminal is connected to a
point that is as close as possible to each supply pin as allowed by the manufacturer’s design rules. In addition,
connect a tantalum capacitor with a value between 4.7 μF and 10 μF in parallel with the chip capacitor. Signal
lines connecting the feedback and gain resistors should be as short as possible to minimize inductance and
microstrip line effect as shown in Figure 55. Place input and output termination resistors as close as possible to
the input/output pins. Traces greater than 1 inch in length should be impedance matched to the corresponding
load termination.
Symmetry between the positive and negative paths in the layout of differential circuitry should be maintained to
minimize the imbalance of amplitude and phase of the differential signal.
Component value selection is another important parameter in working with high-speed and high-performance
amplifiers. Choosing external resistors that are large in value compared to the value of other critical components
will affect the closed loop behavior of the stage because of the interaction of these resistors with parasitic
capacitances. These parasitic capacitors could either be inherent to the device or be a by-product of the board
layout and component placement. Moreover, a large resistor will also add more thermal noise to the signal path.
Either way, keeping the resistor values low will diminish this interaction. On the other hand, choosing very-lowvalue resistors could load down nodes and will contribute to higher overall power dissipation and high distortion.
DEVICE
PACKAGE
EVALUATION BOARD PART NUMBER
LMH6624MF
SOT-23-5
LMH730216
LMH6624MA
SOIC-8
LMH730227
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
25
LMH6624-MIL
SNOSD63 – JUNE 2017
www.ti.com
10.2 Layout Example
Figure 54. EVM Board Layout Example (Top)
Figure 55. EVM Board Layout Example (Bottom)
26
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
LMH6624-MIL
www.ti.com
SNOSD63 – JUNE 2017
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
• Absolute Maximum Ratings for Soldering (SNOA549)
• Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, Application Note OA-15 (SNOA367)
• Semiconductor and IC Package Thermal Metrics (SPRA953)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH6624-MIL
27
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
LMH6624 MDC
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DIESALE
Y
0
400
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising