Texas Instruments | LMH6644-MIL Low-Power, 130-MHz, 75-mA Rail-to-Rail Output Amplifier | Datasheet | Texas Instruments LMH6644-MIL Low-Power, 130-MHz, 75-mA Rail-to-Rail Output Amplifier Datasheet

Texas Instruments LMH6644-MIL Low-Power, 130-MHz, 75-mA Rail-to-Rail Output Amplifier Datasheet
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LMH6644-MIL
SNOSD65 – JUNE 2017
LMH6644-MIL Low-Power, 130-MHz, 75-mA Rail-to-Rail Output Amplifier
1 Features
(VS = ±5 V, TA = 25°C, RL = 2 kΩ, AV = +1.
Typical Values Unless Specified).
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(1)
–3 dB BW (AV = +1) 130 MHz
Supply Voltage Range 2.7 V to 12.8 V
Slew Rate, (AV = –1) 130 V/µs(1)
Supply Current (no load) 2.7 mA/amp
Output Short Circuit Current +115 mA to 145 mA
Linear Output Current ±75 mA
Input Common Mode Voltage 0.5 V Beyond V–, 1
V from V+
Output Voltage Swing 40 mV from Rails
Input Voltage Noise (100 kHz) 17 nV/√Hz
Input Current Noise (100 kHz) 0.9 pA/√Hz
THD (5 MHz, RL = 2 kΩ, VO = 2 VPP, AV = +2) –62
dBc
Settling Time 68 ns
Fully Characterized for 3 V, 5 V, and ±5 V
Overdrive Recovery 100 ns
Output Short Circuit Protected(2)
No Output Phase Reversal with CMVR Exceeded
Slew rate is the average of the rising and falling slew rates.
3 Description
The LMH6644-MIL true single supply voltage
feedback amplifier offers high speed (130 MHz), low
distortion (–62 dBc), and exceptionally high-output
current (approximately 75 mA) at low cost and with
reduced power consumption when compared against
existing devices with similar performance.
Input common mode voltage range extends to 0.5 V
below V– and 1 V from V+. Output voltage range
extends to within 40 mV of either supply rail, allowing
wide dynamic range especially desirable in lowvoltage applications. The output stage is capable of
approximately 75 mA in order to drive heavy loads.
Fast output slew rate (130 V/µs) ensures large peakto-peak output swings can be maintained even at
higher speeds, resulting in exceptional full power
bandwidth of 40 MHz with a 3-V supply. These
characteristics, along with low cost, are ideal features
for a multitude of industrial and commercial
applications.
Device Information(1)
PART NUMBER
LMH6644-MIL
PACKAGE
BODY SIZE (NOM)
SOIC (14)
8.64 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2)
Output short circuit duration is infinite for VS < 6 V at room
temperature and below. For VS > 6 V, allowable short circuit
duration is 1.5 ms.
Closed Loop Gain vs Frequency
for Various Supplies
8.0
2 Applications
6.0
•
•
•
•
•
4.0
±5
2.0
GAIN (dB)
Active Filters
CD/DVD ROM
ADC Buffer Amp
Portable Video
Current Sense Buffer
±1.5V
0.0
±2.5V
VO = 0.2VPP
AV = +2
RF = RL = 2k
100k
1M
10M
200M
FREQUENCY (Hz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6644-MIL
SNOSD65 – JUNE 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
8.2 Functional Block Diagram ....................................... 21
8.3 Feature Description................................................. 21
8.4 Device Functional Modes........................................ 21
1
1
1
2
3
4
5
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application .................................................. 22
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 25
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
3-V Electrical Characteristics .................................... 6
5-V Electrical Characteristics .................................... 8
±5-V Electrical Characteristics ................................ 10
Typical Performance Characteristics ...................... 12
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
Detailed Description ............................................ 21
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
8.1 Overview ................................................................. 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
June 2017
*
Initial release.
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5 Description (continued)
Careful attention has been paid to ensure device stability under all operating voltages and modes. The result is a
very well behaved frequency response characteristic (0.1-dB gain flatness up the 12 MHz under 150-Ω load and
AV = +2) with minimal peaking (typically 2-dB maximum) for any gain setting and under both heavy and light
loads. This along with fast settling time (68 ns) and low distortion allows the device to operate well in an ADC
buffer as well as high-frequency filter applications.
This device offers professional quality video performance with low differential gain (0.01%) and differential phase
(0.01°) characteristics. Differential gain and differential phase characteristics are also well maintained under
heavy loads (150 Ω) and throughout the output voltage range.
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6 Pin Configuration and Functions
Package D14A, PW14A
14-Pin SOIC and 14-Pin TSSOP
Top View
1
14
2
13
OUT D
OUT A
±IN A
A
± +
D
±IN D
+ ±
3
12
4
11
5
10
+IN D
+IN A
V±
V+
+IN C
+IN B
+ ±
±IN B
B
± +
6
9
±IN C
C
7
8
OUT C
OUT B
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
ChA inverting input
+IN A
3
I
ChA non-inverting input
–IN B
6
I
ChB inverting input
+IN B
5
I
ChB non-inverting input
–IN C
9
I
ChC inverting input
+IN C
10
I
ChC non-inverting input
–IN D
13
I
ChD inverting input
+IN D
12
I
ChD non-inverting input
OUT A
1
O
ChA output
OUT B
7
O
ChB output
OUT C
8
O
ChC output
OUT D
14
O
ChD output
V
11
I
Negative supply
V+
4
I
Positive supply
–
4
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7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
±2.5
V
VIN differential
Output short circuit duration
See
(3)
(4)
and
Supply voltage (V+ – V–)
13.5
V
V+ +0.8
V– –0.8
V
Input current
±10
mA
Junction temperature (5)
+150
°C
Infrared or convection reflow (20 s)
235
°C
Wave soldering lead temperature (10 s)
260
°C
+150
°C
Voltage at input/output pins
Soldering information
Storage temperature range, Tstg
(1)
(2)
(3)
(4)
(5)
–65
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
Output short circuit duration is infinite for VS < 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA)/ RθJA . All numbers apply for packages soldered directly onto a PC board.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
(3)
(4)
Electrostatic discharge
(1)
(2)
UNIT
2000
Machine model (MM) (3)
200
Charged-device model (CDM), per JEDEC specification JESD22-C101,
all pins (4)
1000
V
Human body model, 1.5 kΩ in series with 100 pF. Machine Model, 0 Ω in series with 200 pF.
JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 1000-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions (1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage (V+ – V–)
Operating temperature range
(1)
(2)
(2)
MIN
MAX
UNIT
2.7
12.8
V
–40
+85
°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.
7.4 Thermal Information
LMH6644-MIL
THERMAL METRIC (1)
RθJA
(1)
(2)
Junction-to-ambient thermal resistance (2)
D14A
PW14A
14 PINS
14 PINS
145
155
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.
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7.5 3-V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = 3 V, V– = 0 V, VCM = VO = V+/2, VID (input differential voltage) as noted
(where applicable) and RL = 2 kΩ to V+/2
PARAMETER
TEST CONDITIONS
MIN
BW
–3-dB BW
BW0.1dB
V+ = 3 V, V– = 0 V,
VCM = VO = V+/2, VID
RL = 2 kΩ to V+/2
AT
TEMPERATURE
EXTREMES
TYP
MAX
AV = +1, VOUT = 200mVPP
MIN
(1)
80
TYP
(2)
UNIT
MAX
(1)
115
MHz
AV = +2, –1, VOUT = 200mVPP
46
0.1-dB gain
flatness
AV = +2, RL = 150Ω to V+/2,
Rf = 402Ω, VOUT = 200mVPP
19
MHz
PBW
Full power
bandwidth
AV = +1, –1dB, VOUT = 1VPP
40
MHz
en
Input-referred
voltage noise
f = 100kHz
17
f = 1kHz
48
in
Input-referred
current noise
f = 100kHz
f = 1kHz
3.3
THD
Total harmonic
distortion
f = 5MHz, VO = 2VPP, AV = –1,
RL = 100Ω to V+/2
–48
DG
Differential gain
VCM = 1V, NTSC, AV = +2
RL =150Ω to V+/2
0.90
RL =1kΩ to V /2
Differential
phase
pA/√Hz
dBc
0.17%
+
DP
nV/√Hz
0.03%
VCM = 1V, NTSC, AV = +2
RL =150Ω to V+/2
0.05
RL =1kΩ to V+/2
0.03
deg
CT Rej.
Cross-talk
rejection
f = 5MHz, receiver:
Rf = Rg = 510Ω, AV = +2
47
dB
TS
Settling time
VO = 2VPP, ±0.1%, 8pF Load,
VS = 5V
68
ns
SR
Slew rate
120
V/µs
VOS
Input offset
voltage
TC VOS
Input offset
average drift
See
(4)
IB
Input bias
current
See
(5)
IOS
Input offset
current
RIN
Common-mode
input resistance
(1)
(2)
(3)
(4)
(5)
6
(3)
AV = –1, VI = 2VPP
90
±7
±1
±5
±5
mV
µV/°C
–3.25
–1.50
–2.60
µA
1000
20
800
nA
3
MΩ
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Slew rate is the average of the rising and falling slew rates.
Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change.
Positive current corresponds to current flowing into the device.
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3-V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+ = 3 V, V– = 0 V, VCM = VO = V+/2, VID (input differential voltage) as noted
(where applicable) and RL = 2 kΩ to V+/2
PARAMETER
TEST CONDITIONS
MIN
CIN
Common-mode
input
capacitance
CMVR
Input commonmode voltage
range
CMRR ≥ 50dB
CMRR
Common-mode
rejection ratio
VCM Stepped from 0V to 1.5V
AVOL
Large signal
voltage gain
MAX
MIN
TYP
(2)
UNIT
MAX
(1)
2
–0.1
1.6
–0.5
1.8
2.0
72
95
VO = 0.5V to 2.5V
RL = 2kΩ to V+/2
75
80
96
VO = 0.5V to 2.5V
RL = 150Ω to V+/2
70
74
82
pF
–0.2
V
dB
dB
RL = 2kΩ to V+/2, VID = 200mV
2.90
2.98
+
2.80
2.93
Output swing
low
RL = 2kΩ to V+/2, VID = –200mV
25
75
RL = 150Ω to V+/2, VID = –200mV
75
150
Output short
circuit current
RL = 150Ω to V /2, VID = 200mV
Sourcing to V+/2
VID = 200mV (6)
35
50
95
40
55
110
V
mV
mA
+
Sinking to V /2
VID = –200mV (6)
IOUT
Output current
VOUT = 0.5V from either supply
+PSRR
Positive power
supply rejection
ratio
V+ = 3.0V to 3.5V, VCM = 1.5V
IS
Supply current
(per channel)
No load
(6)
TYP
(1)
Output swing
high
VO
ISC
V+ = 3 V, V– = 0 V,
VCM = VO = V+/2, VID
RL = 2 kΩ to V+/2
AT
TEMPERATURE
EXTREMES
75
4.50
±65
mA
85
dB
2.70
4.00
mA
Short circuit test is a momentary test. See Note 7 under 5-V Electrical Characteristics.
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7.6 5-V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = 5 V, V– = 0 V, VCM = VO = V+/2, VID (input differential voltage) as noted
(where applicable) and RL = 2 kΩ to V+/2
PARAMETER
TEST CONDITIONS
AT TEMPERATURE
EXTREMES
MIN
BW
–3-dB BW
BW0.1dB
TYP
MAX
AV = +1, VOUT = 200mVPP
V+ = 5 V, V– = 0 V,
VCM = VO = V+/2, VID
RL = 2 kΩ to V+/2
MIN
(1)
90
TYP
(2)
UNIT
MAX
(1)
120
MHz
AV = +2, –1, VOUT = 200mVPP
46
0.1-dB gain
flatness
AV = +2, RL = 150Ω to V+/2,
Rf = 402Ω, VOUT = 200mVPP
15
MHz
PBW
Full power
bandwidth
AV = +1, –1dB, VOUT = 2VPP
22
MHz
en
Input-referred
voltage noise
f = 100kHz
17
f = 1kHz
48
in
Input-referred
current noise
f = 100kHz
THD
DG
0.90
f = 1kHz
3.3
Total harmonic
distortion
f = 5MHz, VO = 2VPP, AV = +2
–60
Differential gain
NTSC, AV = +2
RL =150Ω to V+/2
RL = 1kΩ to V /2
Differential
phase
pA/√Hz
dBc
0.16%
+
DP
nV/√Hz
0.05%
NTSC, AV = +2
RL = 150Ω to V+/2
0.05
RL = 1kΩ to V+/2
0.01
CT Rej.
Cross-talk
rejection
TS
Settling time
SR
Slew rate
VOS
Input offset
voltage
TC VOS
Input offset
average drift
See
(4)
IB
Input bias
current
See
(5)
IOS
Input offset
current
RIN
Common-mode
input resistance
3
MΩ
CIN
Common-mode
input
capacitance
2
pF
CMVR
Input commonmode voltage
range
CMRR ≥ 50dB
CMRR
Common-mode
rejection ratio
VCM Stepped from 0V to 3.5V
AVOL
Large signal
voltage gain
(1)
(2)
(3)
(4)
(5)
8
f = 5MHz, receiver:
Rf = Rg = 510Ω, AV = +2
deg
(3)
47
VO = 2VPP, ±0.1%, 8pF Load
AV = –1, VI = 2VPP
95
±7
dB
68
ns
125
V/µs
±1
±5
±5
µV/°C
–3.25
–1.70
–2.60
µA
1000
20
800
nA
–0.1
3.6
mV
–0.5
3.8
4.0
72
95
VO = 0.5V to 4.50V
RL = 2kΩ to V+/2
82
86
98
VO = 0.5V to 4.25V
RL = 150Ω to V+/2
72
76
82
–0.2
V
dB
dB
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Slew rate is the average of the rising and falling slew rates.
Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change.
Positive current corresponds to current flowing into the device.
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5-V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+ = 5 V, V– = 0 V, VCM = VO = V+/2, VID (input differential voltage) as noted
(where applicable) and RL = 2 kΩ to V+/2
PARAMETER
TEST CONDITIONS
AT TEMPERATURE
EXTREMES
MIN
MIN
TYP
(2)
Output swing
high
4.90
4.98
RL = 150Ω to V+/2, VID = 200mV
4.65
4.90
Output swing
low
RL = 2kΩ to V+/2, VID = –200mV
Output short
circuit current
RL = 150Ω to V+/2, VID = –200mV
150
115
Sinking to V+/2
VID = –200mV (6) (7)
55
70
140
+PSRR
Positive power
supply rejection
ratio
V+ = 4.0V to 6V
IS
Supply current
(per channel)
No load
V
100
55
VO = 0.5V from either supply
MAX
25
40
Output current
UNIT
(1)
100
Sourcing to V+/2
VID = 200mV (6) (7)
IOUT
(6)
(7)
MAX
(1)
RL = 2kΩ to V+/2, VID = 200mV
VO
ISC
TYP
V+ = 5 V, V– = 0 V,
VCM = VO = V+/2, VID
RL = 2 kΩ to V+/2
mV
mA
79
5.00
±70
mA
90
dB
2.70
4.25
mA
Short circuit test is a momentary test. See Note 7.
Output short circuit duration is infinite for VS < 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms.
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7.7 ±5-V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+ = 5 V, V– = –5 V, VCM = VO = 0 V, VID (input differential voltage) as noted
(where applicable) and RL = 2 kΩ to ground
PARAMETER
TEST CONDITIONS
MIN
BW
–3-dB BW
BW0.1dB
V+ = 5 V, V– = –5 V,
VCM = VO = 0 V, VID
AT TEMPERATURE
EXTREMES
TYP
MAX
AV = +1, VOUT = 200mVPP
MIN (1)
TYP (2)
95
130
UNIT
MAX (1)
MHz
AV = +2, –1, VOUT = 200mVPP
46
0.1-dB gain
flatness
AV = +2, RL = 150Ω to V+/2,
Rf = 806Ω, VOUT = 200mVPP
12
MHz
PBW
Full power
bandwidth
AV = +1, –1dB, VOUT = 2VPP
24
MHz
en
Input-referred
voltage noise
f = 100kHz
17
f = 1kHz
48
in
Input-referred
current noise
f = 100kHz
THD
DG
0.90
f = 1kHz
3.3
Total harmonic
distortion
f = 5MHz, VO = 2VPP, AV = +2
–62
Differential gain
NTSC, AV = +2
RL = 150Ω to V+/2
0.15%
RL = 1kΩ to V+/2
0.01%
Differential
phase
DP
nV/√Hz
NTSC, AV = +2
RL = 150Ω to V+/2
0.04
RL = 1kΩ to V+/2
0.01
pA/√Hz
dBc
deg
CT Rej.
Cross-talk
rejection
f = 5MHz, receiver:
Rf = Rg = 510Ω, AV = +2
47
dB
TS
Settling time
VO = 2VPP, ±0.1%, 8pF Load,
VS = 5V
68
ns
135
V/µs
(3)
SR
Slew rate
VOS
Input offset
voltage
TC VOS
Input offset
average drift
See
(4)
IB
Input bias
current
See
(5)
IOS
Input offset
current
RIN
Common-mode
input resistance
3
MΩ
CIN
Common-mode
input
capacitance
2
pF
CMVR
Input commonmode voltage
range
CMRR ≥ 50dB
CMRR
Common-mode
rejection ratio
VCM Stepped from –5V to 3.5V
(1)
(2)
(3)
(4)
(5)
10
AV = –1, VI = 2VPP
100
±7
±1
±5
±5
µV/°C
–3.25
–1.60
–2.60
µA
1000
20
800
nA
–5.1
3.6
mV
–5.5
3.8
4.0
74
95
–5.2
V
dB
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Slew rate is the average of the rising and falling slew rates.
Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change.
Positive current corresponds to current flowing into the device.
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±5-V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+ = 5 V, V– = –5 V, VCM = VO = 0 V, VID (input differential voltage) as noted
(where applicable) and RL = 2 kΩ to ground
PARAMETER
TEST CONDITIONS
AT TEMPERATURE
EXTREMES
MIN
AVOL
Large signal
voltage gain
TYP (2)
VO = –4.5V to 4.5V,
RL = 2kΩ
84
88
96
VO = –4.0V to 4.0V,
RL = 150Ω
74
78
82
UNIT
MAX (1)
dB
4.90
4.96
RL = 150Ω, VID = 200mV
4.65
4.80
Output swing
low
RL = 2kΩ, VID = –200mV
–4.96
–4.90
RL = 150Ω, VID = –200mV
–4.80
–4.65
Output current
Sourcing to ground
VID = 200mV (6) (7)
35
60
115
Sinking to ground
VID = –200mV (6) (7)
65
85
145
+
V
V
mA
VO = 0.5V from either supply
±75
mA
–
PSRR
Power supply
rejection ratio
(V , V ) = (4.5V, –4.5V) to (5.5V,
–5.5V)
IS
Supply current
(per channel)
No load
(6)
(7)
MIN (1)
RL = 2kΩ, VID = 200mV
Output short
circuit current
IOUT
MAX
Output swing
high
VO
ISC
TYP
V+ = 5 V, V– = –5 V,
VCM = VO = 0 V, VID
78
5.50
90
2.70
dB
4.50
mA
Short circuit test is a momentary test. See (7).
Output short circuit duration is infinite for VS < 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms.
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7.8 Typical Performance Characteristics
V+ = +5 V, V– = –5 V, RF = RL = 2 kΩ, unless specified otherwise.
+3
VS = ±1.5V
VS = ±5V
+2
0
GAIN (dB)
-1
VS = ±5V
-2
-3
VS = ±1.5V
VS = ±2.5V
VS = ±5V
AV = +1
RL = 2k
RL = 2k
+1
NORMALIZED GAIN (dB)
VS = ±2.5V
VOUT = 0.2VPP
0
-1
AV = +10
-2
-3
AV = +5
AV = +2
AV = +1
VOUT = 0.2VPP
100k
1M
10M
200M
10k
100k
1M
FREQUENCY (Hz)
Figure 1. Closed Loop Frequency Response
for Various Supplies
+3
0
-40°C
-2
VOUT = 0.2VPP
25°C
-4
0
-1
-2
-6
GAIN (dB)
NORMALIZED GAIN (dB)
AV = +1
AV = +10
-3
VS = ±1.5V
AV = +5
RL = 2k
AV = +1
AV = +2
10k
100k
1M
VO = 0.2VPP
10M
100M 500M
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 4. Closed Loop Frequency Response
for Various Temperature
±1.5V
7.0
85°C
0
±2.5V
6.5
-2
25°C
6.0
-4
±5V
5.5
GAIN (dB)
GAIN (dB)
100M 500M
FREQUENCY (Hz)
Figure 3. Closed Loop Gain vs Frequency
for Various Gain
5.0
AV = +2
VS = ±5V
RF = 2k
AV = +1
VO = 0.2VPP
100k
-40°C
RL = 2k
RL = 150
1M
VOUT = 0.2VPP
10M
200M
10k
FREQUENCY (Hz)
100k
1M
10M
100M 500M
FREQUENCY (Hz)
Figure 5. Closed Loop Gain vs Frequency
for Various Supplies
12
500
M
Figure 2. Closed Loop Gain vs Frequency
for Various Gain
RL = 2k
+1
100M
85°C
VS = ±1.5V
+2
10M
FREQUENCY (Hz)
Figure 6. Closed Loop Frequency Response
for Various Temperature
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Typical Performance Characteristics (continued)
V+ = +5 V, V– = –5 V, RF = RL = 2 kΩ, unless specified otherwise.
8.0
8.0
±2.5V
6.0
4.0
4VPP
2.0
±5
2.0
0.0
0.0
GAIN (dB)
GAIN (dB)
2VPP
±5V
4.0
±1.5V
6.0
±2.5V
AV = +2
VO = 0.2VPP
RF = RL = 2k
AV = +2
RF = RL = 2k
100k
1M
10M
200M
1M
100k
FREQUENCY (Hz)
10M
200M
FREQUENCY (Hz)
Figure 7. Large Signal Frequency Response
Figure 8. Closed Loop Small Signal Frequency Response
for Various Supplies
±5V
6
±1.5V
4
±1.5V
+0.3
2
+0.2
GAIN (dB)
GAIN (dB)
±2.5V
0
0
RF = 806:
-65
AV = +2
-110
±2.5V
RL = 150:
10M
200M
100K
FREQUENCY (Hz)
-20
VO = 0.4VPP
RF = 806:
150:
1M
±5V
PHASE
AV = +2
100K
+25
-0.1
VO = 0.4VPP
RL
±5V
GAIN
+0.1
PHASE (deg)
±2.5V
-155
±1.5V
1M
10M
200M
FREQUENCY (Hz)
Figure 9. Closed Loop Frequency Response
for Various Supplies
Figure 10. ±0.1dB Gain Flatness
for Various Supplies
5
3
RL = 2k
4
RL = 100:
VOUT (VPP)
VOUT (VPP)
2
3
2
1
VS = 5V
1
VS = 3V
AV = -1
0
100k
1M
10M
100M
FREQUENCY (Hz)
AV = -1
Rf = 2k
RL = 2K to VS/2
0
100K
1M
10M
100M
FREQUENCY (Hz)
Figure 11. VOUT (VPP) for THD < 0.5%
Figure 12. VOUT (VPP) for THD < 0.5%
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Typical Performance Characteristics (continued)
V+ = +5 V, V– = –5 V, RF = RL = 2 kΩ, unless specified otherwise.
80
10
85°C
9
RL =
2K
8
60
GAIN (dB)
VOUT (VPP)
6
5
4
PHASE (Deg)
PHASE
7
40
60
GAIN
20
40
-40°C
20
3
RL = 100:
2
0
VS = ±5V
1
AV = -1
0
100k
1M
10M
100M
0
VS = ±1.5V
RL= 2k
-20
10k
100k
25°C
1M
10M
150M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. Open Loop Gain/Phase
for Various Temperature
Figure 13. VOUT (VPP) for THD < 0.5%
80
-80
85°C
-75
GAIN
60
-70
40
60
20
40
25°C
-65
HD2 (dBc)
PHASE (Deg)
GAIN (dB)
PHASE
-55
-50
20
0
-45
0
VS = ±5V
RL = 2k
-20
10k
100k
10MHz
VS = 5V
-40
-40°C
1M
5MHz
-60
AV = -1
-35 R = 2k to V /2
L
S
10M
-30
150M
0
FREQUENCY (Hz)
1
2
3
4
5
VOUT (VPP)
Figure 16. HD2 (dBc) vs Output Swing
Figure 15. Open Loop Gain/Phase
for Various Temperature
-90
-80
100:,1MHz
-75
-80
-70
-70
-65
100: 5MHz
2k:, 5MHz
HD2 (dBc)
HD3 (dBc)
5MHz
-60
-55
-50
-45
-50
2k:, 10MHz
-40
VS = 5V
-40
10MHz
AV = -1
-35
RL = 2k to VS/2
-30
0
1
2
3
4
5
100:, 10MHz
-30 VS = 5V, AV = +2
RL = 2k: & 100: to VS/2
-20
0.0
1.0
2.0
3.0
4.0
5.0
VOUT (VPP)
VOUT (VPP)
Figure 17. HD3 (dBc) vs Output Swing
14
-60
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Figure 18. HD2 vs Output Swing
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Typical Performance Characteristics (continued)
V+ = +5 V, V– = –5 V, RF = RL = 2 kΩ, unless specified otherwise.
-90
-80
100:,1MHz
VS = 5V
-70
-70
AV = -1
-65
THD (dBc)
HD3 (dBc)
RL = 2k TO VS/2
-75
-80
2k:,5MHz
-60
2k:,10MHz
-50
-60
5MHz
-55
-50
-45
100:,
5MHz
-40
-40
-30 VS = 5V, AV = +2
RL = 2k: &100: to VS/2 100:, 10MHz
-20
0.0
1.0
2.0
3.0
4.0
5.0
10MHz
-35
-30
0
1
2
VOUT (VPP)
3
4
5
VOUT (VPP)
Figure 19. HD3 vs Output Swing
Figure 20. THD (dBc) vs Output Swing
1k
80
100
60
40
30
10
VOLTAGE
CURRENT
1
10
VS = 5V
20 AV = -1
Rf = RL = 2k
CL = 8pF
0
1
1.5
0.5
INPUT STEP AMPLITUDE (VPP)
1
10
2
100
0.1
1M
10
10
VS=±1.5V
VOUT FROM V (V)
VS = ±1.5V
1
1
-
+
1K
10K
100K
FREQUENCY (Hz)
Figure 22. Input Noise vs Frequency
Figure 21. Settling Time vs Input Step Amplitude
(Output Slew and Settle Time)
VOUT FROM V (V)
in (pA/ Hz)
10
100
50
en (nV/ Hz)
±0.1% SETTLING TIME
70
85°C
0.1
85°C
0.1
-40°C
-40°C
25°C
25°C
0.01
0.01
1
10
100
1k
1
10
100
1K
ISOURCE (mA)
ISINK (mA)
Figure 23. VOUT from V+ vs ISOURCE
Figure 24. VOUT from V– vs ISINK
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Typical Performance Characteristics (continued)
V+ = +5 V, V– = –5 V, RF = RL = 2 kΩ, unless specified otherwise.
10
10
VS = ±5V
VS = ±5V
85°C
-40°C
VOUT FROM V (V)
1
-
+
VOUT FROM V (V)
25°C
1
85°
C
0.1
-40°C
85°C
0.1
-40°C
25°C
0.01
0.01
1
10
100
1
1k
100
1k
ISINK (mA)
Figure 25. VOUT from V+ vs ISOURCE
Figure 26. VOUT from V– vs ISINK
180
160
RL = 150:
85°C, Sink
85°C, Sourcing
-40°C, Sink
160
140
25°C, Sink
25°C, Sourcing
140
120
120
-40°C, Sourcing
ISC (mA)
VOUT FROM SUPPLY (mV)
10
ISOURCE (mA)
100
80
100
25°C, Source
80
60
60
85°C, Sinking
40
-40°C, Source
25°C, Sinking
40
85°C, Source
20
-40°C, Sinking
0
20
2
3
4
5
6
7
VS (V)
8
9
2
10
4
5
6
Figure 27. Swing vs VS
8
9
10
Figure 28. Short Circuit Current (to VS/2) vs VS
1
VS = ±2.5
0.9
VS = ±2.5V
0.9
0.8
0.8
VOUT FROM V (V)
85°C
+
0.7
0.6
0.5
25°C
0.4
0.3
0.2
25°C
0.7
0.6
85°C
0.5
0.4
0.3
0.2
-40°C
0.1
0.1
0
0
0
20
40
60
80
100
120
-40°C
0
ISINK(mA)
20
40
60
80
100
120
ISOURCING (mA)
Figure 29. Output Sinking Saturation Voltage vs IOUT
16
7
VS (V)
1
VOUT FROM V- (V)
3
Figure 30. Output Sourcing Saturation Voltage vs IOUT
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Typical Performance Characteristics (continued)
V+ = +5 V, V– = –5 V, RF = RL = 2 kΩ, unless specified otherwise.
1000
90
AV = +1
VS = 5V
80
100
AV = +10
70
+ PSRR
PSRR (dB)
ZOUT (:)
60
10
1
50
40
- PSRR
30
20
0.1
10
0.01
1k
0
10k
100k
1M
10M
100M
10k
100k
FREQUENCY (Hz)
10M
100M
Figure 32. PSRR vs Frequency
100
100
90
90
80
80
CT (rej) (dB)
CMRR (dB)
Figure 31. Closed Loop Output Impedance
vs Frequency AV = +1
70
60
50
70
60
50
VS = 5V
40
40
AV = +6
30
100
1k
Receive CH.: AV = +2, Rf = Rg = 510
30
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 33. CMRR vs Frequency
Figure 34. Crosstalk Rejection vs Frequency
(Output to Output)
2
1
VS = 10V
VS = 5V
0.8
1.5
RL = 150: to V+/2
0.6
1.0
0.4
85°C
0.2
VOS (mV)
VOS (mV)
1M
FREQUENCY (Hz)
85°C
0
-0.2
-0.4
0.5
0
25°C
-0.5
25°C
-1
-40°C
-0.6
-1.5
-0.8
-40°C
-1
-2
-2
VOUT (V)
4
VCM (V)
Figure 35. VOS vs VOUT (Typical Unit)
Figure 36. VOS vs VCM (Typical Unit)
0
1
2
3
4
5
0
2
6
8
10
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Typical Performance Characteristics (continued)
V+ = +5 V, V– = –5 V, RF = RL = 2 kΩ, unless specified otherwise.
1
1
-40°C
0.8
0.8
Unit #1
0.6
0.4
0.4
0.2
0.2
VOS (mV)
VOS (mV)
Unit #1
0.6
0
-0.2
25°C
0
Unit #2
-0.2
Unit #2
-0.4
-0.4
Unit #3
-0.6
-0.6
Unit #3
-0.8
-0.8
-1
-1
2
4
6
8
10
12
2
3
4
5
8
7
9
10
11
VS (V)
Figure 37. VOS vs VS (for 3 Representative Units)
Figure 38. VOS vs VS (for 3 Representative Units)
1
-1000
0.8
-1100
Unit #1
0.6
-1200
0.4
-1300
0.2
IB (nA)
VOS (mV)
85°C
0
Unit #2
-0.2
-40°C
-1400
25°C
-1500
-1600
-0.4
85°C
-1700
-0.6
Unit #3
-1800
-0.8
-1900
-1
2
3
4
5
6
8
7
9
10
2
12
4
6
10
12
Figure 40. IB vs VS
Figure 39. VOS vs VS (for 3 Representative Units)
50
4
45
3.5
VS = 10V
85°C
IS (mA) (PER CHANNEL)
40
35
IOS (nA)
8
VS (V)
VS (V)
30
25
-40°C
20
15
25°C
10
5
2
4
3
2.5
25°C
2
-40°C
1.5
1
0.5
0
85°C
0
18
6
VS (V)
6
8
10
12
-0.5
-2
VS (V)
4
VCM (V)
Figure 41. IOS vs VS
Figure 42. IS vs VCM
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2
6
8
10
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Typical Performance Characteristics (continued)
V+ = +5 V, V– = –5 V, RF = RL = 2 kΩ, unless specified otherwise.
4
VS = 3V
VO = 100mVPP
IS (mA) (PER CHANNEL)
85°C
RL = 2k to VS/2
AV = -1
3
25°C
2
-40°C
1
2
4
6
8
10
20 ns/DIV
40 mV/DIV
12
VS (V)
Figure 43. IS vs VS
Figure 44. Small Signal Step Response
AV = +2
VS = ±5V
VO = 8VPP
AV = +1
RL= 2k
VS=±1.5V
VO=2VPP
AV= -1
RL=2k
4 /DIV
400 mV/DIV
200.0 ns/DIV
Figure 45. Large Signal Step Response
Figure 46. Large Signal Step Response
VS = 3V
VS = ±5V
VO = 100mVPP
VO = 100mVPP
RL = 2k to VS/2
AV = +1, RL = 2k
AV = +1
40 mV/DIV
40.0 nS/DIV
10 ns/DIV
40 mV/DIV
Figure 47. Small Signal Step Response
10.0 ns/DIV
Figure 48. Small Signal Step Response
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Typical Performance Characteristics (continued)
V+ = +5 V, V– = –5 V, RF = RL = 2 kΩ, unless specified otherwise.
VS = ±5V
VS = ±5V
VO = 200mVPP
AV = +2,
RL = 2k
VO = 100mVPP
RL = 2k
AV = -1
40 mV/DIV
20 ns/DIV
40 mV/DIV
Figure 49. Small Signal Step Response
Figure 50. Small Signal Step Response
VS = ±5V
VS = ±5V
VO = 8VPP
VO = 2VPP
AV = +2
RL = 2k
RL = 2k
AV = -1
2 V/DIV
400 mV/DIV
40.0 ns/DIV
20 ns/DIV
Figure 52. Large Signal Step Response
Figure 51. Large Signal Step Response
AV = -1
VS = ±5V
VOUT = 8VPP
RL = 2K:
2 V/DIV
20.0 ns/DIV
100 ns/DIV
Figure 53. Large Signal Step Response
20
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8 Detailed Description
8.1 Overview
The LMH6644-MIL is based on proprietary VIP10 dielectrically isolated bipolar process. This device architecture
features the following:
• Complimentary bipolar devices with exceptionally high ft (∼8 GHz) even under low-supply voltage (2.7 V) and
low-bias current.
• A class A-B turn-around stage with improved noise, offset, and reduced power dissipation compared to
similar speed devices (patent pending).
• Common Emitter push-push output stage capable of 75-mA output current (at 0.5 V from the supply rails)
while consuming only 2.7 mA of total supply current per channel. This architecture allows output to reach
within mV of either supply rail.
• Consistent performance over the entire operating supply voltage range with little variation for the most
important specifications (for example, BW, SR, IOUT, and so forth)
• Significant power saving (∼40%) compared to competitive devices on the market with similar performance.
8.2 Functional Block Diagram
V+
V+
V+
R
R
IN-
IN+
V-
V-
Figure 54. Input Equivalent Circuit
8.3 Feature Description
The LMH6644-MIL is a drop-in replacement for the AD805X family of high-speed op amps in most applications.
In addition, the LMH6644-MIL will typically save about 40% on power dissipation, due to lower supply current,
when compared to competition. All AD805X family’s specified parameters are included in the list of LMH6644MIL ensured specifications in order to ensure equal or better level of performance. However, as in most highperformance parts and due to subtleties of applications, it is strongly recommended that the performance of the
part to be evaluated is tested under actual operating conditions to ensure full compliance to all specifications.
8.4 Device Functional Modes
With 3-V supplies and a common-mode input voltage range that extends 0.5 V below V–, the LMH6644-MIL find
applications in low voltage/low power applications. Even with 3-V supplies, the –3dB BW (@ AV = +1) is typically
115 MHz with a tested limit of 80 MHz. Production testing guarantees that process variations will not compromise
speed. High-frequency response is exceptionally stable, confining the typical –3dB BW over the industrial
temperature range to ±2.5%.
As seen in Typical Performance Characteristics, the LMH6644-MIL output current capability (∼75 mA) is
enhanced compared to AD805X. This enhancement increases the output load range, adding to the LMH6644MIL’s versatility. Since LMH6644-MIL is capable of high-output current, device junction temperature should not to
exceed the Absolute Maximum Ratings.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This device was designed to avoid output phase reversal. With input overdrive, the output is kept near supply rail
(or as closed to it as mandated by the closed loop gain setting and the input voltage). See Figure 56.
However, if the input voltage range of –0.5 V to 1 V from V+ is exceeded by more than a diode drop, the internal
ESD protection diodes will start to conduct. The current in the diodes should be kept at or below 10 mA.
Output overdrive recovery time is less than 100 ns as can be seen in Figure 57.
9.2 Typical Application
Cf
5pF
Photodiode
Equivalent
Circuit
Vbias
Rf
1k:
Rbias
C1
100nF
Q1
2N3904
VCC =
+5V
-1mAPP
-
Cd
Photodiode
10
200pF
Id
Rd
×100k:
R5
510:
R2
1.8k:
x
Vout
+
D1
1N4148
R11
910
:
R10
1k:
R3
1k:
+5V
Figure 55. Single-Supply Photodiode I-V Converter
9.2.1 Design Requirements
The circuit shown in Figure 55 is used to amplify the current from a photodiode into a voltage output. In this
circuit, the emphasis is on achieving high bandwidth and the transimpedance gain setting is kept relatively low.
Because of its high-slew-rate limit and high speed, the LMH6644-MIL lends itself well to such an application. This
circuit achieves approximately 1 V/mA of transimpedance gain and capable of handling up to 1 mApp from the
photodiode. Q1, in a common base configuration, isolates the high capacitance of the photodiode (Cd) from the
op amp input in order to maximize speed. Input is AC coupled through C1 to ease biasing and allow single
supply operation. With 5-V single supply, the device input/output is shifted to near half supply using a voltage
divider from VCC. Note that Q1 collector does not have any voltage swing and the Miller effect is minimized. D1,
tied to Q1 base, is for temperature compensation of Q1’s bias point. Q1 collector current was set to be large
enough to handle the peak-to-peak photodiode excitation and not too large to shift the U1 output too far from
mid-supply.
22
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Typical Application (continued)
9.2.1.1 Input and Output Topology
All input / output pins are protected against excessive voltages by ESD diodes connected to V+ and V– rails (see
Figure 54). These diodes start conducting when the input / output pin voltage approaches 1 Vbe beyond V+ or V–
to protect against over voltage. These diodes are normally reverse biased. Further protection of the inputs is
provided by the two resistors (R in Figure 54), in conjunction with the string of anti-parallel diodes connected
between both bases of the input stage. The combination of these resistors and diodes reduces excessive
differential input voltages approaching 2 Vbe. This occurs most commonly when the device is used as a
comparator (or with little or no feedback) and the device inputs no longer follow each other. In such a case, the
diodes may conduct. As a consequence, input current increases and the differential input voltage is clamped. It is
important to make sure that the subsequent current flow through the device input pins does not violate the
Absolute Maximum Ratings of the device. To limit the current through this protection circuit, extra series resistors
can be placed. Together with the built-in series resistors of several hundred ohms, these external resistors can
limit the input current to a safe number (that is, less than 10 mA). Be aware that these input series resistors may
impact the switching speed of the device and could slow down the device.
9.2.1.2 Single-Supply, Low-Power Photodiode Amplifier
The circuit shown in Figure 55 is used to amplify the current from a photodiode into a voltage output. In this
circuit, the emphasis is on achieving high bandwidth and the transimpedance gain setting is kept relatively low.
Because of its high slew rate limit and high speed, the LMH6644-MIL lends itself well to such an application.
This circuit achieves approximately 1V/mA of transimpedance gain and capable of handling up to 1mApp from the
photodiode. Q1, in a common base configuration, isolates the high capacitance of the photodiode (Cd) from the
Op Amp input in order to maximize speed. Input is AC coupled through C1 to ease biasing and allow singlesupply operation. With 5-V single supply, the device input/output is shifted to near half supply using a voltage
divider from VCC. Note that Q1 collector does not have any voltage swing and the Miller effect is minimized. D1,
tied to Q1 base, is for temperature compensation of Q1’s bias point. Q1 collector current was set to be large
enough to handle the peak-to-peak photodiode excitation and not too large to shift the U1 output too far from
mid-supply.
No matter how low an Rf is selected, there is a need for Cf in order to stabilize the circuit. The reason for this is
that the Op Amp input capacitance and Q1 equivalent collector capacitance together (CIN) will cause additional
phase shift to the signal fed back to the inverting node. Cf will function as a zero in the feedback path counteracting the effect of the CIN and acting to stabilized the circuit. By proper selection of Cf such that the Op Amp
open loop gain is equal to the inverse of the feedback factor at that frequency, the response is optimized with a
theoretical 45° phase margin.
CF =
SQRT (CIN)/(2S ˜ GBWP ˜ RF)
where
•
GBWP is the Gain Bandwidth Product of the Op Amp
(1)
Optimized as such, the I-V converter will have a theoretical pole, fp, at:
fP = SQRT GBWP/(2SRF ˜ CIN)
(2)
With op amp input capacitance of 3 pF and an estimate for Q1 output capacitance of about 3 pF as well, CIN = 6
pF. From the typical performance plots, GBWP is approximately 57 MHz. Therefore, with Rf = 1k, from
Equation 1 and Equation 2:
Cf = ∼4.1 pF and fp = 39 MHz
(3)
For this example, optimum Cf was empirically determined to be around 5 pF. This time domain response is
shown in Figure 58 below showing about 9-ns rise/fall times, corresponding to about 39 MHz for fp. The overall
supply current from the +5 V supply is around 5 mA with no load.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
No matter how low an Rf is selected, there is a need for Cf in order to stabilize the circuit. The reason for this is
that the op amp input capacitance and Q1 equivalent collector capacitance together (CIN) will cause additional
phase shift to the signal fed back to the inverting node. Cf will function as a zero in the feedback path
counteracting the effect of the CIN and acting to stabilized the circuit. By proper selection of Cf such that the Op
Amp open loop gain is equal to the inverse of the feedback factor at that frequency, the response is optimized
with a theoretical 45° phase margin where GBWP is the Gain Bandwidth Product of the Op Amp, optimized as
such, the I-V converter will have a theoretical pole, fp, at: (2) With Op Amp input capacitance of 3pF and an
estimate for Q1 output capacitance of about 3 pF as well, CIN = 6 pF. From the typical performance plots, GBWP
is approximately 57 MHz. Therefore, with Rf = 1k, from Equation 2 and Equation 3 : Cf = ∼4.1 pF and fp = 39
MHz.
For this example, optimum Cf was empirically determined to be around 5 pF. This time domain response is
shown in Figure 58 showing about 9 ns rise/fall times, corresponding to about 39 MHz for fp. The overall supply
current from the +5-V supply is around 5 mA with no load.
9.2.3 Application Curves
VIN (1 V/DIV)
Output
V
+
VOUT (VPP)
Input
V
VS = ±2.5V
-
VS=±5V, VIN=5VPP
AV = +1
1V/DIV
AV=+5, RF=RL=2k
200 ns/DIV
Figure 56. Input and Output Shown with CMVR Exceeded
200 mV/DIV
VOUT (2 V/DIV)
100 ns/DIV
2 V/DIV
Figure 57. Overload Recovery Waveform
20 ns/DIV
Figure 58. Converter Step Response (1 VPP, 20 ns/DIV)
10 Power Supply Recommendations
The LMH6644-MIL device can operate off a single supply or with dual supplies. The input CM capability of the
parts (CMVR) extends all the way down to the V– rail to simplify single supply applications. Supplies should be
decoupled with low inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins.
The use of ground plane is recommended, and as in most high speed devices, it is advisable to remove ground
plane close to device sensitive pins such as the inputs.
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11 Layout
11.1 Layout Guidelines
Generally, a good high-frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see Application Note OA-15, "Frequent Faux Pas in Applying Wideband Current
Feedback Amplifiers", SNOA367, for more information). Texas Instruments suggests the following evaluation
boards as a guide for high-frequency layout and as an aid in device testing and characterization:
Table 1. Printed Circuit Board Layout And Component Values
DEVICE
PACKAGE
EVALUATION BOARD PN
LMH6644MA
14-Pin SOIC
LMH730231
LMH6644MT
14-Pin TSSOP
LMH730131
Another important parameter in working with high-speed and high-performance amplifiers is the component
values selection. Choosing external resistors that are large in value will effect the closed loop behavior of the
stage because of the interaction of these resistors with parasitic capacitances. These capacitors could be
inherent to the device or a by-product of the board layout and component placement. Either way, keeping the
resistor values lower, will diminish this interaction to a large extent. On the other hand, choosing very low value
resistors could load down nodes and will contribute to higher overall power dissipation.
11.2 Layout Example
Figure 59. LMH6644-MIL Layer 1
Figure 60. LMH6644-MIL Layer 2
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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29-Jun-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
LMH6644 MDC
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DIESALE
Y
0
100
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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