Texas Instruments | ADS1282-HT High-Temperature High-Resolution Delta Sigma ADC (Rev. H) | Datasheet | Texas Instruments ADS1282-HT High-Temperature High-Resolution Delta Sigma ADC (Rev. H) Datasheet

Texas Instruments ADS1282-HT High-Temperature High-Resolution Delta Sigma ADC (Rev. H) Datasheet
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ADS1282-HT
SBAS446H – DECEMBER 2009 – REVISED FEBRUARY 2016
ADS1282-HT High-Temperature High-Resolution Delta Sigma ADC
1 Features
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1
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•
•
•
•
•
•
•
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(1)
High Resolution: 124-dB SNR (1000 SPS)
High Accuracy: THD: –102 dB
INL: 0.5 ppm
Low-Noise PGA
Two-Channel Input MUX
Inherently-Stable Modulator With Fast Responding
Over-Range Detection
Flexible Digital Filter:
– Sinc + FIR + IIR (Selectable)
– Linear or Minimum Phase Response
– Programmable High-Pass Filter
– Selectable FIR Data Rates: 250 SPS to 4
kSPS
Filter Bypass Option
Low-Power Consumption: 25 mW (210°C)
Offset and Gain Calibration Engine
SYNC Input
Analog Supply: Unipolar (5 V) or Bipolar (±2.5 V)
Digital Supply: 1.75 to 3.3 V
Supports Extreme Temperature Applications (1)
– Controlled Baseline
– One Assembly/Test Site
– One Fabrication Site
– Available in Extreme (–55°C to 210°C)
Temperature Range
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
2 Applications
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•
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Energy Exploration
Seismic Monitoring
High-Accuracy Instrumentation
Down-Hole Drilling
High Temperature Environments
3 Description
The ADS1282-HT device is an extremely highperformance, single-chip analog-to-digital converter
(ADC) with an integrated, low-noise programmable
gain amplifier (PGA) and two-channel input
multiplexer (MUX). The ADS1282-HT device is
suitable for the demanding needs of energy
exploration and seismic monitoring environments.
Device Information(1)
PART NUMBER
PACKAGE
ADS1282-HT
Texas Instruments high temperature products use highly
optimized silicon (die) solutions with design and process
enhancements to maximize performance over extended
temperatures.
BODY SIZE (NOM)
CDIP SB (28)
7.49 mm × 35.56 mm
TSSOP (28)
4.40 mm × 9.70 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
AVDD
VREFN
VREFP
DVDD
CLK
ADS1282
MUX
Input 1
Input 2
PGA
4th-Order
DS
Modulator
Programmable
Digital Filter
Calibration
SPI
Interface
SCLK
DOUT
DIN
DRDY
Control
SYNC
RESET
PWDN
VCOM
Over-Range
Modulator Output
3
AVSS
DGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS1282-HT
SBAS446H – DECEMBER 2009 – REVISED FEBRUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
1
1
1
2
3
4
5
Absolute Maximum Ratings ...................................... 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Electrical Characteristics (PW Package) .................. 8
Timing Requirements .............................................. 10
Pulse-Sync Timing Requirements........................... 10
Reset Timing Requirements ................................... 11
Read Data Timing Requirements............................ 11
Switching Characteristics ...................................... 11
Modulator Switching Characteristics..................... 11
Typical Characteristics .......................................... 12
8
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
16
17
17
36
36
41
Application and Implementation ........................ 46
9.1 Application Information............................................ 46
9.2 Typical Application ................................................. 46
10 Power Supply Recommendations ..................... 48
11 Device and Documentation Support ................. 50
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
50
53
53
53
53
12 Mechanical, Packaging, and Orderable
Information ........................................................... 53
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (May 2015) to Revision H
•
Page
Relaxed current for standby and power mode from "110 µA" to "250 µA" ............................................................................ 7
Changes from Revision F (August 2011) to Revision G
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Removed data in Specifications for low-power modes .......................................................................................................... 6
•
Removed low-power mode data from graphs in Typical Characteristics ............................................................................ 12
•
Remove low-power mode information from Figure 35 ........................................................................................................ 24
Changes from Revision C (August 2010) to Revision D
Page
•
Changed ƒCLK/128 to ƒCLK/512 in Modulator......................................................................................................................... 21
•
Updated Modulator Input Impedance ................................................................................................................................... 23
•
Updated Figure 36................................................................................................................................................................ 25
•
Updated Table 9 and added footnote................................................................................................................................... 34
•
Updated Modulator Output Mode ......................................................................................................................................... 36
•
Updated Figure 56 and added footnote................................................................................................................................ 36
•
Updated Figure 75................................................................................................................................................................ 46
2
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SBAS446H – DECEMBER 2009 – REVISED FEBRUARY 2016
5 Description (continued)
The converter uses a fourth-order, inherently stable, delta-sigma (ΔΣ) modulator that provides outstanding noise
and linearity performance. The modulator is used either in conjunction with the on-chip digital filter, or can be
bypassed for use with post processing filters.
The flexible input MUX provides an additional external input for measurement, as well as internal self-test
connections. The PGA features outstanding low noise (5 nV/√Hz) and high input impedance, allowing easy
interfacing to geophones and hydrophones over a wide range of gains.
The digital filter provides selectable data rates from 250 to 4000 samples per second (SPS). The high-pass filter
(HPF) features an adjustable corner frequency. On-chip gain and offset scaling registers support system
calibration.
The synchronization input (SYNC) can be used to synchronize the conversions of multiple ADS1282s. The
SYNC input also accepts a clock input for continuous alignment of conversions from an external source.
Two operating modes allow optimization of noise and power. Together, the amplifier, modulator, and filter
dissipate 30 mW. The ADS1282-SP is fully specified from –55°C to 210°C or from –55°C to 175°C for the PW
package.
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6 Pin Configuration and Functions
JDJ or PW Package
28-Pin CDIP SB or TSSOP
Top View
CLK
1
28
BYPAS
SCLK
2
27
DGND
¾
DRDY
3
26
DVDD
DOUT
4
25
DGND
DIN
5
24
¾
RESET
DGND
6
23
¾
PWDN
MCLK
7
22
VREFP
M1
8
21
VREFN
M0
9
20
AVSS
SYNC
10
19
AVDD
MFLAG
11
18
AINN1
DGND
12
17
AINP1
CAPN
13
16
AINN2
CAPP
14
15
AINP2
Pin Functions
PIN
NAME
I/O
DESCRIPTION
CDIP SB
TSSOP
CLK
1
1
Digital input
Master clock input
SCLK
2
2
Digital input
Serial clock input
DRDY
3
3
Digital output
Data ready output: read data on falling edge
DOUT
4
4
Digital output
Serial data output
DIN
5
5
Digital input
Serial data input
MCLK
7
7
Digital I/O
Modulator clock output; if in modulator mode:
MCLK: Modulator clock output
Otherwise, the pin is an unused input (must be tied).
M1
8
8
Digital I/O
Modulator data output 1; if in modulator mode:
M1: Modulator data output 1
Otherwise, the pin is an unused input (must be tied).
M0
9
9
Digital I/O
Modulator data output 0; if in modulator mode:
M0: Modulator data output 0
Otherwise, the pin is an unused input (must be tied).
SYNC
10
10
Digital input
Synchronize input
MFLAG
11
11
Digital output
Modulator Over-Range flag: 0 = normal, 1 = modulator over-range
Digital ground
Digital ground, pin 12 is the key ground point
DGND
6
6
12
12
27
25
29
27
CAPN
13
13
Analog
PGA outputs: Connect 10-nF capacitor from CAPP to CAPN
CAPP
14
14
Analog
PGA outputs: Connect 10-nF capacitor from CAPP to CAPN
AINP2
15
15
Analog input
Positive analog input 2
AINN2
16
16
Analog input
Negative analog input 2
AINP1
17
17
Analog input
Positive analog input 1
AINN1
18
18
Analog input
Negative analog input 1
4
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Pin Functions (continued)
PIN
NAME
CDIP SB
TSSOP
19
AVDD
20
21
AVSS
22
I/O
DESCRIPTION
19
Analog supply
Positive analog power supply
20
Analog supply
Negative analog power supply
VREFN
23
21
Analog input
Negative reference input
VREFP
24
22
Analog input
Positive reference input
PWDN
25
23
Digital input
Power-down input, active low
RESET
26
24
Digital input
Reset input, active low
DVDD
28
26
Digital supply
BYPAS
30
28
Analog
Digital power supply: 1.8 V to 3.3 V
Sub-regulator output: Connect 1-μF capacitor to DGND
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
MIN
MAX
UNIT
AVDD to AVSS
–0.3
5.5
V
AVSS to DGND
–2.8
0.3
V
DVDD to DGND
–0.3
3.9
V
100, momentary
mA
10, continuous
mA
Input current
Input current
Analog input voltage (AINP1, AINN1, AINP2, AINN2, VREFN, VREFP,
CAPP, CAPN)
AVSS – 0.3
AVDD + 0.3
Digital input voltage to DGND (CLK, SCLK, DRDY, DOUT, DIN, MCLK,
M1, M0, MFLAG, SYNC, PWDN, RESET)
–0.3
DVDD + 0.3
Storage temperature, Tstg
–60
150
(1)
V
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Operating temperature range
NOM
–55
MAX
UNIT
125
°C
7.3 Thermal Information
ADS1282-HT
THERMAL METRIC
(1)
JDJ (CDIP SB)
PW (TSSOP)
28 PINS
28 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
43.1
54.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
14.03
11.3
°C/W
RθJB
Junction-to-board thermal resistance
23.2
13
°C/W
ψJT
Junction-to-top characterization parameter
N/A
0.5
°C/W
ψJB
Junction-to-board characterization parameter
N/A
12.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.98
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.4 Electrical Characteristics
Limit specifications at –55°C to 210°C. Typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK (1) = 4.096 MHz, VREFP = 2.5 V,
VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1, and ƒDATA = 1000 SPS, unless otherwise noted.
TEST
CONDITIONS
PARAMETER
TA = 210°C (2)
TA = –55°C to 125°C
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
ANALOG INPUTS
VIN = (AINP –
AINN)
Full-scale input voltage
Absolute input range
AINP
or
AINN
±VREF/(2 × PGA)
AVSS + 0.7
PGA input voltage noise density
Differential input impedance
AVDD –
1.25
AVDD –
1.25
AVSS + 0.7
5
(3)
Common-mode input impedance
Input bias current
Crosstalk
V
ƒ = 31.25 Hz
MUX ON-resistance
V
nV/√Hz
1
GΩ
100
MΩ
1
1000
nA
–128
–123
dB
30
45
Ω
PGA OUTPUT (CAPP, CAPN)
Absolute output range
AVSS + 0.4
PGA differential output
impedance
AVDD – 0.4
AVSS + 0.4
600
Output impedance tolerance
±10%
External bypass capacitance
10
Modulator differential input
impedance
55
AVDD – 0.4
V
Ω
600
±10%
100
10
nF
kΩ
AC PERFORMANCE
Signal-to-noise ratio (4)
Total harmonic
distortion (5)
Spurious-free dynamic
range
SNR
THD
112
124
110
122
dB
PGA = 1...16
–122
–99
–102
–99
PGA = 32
–117
–99
–98
–94
PGA = 64
–115
SFDR
dB
–93
dB
123
DC PERFORMANCE
No missing
codes
Resolution
Data rate
ƒDATA
Integral nonlinearity (INL) (6)
31
FIR filter mode
250
Sinc filter mode
8000
Differential input
Offset error
Offset error after calibration (8)
Shorted input
Offset drift
Gain error (9)
–1.5%
Gain error after calibration (8)
Gain drift
4000
250
128000
8000
0.00005
0.0090
0.002
50
200
99
1
2
0.02
0.19
–1%
–0.5%
–1.5%
0.0002%
–1%
2
3
PGA = 16
9
11
0.3%
ƒCM = 60 Hz (11)
82
110
4000
SPS
128000
SPS
0.01 % FSR (7)
250
μV
μV
μV/°C
–0.5%
0.0002%
PGA = 1
Gain matching (10)
Common-mode rejection
bits
31
0.8%
ppm/°C
ppm/°C
0.8%
82
137
dB
(1)
(2)
ƒCLK = system clock.
Minimum and maximum parameters are characterized for operation at TA = 210°C, but may not be production tested at that
temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
(3) Input impedance is improved by disabling input chopping (CHOP bit = 0).
(4) VIN = 20mVDC/PGA, see Table 1.
(5) VIN = 31.25 Hz, –0.5 dBFS.
(6) Best-fit method.
(7) FSR: Full-scale range = ±VREF / (2 × PGA).
(8) Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings).
(9) The PGA output impedance and the modulator input impedance results in –1% systematic gain error.
(10) Gain match relative to PGA = 1.
(11) ƒCM is the input common-mode frequency. ƒPS is the power-supply frequency.
6
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Electrical Characteristics (continued)
Limit specifications at –55°C to 210°C. Typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK(1) = 4.096 MHz,
VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1, and ƒDATA = 1000 SPS, unless otherwise
noted.
TEST
CONDITIONS
PARAMETER
Power-supply rejection
AVDD
,
AVSS ƒPS = 60 Hz (11)
DVD
D
TA = 210°C (2)
TA = –55°C to 125°C
MIN
TYP
80
90
MAX
MIN
TYP
MAX
UNIT
83
dB
90
115
0.5
5
101
VOLTAGE REFERENCE INPUTS
(VREF = VREFP –
VREFN)
Reference input voltage
(AVDD –
AVSS) + 0.2
0.5
(AVDD –
AVSS) + 0.2
AVSS – 0.1
VREFP –
0.5
VREFN +
0.5
AVDD + 0.1
Negative reference input
VREF
N
AVSS – 0.1
VREFP –
0.5
Positive reference input
VREF
P
VREFN + 0.5
AVDD + 0.1
Reference input impedance
85
85
V
V
V
kΩ
DIGITAL FILTER RESPONSE
Passband ripple
±0.003
Passband (–0.01 dB)
0.375 × ƒDATA
Bandwidth (–3 dB)
0.413 × ƒDATA
High-pass filter corner
0.1
Stop band attenuation (12)
135
Stop band
Group delay
Settling time (latency)
dB
Hz
Hz
10
Hz
dB
0.500 × ƒDATA
Minimum phase
filter
Hz
5 / ƒDATA
s
Linear phase
filter
31 / ƒDATA
Minimum phase
filter
62 / ƒDATA
s
Linear phase
filter
62 / ƒDATA
s
DIGITAL INPUT/OUTPUT
VIH
0.8 × DVDD
DVDD
0.8 × DVDD
DVDD
V
VIL
DGND
0.2 × DVDD
DGND
0.2 × DVDD
V
VOH
IOH = 1 mA
VOL
IOL = 1 mA
Input leakage
0 < VDIGITAL IN <
DVDD
0.8 × DVDD
0.8 × DVDD
V
0.2 × DVDD
0.2 × DVDD
±10
±10
V
μA
POWER SUPPLY
AVSS
AVDD
DVDD
AVDD, AVSS current
DVDD current
–2.6
0
–2.6
0
V
AVSS + 4.75
AVSS +
5.25
AVSS +
4.75
AVSS +
5.25
V
3.6
1.75
3.6
V
5.2
10
|mA|
3000
3700
|μA|
3000
3700
|μA|
1.2
2
mA
1.75
High-resolution
mode
4.5
7.2
Standby mode
68
250
Power-down
mode
68
250
All modes
0.6
1.5
Modulator mode
0.1
Standby mode
73
175
Power-down
mode (13)
32
120
1.1
mA
576
950
μA
186
240
μA
(12) Input frequencies in the range of NƒCLK / 512 ± ƒDATA / 2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency
ranges intermodulation = 120 dB, typ.
(13) CLK input stopped.
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Electrical Characteristics (continued)
Limit specifications at –55°C to 210°C. Typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK(1) = 4.096 MHz,
VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1, and ƒDATA = 1000 SPS, unless otherwise
noted.
TEST
CONDITIONS
PARAMETER
Power dissipation
TA = 210°C (2)
TA = –55°C to 125°C
MIN
TYP
MAX
High-resolution
mode
25
41
Standby mode
0.58
1.1
Power-down
mode
0.45
0.95
MIN
UNIT
TYP
MAX
29.7
56.1
mW
16.9
21.6
mW
15.6
19.3
mW
7.5 Electrical Characteristics (PW Package)
Limit specifications at –55°C to 175°C. Typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK (1) = 4.096 MHz, VREFP = 2.5 V,
VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1, and ƒDATA = 1000 SPS, unless otherwise noted.
PARAMETER
TEST CONDITIONS
TA = 175°C (2)
TA = –55°C to 125°C
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Full-scale input voltage
Absolute input range
±VREF / (2 ×
PGA)
VIN = (AINP – AINN)
AINP
or
AINN
AVSS + 0.7
±VREF / (2 ×
PGA)
AVDD –
1.25
V
AVDD –
1.25
AVSS + 0.7
V
PGA input voltage noise density
5
5
Differential input impedance (3)
1
1
GΩ
100
100
MΩ
Common-mode input impedance
Input bias current
Crosstalk
f = 31.25 Hz
MUX on-resistance
nV/√Hz
1
1000
nA
–128
–123
dB
30
45
Ω
PGA OUTPUT (CAPP, CAPN)
AVSS + 0.4
Absolute output range
PGA differential output
impedance
AVDD – 0.4
600
Output impedance tolerance
±10%
External bypass capacitance
10
Modulator differential input
impedance
55
AVDD –
0.4
AVSS + 0.4
V
Ω
600
±10%
100
10
nF
55
kΩ
AC PERFORMANCE
Signal-to-noise ratio (4)
Total harmonic
distortion (5)
Spurious-free dynamic
range
SNR
THD
112
124
112
122
dB
PGA = 1...16
–122
–99
–112
–99
PGA = 32
–117
–99
–106
–94
PGA = 64
–115
SFDR
dB
–102
dB
123
DC PERFORMANCE
Resolution
Data rate
(1)
(2)
(3)
(4)
(5)
8
No missing codes
ƒDATA
31
31
bits
FIR filter mode
250
4000
250
4000
SPS
Sinc filter mode
8000
128000
8000
128000
SPS
ƒCLK = System clock
Minimum and maximum parameters are characterized for operation at TA = 175°C, but may not be production tested at that
temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
Input impedance is improved by disabling input chopping (CHOP bit = 0).
VIN = 20 mVDC / PGA, see Table 1.
VIN = 31.25 Hz, –0.5 dBFS.
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SBAS446H – DECEMBER 2009 – REVISED FEBRUARY 2016
Electrical Characteristics (PW Package) (continued)
Limit specifications at –55°C to 175°C. Typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK(1) = 4.096 MHz,
VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1, and ƒDATA = 1000 SPS, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
Integral nonlinearity (INL) (6)
MIN
Differential input
Offset error
Offset error after calibration (8)
Shorted input
Offset drift
Gain error (9)
–1.5%
Gain error after calibration (8)
Gain drift
TYP
MAX
0.00005
50
MAX
0.009
0.00004
0.009
200
50
200
2
0.02
0.19
–1%
–0.5%
–1.5%
–1%
2
2
PGA = 16
9
11
ƒPS = 60 Hz (11)
DVDD
UNIT
%
FSR (7)
μV
μV
μV/°C
–0.5%
0.0002%
PGA = 1
ƒCM = 60 Hz (11)
AVDD,
AVSS
TYP
1
0.3%
Common-mode rejection
MIN
0.0002%
Gain matching (10)
Power-supply rejection
TA = 175°C (2)
TA = –55°C to 125°C
0.8%
0.4%
82
110
82
80
90
84
90
115
106
0.5
5
ppm/°C
ppm/°C
0.8%
114
dB
dB
VOLTAGE REFERENCE INPUTS
(VREF = VREFP –
VREFN)
Reference input voltage
Negative reference
input
VREFN
Positive reference input
VREFP
(AVDD –
AVSS) + 0.2
0.5
(AVDD –
AVSS) +
0.2
AVSS – 0.1
VREFP –
0.5
AVSS – 0.1
VREFP –
0.5
V
VREFN + 0.5
AVDD + 0.1
VREFN +
0.5
AVDD +
0.1
V
Reference input impedance
85
85
V
kΩ
DIGITAL FILTER RESPONSE
Passband ripple
±0.003
±0.003
Passband (–0.01 dB)
0.375 × ƒDATA
0.375 × ƒDATA
Bandwidth (–3 dB)
0.413 × ƒDATA
0.413 × ƒDATA
High-pass filter corner
0.1
Stop band attenuation (12)
135
Stop band
10
0.1
Hz
Hz
10
135
0.500 × ƒDATA
dB
Hz
dB
0.500 × ƒDATA
Hz
DIGITAL INPUT/OUTPUT
VIH
VIL
VOH
IOH = 1 mA
0.8 × DVDD
DVDD
DGND
0.2 × DVDD
0.8 × DVDD
IOL = 1 mA
VOL
Input leakage
0.8 × DVDD
DVDD
V
DGND
0.2 ×
DVDD
V
0.8 × DVDD
0.2 × DVDD
0 < VDIGITAL IN <
DVDD
V
0.2 ×
DVDD
±10
±10
V
μA
POWER SUPPLY
AVSS
AVDD
DVDD
(6)
(7)
(8)
(9)
(10)
(11)
(12)
–2.6
0
–2.6
0
V
AVSS + 4.75
AVSS +
5.25
AVSS +
4.75
AVSS +
5.25
V
1.75
3.6
1.75
3.6
V
Best-fit method.
FSR: Full-scale range = ±VREF / (2 × PGA).
Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings).
The PGA output impedance and the modulator input impedance results in –1% systematic gain error.
Gain match relative to PGA = 1.
ƒCM is the input common-mode frequency. ƒPS is the power-supply frequency.
Input frequencies in the range of NƒCLK / 512 ± ƒDATA / 2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency
ranges intermodulation = 120 dB, typ.
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Electrical Characteristics (PW Package) (continued)
Limit specifications at –55°C to 175°C. Typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK(1) = 4.096 MHz,
VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1, and ƒDATA = 1000 SPS, unless otherwise
noted.
PARAMETER
AVDD, AVSS current
DVDD current
Power dissipation
TA = 175°C (2)
TA = –55°C to 125°C
TEST CONDITIONS
MIN
TYP
MAX
High-resolution
mode
4.5
7.2
Standby mode
68
Power-down mode
68
All modes
0.6
Modulator mode
0.1
Standby mode
73
175
Power-down
mode (13)
32
120
High-resolution
mode
25
41
Standby mode
0.58
1.1
Power-down mode
0.45
0.95
MIN
UNIT
TYP
MAX
5.2
9.2
|mA|
110
52
900
|μA|
110
52
900
|μA|
1.5
0.7
1.5
mA
1.05
mA
255
600
μA
118
220
μA
31
41
mW
2.5
5
mW
2.06
4.5
mW
(13) CLK input stopped.
7.6 Timing Requirements
At TA = –55°C to 210°C and DVDD = 1.65 to 3.6 V, unless otherwise noted.
TA = –55°C to 125°C
TA = 175°C
MIN
MAX
TA = 210°C
MIN
MAX
MIN
MAX
UNIT
tSCLK
SCLK period
2
16
2
16
2
16
1 / ƒCLK
tSPWH, L
SCLK pulse width, high and low (1)
0.8
10
0.8
10
0.8
10
1 / ƒCLK
tDIST
DIN valid to SCLK rising edge: setup time
50
50
50
ns
tDIHD
Valid DIN to SCLK rising edge: hold time
50
50
50
ns
tDOPD
SCLK falling edge to valid new DOUT:
propagation delay (2)
tDOHD
SCLK falling edge to DOUT invalid: hold time
tSCDL
Final SCLK rising edge of command to first SCLK
rising edge for register read/write data
100
100
100
ns
0
0
0
ns
24
24
24
1 / ƒCLK
DIGITAL INPUT/OUTPUT
Clock input
ƒCLK
Serial clock
rate
ƒSCLK
(1)
(2)
1
4.096
1
ƒCLK/2
4.096
MHz
ƒCLK/2
MHz
Holding SCLK low for 64 DRDY falling edges resets the serial interface.
Load on DOUT = 20 pF || 100 kΩ.
7.7 Pulse-Sync Timing Requirements
See Figure 46 and Figure 47 for timing diagrams.
MIN
MAX
1
Infinite
UNIT
tSYNC
SYNC period (1)
tCSHD
CLK to SYNC hold time to not latch on CLK edge
10
tSCSU
SYNC to CLK setup time to latch on CLK edge
10
ns
2
1 / ƒCLK
tSPWH,
tDR
(1)
10
L
SYNC pulse width, high or low
Time for data ready (SINC filter)
n/ƒDATA
ns
See Device Support, Table 20
Time for data ready (FIR filter)
62.98046875 / ƒDATA + 466 / ƒCLK
Continuous-Sync mode; a free-running SYNC clock input without causing re-synchronization.
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7.8 Reset Timing Requirements
See Figure 48 for timing diagram.
MIN
MAX
UNIT
tCRHD
CLK to RESET hold time
10
tRCSU
RESET to CLK setup time
10
ns
ns
tRST
RESET low
2
1 / ƒCLK
tDR
Time for data ready
62.98046875 / ƒDATA + 468 / ƒCLK
s
7.9 Read Data Timing Requirements
MIN
tDDPD
DRDY to valid MSB on DOUT propagation delay (see Figure 54) (1)
tDR
Time for new data after data read command (see Figure 55)
(1)
0
MAX
UNIT
100
ns
1
ƒDATA
Load on DOUT = 20 pF || 100 kΩ.
7.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Group delay (1)
Settling time
(latency)
(1)
TEST CONDITIONS
MIN
Minimum phase filter
TYP
MAX
UNIT
5 / ƒDATA
Linear phase filter
31 / ƒDATA
Minimum phase filter
62 / ƒDATA
Linear phase filter
62 / ƒDATA
s
s
At DC. See Figure 42.
7.11 Modulator Switching Characteristics
See Figure 56.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
ns
tMCD0, 1
MCLK rising edge to M0, M1 valid
propagation delay (1)
tCMD
CLK rising edge (after SYNC rising
edge) to MCLK rising edge CMD
tCSHD
CLK to SYNC hold time to not latch
on CLK edge
10
ns
tSCSU
SYNC to CLK setup time to latch on
CLK edge
10
ns
tSYMD
SYNC to stable bit stream
(1)
5
1/ƒCLK
16
1/ƒMOD
Load on M0 and M1 = 20 pF || 100 kΩ.
tSCLK
tSCDL
tSPWH
SCLK
tDIST
tSPWL
tSCDL
DIN
tDIHD
tDOHD
DOUT
tDOPD
Figure 1. Timing Diagram
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7.12 Typical Characteristics
At 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA
= 1, and ƒDATA = 1000 SPS, unless otherwise noted.
0
-20
-60
-80
-100
-120
8192-Point FFT
VIN = -20dBFS, 31.25Hz
PGA = 1
THD = -120.1dB
-20
-40
Amplitude (dB)
-40
Amplitude (dB)
0
8192-Point FFT
VIN = -0.5dBFS, 31.25Hz
PGA = 1
THD = -124.0dB
-60
-80
-100
-120
-140
-140
-160
-160
-180
-180
0
50
100 150 200 250 300 350 400 450
Frequency (Hz)
500
0
50
100 150 200 250 300 350 400 450
Frequency (Hz)
Figure 2. Output Spectrum
0
-60
-80
-100
-120
8192-Point FFT
Shorted Input
SNR = 124.0dB
-20
-40
Amplitude (dB)
-40
Amplitude (dB)
Figure 3. Output Spectrum
0
8192-Point FFT
VIN = -0.5dBFS, 31.25Hz
PGA = 16
THD = -122.4dB
-20
-60
-80
-100
-120
-140
-140
-160
-160
-180
-180
0
50
100 150 200 250 300 350 400 450
Frequency (Hz)
500
0
50
100 150 200 250 300 350 400 450
Frequency (Hz)
Figure 4. Output Spectrum
8192-Point FFT
20mVDC
SNR = 124.2dB
-20
Amplitude (dB)
-40
500
Figure 5. Output Spectrum
-60
-80
-100
-120
-140
-100
Total Harmonic Distortion (dB)
0
THD Limited by
Signal Generator
-105
-110
PGA = 1
PGA = 8
-115
-120
-125
-160
VIN = –0.5 dBFS
-130
-180
0
50
100 150 200 250 300 350 400 450
Frequency (Hz)
500
10
Figure 6. Output Spectrum
12
500
20
30
40
50
60
70
Input Frequency (Hz)
80
90
100
Figure 7. THD vs Input Frequency
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Typical Characteristics (continued)
At 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP
= 10 nF, PGA = 1, and ƒDATA = 1000 SPS, unless otherwise noted.
-100
126
125
-105
123
-110
THD (dB)
SNR (dB)
124
122
121
120
-115
-120
119
118
-125
117
-55 -35 -15
5
25 45 65 85 105 125 145 165 185 205
-130
-55
-35
-15
5
25
Temperature (°C)
Figure 8. SNR (1000 SPS) vs Temperature
65
85
105
125
145
165
185
205
Figure 9. THD (G = 8) vs Temperature
-110
130
PGA = 1
PGA = 8
Total Harmonic Distortion (dB)
Signal-to-Noise Ratio (dB)
45
Temperature (°C)
125
PGA = 8
120
115
110
105
-115
-120
-125
PGA = 1
-130
100
0
1
2
3
VREF (V)
4
5
0
5.5
Figure 10. SNR vs Reference Voltage
2
123
122
121
VIN = 20mVDC
Data Rate = fCLK/4096
119
0.5
1.0
1.5
2.0
2.5
3.0
fCLK (MHz)
3.5
4.0
4.5
Total Harmonic Distortion (dB)
124
120
3
VREF (V)
4
5
6
Figure 11. THD vs Reference Voltage
-110
125
Signal-to-Noise Ratio (dB)
1
PGA = 8
VIN = 31.25Hz, -0.5dBFS
Data Rate = fCLK/4096
-115
-120
-125
-130
0.5
Figure 12. SNR vs Clock Frequency
1.0
1.5
2.0
2.5
3.0
fCLK (MHz)
3.5
4.0
Figure 13. THD vs Clock Frequency
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Typical Characteristics (continued)
At 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP
= 10 nF, PGA = 1, and ƒDATA = 1000 SPS, unless otherwise noted.
130
140
120
120
Power-Supply Rejection (dB)
Common-Mode Rejection (dB)
DVDD
110
100
90
80
70
AVDD
100
80
AVSS
60
40
20
0
10
100
1k
10k
Input Frequency (Hz)
100k
1M
10
Figure 14. CMR vs Input Frequency
100
1k
10k
100k
Power-Supply Frequency (Hz)
1M
Figure 15. Power-Supply Rejection vs Frequency
4
30
2
20
PGA = 2
IN L ( p p m )
Integral Nonlinearity (ppm)
3
1
0
-1
PGA = 8
PGA = 32
10
0
-2
-3
-4
-100
-75
-50
-25
0
25
50
Input Amplitude (% Full-Scale)
75
-10
-55 -35 -15
100
25 45 65 85 105 125 145 165 185 205
Temperature (°C)
Figure 16. INL vs Input Amplitude
Figure 17. INL vs Temperature
0
35
Shorted Input
8192-Point FFT
Adjacent Channel VIN = -0.5dBFS, 31.25Hz
-20
-40
-60
30
Power (mW)
Amplitude (dB)
5
-80
-100
-120
25
20
-140
15
-160
-180
0
50
100 150 200 250 300 350 400 450
Frequency (Hz)
500
10
-55
-25
Figure 18. Crosstalk Output Spectrum
14
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5
35
65
95
125
Temperature (°C)
155
185
215
Figure 19. Power vs Temperature
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Typical Characteristics (continued)
At 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP
= 10 nF, PGA = 1, and ƒDATA = 1000 SPS, unless otherwise noted.
30
30
25 Units
25
25
20
20
Occurrences
Power (mW)
PGA = 8
15
10
15
10
PGA = 1
5
5
0
0
1.0
1.5
2.0
2.5
3.0
fCLK (MHz)
3.5
4.0
4.5
-100 -80 -60 -40 -20
0
20
Offset (mV)
Figure 20. Power vs Clock Frequency
60
80
100
Figure 21. Offset Histogram
90
10
25 Units
80
8
70
Occurrences
Occurrences
40
6
4
25 Units Based on
+20°C Intervals
Over the Range of
-40°C to +85°C
60
50
40
30
20
2
PGA = 8
PGA =1
10
0
0.10
0.08
0.06
0.04
-0.3
0.02
-0.4
0
-0.5
-0.02
-0.8 -0.7 -0.6
Gain Error (%)
-0.04
-0.9
-0.06
-1.0
-0.10
-1.1
-0.08
0
-1.2
Offset Drift (mV/°C)
Figure 22. Gain Error Histogram
90
80
25 Units Based on +20°C Intervals
Over the Range of -40°C to +85°C
Figure 23. Offset Drift Histogram
8
70
6
PGA = 16
Occurrences
Occurrences
PGA = 32
60
50
Worst-Case Gain Match Relative PGA = 1 (25 Units)
PGA = 1, 2, 4
PGA = 8, 64
40
30
4
2
20
10
Gain Drift (ppm/°C)
Gain Error (%)
Figure 24. Gain Drift Histogram
Figure 25. Gain Match Histogram
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0.02
0.06
0.10
0.14
0.18
0.22
0.26
0.30
0.34
0.38
0.42
0.46
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
0.50
0
0
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8 Detailed Description
8.1 Overview
The ADS1282-HT is a high-performance analog-to-digital converter (ADC) intended for energy exploration,
seismic monitoring, chromatography, and other exacting applications. The converter provides 24- or 32-bit output
data in data rates from 250 SPS to 4000 SPS. The Functional Block Diagram shows the block diagram of the
ADS1282-HT.
The two-channel input MUX allows five configurations: Input 1; Input 2; Input 1 and Input 2 shorted together;
shorted with 400-Ω test; and common-mode test. The input MUX is followed by a continuous time PGA, featuring
very low noise of 5 nV/√Hz. The PGA is controlled by register settings, allowing gains of 1 to 64.
The inherently-stable, fourth-order, delta-sigma modulator measures the differential input signal VIN = (AINP –
AINN) PGA against the differential reference VREF = (VREFP – VREFN). A digital output (MFLAG) indicates that
the modulator is in overload as a result of an overdrive condition. The modulator output is available directly on
the MCLK, M0, and M1 output pins when in modulator mode. The modulator connects to an on-chip digital filter
that provides the output code readings.
The digital filter consists of a variable decimation rate, fifth-order sinc filter followed by a variable phase,
decimate-by-32, finite-impulse response (FIR) low-pass filter with programmable phase, and then by an
adjustable high-pass filter for DC removal of the output reading. The output of the digital filter can be taken from
the sinc, the FIR low-pass, or the infinite impulse response (IIR) high-pass sections.
Gain and offset registers scale the digital filter output to produce the final code value. The scaling feature can be
used for calibration and sensor gain matching. The output data word is provided as either a 24-bit word or a full
32-bit word, allowing complete utilization of the inherently high resolution.
The SYNC input resets the operation of both the digital filter and the modulator, allowing synchronization
conversions of multiple ADS1282-HT devices to an external event. The SYNC input supports a continuouslytoggled input mode that accepts an external data frame clock locked to the conversion rate.
The RESET input resets the register settings and also restarts the conversion process. The PWDN input sets the
device into a micro-power state. The register settings are not retained in PWDN mode. Use the STANDBY
command in its place if it is desired to retain register settings (the quiescent current in the Standby mode is
slightly higher).
Noise-immune Schmitt-trigger and clock-qualified inputs (RESET and SYNC) provide increased reliability in highnoise environments. The serial interface is used to read conversion data, in addition to reading from and writing
to the configuration registers.
The device features unipolar and bipolar analog power supplies (AVDD and AVSS, respectively) for input range
flexibility and a digital supply accepting 1.8 V to 3.3 V. The analog supplies may be set to 5 V to accept unipolar
signals (with input offset) or set lower in the range of ±2.5 V to accept true bipolar input signals (ground
referenced).
An internal sub-regulator is used to supply the digital core from DVDD. The BYPAS pin (pin 28) is the subregulator output and requires a 1-μF capacitor for noise reduction. BYPAS should not be used to drive external
circuitry.
16
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VREFP
VREFN
AVDD
CAPN
CAPP
8.2 Functional Block Diagram
ADS1282
AINP2
AINN2
AINP1
AINN1
BYPAS
CLK
+1.8V
(Digital core)
DVDD
LDO
MUX
300W
400W
PGA
4th-Order
DS
Modulator
300W
400W
Programmable
Digital Filter
Calibration
Serial
Interface
Over-Range
Detection
SYNC
Control
RESET
PWDN
AVDD + AVSS
2
AVSS
DRDY
SCLK
DIN
DOUT
MFLAG
MCLK
M0
M1
DGND
8.3 Feature Description
8.3.1 Noise Performance
The ADS1282-HT device offers outstanding noise performance (SNR). SNR depends on the data rate, the PGA
setting, and the mode. As the bandwidth is reduced by decreasing the data rate, the SNR improves
correspondingly. Similarly, as the PGA gain is increased, the SNR decreases. Table 1 summarizes the noise
performance versus data rate, PGA setting, and mode.
8.3.2 Input-Referred Noise
The input-referred noise is related to SNR by Equation 1:
FSRRMS
SNR = 20log
NRMS
where:
•
•
FSRRMS = Full-scale range RMS = (VREFP – VREFN)/(2 × √2 × PGA)
NRMS = Noise RMS (input-referred)
(1)
8.3.3 Idle Tones
The ADS1282-HT modulator incorporates an internal dither signal that randomizes the idle tone energy. Lowlevel idle tones may still be present, typically –137-dB less than full-scale. The low-level idle tones can be shifted
out of the passband with an external offset = 20 mV/PGA. See the Application Information section for the
recommended offset circuit.
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Feature Description (continued)
8.3.4 Operating Mode
The default mode is high-resolution.
Table 1. Signal-to-Noise Ratio (dB) (1)
PGA
(1)
DATA RATE (SPS)
1
2
4
8
16
32
64
250
130
130
129
128
125
119
114
500
127
127
126
125
122
116
111
1000
124
124
123
122
119
113
108
2000
121
121
120
119
116
111
106
4000
118
118
117
116
113
108
103
VIN = 20 mVDC / PGA.
8.3.5 Analog Inputs and Multiplexer
Figure 26 shows a diagram of the input multiplexer.
ESD diodes protect the multiplexer inputs. If either input is taken less than AVSS – 0.3 V or greater than AVDD +
0.3 V, the ESD protection diodes may turn on. If these conditions are possible, external Schottky clamp diodes
and/or series resistors may be required to limit the input current to safe values (see the Absolute Maximum
Ratings).
Also, overdriving one unused input may affect the conversions of the other input. If overdriven inputs are
possible, TI recommends clamping the signal with external Schottky diodes.
AVDD
S1
AINP1
ESD Diodes
S2
AINP2
400W
(+)
S3
S7
AVSS
To PGA
AVDD + AVSS
AVDD
2
400W
S4
S5
AINN1
ESD Diodes
AINN2
(-)
S6
AVSS
Figure 26. Analog Inputs and Multiplexer
The specified input operating range of the PGA is shown in Equation 2:
AVSS + 0.7V < (AINN or AINP) < AVDD - 1.25V
(2)
Absolute input levels (input signal level and common-mode level) should be maintained within these limits for
best operation.
18
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The multiplexer connects one of the two external differential inputs to the preamplifier inputs, in addition to
internal connections for various self-test modes. Table 2 summarizes the multiplexer configurations for Figure 26.
Table 2. Multiplexer Modes
MUX[2:0]
SWITCHES
000
S1, S5
AINP1 and AINN1 connected to preamplifier
DESCRIPTION
001
S2, S6
AINP2 and AINN2 connected to preamplifier
010
S3, S4
Preamplifier inputs shorted together through 400Ω internal resistors
011
S1, S5, S2, S6
100
S6, S7
AINP1, AINN1 and AINP2, AINN2 connected together and to the preamplifier
External short, preamplifier inputs shorted to AINN2 (common-mode test)
The typical on-resistance (RON) of the multiplexer switch is 30 Ω. When the multiplexer is used to drive an
external load on one input by a signal generator on the other input, on-resistance and on-resistance amplitude
dependency can lead to measurement errors. Figure 27 shows THD versus load resistance and amplitude. THD
improves with high-impedance loads and with lower amplitude drive signals. The data are measured with the
circuit from Figure 28 with MUX[2:0] = 011.
Total Harmonic Distortion (dB)
0
PGA = 1
PGA = 2
PGA = 4
PGA = 8
PGA = 16
PGA = 32
PGA = 64
-20
-40
-60
-80
-100
-120
-140
0.1k
1k
10k
100k
1M
10M
RLOAD (W)
Figure 27. THD vs External Load and Signal Magnitude (PGA) (See Figure 28)
500W
500W
RLOAD
ADS1282
Input 1
Input 2
Figure 28. Driving an External Load Through the MUX
8.3.6 PGA (Programmable Gain Amplifier)
The PGA of the ADS1282-HT is a low-noise, continuous-time, differential-in/differential-out CMOS amplifier. The
gain is programmable from 1 to 64, set by register bits, PGA[2:0]. The PGA differentially drives the modulator
through 300-Ω internal resistors. A COG capacitor (10 nF typical) must be connected to CAPP and CAPN to filter
modulator sampling glitches. The external capacitor also serves as an anti-alias filter. The corner frequency is
given in Equation 3:
1
fP =
6.3 ´ 600 ´ C
(3)
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Referring to Figure 29, amplifiers A1 and A2 are chopped to remove the offset, offset drift, and the 1/f noise.
Chopping moves the effects to ƒCLK/128 (8 kHz), which is safely out of the passband. Chopping can be disabled
by setting the CHOP register bit = 0. With chopping disabled, the impedance of the PGA increases substantially
(>> 1 GΩ). As shown in Figure 30, chopping maintains flat noise density; if chopping is disabled, however, it
results in a rising 1/f noise profile.
The PGA has programmable gains from 1 to 64. Table 3 shows the register bit setting for the PGA and resulting
full-scale differential range.
The specified output operating range of the PGA is shown in Equation 4:
AVSS + 0.4V < (CAPN or CAPP) < AVDD - 0.4V
(4)
PGA output levels (signal plus common-mode) should be maintained within these limits for best operation.
Table 3. PGA Gain Settings
(1)
DIFFERENTIAL INPUT RANGE (V) (1)
PGA[2:0]
GAIN
000
1
±2.5
001
2
±1.25
010
4
±0.625
011
8
±0.312
100
16
±0.156
101
32
±0.078
110
64
±0.039
VREF = 5 V
AVDD
MUX (+)
300W
A1
CAPP
CHOP
Gain Control
PGA[2:0] Bits
10nF
(1)
300W
CAPN
A2
(55kW, typ )
Modulator
Effective
Impedance
MUX (-)
Chopping Control CHOP Bit
AVSS
Figure 29. PGA Block Diagram
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PGA Noise (nV/ÖHz)
100
PGA CHOP Off
10
PGA CHOP On
1
10
100
Frequency (Hz)
1k
Figure 30. PGA Noise
8.3.7 ADC
The ADC block of the ADS1282-HT is composed of two sections: a high-accuracy modulator and a
programmable digital filter.
8.3.8 Modulator
The high-performance modulator is an inherently-stable, fourth-order, ΔΣ, 2 + 2 pipelined structure, as Figure 31
shows. It shifts the quantization noise to a higher frequency (out of the passband) where digital filtering can
easily remove it. The modulator can be filtered either by the on-chip digital filter or by use of post-processing
filters.
fCLK/4
Analog Input (VIN)
MCLK
2nd-Order
DS
1st-Stage
M0
2nd-Order
DS
2nd-Stage
M1
4th-Order Modulator
Figure 31. Fourth-Order Modulator
The modulator first stage converts the analog input voltage into a pulse-code modulated (PCM) stream. When
the level of differential analog input (AINP – AINN) is near one-half the level of the reference voltage 1/2 ×
(VREFP – VREFN), the ‘1’ density of the PCM data stream is at its highest. When the level of the differential
analog input is near zero, the PCM ‘0’ and ‘1’ densities are nearly equal. At the two extremes of the analog input
levels (+FS and –FS), the ‘1’ density of the PCM streams is approximately 90% and 10%, respectively.
The modulator second stage produces a '1' density data stream designed to cancel the quantization noise of the
first stage. The data streams of the two stages are then combined before the digital filter stage, as shown in
Equation 5.
Y[n] = 3M0[n - 2] - 6M0[n - 3] + 4M0[n - 4]
+ 9(M1[n] - 2M1[n - 1] + M1[n - 2])
(5)
M0[n] represents the most recent first-stage output while M0[n – 1] is the previous first-stage output. When the
modulator output is enabled, the digital filter shuts down to save power.
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The modulator is optimized for input signals within a 4-kHz passband. As Figure 32 shows, the noise shaping of
the modulator results in a sharp increase in noise greater than 6 kHz. The modulator has a chopped input
structure that further reduces noise within the passband. The noise moves out of the passband and appears at
the chopping frequency (ƒCLK / 512 = 8 kHz). The component at 5.8 kHz is the tone frequency, shifted out of
band by an external 20 mV/PGA offset. The frequency of the tone is proportional to the applied DC input and is
given by PGA × VIN/0.003 (in kHz).
0
VIN = 20mVDC
-20
Magnitude (dB)
-40
-60
-80
-100
-120
-140
-160
-180
1
10
100
1k
10k
100k
Frequency (Hz)
1-Hz resolution
Figure 32. Modulator Output Spectrum
8.3.9 Modulator Over-Range
The ADS1282-HT modulator is inherently stable, and therefore, has predictable recovery behavior resulting from
an input overdrive condition. The modulator does not exhibit self-resetting behavior, which often results in an
unstable output data stream.
The ADS1282-HT modulator outputs a 1s density data stream at 90% duty cycle with the positive full-scale input
signal applied (10% duty cycle with the negative full-scale signal). If the input is overdriven past 90% modulation,
but less than 100% modulation (10% and 0% for negative overdrive, respectively), the modulator remains stable
and continues to output the 1s density data stream. The digital filter may or may not clip the output codes to +FS
or –FS, depending on the duration of the overdrive. When the input returns to the normal range from a long
duration overdrive (worst case), the modulator returns immediately to the normal range, but the group delay of
the digital filter delays the return of the conversion result to within the linear range (31 readings for linear phase
FIR). 31 additional readings (62 total) are required for completely settled data.
If the inputs are sufficiently overdriven to drive the modulator to full duty cycle, all 1s or all 0s, the modulator
enters a stable saturated state. The digital output code may clip to +FS or –FS, again depending on the duration.
A small duration overdrive may not always clip the output code. When the input returns to the normal range, the
modulator requires up to 12 modulator clock cycles (ƒMOD) to exit saturation and return to the linear region. The
digital filter requires an additional 62 conversions for fully settled data (linear phase FIR).
In the extreme case of over-range, either input is overdriven, exceeding the voltage of either analog supply
voltage plus an internal ESD diode drop. The internal diodes begin to conduct and the signal on the input is
clipped. When the input overdrive is removed, the diodes recover quickly. Keep in mind that the input current
must be limited to 100-mA peak or 10 mA continuous if an overvoltage condition is possible.
22
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8.3.10 Modulator Input Impedance
The modulator samples the buffered input voltage with an internal capacitor to perform conversions. The
charging of the input sampling capacitor draws a transient current from the PGA output. The average value of the
current can be used to calculate an effective input impedance of:
REFF = 1 / (ƒMOD × CS)
where
•
•
ƒMOD = Modulator sample frequency
– Mode = CLK / 4
CS = Input sampling capacitor (17 pF, typ)
(6)
The resulting modulator input impedance for CLK = 4.096 MHz is 55 kΩ. The modulator input impedance and the
PGA output resistors result in a systematic gain error of –1%. CS can vary ±20% over production lots, affecting
the gain error.
8.3.11 Modulator Over-Range Detection (MFLAG)
The ADS1282-HT has a fast-responding over-range detection that indicates when the differential input exceeds
±100% full scale. The threshold tolerance is ±2.5%.The MFLAG output asserts high when in an over-range
condition. As Figure 33 and Figure 34 illustrate, the absolute differential input is compared to 100% of range. The
output of the comparator is sampled at the rate of ƒMOD / 2, yielding the MFLAG output. The minimum MFLAG
pulse width is ƒMOD / 2.
AINP
å
IABSI
P
100% FS
AINN
Q
MFLAG
Pin
fMOD/2
VIN (% of Full-Scale)
Figure 33. Modulator Over-Range Block Diagram
+100
(AINP - AINN)
0
Time
-100
MFLAG
Pin
Figure 34. Modulator Over-Range Flag Operation
8.3.12 Voltage Reference Inputs (VREFP, VREFN)
The voltage reference for the ADS1282-HT is the differential voltage between VREFP and VREFN: VREF =
VREFP – VREFN. The reference inputs use a structure similar to that of the analog inputs with the circuitry of the
reference inputs shown in Figure 35. The average load presented by the switched capacitor reference input can
be modeled with an effective differential impedance of REFF = tSAMPLE / CIN (tSAMPLE = 1/ƒMOD). The effective
impedance of the reference inputs loads the external reference.
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AVDD
ESD
Diodes
VREFP
REFF = 85 kΩ
11.5pF
(fMOD = 1.024 MHz)
VREFN
ESD
Diodes
REFF =
1
fMOD ´ CX
AVSS
Figure 35. Simplified Reference Input Circuit
The ADS1282-HT reference inputs are protected by ESD diodes. In order to prevent these diodes from turning
on, the voltage on either input must stay within the range shown in Equation 7:
AVSS - 300mV < (VREFP or VREFN) < AVDD + 300mV
(7)
The minimum valid input for VREFN is AVSS – 0.1 V and maximum valid input for VREFP is AVDD + 0.1 V.
A high-quality 5 V reference voltage is necessary for achieving the best performance from the ADS1282-HT.
Noise and drift on the reference degrade overall system performance, and it is critical that special care be given
to the circuitry generating the reference voltages in order to achieve full performance. See Application
Information for reference recommendations.
8.3.13
Digital Filter
The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of
filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for
higher data rate.
The digital filter is comprised of three cascaded filter stages: a variable-decimation, fifth-order sinc filter; a fixeddecimation FIR, low-pass filter (LPF) with selectable phase; and a programmable, first-order, high-pass filter
(HPF), as shown in Figure 36.
The output can be taken from one of the three filter blocks, as Figure 36 shows. To implement the digital filter
completely off-chip, select the filter bypass setting (modulator output). For partial filtering by the ADS1282-HT,
select the sinc filter output. For complete on-chip filtering, activate both the sinc and FIR stages. The HPF can
then be included to remove DC and low frequencies from the data. Table 4 shows the filter options.
Table 4. Digital Filter Selection
24
FILTR[1:0] BITS
DIGITAL FILTERS SELECTED
00
Bypass; modulator output mode
01
Sinc
10
Sinc + FIR
11
Sinc + FIR + HPF
(low-pass and high-pass)
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8.3.13.1 Sinc Filter Stage (Sinx/X)
The sinc filter is a variable decimation rate, fifth-order, low-pass filter. Data are supplied to this section of the filter
from the modulator at the rate of ƒMOD (ƒCLK/4). The sinc filter attenuates the high-frequency noise of the
modulator, then decimates the data stream into parallel data. The decimation rate affects the overall data rate of
the converter; it is set by the DR[2:0] register bits, as shown in Table 5.
Equation 8 shows the scaled Z-domain transfer function of the sinc filter.
5
1 - Z-N
H(Z) =
-1
N(1 - Z )
(8)
Table 5. Sinc Filter Data Rates (Clk = 4.096 MHz)
DR[2:0] REGISTER
DECIMATION RATIO (N)
SINC DATA RATE (SPS)
000
128
8000
001
64
16000
010
32
32000
011
16
64000
100
8
128000
3
Direct Modulator
Bit Stream
Filter Mode
(Register Select)
30
Filter
MUX
Coefficient Filter
(FIR)
(Decimate by 32)
Sinc Filter
(Decimate by
8 to 128)
From Modulator
High-Pass Filter
(IIR)
CAL
Block
Code
Clip
To Output Register
31
Figure 36. Digital Filter and Output Code Processing
Equation 9 shows the frequency domain transfer function of the sinc filter.
5
sin
½H(f)½ =
N sin
pN ´ f
fMOD
p´f
fMOD
where
•
N = Decimation ratio (see Table 5)
(9)
The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these
frequencies, the filter has zero gain. Figure 37 shows the frequency response of the sinc filter and Figure 38
shows the roll-off of the sinc filter.
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0
-20
Gain (dB)
-40
-60
-80
-100
-120
-140
0
1
2
3
4
Normalized Frequency (fIN/fDATA)
5
Figure 37. Sinc Filter Frequency Response
0
-0.5
Gain (dB)
-1.0
-1.5
-2.0
-2.5
-3.0
0
0.05
0.10
0.15
0.20
Normalized Frequency (fIN/fDATA)
Figure 38. Sinc Filter Roll-Off
8.3.13.2 FIR Stage
The second stage of the ADS1282-HT digital filter is an FIR low-pass filter. Data are supplied to this stage from
the sinc filter. The FIR stage is segmented into four sub-stages, as shown in Figure 39. The first two sub-stages
are half-band filters with decimation ratios of 2. The third sub-stage decimates by 4 and the fourth sub-stage
decimates by 2. The overall decimation of the FIR stage is 32. Two coefficient sets are used for the third and
fourth sections, depending on the phase selection. Table 19 (in Device Support) lists the FIR stage coefficients.
Table 6 lists the data rates and overall decimation ratio of the FIR stage.
Table 6. Fir Filter Data Rates
26
DR[2:0] REGISTER
DECIMATION RATIO (N)
FIR DATA RATE (SPS)
000
4096
250
001
2048
500
010
1024
1000
011
512
2000
100
256
4000
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FIR Stage 2
Decimate by 2
FIR Stage 1
Decimate by 2
Sinc
Filter
FIR Stage 3
Decimate by 4
FIR Stage 4
Decimate by 2
Output
Coefficients
Linear
Minimum
PHASE Select
Figure 39. Fir Filter Sub-Stages
2.0
20
1.5
0
1.0
-20
Magnitude (dB)
Magnitude (mdB)
As shown in Figure 40, the FIR frequency response provides a flat passband to 0.375 of the data rate (±0.003dB passband ripple). Figure 41 shows the transition from passband to stop band.
0.5
0
-0.5
-1.0
-40
-60
-80
-100
-120
-1.5
-140
-2.0
-160
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0
Normalized Input Frequency (fIN/fDATA)
Figure 40. FIR Passband Magnitude Response (FDATA =
500 Hz)
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8
Normalized Input Frequency (fIN/fDATA)
0.9
1.0
Figure 41. FIR Transition Band Magnitude Response
Although not shown in Figure 41, the passband response repeats at multiples of the modulator frequency
(NƒMOD – ƒ0 and NƒMOD + ƒ0, where N = 1, 2, and so forth, and ƒ0 = passband). These image frequencies, if
present in the signal and not externally filtered, fold back (or alias) into the passband and cause errors. A lowpass signal filter reduces the effect of aliasing. Often, the RC low-pass filter provided by the PGA output resistors
and the external capacitor connected to CAPP and CAPN provides sufficient signal attenuation.
8.3.13.3 Group Delay and Step Response
The FIR block is implemented as a multi-stage FIR structure with selectable linear or minimum phase response.
The passband, transition band, and stop band responses of the filters are nearly identical but differ in the
respective phase responses.
8.3.13.3.1 Linear Phase Response
Linear phase filters exhibit constant delay time versus input frequency (that is, constant group delay). Linear
phase filters have the property that the time delay from any instant of the input signal to the same instant of the
output data is constant and is independent of the signal nature. This filter behavior results in essentially zero
phase error when analyzing multi-tone signals. However, the group delay and settling time of the linear phase
filter are somewhat larger than the minimum phase filter, as shown in Figure 42.
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1.4
Minimum Phase Filter
1.2
Amplitude (dB)
1.0
0.8
0.6
0.4
0.2
Linear Phase Filter
0
-0.2
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Time Index (1/fDATA)
Figure 42. FIR Step Response
8.3.13.3.2 Minimum Phase Response
The minimum phase filter provides a short delay from the arrival of an input signal to the output, but the
relationship (phase) is not constant versus frequency, as shown in Figure 43. The filter phase is selected by the
PHS bit, as Table 7 shows.
35
Linear Phase Filter
Group Delay (1/fDATA)
30
25
20
15
10
Minimum Phase Filter
5
0
20
40
60
80 100 120
Frequency (Hz)
140 160 180
200
Figure 43. FIR Group Delay (FDATA = 500 Hz)
Table 7. Fir Phase Selection
PHS BIT
28
FILTER PHASE
0
Linear
1
Minimum
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8.3.13.4 HPF Stage
The last stage of the ADS1282-HT filter block is a first-order HPF implemented as an IIR structure. This filter
stage blocks DC signals and rolls off low-frequency components below the cut-off frequency. The transfer
function for the filter is shown in Equation 16 of the Device Support.
The high-pass corner frequency is programmed by registers HPF[1:0], in hexadecimal. Equation 10 is used to set
the high-pass corner frequency. Table 8 lists example values for the high-pass filter.
HPF[1:0] = 65,536 1 -
1-2
cos wN + sin wN - 1
cos wN
where
•
•
•
•
HPF = High-pass filter register value (converted to hexadecimal)
ωN = 2πƒHP/ƒDATA (normalized frequency, radians)
ƒHP = High-pass corner frequency (Hz)
ƒDATA = Data rate (Hz)
(10)
Table 8. High-Pass Filter Value Examples
ƒHP (Hz)
DATA RATE (SPS)
HPF[1:0]
0.5
250
0337h
1
500
0337h
1
1000
019Ah
The HPF causes a small gain error, in which case the magnitude of the error depends on the ratio of ƒHP/ƒDATA.
For many common values of (ƒHP/ƒDATA), the gain error is negligible. Figure 44 shows the gain error of the HPF.
The gain error factor is illustrated in Equation 15 (see the Device Support).
0
Gain Error (dB)
-0.10
-0.20
-0.30
-0.40
-0.50
0.0001
0.001
0.01
0.1
Frequency Ratio (fHP/fDATA)
Figure 44. HPF Gain Error
Figure 45 shows the first-order amplitude and phase response of the HPF. In the case of applying step inputs or
synchronizing, the settling time of the filter should be taken into account.
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0
90
-7.5
75
-15.0
60
Amplitude
45
-22.5
Phase
-30.0
30
-37.5
15
-45.0
0.01
Phase (°)
Amplitude (dB)
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0
0.1
1
10
Normalized Frequency (f/fC)
100
Figure 45. HPF Amplitude and Phase Response
8.3.14 Master Clock Input (CLK)
The ADS1282-HT requires a clock input for operation. The clock is applied to the CLK pin. The data conversion
rate scales directly with the CLK frequency. Power consumption versus CLK frequency is relatively constant (see
the Typical Characteristics).
As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance.
Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock
input; keep the clock trace as short as possible and use a 50-Ω series resistor close to the source.
8.3.15 Synchronization (SYNC Pin and Sync Command)
The ADS1282-HT can be synchronized to an external event, as well as synchronized to other ADS1282-HT
devices if the sync event is applied simultaneously.
The ADS1282-HT has two sources for synchronization: the SYNC input pin and the SYNC command. The
ADS1282-HT also has two synchronizing modes: Pulse-sync and Continuous-sync. In Pulse-sync mode, the
ADS1282-HT synchronizes to a single sync event. In Continuous-sync mode, either a single SYNC event is used
to synchronize conversions or a continuous clock is applied to the pin with a period equal to integer multiples of
the data rate. When the periods of the sync input and the DRDY output do not match, the ADS1282-HT resynchronizes and conversions are restarted.
8.3.16 Pulse-Sync Mode
In pulse-sync mode, the ADS1282-HT stops and restarts the conversion process when a sync event occurs (by
pin or command). When the sync event occurs, the device resets the internal memory; DRDY goes high (pulse
SYNC mode) otherwise in Continuous SYNC mode, DRDY continues to toggle, and after the digital filter has
settled, new conversion data are available, as shown in Figure 46 and Pulse-Sync Timing Requirements.
Resynchronization occurs on the next rising CLK edge after the rising edge of the SYNC pin or after the eighth
rising SCLK edge for opcode SYNC commands. To be effective, the SYNC opcode should be broadcast to all
devices simultaneously.
8.3.17 Continuous-Sync Mode
In Continuous-sync mode, either a single sync pulse or a continuous clock may be applied. When a single sync
pulse is applied (rising edge), the device behaves similar to the Pulse-sync mode. However, in this mode, DRDY
continues to toggle unaffected but the DOUT output is held low until data are ready, 63 DRDY periods later.
When the conversion data are non-zero, new conversion data are ready (as shown in Figure 46).
When a continuous clock is applied to the SYNC pin, the period must be an integral multiple of the output data
rate or the device re-synchronizes. Synchronization results in the restarting of the digital filter and an interruption
of 63 readings (refer to Pulse-Sync Timing Requirements).
30
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When the sync input is first applied, the device re-synchronizes (under the condition tSYNC ≠ N / ƒDATA). DRDY
continues to output but DOUT is held low until the new data are ready. Then, if SYNC is applied again and the
period matches an integral multiple of the output data rate, the device freely runs without re-synchronization. The
phase of the applied clock and output data rate (DRDY) are not matched because of the initial delay of DRDY
after SYNC is first applied. Figure 47 shows the timing for Continuous-Sync mode.
A SYNC clock input should be applied after the Continuous-Sync mode is set. The first rising edge of SYNC then
causes a synchronization.
tCSHD
System Clock
(fCLK)
tSCSU
SYNC Command
tSPWH
SYNC Pin
New Data
Ready
tSPWL
tDR
DRDY
(Pulse-Sync)
New Data
Ready
tDR
DRDY
(Continuous-Sync)
DOUT
Figure 46. Pulse-Sync Timing, Continuous-Sync Timing With Single Sync
tSCSU
tCSHD
System Clock
(fCLK)
tSPWL
tSPWH
SYNC
tSYNC
DRDY
1/fDATA
Figure 47. Continuous-Sync Timing With Sync Clock
8.3.18 Reset (RESET Pin and Reset Command)
The ADS1282-HT may be reset in two ways: toggle the RESET pin low or send a Reset command. When using
the RESET pin, take it low and hold for at least 2 / ƒCLK to force a reset. The ADS1282-HT is held in reset until
the pin is released. By command, RESET takes effect on the next rising edge of ƒCLK after the eighth rising edge
of SCLK of the command. To ensure the Reset command can function, the SPI interface may require resetting
itself; see Serial Interface.
In reset, registers are set to default and the conversions are synchronized on the next rising edge of CLK. New
conversion data are available, as shown in Figure 48 and Reset Timing Requirements.
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Settled
Data
DRDY
tDR
tCRHD
System Clock
(fCLK)
tRCSU
tRST
RESET Pin
or
RESET Command
Figure 48. Reset Timing
8.3.19 Power-Down (PWDN Pin and Standby Command)
There are two ways to power-down the ADS1282-HT: take the PWDN pin low or send a Standby command.
When the PWDN pin is pulled low, the internal circuitry is disabled to minimize power and the contents of the
register settings are reset.
In power-down, the device outputs remain active and the device inputs must not float. When the Standby
command is sent, the SPI port and the configuration registers are kept active. Figure 49 and Pulse-Sync Timing
Requirements show the timing.
PWDN Pin
Wakeup
Command
DRDY
tDR
Figure 49. PWDN Pin and Wake-Up Command Timing
(Pulse-Sync Timing Requirements Shows tDR)
8.3.20 Power-On Sequence
The ADS1282-HT has three power supplies: AVDD, AVSS, and DVDD. Figure 50 shows the power-on sequence
of the ADS1282-HT. The power supplies can be sequenced in any order. The supplies [the difference of
(AVDD – AVSS) and DVDD] generate an internal reset whose outputs are summed to generate a global internal
reset. After the supplies have crossed the minimum thresholds, 216 ƒCLK cycles are counted before releasing the
internal reset. After the internal reset is released, new conversion data are available, as shown in Figure 50 and
Pulse-Sync Timing Requirements.
AVDD - AVSS
DVDD
3.5V nom
1V nom
CLK
16
Internal Reset
2
fCLK
DRDY
tDR
Figure 50. Power-On Sequence
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8.3.21 Serial Interface
A serial interface is used to read the conversion data and access the configuration registers. The interface
consists of three basic signals: SCLK, DIN, and DOUT. An additional output, DRDY, transitions low in Read Data
Continuous mode when data are ready for retrieval. Figure 51 shows the connection when multiple converters
are used.
FPGA or Processor
SCLK
DOUT1
ADS1282
DIN2
DRDY1
SCLK
DOUT2
ADS1282
DIN2
DRDY2
SCLK
DOUT1
DIN1
IRQ
SCLK (optional)
DOUT2
DIN2
IRQ (optional)
Figure 51. Interface for Multiple Devices
8.3.21.1 Serial Clock (SCLK)
The serial clock (SCLK) is an input that is used to clock data into (DIN) and out of (DOUT) the ADS1282-HT.
This input is a Schmitt-trigger input that has a high degree of noise immunity. However, TI recommends keeping
SCLK as clean as possible to prevent possible glitches from inadvertently shifting the data.
Data are shifted into DIN on the rising edge of SCLK and data are shifted out of DOUT on the falling edge of
SCLK. If SCLK is held low for 64 DRDY cycles, data transfer or commands in progress terminate and the SPI
interface resets. The next SCLK pulse starts a new communication cycle. This time-out feature can be used to
recover the interface when a transmission is interrupted or SCLK inadvertently glitches. SCLK should remain low
when not active.
8.3.21.2 Data Input (DIN)
The data input pin (DIN) is used to input register data and commands to the ADS1282-HT. Keep DIN low when
reading conversion data in the Read Data Continuous mode (except when issuing a STOP Read Data
Continuous command). Data on DIN are shifted into the converter on the rising edge of SCLK. In Pin mode, DIN
is not used.
8.3.21.3 Data Output (DOUT)
The data output pin (DOUT) is used to output data from the ADS1282-HT. Data are shifted out on DOUT on the
falling edge of SCLK.
8.3.21.4 Data Ready (DRDY)
DRDY is an output; when it transitions low, this transition indicates new conversion data are ready, as shown in
Figure 52. When reading data by the continuous mode, the data must be read within four CLK periods before
DRDY goes low again or the data are overwritten with new conversion data. When reading data by the command
mode, the read operation can overlap the occurrence of the next DRDY without data corruption.
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DRDY
DOUT
Bit 31
Bit 30
Bit 29
SCLK
Figure 52. DRDY With Data Retrieval
DRDY resets high on the first falling edge of SCLK. Figure 52 and Figure 53 show the function of DRDY with and
without data readback, respectively.
If data are not retrieved (no SCLK provided), DRDY pulses high for four ƒCLK periods during the update time, as
shown in Figure 53.
4/fCLK
Data Updating
DRDY
Figure 53. DRDY With No Data Retrieval
8.3.22 Data Format
The ADS1282-HT provides 32 bits of conversion data in binary twos complement format, as shown in Table 9.
The LSB of the data is a redundant sign bit: '0' for positive numbers and '1' for negative numbers. However,
when the output is clipped to +FS, the LSB = 1; when the output is clipped to –FS, the LSB = 0. If desired, the
data readback may be stopped at 24 bits. In sinc filter mode, the output data are scaled by 1/2.
Table 9. Ideal Output Code Versus Input Signal
INPUT SIGNAL VIN
(AINP – AINN)
VREF
>
2 x PGA
VREF
2 x PGA
VREF
2PGA ´ (230 - 1)
0
-VREF
2PGA ´ (230 - 1)
<
34
´
230 - 1
SINC FILTER(2)
7FFFFFFFh
(3)
7FFFFFFEh
3FFFFFFFh
00000002h
00000001h
00000000h
00000000h
FFFFFFFFh
FFFFFFFFh
80000001h
C0000000h
80000000h
(3)
230
-VREF
2PGA
FIR FILTER
230
-VREF
2PGA
32-BIT IDEAL OUTPUT CODE(1)
´
230 - 1
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(1) Excludes effects of noise, linearity, offset, and gain errors.
(2) Due to the reduction in oversampling ratio (OSR) related to the sinc filter high data rates, full 32-bit available resolution is reduced.
(3) In sinc filter mode, the output does not clip at half-scale code when the full-scale range is exceeded.
8.3.23 Reading Data
The ADS1282-HT has two ways to read conversion data: Read Data Continuous and Read Data By Command.
8.3.23.1 Read Data Continuous
In the Read Data Continuous mode, the conversion data are shifted out directly from the device without the need
for sending a read command. This mode is the default mode at power-on. This mode is also enabled by the
RDATAC command. When DRDY goes low, indicating that new data are available, the MSB of data appears on
DOUT, as shown in Figure 54. The data are normally read on the rising edge of SCLK, at the occurrence of the
first falling edge of SCLK, DRDY returns high. After 32 bits of data have been shifted out, further SCLK
transitions cause DOUT to go low. If desired, the read operation may be stopped at 24 bits. The data shift
operation must be completed within four CLK periods before DRDY falls again or the data may be corrupted.
When a Stop Read Data Continuous command is issued, the DRDY output is blocked but the ADS1282-HT
continues conversions. In stop continuous mode, the data can only be read by command.
8.3.23.2 Read Data by Command
The Read Data Continuous mode is stopped by the SDATAC command. In this mode, conversion data are read
by command. In the Read Data By Command mode, a read data command must be sent to the device for each
data conversion (as shown in Figure 55). When the read data command is received (on the eighth SCLK rising
edge), data are available to read only when DRDY goes low (tDR). When DRDY goes low, conversion data
appear on DOUT. The data may be read on the rising edge of SCLK.
DRDY
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
25 26 27 28 29 30
31 32
SCLK
DOUT
Data Byte 1 (MSB)
Data Byte 2 (MSB - 1)
Data Byte 4 (LSB)
tDDPD
DIN
Figure 54. Read Data Continuous
DRDY
tDR
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
33 34 35 36 37 38
39 40
SCLK
DOUT
DIN
Don't Care
Command Byte (0001 0010)
Data Byte 1 (MSB)
Date Byte 4 (LSB)
tDDPD
Figure 55. Read Data By Command, Rdata (TDDPD Timing Is Given In Read Data Timing Requirements)
8.3.24 One-Shot Operation
The ADS1282-HT can perform very power-efficient, one-shot conversions using the STANDBY command while
under software control. Figure 73 shows this sequence. First, issue the STANDBY command to set the Standby
mode.
When ready to make a measurement, issue the WAKEUP command. Monitor DRDY; when it goes low, the fully
settled conversion data are ready and may be read directly in Read Data Continuous mode. Afterwards, issue
another STANDBY command. When ready for the next measurement, repeat the cycle starting with another
WAKEUP command.
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8.4 Device Functional Modes
8.4.1 Modulator Output Mode
The modulator digital stream output is accessible directly, bypassing and disabling the internal digital filter. The
modulator output mode is activated by setting the CONFIG0 register bits FILTR[1:0] = 00. Pins M0 and M1 then
become the modulator data outputs and the MCLK becomes the modulator clock output. When not in the
modulator mode, these pins are inputs and must be tied.
The modulator output is composed of three signals: one output for the modulator clock (MCLK) and two outputs
for the modulator data (M0 and M1). The modulator clock output rate is ƒMOD (ƒCLK / 4). The SYNC input resets
the MCLK phase, as shown in Figure 56. The SYNC input is latched on the rising edge of CLK. The MCLK
resets and the next rising edge of MCLK occurs five CLK periods later.
The modulator output data are two bits wide, which must be merged together before being filtered. Use the time
domain equation of Equation 5 to merge the data outputs.
tCSHD
CLK
tCMD
tSCSU
SYNC
tSYMD
MCLK
(1)
tMCD0, 1
M0
M1
(1) MCLK = ƒCLK / 4.
Figure 56. Modulator Mode Timing
8.5 Programming
8.5.1 Commands
The commands listed in Table 10 control the operation of the ADS1282-HT. Most commands are stand-alone
(that is, 1 byte in length); the register reads and writes require a second command byte in addition to the actual
data bytes.
A delay of 24 ƒCLK cycles between commands and between bytes within a command is required, starting from
the last SCLK rising edge of one command to the first SCLK rising edge of the following command. This delay is
shown in Figure 57.
In Read Data Continuous mode, the ADS1282-HT places conversion data on the DOUT pin as SCLK is applied.
As a consequence of the potential conflict of conversion data on DOUT and data placed on DOUT resulting from
a register or Read Data By Command operation, it is necessary to send a STOP Read Data Continuous
command before Register or Data Read By Command. The STOP Read Data Continuous command disables the
direct output of conversion data on the DOUT pin.
DIN
Command
Byte
Command
Byte
SCLK
(1)
tSCLKDLY
(1)
tSCLKDLY = 24/ƒCLK (min).
Figure 57. Consecutive Commands
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Programming (continued)
Table 10. Command Descriptions
COMMAND
TYPE
DESCRIPTION
1st COMMAND BYTE (1) (2)
WAKEUP
Control
Wake-up from Standby mode
0000 000X (00h or 01h)
STANDBY
Control
Enter Standby mode
0000 001X (0 h or 03h)
SYNC
Control
Synchronize the A/D conversion
0000 010X (04h or 5h)
RESET
Control
Reset registers to default values
0000 011X (06h or 07h)
RDATAC
Control
Read data continuous
0001 0000 (10h)
SDATAC
Control
Stop read data continuous
0001 0001 (11h)
RDATA
Data
RREG
Register
Read nnnnn register(s) at address rrrrr (4)
00r rrrr (20h + 000r rrrr)
000n nnnn (00h + n nnnn)
WREG
Register
Write nnnnn register(s) at address rrrrr
010r rrrr (40h + 000r rrrr)
000n nnnn (00h + n nnnn)
OFSCAL
Calibration
Offset calibration
0110 0000 (60h)
GANCAL
Calibration
Gain calibration
0110 0001 (61h)
(1)
(2)
(3)
(4)
Read data by command
(4)
2nd COMMAND BYTE (3)
0001 0010 (12h)
X = Don't care.
rrrrr = starting address for register read and write commands.
nnnnn = number of registers to be read/written – 1. For example, to read/write three registers, set nnnnn = 2 (00010).
Required to cancel Read Data Continuous mode before sending a command.
8.5.1.1 WAKEUP: Wake-Up from Standby Mode
This command is used to exit the standby mode. Upon sending the command, the time for the first data to be
ready is illustrated in Figure 49 and Table 9. Sending this command during normal operation has no effect; for
example, reading data by the Read Data Continuous method with DIN held low.
8.5.1.2 STANDBY: Standby Mode
This command places the ADS1282-HT into Standby mode. In Standby, the device enters a reduced power state
where a low quiescent current remains to keep the register settings and SPI interface active. For complete
device shutdown, take the PWDN pin low (register settings are not saved). To exit Standby mode, issue the
WAKEUP command. The operation of Standby mode is shown in Figure 58.
0000 001X
(STANDBY)
DIN
0000 000X
(WAKEUP)
SCLK
Operating
Standby Mode
Operating
Figure 58. Standby Command Sequence
8.5.1.3 SYNC: Synchronize the A/D Conversion
This command synchronizes the A/D conversion. Upon receipt of the command, the reading in progress is
cancelled and the conversion process is re-started. In order to synchronize multiple ADS1282-HTs, the command
must be sent simultaneously to all devices. The SYNC pin must be high for this command.
8.5.1.4 RESET: Reset the Device
The RESET command resets the registers to default values, enables the Read Data Continuous mode, and
restarts the conversion process; the RESET command is functionally the same as the RESET pin. See Figure 48
for the RESET command timing.
8.5.1.5 RDATAC: Read Data Continuous
This command enables the Read Data Continuous mode (default mode). In this mode, conversion data can be
read from the device directly without the need to supply a data read command. Each time DRDY falls low, new
data are available to read. See Read Data Continuous for more details.
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8.5.1.6 SDATAC: Stop Read Data Continuous
This command stops the Read Data Continuous mode. Exiting the Read Data Continuous mode is required
before sending Register and Data read commands. This command suppresses the DRDY output, but the
ADS1282-HT continues conversions.
8.5.1.7 RDATA: Read Data By Command
This command reads the conversion data. See Read Data by Command for more details.
8.5.1.8 RREG: Read Register Data
This command is used to read single or multiple register data. The command consists of a two-byte op-code
argument followed by the output of register data. The first byte of the op-code includes the starting address, and
the second byte specifies the number of registers to read – 1.
First command byte: 001r rrrr, where rrrrr is the starting address of the first register.
Second command byte: 000n nnnn, where nnnnn is the number of registers – 1 to read.
Starting with the 16th falling edge of SCLK, the register data appear on DOUT.
The RREG command is illustrated in Figure 59. The a delay of 24 ƒCLK cycles is required between each byte
transaction.
8.5.1.9 WREG: Write to Register
This command writes single or multiple register data. The command consists of a two-byte op-code argument
followed by the input of register data. The first byte of the op-code contains the starting address and the second
byte specifies the number of registers to write – 1.
First command byte: 001r rrrr, where rrrrr is the starting address of the first register.
Second command byte: 000n nnnn, where nnnnn is the number of registers – 1 to write.
Data byte(s): one or more register data bytes, depending on the number of registers specified.
Figure 60 illustrates the WREG command.
A delay of 24 ƒCLK cycles is required between each byte transaction.
8.5.1.10 OFSCAL: Offset Calibration
This command performs an offset calibration. The inputs to the converter (or the inputs to the external preamplifier) should be zeroed and allowed to stabilize before sending this command. The offset calibration register
updates after this operation. See Calibration Commands for more details.
8.5.1.11 GANCAL: Gain Calibration
This command performs a gain calibration. The inputs to the converter should have a stable DC input, preferably
close to (but not exceeding) positive full-scale. The gain calibration register updates after this operation. See
Calibration Commands for more details.
tDLY
1
2
3
4
5
6
7
8
9
tDLY
10 11 12 13 14 15 16
tDLY
17 18 19 20 21 22 23 24
25 26
SCLK
DIN
Command Byte 1
DOUT
Command Byte 2
Don't Care
Register Data 5
Register Data 6
Example: Read six registers, starting at register 05h (OFC0)
Command Byte 1 = 0010 0101
Command Byte 2 = 0000 0101
Figure 59. Read Register Data ( Shows tDLY)
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tDLY
1
2
3
4
5
6
7
8
9
tDLY
10 11 12 13 14 15 16
tDLY
17 18 19 20 21 22 23 24
25 26
SCLK
DIN
Command Byte 1
Command Byte 2
Register Data 5
Register Data 6
Example: Write six registers, starting at register 05h (OFC0)
Command Byte 1 = 0100 0101
Command Byte 2 = 0000 0101
Figure 60. Write Register Data ( Shows tDLY)
tDLY = 24 / ƒCLK
(11)
8.5.2 Calibration Commands
Calibration commands may be sent to the ADS1282-HT to calibrate the conversion data. The values of the offset
and gain calibration registers are internally written to perform calibration. The appropriate input signals must be
applied to the ADS1282-HT inputs before sending the commands. Use slower data rates to achieve more
consistent calibration results; this effect is a byproduct of the lower noise that these data rates provide. Also, if
calibrating at power-on, be sure the reference voltage is fully settled.
Figure 61 shows the calibration command sequence. After the analog input voltage (and reference) have
stabilized, send the Stop Data Continuous command followed by the SYNC and Read Data Continuous
commands. 64 data periods later, DRDY goes low. After DRDY goes low, send the Stop Data Continuous, then
the Calibrate command followed by the Read Data Continuous command. After 16 data periods, calibration is
complete and conversion data may be read at this time. The SYNC input must remain high during the calibration
sequence.
The calibration commands apply to specific PGA settings. If the PGA is changed, recalibration is necessary.
Calibration is bypassed in the sinc filter mode.
8.5.2.1 OFSCAL Command
The OFSCAL command performs an offset calibration. Before sending the offset calibration command, a zero
input signal must be applied to the ADS1282-HT and the inputs allowed to stabilize. When the command is sent,
the ADS1282-HT averages 16 readings and then writes this value to the OFC register. The contents of the OFC
register may be subsequently read or written. During offset calibration, the full-scale correction is bypassed.
8.5.2.2 GANCAL Command
The GANCAL command performs a gain calibration. Before sending the GANCAL command, a DC input signal
must be applied that is in the range of, but not exceeding, positive or negative full-scale. After the signal has
stabilized, the command can be sent. The ADS1282-HT averages 16 readings, then computes the value that
compensates for the gain error. The gain correction value is then written to the FSC register. The contents of the
GANCAL register may be subsequently read or written. While the gain calibration command corrects for gain
errors greater than 1 (gain correction <1), to avoid input overload, the analog inputs cannot exceed full-scale
range. The gain calibration should be performed after the offset calibration.
VIN
Fully stable input and reference voltage.
Commands
SDATAC
DRDY
SYNC
RDATAC
SDATAC
OFSCAL or
GANCAL
64 Data Periods
RDATAC
16 Data
Periods
Calibration
Complete
SYNC
Figure 61. Offset/Gain Calibration Timing
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8.5.3 User Calibration
System calibration of the ADS1282-HT can be performed without using the calibration commands. This
procedure requires the calibration values to be externally calculated and then written to the calibration registers.
The steps for this procedure are:
1. Set the OFSCAL[2:0] register = 0h and GANCAL[2:0] = 400000h. These values set the offset and gain
registers to 0 and 1, respectively.
2. Apply a zero differential input to the input of the system. Wait for the system to settle and then average n
output readings. Higher numbers of averaged readings result in more consistent calibration. Write the
averaged value to the OFC register.
3. Apply a differential positive or negative DC signal, or an AC signal, less than the full-scale input to the
system. Wait for the system to settle and then average the n output readings.
The value written to the FSC registers is calculated by Equation 12.
DC signal calibration is shown in Equation 12. The expected output code is based on 31-bit output data.
FSC[2:0] = 400000h ´
Expected Output Code
Actual Output Code
(12)
For AC signal calibration, use an RMS value of collected data (as shown in Equation 13).
Expected RMS Value
FSC[2:0] = 400000h ´
Actual RMS Value
(13)
8.5.4 Configuration Guide
After RESET or power-on, the registers can be configured using the following procedure:
1. Reset the serial interface. Before using the serial interface, it may be necessary to recover the serial
interface (undefined I/O power-up sequencing may cause false SCLK detection). To reset the SPI interface,
toggle the RESET pin or, when in Read Data Continuous mode, hold SCLK low for 64 DRDY periods.
2. Configure the registers. The registers are configured by either writing to them individually or as a group.
Software may be configured in either mode. The SDATAC command must be sent before register read/write
operations to cancel the Read Data Continuous mode.
3. Verify register data. The register may be read back for verification of device communications.
4. Set the data mode. After register configuration, the device may be configured for Read Data Continuous
mode, either by the Read Data Continuous command or configured in Read Data By Register mode using
SDATAC command.
5. Synchronize readings. Whenever SYNC is high, the ADS1282-HT freely runs the data conversions. To stop
and re-sync the conversions, take SYNC low and then high.
6. Read data. If the Read Data Continuous mode is active, the data are read directly after DRDY falls by
applying SCLK pulses. If the Read Data Continuous mode is inactive, the data can only be read by Read
Data By Command. The Read Data opcode command must be sent in this mode to read each conversion
result (DRDY only asserts after each read data command is sent).
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8.6 Register Maps
8.6.1 ADS1282-HT Register Map Information
Collectively, the registers contain all the information needed to configure the part, such as data rate, filter
selection, calibration, and so forth. The registers are accessed by the RREG and WREG commands. The
registers can be accessed individually or as a block of registers by sending or receiving consecutive bytes. After
a register write operation the ADC resets, resulting in an interruption of 63 readings.
Table 11. ADS1282-HT Register Map
ADDRESS
REGISTER
RESET
VALUE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
00h
ID
X0h
ID3
ID2
ID1
ID0
0
0
0
0
01h
CONFIG0
52h
SYNC
MODE
DR2
DR1
DR0
PHS
FILTR1
FILTR0
02h
CONFIG1
08h
0
MUX2
MUX1
MUX0
CHOP
PGA2
PGA1
PGA0
03h
HPF0
32h
HPF07
HPF06
HPF05
HPF04
HPF03
HPF02
HPF01
HPF00
04h
HPF1
03h
HPF15
HPF14
HPF13
HPF12
HPF11
HPF10
HPF09
HPF08
05h
OFC0
00h
OFC07
OFC06
OFC05
OFC04
OFC03
OFC02
OFC01
OFC00
06h
OFC1
00h
OFC15
OFC14
OFC13
OFC12
OFC11
OFC10
OFC09
OFC08
07h
OFC2
00h
OFC23
OFC22
OFC21
OFC20
OFC19
OFC18
OFC17
OFC16
08h
FSC0
00h
FSC07
FSC06
FSC05
FSC04
FSC03
FSC02
FSC01
FSC00
09h
FSC1
00h
FSC15
FSC14
FSC13
FSC12
FSC11
FSC10
FSC09
FSC08
0Ah
FSC2
40h
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
BIT 0
8.6.2 ID Register
Figure 62. ID: ID Register (Address 00h)
7
ID3
6
ID2
5
ID1
4
ID0
3
2
1
0
0
0
Reserved
0
0
Reset value = X0h
Table 12. ID Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
ID[3:0]
Factory-programmed identification bits (read-only)
3:0
Reserved
Always write '0'
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8.6.3 Configuration Registers
8.6.3.1 Configuration Register 0
Figure 63. CONFIG0: Configuration Register 0 (Address 01h)
7
SYNC
6
MODE
5
DR2
4
DR1
3
DR0
2
PHASE
1
FILTR1
0
FILTR0
Reset value = 52h
Table 13. Configuration Register 0 Field Descriptions
Bit
Field
7
SYNC
Synchronization mode
0: Pulse SYNC mode (default)
1: Continuous SYNC mode
Reset
Description
6
MODE
1: High-resolution mode (default)
5:3
DR[2:0]
Data Rate Select (1)
000: 250SPS
001: 500SPS
010: 1000SPS (default)
011: 2000SPS
100: 4000SPS
2
PHASE
FIR Phase Response
0: Linear phase (default)
1: Minimum phase
FILTR[1:0]
Digital Filter Select
Digital filter configuration
00: On-chip filter bypassed, modulator output mode
01: Sinc filter block only
10: Sinc + LPF filter blocks (default)
11: Sinc + LPF + HPF filter blocks
1:0
(1)
Type
Sample rate based on 4.096-Mhz clock.
8.6.3.2 Configuration Register 1
Figure 64. CONFIG1: Configuration Register 1 (Address 02h)
7
RSVD
0
6
MUX2
5
MUX1
4
MUX0
3
CHOP
2
PGA2
1
PGA1
0
PGA0
Reset value = 08h
Table 14. Configuration Register 1 Field Descriptions
Bit
Type
Reset
Description
Reserved
Always write '0'
6:4
MUX[2:0]
MUX Select
000: AINP1 and AINN1 (default)
001: AINP2 and AINN2
010: Internal short via 400Ω
011:AINP1 and AINN1 connected to AINP2 and AINN2
100: External short to AINN2
CHOP
PGA Chopping Enable
0: PGA chopping disabled
1: PGA chopping enabled (default)
PGA[2:0]
PGA Gain Select
000: G = 1 (default)
001: G = 2
010: G = 4
011: G = 8
100: G = 16
101: G = 32
110: G = 64
3
2:0
42
Field
7
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8.6.4 HPF1 and HPF0
These two bytes (high-byte and low-byte, respectively) set the corner frequency of the high-pass filter.
8.6.4.1 High-Pass Filter Corner Frequency, Low Byte
Figure 65. HPF0: High-Pass Filter Corner Frequency, Low Byte (Address 03h)
7
HP07
6
HP06
5
HP05
4
HP04
3
HP03
2
HP02
1
HP01
0
HP00
Reset value = 32h
8.6.4.2 High-Pass Filter Corner Frequency, High Byte
Figure 66. HPF1: High-Pass Filter Corner Frequency, High Byte (Address 04h)
7
HP15
6
HP14
5
HP13
4
HP12
3
HP11
2
HP10
1
HP09
0
HP08
1
OC01
0
OC00
1
OC09
0
OC08
1
OC17
0
OC16
Reset value = 03h
8.6.5 OFC2, OFC1, OFC0
These three bytes set the offset calibration value.
8.6.5.1 Offset Calibration, Low Byte
Figure 67. OFC0: Offset Calibration, Low Byte (Address 05h)
7
OC07
6
OC06
5
OC05
4
OC04
3
OC03
2
OC02
Reset value = 00h
8.6.5.2 Offset Calibration, Mid Byte
Figure 68. OFC1: Offset Calibration, Mid Byte (Address 06h)
7
OC15
6
OC14
5
OC13
4
OC12
3
OC11
2
OC10
Reset value = 00h
8.6.5.3 Offset Calibration, High Byte
Figure 69. OFC2: Offset Calibration, High Byte (Address 07h)
7
OC23
6
OC22
5
OC21
4
OC20
3
OC19
2
OC18
Reset value = 00h
8.6.6 FSC2, FSC1, FSC0
These three bytes set the full-scale calibration value.
8.6.6.1 Full-Scale Calibration, Low Byte
Figure 70. FSC0: Full-Scale Calibration, Low Byte (Address 08h)
7
FSC07
6
FSC06
5
FSC05
4
FSC04
3
FSC03
2
FSC02
1
FSC01
0
FSC00
Reset value = 00h
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8.6.6.2 Full-Scale Calibration, Mid Byte
Figure 71. FSC1: Full-Scale Calibration, Mid Byte (Address 09h)
7
FSC15
6
FSC14
5
FSC13
4
FSC12
3
FSC11
2
FSC10
1
FSC09
0
FSC08
Reset value = 00h
8.6.6.3 Full-Scale Calibration, High Byte
Figure 72. FSC2: Full-Scale Calibration, High Byte (Address 0Ah)
7
FSC23
6
FSC22
5
FSC21
4
FSC20
3
FSC19
2
FSC18
1
FSC17
0
FSC16
Reset value = 40h
8.6.7 Offset and Full-Scale Calibration Registers
The conversion data can be scaled for offset and gain before yielding the final output code. As shown in
Figure 74, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the
full-scale register (FSC). Equation 14 shows the scaling:
FSC[2:0]
Final Output Data = (Input - OFC[2:0]) ´
400000h
(14)
The values of the offset and full-scale registers are set by writing to them directly, or they are set automatically
by calibration commands.
The offset and full-scale calibrations apply to specific PGA settings. When the PGA changes, the contents of
these registers may have to be recalculated. Calibration is bypassed in the sinc filter mode.
Standby
ADS1282 Status
Performing One-Shot Conversion
Standby
DRDY
DIN
(1)
STANDBY
STANDBY
WAKEUP
Settled
Data
DOUT
(1) See Figure 49 and for time to new data.
Figure 73. One-Shot Conversions Using the Standby Command
AINP
Modulator
AINN
Digital
Filter
+
S
´
OFC
Register
FSC Register
400000h
-
Output Data
Clipped to 32 Bits
Final Output
Figure 74. Calibration Block Diagram
44
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8.6.7.1 OFC[2:0] Registers
The offset calibration is a 24-bit word, composed of three 8-bit registers, as shown in Table 17. The offset
register is left-justified to align with the 32-bits of conversion data. The offset is in twos complement format with a
maximum positive value of 7FFFFFh and a maximum negative value of 800000h. This value is subtracted from
the conversion data. A register value of 00000h has no offset correction (default value). While the offset
calibration register value can correct offsets ranging from –FS to +FS (as shown in Table 15), to avoid input
overload, the analog inputs cannot exceed the full-scale range.
Table 15. Offset Calibration Values
FINAL OUTPUT CODE (1)
OFC REGISTER
(1)
7FFFFFh
80000000h
000001h
FFFFFF00h
000000h
00000000h
FFFFFFh
00000100h
800000h
7FFFFF00h
Full 32-bit final output code with zero code input.
8.6.7.2 FSC[2:0] Registers
The full-scale calibration is a 24-bit word, composed of three 8-bit registers, as shown in Table 18. The full-scale
calibration value is 24-bit, straight offset binary, normalized to 1 at code 400000h. Table 16 summarizes the
scaling of the full-scale register. A register value of 400000h (default value) has no gain correction (gain = 1).
While the gain calibration register value corrects gain errors greater than 1 (gain correction <1), the full-scale
range of the analog inputs cannot be exceeded to avoid input overload.
Table 16. Full-Scale Calibration Register Values
FSC REGISTER
GAIN CORRECTION
800000h
2
400000h
1
200000h
0.5
000000h
0
Table 17. Offset Calibration Word
REGISTER
BYTE
OFC0
LSB
7
6
5
4
BIT ORDER
3
2
1
OFC1
MID
15
14
13
12
11
10
9
8
OFC2
MSB
23 (MSB)
22
21
20
19
18
17
16
0 (LSB)
0 (LSB)
Table 18. Full-Scale Calibration Word
REGISTER
BYTE
FSC0
LSB
7
6
5
4
BIT ORDER
3
2
1
FSC1
MID
15
14
13
12
11
10
9
8
FSC2
MSB
23 (MSB)
22
21
20
19
18
17
16
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ADS1282-HT is a very-high-resolution ADC. Optimal performance requires giving special attention to the
support circuitry and PCB design. Locate noisy digital components, such as microcontrollers, oscillators, and so
forth, in an area of the PCB away from the converter or front-end components. Locating the digital components
close to the power-entry point keeps the digital current path short and separate from sensitive analog
components.
9.2 Typical Application
9.2.1 Geophone Interface Typical Application
Figure 75 shows a typical geophone front-end application. The application shows the ADS1282-HT operation
with dual ±2.5-V analog supplies. The ADS1282-HT can also operate with a single 5-V analog supply.
+2.5V
15
+2.5V
Test
Source
-2.5V
19
20
AVDD
AVSS
AINP2
16
AINN2
R1
100W
Geophone
R3
100W
17
C2
1nF, COG
R5
20kW
R6
20kW
(2)
R2
100W
C3
1nF, COG
AINP1
C4
10nF
COG
R4
100W
18
AINN1
ADS1282
-2.5V
R8
(1)
75kW
+6.5V
(+2.8V REF5050)
1 mF
14
C6
10nF
COG 13
CAPN
R9
R7
1kW
REF02
(REF5050)
CAPP
(1)
75kW
22
VREFP
1mF
+
C5
100mF
C7
0.1mF
21
-2.5V
VREFN
DGND
6, 12, 25, 27
(1) Optional 20-mV offset. Match to 0.1% to maintain CMR.
Figure 75. Geophone Interface Application
46
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Typical Application (continued)
9.2.1.1 Detailed Design Procedure
The geophone input signal is filtered both differentially, by components C4 and R1 to R4 and filtered
independently by components C2, C3 and R1, R2. The differential filter removes high-frequency normal mode
components from the input signal. The independent filters remove high-frequency components that are common
to both input signals leads (common-mode filter). The recommended input filters may not be required for all
applications depending on the system requirements.
Resistors R5 and R6 bias the signals inputs to midsupply (ground), and also provide the bias current return path
for the ADS1282-HT inputs. For single-supply operation, set the bias to a low impedance 2.5 V (AVDD/2).
Resistors R5 and R6 can also influence common-mode attenuation. To maintain good CMR performance,
resistors R5 and R6 may require matching.
Diode clamps protect the ADS1282-HT inputs from voltage transients and overloads.
The REF02 5-V reference provides the reference to the ADS1282-HT. The reference output is filtered by the
optional R7 and C5 filter network. The filter requires several seconds to settle after power-on. Capacitor C7
provides high-frequency bypassing of the reference inputs and should be placed close to the ADS1282-HT pins.
R7 (1-kΩ) results in a systematic gain error (–1.2%).
Alternatively, the REF5050 (5-V) or REF5045 (4.5-V) reference can be used. The REF5045 reference has the
advantage of operating from the 5-V power supply. The REF5050 requires 5.2-V minimum power supply.
Optional components R8, and R9 provides a 20mV offset to the ADS1282-HT. The internal 300-Ω resistors form a
voltage divider with the external resistors to provide the offset. The offset moves the low level idle tones out of
the passband. The offset is independent of the PGA setting. To maintain good CMR performance, R10 and R11
should be matched to 0.1%, and the traces routed back directly to the reference.
Capacitor C6 (10-nF) filters the PGA output glitches caused by sampling of the modulator. The capacitor also
forms a low-pass filter on the input signal with a cut-off frequency ≉ 25 kHz.
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Typical Application (continued)
9.2.2 Digital Connection to a Field Programmable Gate Array (FPGA) Device Typical Application
Figure 76 shows the digital connection to a field programmable gate array (FPGA) device. In this example, two
ADS1282-HT devices are shown connected. The DRDY output from each ADS1282-HT device can be used;
however, when the devices are synchronized, the DRDY output from only one device is sufficient. A shared
SCLK line between the devices is optional.
4.096-MHz Clock
47 W
+3.3 V
26
(1)
DVDD
CLK
ADS1282
1 mF
RESET
28
BYPAS
DOUT
DIN
1 mF
SCLK
SYNC
DGND
MFLAG
1
47 W
24
4
RESET
47 W
DOUT1
47 W
5
CLK Input
DIN1
47 W
2
SCLK1
47 W
10
SYNC
47 W
11
MFLAG1
6, 12, 25, 27
+3.3 V
26
(1)
DVDD
CLK
ADS1282
1 mF
RESET
28
BYPAS
DOUT
DIN
1 mF
SCLK
SYNC
MFLAG
DGND
DRDY
1
FPGA
24
4
47 W
DOUT2
5
DIN2
2
SCLK2
47 W
10
47 W
11
3
47 W
MFLAG2
DRDY
6, 12, 25, 27
NOTE: Dashed line is optional.
(1) For DVDD < 2.25 V, see the Power Supply Recommendations.
Figure 76. Microcontroller Interface With Dual ADS1282-HTs
9.2.2.1 Detailed Design Procedure
The modulator over-range flag (MFLAG) from each device ties to the FPGA. For synchronization, one SYNC
control line connects all ADS1282-HT devices. The RESET line also connects to all ADS1282-HT devices.
For best performance, the FPGA and the ADS1282-HTs should operate from the same clock. Avoid ringing on
the digital inputs. 47-Ω resistors in series with the digital traces can help to reduce ringing by controlling
impedances. Place the resistors at the source (driver) end of the trace. Unused digital inputs should not float; use
pullups or pulldowns to DVDD or GND. This includes the modulator data pins, M0, M1, and MCLK.
10 Power Supply Recommendations
The DVDD power supply operates over the range of 1.75 to 3.6 V. If DVDD is operated at less than 2.25 V,
connect the DVDD pin to the BYPAS pin. If DVDD is greater than or equal to 2.25 V, do not connect DVDD to
the BYPAS pin. Figure 77 shows this connection.
48
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1.75 V to 3.6 V
DVDD
Tie DVDD to BYPAS if
DVDD power is < 2.25 V.
Otherwise float BYPAS.
ADS1282
BYPAS
1 μF
Figure 77. DVDD Power
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11 Device and Documentation Support
11.1 Device Support
Table 19. FIR Stage Coefficients
SECTION 1
COEFFICIENT
b0
–10944
SECTION 3
SECTION 4
SCALING = 134217728
SCALING = 1 / 8388608
–774
SCALING = 134217728
LINEAR PHASE
MINIMUM PHASE
LINEAR PHASE
MINIMUM PHASE
–73
819
–132
11767
133882
b1
0
0
–874
8211
–432
b2
103807
8994
–4648
44880
–75
769961
b3
0
0
–16147
174712
2481
2940447
b4
–507903
–51663
–41280
536821
6692
8262605
b5
0
0
–80934
1372637
7419
17902757
b6
2512192
199523
–120064
3012996
–266
30428735
b7
4194304
0
–118690
5788605
–10663
40215494
b8
2512192
–629120
–18203
9852286
–8280
39260213
b9
0
0
224751
14957445
10620
23325925
b10
–507903
2570188
580196
20301435
22008
–1757787
b11
0
4194304
893263
24569234
348
–21028126
b12
103807
2570188
891396
26260385
–34123
–21293602
b13
0
0
293598
24247577
–25549
–3886901
b14
–10944
–629120
–987253
18356231
33460
14396783
b15
0
–2635779
9668991
61387
16314388
b16
199523
–3860322
327749
–7546
1518875
b17
0
–3572512
–7171917
–94192
–12979500
b18
–51663
–822573
–10926627
–50629
–11506007
b19
0
4669054
–10379094
101135
2769794
b20
8994
12153698
–6505618
134826
12195551
b21
0
19911100
–1333678
–56626
6103823
b22
–774
25779390
2972773
–220104
–6709466
27966862
5006366
–56082
–9882714
4566808
263758
–353347
2505652
231231
8629331
126331
–215231
5597927
b27
–1496514
–430178
–4389168
b28
–1933830
34715
–7594158
b29
–1410695
580424
–428064
b30
–502731
283878
6566217
b31
245330
–588382
4024593
b32
565174
–693209
–3679749
b33
492084
366118
–5572954
b34
231656
1084786
332589
5136333
b23
b24
b25
b26
50
SECTION 2
Only half shown;
symmetric starting
with b22.
b35
–9196
132893
b36
–125456
–1300087
2351253
b37
–122207
–878642
–3357202
b38
–61813
1162189
–3767666
b39
–4445
1741565
1087392
b40
22484
–522533
3847821
b41
22245
–2490395
919792
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Device Support (continued)
Table 19. FIR Stage Coefficients (continued)
SECTION 1
COEFFICIENT
SECTION 2
SCALING = 1 / 8388608
SECTION 3
SECTION 4
SCALING = 134217728
SCALING = 134217728
MINIMUM PHASE
LINEAR PHASE
MINIMUM PHASE
b42
LINEAR PHASE
10775
–688945
–2918303
b43
940
2811738
–2193542
b44
–2953
2425494
1493873
b45
–2599
–2338095
2595051
b46
–1052
–4511116
–79991
b47
–43
641555
–2260106
b48
214
6661730
–963855
b49
132
2950811
1482337
b50
33
–8538057
1480417
b51
–10537298
–586408
b52
9818477
–1497356
b53
41426374
–168417
b54
56835776
1166800
b55
Only half shown;
symmetric starting
with b53.
–675082
b56
b57
644405
–806095
b58
211391
b59
740896
b60
141976
b61
–527673
b62
–327618
b63
278227
b64
363809
b65
–70646
b66
–304819
b67
–63159
b68
205798
b69
124363
b70
–107173
b71
–131357
b72
31104
b73
107182
b74
15644
b75
–71728
b76
–36319
b77
38331
b78
38783
b79
–13557
b80
–31453
b81
–1230
b82
20983
b83
7729
b84
–11463
b85
–8791
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Device Support (continued)
Table 19. FIR Stage Coefficients (continued)
SECTION 1
COEFFICIENT
SECTION 2
SCALING = 1 / 8388608
SECTION 3
SECTION 4
SCALING = 134217728
SCALING = 134217728
LINEAR PHASE
MINIMUM PHASE
LINEAR PHASE
MINIMUM PHASE
b86
4659
b87
7126
b88
–732
b89
–4687
b90
–976
b91
2551
b92
1339
b93
–1103
b94
–1085
b95
314
b96
681
b97
16
b98
–349
b99
–96
b100
144
b101
78
b102
–46
b103
–42
b104
9
b105
16
b106
0
b107
–4
1+
1-2
cos wN + sin wN - 1
cos wN
HPF Gain =
2-
cos wN + sin wN - 1
cos wN
(15)
See HPF Stage for an example of how to use this equation.
11.1.1 HPF Transfer Function
-1
2-a
1-Z
´
HPF(Z) =
-1
1 - bZ
2
(16)
where b is calculated as shown in Equation 17:
2 2
b=
52
(1 + (1 - a) )
2
(17)
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Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: ADS1282-HT
ADS1282-HT
www.ti.com
SBAS446H – DECEMBER 2009 – REVISED FEBRUARY 2016
Table 20. tDR Time for Data Ready (Sinc Filter)
(1)
ƒDATA
ƒCLK (1)
128k
440
64k
616
32k
968
16k
1672
8k
2824
For SYNC and Wake-Up commands, ƒCLK = number of CLK cycles
from next rising CLK edge directly after eighth rising SCLK edge to
DRDY falling edge. For Wake-Up command only, subtract two ƒCLK
cycles.
Table 20 is referenced by Pulse-Sync Timing Requirements.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: ADS1282-HT
53
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS1282HPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 175
ADS1282H
ADS1282SJDJ
ACTIVE
CDIP SB
JDJ
28
1
TBD
Call TI
N / A for Pkg Type
-55 to 210
ADS1282SJDJ
ADS1282SKGDA
ACTIVE
XCEPT
KGD
0
80
Green (RoHS
& no Sb/Br)
Call TI
N / A for Pkg Type
-55 to 210
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS1282-HT :
• Catalog: ADS1282
• Space: ADS1282-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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