Texas Instruments | SM470R1B1M-HT 16-/32-Bit RISC Flash Microcontroller (Rev. I) | Datasheet | Texas Instruments SM470R1B1M-HT 16-/32-Bit RISC Flash Microcontroller (Rev. I) Datasheet

Texas Instruments SM470R1B1M-HT 16-/32-Bit RISC Flash Microcontroller (Rev. I) Datasheet
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SM470R1B1M-HT
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
SM470R1B1M-HT 16-/32-Bit RISC Flash Microcontroller
1 Device Overview
1.1
Features
1
• High-Performance Static CMOS Technology
• SM470R1x 16-/32-Bit RISC Core ( ARM7TDMI™)
– 60-MHz System Clock (Pipeline Mode)
– Independent 16-/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
• Integrated Memory
– 1MB Program Flash
• Two Banks With 16 Contiguous Sectors
– 64KB Static RAM (SRAM)
– Memory Security Module (MSM)
– JTAG Security Module
• Operating Features
– Low-Power Modes: STANDBY and HALT
– Industrial Temperature Range
• 470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory/Peripherals
– Digital Watchdog (DWD) Timer
– Analog Watchdog (AWD) Timer
– Enhanced Real-Time Interrupt (RTI)
– Interrupt Expansion Module (IEM)
– System Integrity and Failure Detection
– ICE Breaker
• Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
• Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock
Module With Prescaler
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
• Twelve Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
– Three Serial Communication Interfaces (SCIs)
• 224 Selectable Baud Rates
• Asynchronous/Isosynchronous Modes
•
•
•
•
•
•
•
•
•
(1)
– Two High-End CAN Controllers (HECC)
• 32-Mailbox Capacity
• Fully Compliant With CAN Protocol, Version
2.0B
– Five Inter-Integrated Circuit (I2C) Modules
• Multi-Master and Slave Interfaces
• Up to 400 Kbps (Fast Mode)
• 7- and 10-Bit Address Capability
High-End Timer Lite (HET)
– 12 Programmable I/O Channels:
• 12 High-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
• 64-Instruction Capacity
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External Clock
(CLK)
12-Channel, 10-Bit Multi-Buffered ADC (MibADC)
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55-µs Minimum Sample and Conversion Time
– Calibration Mode and Self-Test Features
Flexible Interrupt Handling
Expansion Bus Module (EBM)
– Supports 8- and 16-Bit Expansion Bus Memory
Interface Mappings
– 42 I/O Expansion Bus Pins
46 Dedicated General-Purpose I/O (GIO) Pins and
47 Additional Peripheral I/Os
Sixteen External Interrupts
On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1 (1) (JTAG) Test-Access Port
Available in KGD, HFQ, HKP, and PGE Packages
The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture specification. Boundary scan is not
supported on this device.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SM470R1B1M-HT
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
1.2
•
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Applications
Supports Extreme Temperature Applications:
– Controlled Baseline
– One Assembly/Test Site
– One Fabrication Site
– Available in Extreme (–55°C to 220°C)
Temperature Range (2)
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
– Texas Instruments' high temperature products
use highly optimized silicon (die) solutions with
design and process enhancements to
maximize performance over extended
temperatures.
(2)
1.3
Custom temperature ranges available
Description
The SM470R1B1M (3) devices are members of the Texas Instruments SM470R1x family of generalpurpose 16-/32-bit reduced instruction set computer (RISC) microcontrollers. The B1M microcontroller
offers high performance using the high-speed ARM7TDMI 16-/32-bit RISC central processing unit (CPU),
resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The
SM470R1B1M uses the big-endian format where the most significant byte of a word is stored at the lowest
numbered byte and the least significant byte of a word is stored at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while
maintaining low costs. The B1M RISC core architecture offers solutions to these performance and cost
demands while maintaining low power consumption.
The B1M devices contain the following:
• ARM7TDMI 16-/32-bit RISC CPU
• SM470R1x system module (SYS) with 470+ enhancements
• 1MB flash
• 64KB SRAM
• ZPLL clock module
• DWD timer
• AWD timer
• Enhanced RTI module
• IEM
• MSM
• JTAG security module
• Two SPI modules
• Three SCI modules
• Two HECC
• Five I2C modules
• 10-bit MibADC, with 12 input channels
• HET controlling 12 I/Os
• ECP
(3)
2
Throughout the remainder of this document, the SM470R1B1M will be referred to as either the full device name or as B1M.
Device Overview
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•
•
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
EBM
Up to 93 I/O pins
The functions performed by the 470+ system module (SYS) include:
• Address decoding
• Memory protection
• Memory and peripherals bus supervision
• Reset and abort exception management
• Prioritization for all internal interrupt sources
• Device clock control
• Parallel signature analysis (PSA)
The enhanced RTI module on the B1M has the option to be driven by the oscillator clock. The DWD is a
25-bit resettable decrementing counter that provides a system reset when the watchdog counter expires.
This data sheet includes device-specific information such as memory and peripheral select assignment,
interrupt priority, and a device memory map. For a more detailed functional description of the SYS
module, see the TMS470R1x System Module Reference Guide (SPNU189).
The B1M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory
implemented with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up
to 24 MHz or 30 MHz, depending on the input voltage. When in pipeline mode, the flash operates with a
system clock frequency of up to 48 MHz or 60 MHz, depending on the input voltage. For more detailed
information on the flash, see Section 8.2.1.4.
The MSM and the JTAG security module prevent unauthorized access and visibility to on-chip memory,
thereby preventing reverse engineering or manipulation of proprietary code.
The B1M device has twelve communication interfaces: two SPIs, three SCIs, two HECCs, and five I2Cs.
The SPI provides a convenient method of serial interaction for high-speed communications between
similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous
communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ)
format. The HECC uses a serial, multimaster communication protocol that efficiently supports distributed
realtime control with robust communication rates of up to 1 Mbps. These CAN peripherals are ideal for
applications operating in noisy and harsh environments (for example, industrial fields) that require reliable
serial communication or multiplexed wiring. The I2C module is a multimaster communication module
providing an interface between the B1M microcontroller and an I2C-compatible device through the I2C
serial bus. The I2C supports both 100 Kbps and 400 Kbps speeds. For more detailed functional
information on the SPI, SCI, and CAN peripherals, see the specific reference guides (SPNU195,
SPNU196, and SPNU197). For more detailed functional information on the I2C, see the TMS470R1x InterIntegrated Circuit (I2C) Reference Guide (SPNU223).
The HET is an advanced intelligent timer that provides sophisticated timing functions for realtime
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose
I/O. It is especially well-suited for applications requiring multiple sensor information and drive actuators
with complex and accurate time pulses. The HET used in this device is the high-end timer lite. It has fewer
I/Os than the usual 32 in a standard HET. For more detailed functional information on the HET, see the
TMS470R1x High-End Timer (HET) Reference Guide (SPNU199).
The B1M HET peripheral contains the XOR-share feature. This feature allows two adjacent HET highresolution channels to be XORed together, making it possible to output smaller pulses than a standard
HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer
(HET) Reference Guide (SPNU199).
Device Overview
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The B1M device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can
be converted individually or can be grouped by software for sequential conversion sequences. There are
three separate groupings, two of which can be triggered by an external event. Each sequence can be
converted once when triggered or configured for continuous conversion mode. For more detailed
functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter
(MibADC) Reference Guide (SPNU206).
The ZPLL clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a
prescaler (with prescale values of 1 to 8). The function of the ZPLL is to multiply the external frequency
reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module.
The SYS module subsequently provides system clock (SYSCLK), realtime interrupt clock (RTICLK), CPU
clock (MCLK), and peripheral interface clock (ICLK) to all other B1M device modules. For more detailed
functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock
Module Reference Guide (SPNU212).
NOTE
ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the
continuous system clock from an external resonator/crystal reference.
The EBM is a standalone module that supports the multiplexing of the GIO functions and the expansion
bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module (EBM)
Reference Guide (SPNU222).
The B1M device also has an external clock prescaler (ECP) module that when enabled, outputs a
continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable
ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the
ECP, see the TMS470R1x External Clock Prescaler (ECP) Reference Guide (SPNU202).
Table 1-1. Device Information(1)
PART NUMBER
PACKAGE
TA
KGD (0)
SM470R1B1M-HT
CFP (TBAR) (84)
LQFP (144)
4
–55°C to 220°C
CFP (84)
Device Overview
–55°C to 150°C
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(1) For more information, see Section 10, Mechanical Packaging and Orderable Information.
Functional Block Diagram
External
Pins
External
Pins
FLASH
(1M Byte)
2 Banks
16 Sectors
VCCP
FLTP2
OSCIN
Memory
Security
Module
(MSM)
RAM
(64K Bytes)
ZPLL
OSCOUT
Crystal
1.4
PLLDIS
ADIN[11:0]
CPU Address Data Bus
MibADC
64−Word
FIFO
TRST
ADEVT
ADREFHI
ADREFLO
VCCAD
TCK
SM470R1x CPU
VSSAD
TDI
TDO
HET
64 Words
Expansion Address/Data Bus
ICE Breaker
TMS
TMS2
RST
SM470R1x System Module
with Enhanced RTI Module(A)
AWD
TEST
PORRST
CLKOUT
DMA Controller
16 Channels
Interrupt Expansion
Module (IEM)
SCC
I2C4SDA
Digital
Watchdog
(DWD)
I2C4
I2C4SCL
Analog
Watchdog
(AWD)
HECC1
HECC2
HET[0:8;18,20,22]
CAN1HTX
CAN1HRX
CAN2HTX
CAN2SRX
SCI1CLK
SCI1
SCI1TX
SCI1RX
SCI2CLK
SCI2
SCI2TX
SCI2RX
I2C5SDA
I2C5
I2C5SCL
I2C3
I2C2
SCI3
SPI2
SPI1
ECP
GIO/EBM
I2C3SCL
I2C2SDA
I2C2SCL
I2C1SDA
I2C1SCL
GIOH[5,0]
GIOF[7:0]
GIOG[7:0]
GIOD[5:0]
GIOE[7:0]/INT[15:8]
GIOB[0]
GIOC[4:0]
GIOA[0]/INT[0]
GIOA[7:2]/INT[7:2]
GIOA[1]/INT[1]/ECLK
SPI1CLK
SPI1SIMO
SPI1SOMI
SPI1SCS
SPI1ENA
SPI2CLK
SPI2SIMO
SPI2SOMI
SPI2SCS
SPI2ENA
SCI3CLK
SCI3TX
SCI3RX
I2C1
I2C3SDA
The enhanced RTI module is the system module with two extra bits to disable the ZPLL while in STANDBY mode.
Device Overview
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Table of Contents
1
2
3
4
Device Overview ......................................... 1
1.1
Features .............................................. 1
1.2
Applications ........................................... 2
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 5
6
Bare Die Information ................................ 10
Pin Configuration and Functions ................... 15
5.1
Features ............................................. 17
5.2
Pin Functions (HFQ/HKP Package)................. 18
5.3
Pin Functions (PGE Package) ...................... 23
7
8
6.1
Absolute Maximum Ratings ......................... 30
6.2
........................................
Recommended Operating Conditions ..............
Electrical Characteristics ............................
Thermal Characteristics .............................
ZPLL and Clock Specifications .....................
RST and PORRST Timings .........................
JTAG Scan Interface Timing ........................
Output Timings ......................................
Input Timings ........................................
Flash Timings .......................................
SPIn Master Mode Timing Parameters .............
ESD Ratings
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
9
SPIn Slave Mode Timing Parameters............... 42
SCIN Isosynchronous Mode Timings - Internal
Clock ................................................ 45
SCIN Isosynchronous Mode Timings - External
Clock ................................................ 46
6.16
I2C Timing ........................................... 47
6.17
Standard Can Controller (SCC) Mode Timings ..... 48
6.18
Expansion Bus Module Timing ...................... 49
6.19
Multi-Buffered A-to-D Converter (MibADC) ......... 51
Parameter Measurement Information .............. 55
7.1
Specifications ........................................... 30
6.3
6
6.15
Revision History ......................................... 7
Device Characteristics .................................. 9
Bare Die .................................................. 10
4.1
5
6.13
6.14
External Reference Resonator/Crystal Oscillator
Clock Option ........................................ 55
Detailed Description ................................... 56
............................................
8.1
Overview
8.2
Memory .............................................. 61
56
Device and Documentation Support ............... 68
30
9.1
Device Support ...................................... 68
30
9.2
Development Support ............................... 69
31
9.3
Device Nomenclature ............................... 69
32
9.4
Documentation Support ............................. 71
34
9.5
Community Resources .............................. 71
36
9.6
Trademarks.......................................... 71
37
9.7
Electrostatic Discharge Caution ..................... 72
38
9.8
Glossary ............................................. 72
39
39
40
10 Mechanical Packaging and Orderable
Information .............................................. 73
10.1
Packaging Information
Table of Contents
..............................
73
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (September 2013) to Revision I
•
•
Page
Added ESD Ratings table, Detailed Description section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................... 1
Updated ICC standby mode maximum from 1.3 mA to to 28 mA ............................................................. 32
Revision History
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Changes from Revision G (July 2013) to Revision H
•
•
8
Page
Changed temperature range condition on Electrical Characteristics table .................................................. 31
Added Thermal Information table ................................................................................................. 32
Revision History
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3 Device Characteristics
CHARACTERISTICS (1)
DEVICE DESCRIPTION
SM470R1B1M
COMMENTS
MEMORY
For the number of memory selects on this device, see Table 8-5, SM470R1B1M Memory Selection Assignment.
Pipeline/non-pipeline
INTERNAL MEMORY
1MB flash
64KB SRAM
MSM
JTAG security module
Flash is pipeline-capable.
The B1M RAM is implemented in one 64K array selected by two
memory-select signals (see Table 8-5, SM470R1B1M Memory
Selection Assignment ).
PERIPHERALS
For the device-specific interrupt priority configurations, see Table 8-2, Interrupt Priority. And for the 1K peripheral address ranges and their
peripheral selects, see Table 8-7, B1M Peripherals, System Module, and Flash Base Addresses.
CLOCK
Expansion bus
ZPLL
Zero-pin PLL has no external loop filter pins.
EBM
Expansion bus module with 42 pins. Supports 8- and 16-bit
memories. See Table 8-3 for details.
46 I/O
Port A has 8 external pins.
Port B has only 1 external pin.
Port C has 5 external pins.
Port D has 6 external pins.
Ports E, F, and G each have 8 external pins.
Port H has 2 external pins.
GENERAL-PURPOSE I/Os
(1)
ECP
Yes
SCI
3 (3 pin)
CAN (HECC and/or SCC)
2 HECC
SPI (5-pin, 4-pin, or 3-pin)
2 (5 pin)
I2C
5
HET with XOR share
12 I/O
HET RAM
64-instruction capacity
MibADC
10-bit, 12-channel
64-word FIFO
CORE VOLTAGE
1.8 V
I/O VOLTAGE
3.3 V
PINS
84 or 144
PACKAGES
HFQ, HKP, or PGE
Two HECC
The high-resolution (HR) SHARE feature allows even-numbered HR
pins to share the next higher odd-numbered HR pin structures. This
HR sharing is independent of whether or not the odd pin is available
externally. If an odd pin is available externally and shared, then the
odd pin can only be used as a general-purpose I/O. For more
information on HR SHARE, see the TMS470R1x High-End Timer
(HET) Reference Guide (SPNU199).
Both the logic and registers for a full 16-channel MibADC are
present.
This table identifies all the characteristics of the B1M device except the SYSTEM and CPU, which are generic.
Device Characteristics
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4 Bare Die
4.1
Bare Die Information
DIE SIZE
DIE PAD SIZE
DIE PAD
COORDINATES (1)
DIE
THICKNESS
DIE PAD
COMPOSITION
BACKSIDE
FINISH
BACKSIDE
POTENTIAL
208.858 × 211.890 mils/
5304.99 × 5382.01 µm
65.1 × 65.1 (µm)
See Table 4-1
11 mils
AlCu
Silicon with
backgrind
Ground
(1)
10
Pads 12, 22, 26, 136, 143, 146, 149 and 152 are test pads, no connections required. It is highly recommended to leave them open.
Bare Die
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Table 4-1. Bond Pad Coordinates
PAD NO.
BOND PAD COORDINATES (µm)
PAD SIZE (µm)
X MIN
Y MIN
X MAX
Y MAX
X
Y
1
178.955
10.08
244.055
75.18
65.1
65.1
2
368.2
10.08
433.3
75.18
65.1
65.1
3
557.445
10.08
622.545
75.18
65.1
65.1
4
664.335
10.08
729.435
75.18
65.1
65.1
5
853.58
10.08
918.68
75.18
65.1
65.1
6
1042.825
10.08
1107.925
75.18
65.1
65.1
7
1149.715
10.08
1214.815
75.18
65.1
65.1
8
1338.96
10.08
1404.06
75.18
65.1
65.1
9
1445.85
10.08
1510.95
75.18
65.1
65.1
10
1552.74
10.08
1617.84
75.18
65.1
65.1
11
1659.63
10.08
1724.73
75.18
65.1
65.1
12
1766.52
10.08
1831.62
75.18
65.1
65.1
13
1866.2
10.08
1931.3
75.18
65.1
65.1
14
1965.88
10.08
2030.98
75.18
65.1
65.1
15
2065.56
10.08
2130.66
75.18
65.1
65.1
16
2165.24
10.08
2230.34
75.18
65.1
65.1
17
2272.13
10.08
2337.23
75.18
65.1
65.1
18
2396.1
10.08
2461.2
75.18
65.1
65.1
19
2520.07
10.08
2585.17
75.18
65.1
65.1
20
2626.96
10.08
2692.06
75.18
65.1
65.1
21
2733.85
10.08
2798.95
75.18
65.1
65.1
22
2840.74
10.08
2905.84
75.18
65.1
65.1
23
2947.63
10.08
3012.73
75.18
65.1
65.1
24
3054.52
10.08
3119.62
75.18
65.1
65.1
25
3243.765
10.08
3308.865
75.18
65.1
65.1
26
3350.655
10.08
3415.755
75.18
65.1
65.1
27
3539.9
10.08
3605
75.18
65.1
65.1
28
3646.79
10.08
3711.89
75.18
65.1
65.1
29
3746.47
10.08
3811.57
75.18
65.1
65.1
30
3846.15
10.08
3911.25
75.18
65.1
65.1
31
3953.04
10.08
4018.14
75.18
65.1
65.1
32
4142.285
10.08
4207.385
75.18
65.1
65.1
33
4331.53
10.08
4396.63
75.18
65.1
65.1
34
4431.21
10.08
4496.31
75.18
65.1
65.1
35
4530.89
10.08
4595.99
75.18
65.1
65.1
36
4630.57
10.08
4695.67
75.18
65.1
65.1
37
4730.25
10.08
4795.35
75.18
65.1
65.1
38
4829.93
10.08
4895.03
75.18
65.1
65.1
39
4936.82
10.08
5001.92
75.18
65.1
65.1
40
5150.04
178.955
5215.14
244.055
65.1
65.1
41
5150.04
368.2
5215.14
433.3
65.1
65.1
42
5150.04
557.445
5215.14
622.545
65.1
65.1
43
5150.04
666.26
5215.14
731.36
65.1
65.1
44
5150.04
855.505
5215.14
920.605
65.1
65.1
45
5150.04
1044.75
5215.14
1109.85
65.1
65.1
46
5150.04
1153.565
5215.14
1218.665
65.1
65.1
Bare Die
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SM470R1B1M-HT
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
www.ti.com
Table 4-1. Bond Pad Coordinates (continued)
PAD NO.
12
BOND PAD COORDINATES (µm)
X MIN
Y MIN
X MAX
PAD SIZE (µm)
Y MAX
X
Y
47
5150.04
1262.38
5215.14
1327.48
65.1
65.1
48
5150.04
1371.195
5215.14
1436.295
65.1
65.1
49
5150.04
1480.01
5215.14
1545.11
65.1
65.1
50
5150.04
1669.255
5215.14
1734.355
65.1
65.1
51
5150.04
1778.07
5215.14
1843.17
65.1
65.1
52
5150.04
1886.885
5215.14
1951.985
65.1
65.1
53
5150.04
1995.7
5215.14
2060.8
65.1
65.1
54
5150.04
2184.945
5215.14
2250.045
65.1
65.1
55
5150.04
2293.76
5215.14
2358.86
65.1
65.1
56
5150.04
2402.575
5215.14
2467.675
65.1
65.1
57
5150.04
2511.39
5215.14
2576.49
65.1
65.1
58
5150.04
2700.635
5215.14
2765.735
65.1
65.1
59
5150.04
2809.45
5215.14
2874.55
65.1
65.1
60
5150.04
2998.695
5215.14
3063.795
65.1
65.1
61
5150.04
3187.94
5215.14
3253.04
65.1
65.1
62
5150.04
3296.755
5215.14
3361.855
65.1
65.1
63
5150.04
3486
5215.14
3551.1
65.1
65.1
64
5150.04
3675.245
5215.14
3740.345
65.1
65.1
65
5150.04
3784.06
5215.14
3849.16
65.1
65.1
66
5150.04
3973.305
5215.14
4038.405
65.1
65.1
67
5150.04
4082.12
5215.14
4147.22
65.1
65.1
68
5150.04
4190.935
5215.14
4256.035
65.1
65.1
69
5150.04
4299.75
5215.14
4364.85
65.1
65.1
70
5150.04
4408.565
5215.14
4473.665
65.1
65.1
71
5150.04
4517.38
5215.14
4582.48
65.1
65.1
72
5150.04
4626.195
5215.14
4691.295
65.1
65.1
73
5150.04
4735.01
5215.14
4800.11
65.1
65.1
74
5150.04
4843.825
5215.14
4908.925
65.1
65.1
75
5150.04
4952.64
5215.14
5017.74
65.1
65.1
76
4981.165
5148.85
5046.265
5213.95
65.1
65.1
77
4862.935
5148.85
4928.035
5213.95
65.1
65.1
78
4738.965
5148.85
4804.065
5213.95
65.1
65.1
79
4614.995
5148.85
4680.095
5213.95
65.1
65.1
80
4496.765
5148.85
4561.865
5213.95
65.1
65.1
81
4378.535
5148.85
4443.635
5213.95
65.1
65.1
82
4189.29
5148.85
4254.39
5213.95
65.1
65.1
83
4000.045
5148.85
4065.145
5213.95
65.1
65.1
84
3881.815
5148.85
3946.915
5213.95
65.1
65.1
85
3757.845
5148.85
3822.945
5213.95
65.1
65.1
86
3639.615
5148.85
3704.715
5213.95
65.1
65.1
87
3450.37
5148.85
3515.47
5213.95
65.1
65.1
88
3332.14
5148.85
3397.24
5213.95
65.1
65.1
89
3213.91
5148.85
3279.01
5213.95
65.1
65.1
90
3095.68
5148.85
3160.78
5213.95
65.1
65.1
91
2906.435
5148.85
2971.535
5213.95
65.1
65.1
92
2717.19
5148.85
2782.29
5213.95
65.1
65.1
Bare Die
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
Table 4-1. Bond Pad Coordinates (continued)
PAD NO.
BOND PAD COORDINATES (µm)
PAD SIZE (µm)
X MIN
Y MIN
X MAX
Y MAX
X
Y
93
2598.96
5148.85
2664.06
5213.95
65.1
65.1
94
2480.73
5148.85
2545.83
5213.95
65.1
65.1
95
2362.5
5148.85
2427.6
5213.95
65.1
65.1
96
2244.27
5148.85
2309.37
5213.95
65.1
65.1
97
2126.04
5148.85
2191.14
5213.95
65.1
65.1
98
1936.795
5148.85
2001.895
5213.95
65.1
65.1
99
1747.55
5148.85
1812.65
5213.95
65.1
65.1
100
1629.32
5148.85
1694.42
5213.95
65.1
65.1
101
1511.09
5148.85
1576.19
5213.95
65.1
65.1
102
1321.845
5148.85
1386.945
5213.95
65.1
65.1
103
1203.615
5148.85
1268.715
5213.95
65.1
65.1
104
1085.385
5148.85
1150.485
5213.95
65.1
65.1
105
967.155
5148.85
1032.255
5213.95
65.1
65.1
106
843.185
5148.85
908.285
5213.95
65.1
65.1
107
719.215
5148.85
784.315
5213.95
65.1
65.1
108
595.245
5148.85
660.345
5213.95
65.1
65.1
109
471.275
5148.85
536.375
5213.95
65.1
65.1
110
347.305
5148.85
412.405
5213.95
65.1
65.1
111
223.335
5148.85
288.435
5213.95
65.1
65.1
112
10.08
4979.975
75.18
5045.075
65.1
65.1
113
10.08
4868.5
75.18
4933.6
65.1
65.1
114
10.08
4757.025
75.18
4822.125
65.1
65.1
115
10.08
4645.55
75.18
4710.65
65.1
65.1
116
10.08
4534.075
75.18
4599.175
65.1
65.1
117
10.08
4410.105
75.18
4475.205
65.1
65.1
118
10.08
4286.135
75.18
4351.235
65.1
65.1
119
10.08
4162.165
75.18
4227.265
65.1
65.1
120
10.08
4038.195
75.18
4103.295
65.1
65.1
121
10.08
3912.825
75.18
3977.925
65.1
65.1
122
10.08
3801.35
75.18
3866.45
65.1
65.1
123
10.08
3689.875
75.18
3754.975
65.1
65.1
124
10.08
3578.4
75.18
3643.5
65.1
65.1
125
10.08
3466.925
75.18
3532.025
65.1
65.1
126
10.08
3355.45
75.18
3420.55
65.1
65.1
127
10.08
3243.975
75.18
3309.075
65.1
65.1
128
10.08
3132.5
75.18
3197.6
65.1
65.1
129
10.08
3021.025
75.18
3086.125
65.1
65.1
130
10.08
2909.55
75.18
2974.65
65.1
65.1
131
10.08
2720.305
75.18
2785.405
65.1
65.1
132
10.08
2608.83
75.18
2673.93
65.1
65.1
133
10.08
2497.355
75.18
2562.455
65.1
65.1
134
10.08
2385.88
75.18
2450.98
65.1
65.1
135
10.08
2274.405
75.18
2339.505
65.1
65.1
136
10.08
2162.93
75.18
2228.03
65.1
65.1
137
10.08
2051.455
75.18
2116.555
65.1
65.1
138
10.08
1862.21
75.18
1927.31
65.1
65.1
Bare Die
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
www.ti.com
Table 4-1. Bond Pad Coordinates (continued)
PAD NO.
14
BOND PAD COORDINATES (µm)
PAD SIZE (µm)
X MIN
Y MIN
X MAX
Y MAX
X
Y
139
10.08
1672.965
75.18
1738.065
65.1
65.1
140
10.08
1561.49
75.18
1626.59
65.1
65.1
141
10.08
1372.245
75.18
1437.345
65.1
65.1
142
10.08
1260.77
75.18
1325.87
65.1
65.1
143
10.08
1149.295
75.18
1214.395
65.1
65.1
144
10.08
1037.82
75.18
1102.92
65.1
65.1
145
10.08
926.345
75.18
991.445
65.1
65.1
146
10.08
814.87
75.18
879.97
65.1
65.1
147
10.08
703.395
75.18
768.495
65.1
65.1
148
10.08
514.15
75.18
579.25
65.1
65.1
149
10.08
402.675
75.18
467.775
65.1
65.1
150
10.08
291.2
75.18
356.3
65.1
65.1
151
10.08
179.725
75.18
244.825
65.1
65.1
152
4.9
5154.1
69.93
5219.13
65.03
65.03
Bare Die
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
5 Pin Configuration and Functions
SM470R1B1M
Figure 5-1. SM470R1B1M HFQ/HKP Packages, 84-Pin CQFP Ceramic Quad Flatpack (Top View)
Pin Configuration and Functions
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15
SM470R1B1M-HT
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108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADEVT
GIOF[7]/INT[15]
GIOF[6]/INT[14]
GIOA[5]/INT[5]
PLLDIS
GIOF[5]/INT[13]
I2C2SCL
I2C2SDA
GIOF[4]/INT[12]
VCC
VSS
GIOF[3]/INT[11]
GIOF[2]/INT[10]
I2C1SCL
I2C1SDA
VCCIO
VSSIO
CAN1HTX
CAN1HRX
GIOF[1]/INT[9]
CLKOUT
GIOF[0]/INT[8]
GIOA[7]/INT[7]
GIOA[6]/INT[6]
GIOE[7]
TCK
TDO
TDI
HET[0]
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
HET[1]
HET[2]
GIOE[6]
VCCIO
VSSIO
GIOE[5]
HET[3]
HET[4]
GIOE[4]
HET[5]
SPI2SCS
GIOE[3]
SPI2ENA
SPI2SIMO
GIOE[2]
SPI2SOMI
SPI2CLK
CAN2HTX
CAN2HRX
VCC
VSS
SCI2CLK
SCI2RX
SCI2TX
SCI1CLK
GIOE[1]
SCI1RX
SCI1TX
GIOE[0]
GIOB[0]
GIOD[0]
I2C4SDA
I2C4SCL
GIOD[1]
I2C5SDA
I2C5SCL
SPI1SCS
SPI1ENA
GIOG[4]
SPI1CLK
SPI1SIMO
GIOG[3]
SPI1SOMI
GIOG[2]
HET[6]
GIOG[1]
HET[7]
HET[8]
VCC
VSS
HET[18]
TMS2
TMS
HET[20]
HET[22]
GIOG[0]
SCI3TX
SCI3RX
GIOD[5]
SCI3CLK
VCCIO
VSSIO
GIOD[4]
I2C3SCL
I2C3SDA
GIOD[3]
VCC
OSCOUT
OSCIN
VSS
GIOD[2]
AWD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
ADREFHI
ADREFLO
VCCAD
VSSAD
ADIN[4]
ADIN[3]
ADIN[2]
ADIN[1]
ADIN[0]
PORRST
GIOC[4]
GIOC[3]
RST
VSS
VCC
TEST
GIOH[5]
GIOC[2]
GIOA[4]/INT[4]
GIOC[1]
VSS
VCC
VCCP
FLTP2
GIOA[3]/INT[3]
GIOA[2]/INT[2]
GIOC[0]
GIOA[1]/INT[1]/ECLK
VCCIO
VSSIO
GIOH[0]
GIOG[7]
GIOA[0]/INT[0]
GIOG[6]
GIOG[5]
TRST
Figure 5-2. SM470R1B1M-HT PGE Package, 144-Pin LQFP Plastic Low-Profile Quad Flatpack Without
Expansion Bus (Top View)
16
Pin Configuration and Functions
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADEVT
EBADDR[13]/EBDATA[15]
EBADDR[12]/EBDATA[14]
GIOA[5]/INT[5]
PLLDIS
EBADDR[11]/EBDATA[13]
I2C2SCL
I2C2SDA
EBADDR[10]/EBDATA[12]
VCC
VSS
EBADDR[9]/EBDATA[11]
EBADDR[8]/EBDATA[10]
I2C1SCL
I2C1SDA
VCCIO
VSSIO
CAN1HTX
CAN1HRX
EBADDR[7]/EBDATA[9]
CLKOUT
EBADDR[6]/EBDATA[8]
GIOA[7]/INT[7]
GIOA[6]/INT[6]
EBDATA[7]
TCK
TDO
TDI
HET[0]
www.ti.com
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
HET[1]
HET[2]
EBDATA[6]
VCCIO
VSSIO
EBDATA[5]
HET[3]
HET[4]
EBDATA[4]
HET[5]
SPI2SCS
EBDATA[3]
SPI2ENA
SPI2SIMO
EBDATA[2]
SPI2SOMI
SPI2CLK
CAN2HTX
CAN2HRX
VCC
VSS
SCI2CLK
SCI2RX
SCI2TX
SCI1CLK
EBDATA[1]
SCI1RX
SCI1TX
EBDATA[0]
EBDMAREQ[0]
EBADDR[0]
EBADDR[23]/EBADDR[15]
EBADDR[24]/EBADDR[16]
EBADDR[1]
EBADDR[26]/EBADDR[18]
EBADDR[25]/EBADDR[17]
SPI1SCS
SPI1ENA
EBADDR[18]/EBADDR[10]
SPI1CLK
SPI1SIMO
EBADDR[17]/EBADDR[9]
SPI1SOMI
EBADDR[16]/EBADDR[8]
HET[6]
EBADDR[15]/EBADDR[7]
HET[7]
HET[8]
VCC
VSS
HET[18]
TMS2
TMS
HET[20]
HET[22]
EBADDR[14]/EBADDR[6]
SCI3TX
SCI3RX
EBADDR[5]
SCI3CLK
VCCIO
VSSIO
EBADDR[4]
I2C3SCL
I2C3SDA
EBADDR[3]
VCC
OSCOUT
OSCIN
VSS
EBADDR[2]
AWD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
ADREFHI
ADREFLO
VCCAD
VSSAD
ADIN[4]
ADIN[3]
ADIN[2]
ADIN[1]
ADIN[0]
PORRST
EBCS[6]
EBCS[5]
RST
VSS
VCC
TEST
EBHOLD
EBWR[1]
GIOA[4]/INT[4]
EBWR[0]
VSS
VCC
VCCP
FLTP2
GIOA[3]/INT[3]
GIOA[2]/INT[2]
EBOE
GIOA[1]/INT[1]/ECLK
VCCIO
VSSIO
EBADDR[22]/EBADDR[14]
EBADDR[21]/EBADDR[13]
GIOA[0]/INT[0]
EBADDR[20]/EBADDR[12]
EBADDR[19]/EBADDR[11]
TRST
Figure 5-3. SM470R1B1M-HT PGE Package 144-Pin LQFP Plastic Low-Profile Quad Flatpack With
Expansion Bus (Top View)
5.1
Features
The reduced pin count version of SM470R1B1M has the following features.
• Communication interfaces
– Two SPIs
– Two SCIs
– Two HECC
– Two I2C modules
• 4-channel, 10-bit MibADC
Pin Configuration and Functions
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
•
•
5.2
www.ti.com
High-end timer lite (HET) controlling seven programmable I/O channels
Eight general-purpose I/Os
Pin Functions (HFQ/HKP Package)
PIN
NAME
PAD
NO.
HFQ/
HKP (4)
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
HIGH-END TIMER (HET)
HET[0]
76
42
HET[1]
75
NC
HET[2]
74
41
HET[3]
69
38
HET[4]
68
37
HET[5]
66
36
HET[6]
9
6
HET[7]
11
NC
HET[8]
13
7
HET[18]
16
NC
HET[20]
19
NC
HET[22]
20
NC
Timer input capture or output compare. The
HET[8:0,18,20,22] applicable pins can be
programmed as general-purpose
input/output (GIO) pins. All are highresolution pins.
3.3 V
2 mA -z
IPD (20 µA)
The high-resolution (HR) SHARE feature
allows even HR pins to share the next higher
odd HR pin structures. This HR sharing is
independent of whether or not the odd pin is
available externally. If an odd pin is available
externally and shared, then the odd pin can
only be used as a general-purpose I/O. For
more information on HR SHARE, see the
TMS470R1x High-End Timer (HET)
Reference Guide (SPNU199).
HIGH-END CAN CONTROLLER (HECC)
CAN1HRX
86
49
5-V tolerant
4 mA
CAN1HTX
87
50
3.3 V
2 mA -z
CAN2HRX
57
29
5-V tolerant
4 mA
CAN2HTX
58
30
3.3 V
2 mA -z
GIOA[0]/INT[0]
147
83
GIOA[1]/INT[1]/ECLK
140
80
GIOA[2]/INT[2]
138
79
GIOA[3]/INT[3]
137
78
GIOA[4]/INT[4]
130
73
GIOA[5]/INT[5]
101
58
GIOA[6]/INT[6]
81
46
GIOA[7]/INT[7]
82
47
GIOB[0]/EBDMAREQ0
46
NC
GIOC[0]/EBOE
139
NC
GIOC[1]/EBWR[0]
131
NC
GIOC[2]/EBWR[1]
129
NC
GIOC[3]/EBCS[5]
123
NC
GIOC[4]/EBCS[6]
122
NC
HECC1 receive pin or GIO pin
IPU (20 µA)
HECC1 transmit pin or GIO pin
HECC2 receive pin or GIO pin
IPU (20 µA)
HECC2 transmit pin or GIO pin
GENERAL-PURPOSE I/O (GIO)
(1)
(2)
(3)
(4)
18
General-purpose input/output pins.
GIOA[7:0]/INT[7:0] are interrupt-capable
pins.
5-V tolerant
4 mA
GIOA[1]/INT[1]/ECLK pin is multiplexed with
the external clock-out function of the
external clock prescale (ECP) module.
3.3 V
2 mA -z
IPD (20 µA)
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:],
GIOF[7:0], GIOG[7:0], and GIOH[5,0] are
multiplexed with the expansion bus module.
See Table 8-3.
PWR = power, GND = ground, REF = reference voltage, NC = no connect
All I/O pins, except RST , are configured as inputs while PORRST is low and immediately after PORRST goes high.
IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)
Any pins marked as NC are physically connected to ground internal to the package. Care must be used to keep these pins in a high
impedance input state.
Pin Configuration and Functions
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
PIN
PAD
NO.
HFQ/
HKP (4)
GIOD[0]/EBADDR[0]
45
NC
GIOD[1]/EBADDR[1]
42
NC
GIOD[2]/EBADDR[2]
38
NC
GIOD[3]/EBADDR[3]
33
NC
GIOD[4]/EBADDR[4]
30
NC
GIOD[5]/EBADDR[5]
25
NC
GIOE[0]/EBDATA[0]
47
NC
GIOE[1]/EBDATA[1]
50
NC
GIOE[2]/EBDATA[2]
61
NC
GIOE[3]/EBDATA[3]
64
NC
GIOE[4]/EBDATA[4]
67
NC
GIOE[5]/EBDATA[5]
70
NC
GIOE[6]/EBDATA[6]
73
NC
GIOE[7]/EBDATA[7]
80
NC
GIOF[0]/INT[8]/
EBADDR[6]/EBDATA[8]
83
GIOF[1]/INT[9]/
EBADDR[7]/EBDATA[9]
85
GIOF[2]/INT[10]/
EBADDR[8]/EBDATA[10]
92
GIOF[3]/INT[11]/
EBADDR[9]/EBDATA[11]
93
GIOF[4]/INT[12]/
EBADDR[10]/EBDATA[12]
96
GIOF[5]/INT[13]/
EBADDR[11]/EBDATA[13]
99
NAME
GIOF[6]/INT[14]/
EBADDR[12]/EBDATA[14]
102
GIOF[7]/INT[15]/
EBADDR[13]/EBDATA[15]
103
GIOG[0]/EBADDR[14]/
EBADDR[6]
21
GIOG[1]/EBADDR[15]/
EBADDR[7]
10
GIOG[2]/EBADDR[16]/
EBADDR[8]
8
GIOG[3]/EBADDR[17]/
EBADDR[9]
6
GIOG[4]/EBADDR[18]/
EBADDR[10]
3
GIOG[5]/EBADDR[19]/
EBADDR[11]
150
GIOG[6]/EBADDR[20]/EBADDR[12]
148
GIOG[7]/EBADDR[21]/
EBADDR[13]
145
GIOH[0]/EBADDR[22]/
EBADDR[14]
144
GIOH[5]/EBHOLD
128
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
NC
NC
NC
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:],
GIOF[7:0], GIOG[7:0], and GIOH[5,0] are
multiplexed with the expansion bus module.
NC
NC
3.3 V
2 mA -z
IPD (20 µA)
GIOF[7:0]/INT[15:8] are interrupt-capable
pins.
NC
See Table 8-3.
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Pin Configuration and Functions
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SM470R1B1M-HT
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
www.ti.com
PIN
NAME
PAD
NO.
HFQ/
HKP (4)
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
2 mA -z
IPD (20 µA)
DESCRIPTION
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
59
ADEVT
104
ADIN[0]
120
NC
ADIN[1]
119
NC
ADIN[2]
118
NC
ADIN[3]
117
NC
ADIN[4]
116
NC
ADIN[5]
111
NC
ADIN[6]
110
63
ADIN[7]
109
NC
ADIN[8]
108
62
ADIN[9]
107
61
ADIN[10]
106
60
ADIN[11]
105
NC
ADREFHI
112
ADREFLO
113
VCCAD
114
VSSAD
115
64
MibADC event input. Can be programmed
as a GIO pin.
3.3 V
MibADC analog input pins
3.3 VREF
MibADC module high-voltage reference
input
65
GND REF
MibADC module low-voltage reference input
66
3.3-V PWR
MibADC analog supply voltage
67
GND
MibADC analog ground reference
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1CLK
4
SPI1ENA
2
SPI1SCS
1
SPI1SIMO
5
SPI1SOMI
7
3
SPI1 clock. SPI1CLK can be programmed
as a GIO pin.
2
SPI1 chip enable. Can be programmed as a
GIO pin.
1
5-V tolerant
4 mA
SPI1 slave chip select. Can be programmed
as a GIO pin.
4
SPI1 data stream. Slave in/master out. Can
be programmed as a GIO pin.
5
SPI1 data stream. Slave out/master in. Can
be programmed as a GIO pin.
31
SPI2 clock. Can be programmed as a GIO
pin.
34
SPI2 chip enable. Can be programmed as a
GIO pin.
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2CLK
59
SPI2ENA
63
SPI2SCS
65
SPI2SIMO
62
SPI2SOMI
60
35
5-V tolerant
4 mA
SPI2 slave chip select. Can be programmed
as a GIO pin.
33
SPI2 data stream. Slave in/master out. Can
be programmed as a GIO pin.
32
SPI2 data stream. Slave out/master in. Can
be programmed as a GIO pin.
INTER-INTEGRATED CIRCUIT 1 (I2C1)
I2C1SDA
90
NC
I2C1SCL
91
NC
20
5-V tolerant
4 mA
Pin Configuration and Functions
I2C1 serial data pin or GIO pin
I2C1 serial clock pin or GIO pin
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
PIN
NAME
PAD
NO.
HFQ/
HKP (4)
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
INTER-INTEGRATED CIRCUIT 2 (I2C2)
I2C2SDA
97
55
I2C2SCL
98
56
5-V tolerant
4 mA
5-V tolerant
4 mA
5-V tolerant
4 mA
5-V tolerant
4 mA
I2C2 serial data pin or GIO pin
I2C2 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 3 (I2C3)
I2C3SDA
32
NC
I2C3SCL
31
NC
I2C3 serial data pin or GIO pin
I2C3 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 4 (I2C4)
I2C4SDA
44
23
I2C4SCL
43
22
I2C4 serial data pin or GIO pin
I2C4 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 5 (I2C5)
I2C5SDA
41
NC
I2C5SCL
40
NC
I2C5 serial data pin or GIO pin
I2C5 serial clock pin or GIO pin
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
OSCIN
36
19
OSCOUT
35
18
PLLDIS
100
57
1.8 V
Crystal connection pin or external clock input
2 mA
3.3 V
External crystal connection pin
IPD (20 µA)
Enable/disable the ZPLL. The ZPLL can be
bypassed and the oscillator becomes the
system clock. If not in bypass mode, TI
recommends that this pin be connected to
ground or pulled down to ground by an
external resistor.
IPD (20 µA)
SCI1 clock. SCI1CLK can be programmed
as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
SCI1CLK
51
26
3.3 V
2 mA -z
SCI1RX
49
25
5-V tolerant
4 mA
SCI1TX
48
24
3.3 V
2 mA -z
IPU (20 µA)
SCI1 data transmit. SCI1TX can be
programmed as a GIO pin.
IPD (20 µA)
SCI2 clock. SCI2CLK can be programmed
as a GIO pin.
SCI1 data receive. SCI1RX can be
programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
SCI2CLK
54
NC
3.3 V
2 mA -z
SCI2RX
53
NC
5-V tolerant
4 mA
SCI2TX
52
NC
3.3 V
2 mA -z
IPU (20 µA)
SCI2 data transmit. SCI2TX can be
programmed as a GIO pin.
IPD (20 µA)
SCI3 clock. SCI3CLK can be programmed
as a GIO pin.
SCI2 data receive. SCI2RX can be
programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 3 (SCI3)
SCI3CLK
27
14
3.3 V
2 mA -z
SCI3RX
24
13
5-V tolerant
4 mA
SCI3TX
23
12
3.3 V
2 mA -z
CLKOUT
84
48
3.3 V
8 mA
PORRST
121
68
3.3 V
SCI3 data receive. SCI3RX can be
programmed as a GIO pin.
IPU (20 µA)
SCI3 data transmit. SCI3TX can be
programmed as a GIO pin.
SYSTEM MODULE (SYS)
Bidirectional pin. CLKOUT can be
programmed as a GIO pin or the output of
SYSCLK, ICLK, or MCLK.
IPD (20 µA)
Input master chip power-up reset. External
VCC monitor circuitry must assert a power-on
reset.
Bidirectional reset. The internal circuitry can
assert a reset, and an external system reset
can assert a device reset.
RST
124
69
3.3 V
4 mA
IPU (20 µA)
On this pin, the output buffer is implemented
as an open drain (drives low only).
To ensure an external reset is not arbitrarily
generated, TI recommends that an external
pullup resistor be connected to this pin.
Pin Configuration and Functions
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SM470R1B1M-HT
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
www.ti.com
PIN
NAME
PAD
NO.
HFQ/
HKP (4)
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
AWD
39
21
3.3 V
Analog watchdog reset. The AWD pin
provides a system reset if the WD KEY is
not written in time by the system, providing
an external RC network circuit is connected.
If the user is not using AWD, TI
recommends that this pin be connected to
ground or pulled down to ground by an
external resistor.
8 mA
For more details on the external RC network
circuit, see the TMS470R1x System Module
Reference Guide (SPNU189).
TEST/DEBUG (T/D)
TCK
79
TDI
77
TDO
78
TEST
127
TMS
18
TMS2
17
45
43
IPD (20 µA)
Test clock. TCK controls the test hardware
(JTAG).
8 mA
IPU (20 µA)
Test data in. TDI inputs serial data to the
test instruction register, test data register,
and programmable test address (JTAG).
8 mA
IPD (20 µA)
Test data out. TDO outputs serial data from
the test instruction register, test data
register, identification register, and
programmable test address (JTAG).
IPD (20 µA)
Test enable. Reserved for internal use only.
TI recommends that this pin be connected to
ground or pulled down to ground by an
external resistor.
8 mA
IPU (20 µA)
Serial input for controlling the state of the
CPU test access port (TAP) controller
(JTAG).
8 mA
IPU (20 µA)
Serial input for controlling the second TAP.
TI recommends that this pin be connected to
VCCIO or pulled up to VCCIO by an external
resistor.
IPD (20 µA)
Test hardware reset to TAP1 and TAP2.
IEEE Standard 1149-1 (JTAG) BoundaryScan Logic. TI recommends that this pin be
pulled down to ground by an external
resistor.
3.3 V
44
72
11
10
3.3 V
84
TRST
151
FLASH
NC
Flash test pad 2. For proper operation,
this pin must not be connected [no
connect (NC)].
FLTP2
135
77
NC
VCCP
134
76
3.3-V PWR
Flash external pump voltage (3.3 V)
1.8-V PWR
Core logic supply voltage
SUPPLY VOLTAGE CORE (1.8 V)
VCC
22
14
8
34
17
56
28
95
54
126
71
133
75
Pin Configuration and Functions
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
PIN
PAD
NO.
NAME
TYPE (1)
HFQ/
HKP (4)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
VCCIO
28
15
72
40
89
52
141
81
3.3-V PWR
Digital I/O supply voltage
SUPPLY GROUND CORE
VSS
15
9
37
20
55
27
94
53
125
70
132
74
29
16
71
39
88
51
142
82
GND
Core supply ground reference
GND
Digital I/O supply ground reference
SUPPLY GROUND DIGITAL I/O
VSSIO
5.3
Pin Functions (PGE Package)
PIN
NAME
NO.
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
HIGH-END TIMER (HET)
HET[0]
73
HET[1]
72
HET[2]
71
HET[3]
66
HET[4]
65
HET[5]
63
HET[6]
9
HET[7]
11
HET[8]
12
HET[18]
15
HET[20]
18
HET[22]
19
Timer input capture or output compare. The
HET[8:0,18,20,22] applicable pins can be programmed
as general-purpose input/output (GIO) pins. All are
high-resolution pins.
3.3 V
2 mA -z
IPD (20 µA)
The high-resolution (HR) SHARE feature allows even
HR pins to share the next higher odd HR pin
structures. This HR sharing is independent of whether
or not the odd pin is available externally. If an odd pin
is available externally and shared, then the odd pin can
only be used as a general-purpose I/O. For more
information on HR SHARE, see the TMS470R1x HighEnd Timer (HET) Reference Guide (SPNU199).
HIGH-END CAN CONTROLLER (HECC)
CAN1HRX
83
5-V tolerant
4 mA
CAN1HTX
CAN2HRX
84
3.3 V
2 mA -z
54
5-V tolerant
4 mA
CAN2HTX
55
3.3 V
2 mA -z
HECC1 receive pin or GIO pin
IPU (20 µA)
HECC1 transmit pin or GIO pin
HECC2 receive pin or GIO pin
IPU (20 µA)
HECC2 transmit pin or GIO pin
STANDARD CAN CONTROLLER (SCC)
CANSRX
(1)
(2)
(3)
-
5-V tolerant
4 mA
SCC receive pin. The CANSRX signal is only
connected to the pad and not to a package pin. For
reduced power consumption in low power mode,
CANSRX should be driven output LOW.
PWR = power, GND = ground, REF = reference voltage, NC = no connect
All I/O pins, except RST , are configured as inputs while PORRST is low and immediately after PORRST goes high.
IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)
Pin Configuration and Functions
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SM470R1B1M-HT
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
PIN
NAME
CANSTX
NO.
-
TYPE (1)
(2)
3.3 V
www.ti.com
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
2 mA -z
IPU (20 µA)
DESCRIPTION
SCC transmit pin. The CANSTX signal is only
connected to the pad and not to a package pin. For
reduced power consumption in low power mode,
CANSTX should be driven output LOW.
GENERAL-PURPOSE I/O (GIO)
GIOA[0]/INT[0]
141
GIOA[1]/INT[1]/ECLK
136
GIOA[2]/INT[2]
134
GIOA[3]/INT[3]
133
GIOA[4]/INT[4]
127
GIOA[5]/INT[5]
98
GIOA[6]/INT[6]
78
GIOA[7]/INT[7]
79
GIOB[0]/EBDMAREQ0
43
GIOC[0]/EBOE
135
GIOC[1]/EBWR[0]
128
GIOC[2]/EBWR[1]
126
GIOC[3]/EBCS[5]
120
GIOC[4]/EBCS[6]
119
24
General-purpose input/output pins. GIOA[7:0]/INT[7:0]
are interrupt-capable pins.
5-V tolerant
3.3 V
4 mA
2 mA -z
GIOA[1]/INT[1]/ECLK pin is multiplexed with the
external clock-out function of the external clock
prescale (ECP) module.
IPD (20 µA)
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0],
GIOG[7:0], and GIOH[5,0] are multiplexed with the
expansion bus module.
See Table 8-3.
Pin Configuration and Functions
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
PIN
NAME
NO.
GIOD[0]/EBADDR[0]
42
GIOD[1]/EBADDR[1]
39
GIOD[2]/EBADDR[2]
35
GIOD[3]/EBADDR[3]
30
GIOD[4]/EBADDR[4]
27
GIOD[5]/EBADDR[5]
23
GIOE[0]/EBDATA[0]
44
GIOE[1]/EBDATA[1]
47
GIOE[2]/EBDATA[2]
58
GIOE[3]/EBDATA[3]
61
GIOE[4]/EBDATA[4]
64
GIOE[5]/EBDATA[5]
67
GIOE[6]/EBDATA[6]
70
GIOE[7]/EBDATA[7]
77
GIOF[0]/INT[8]/
EBADDR[6]/EBDATA[8]
80
GIOF[1]/INT[9]/
EBADDR[7]/EBDATA[9]
82
GIOF[2]/INT[10]/
EBADDR[8]/EBDATA[10]
89
GIOF[3]/INT[11]/
EBADDR[9]/EBDATA[11]
90
GIOF[4]/INT[12]/
EBADDR[10]/EBDATA[12]
93
GIOF[5]/INT[13]/
EBADDR[11]/EBDATA[13]
96
GIOF[6]/INT[14]/
EBADDR[12]/EBDATA[14]
99
GIOF[7]/INT[15]/
EBADDR[13]/EBDATA[15]
100
GIOG[0]/EBADDR[14]/
EBADDR[6]
20
GIOG[1]/EBADDR[15]/
EBADDR[7]
10
GIOG[2]/EBADDR[16]/
EBADDR[8]
8
GIOG[3]/EBADDR[17]/
EBADDR[9]
6
GIOG[4]/EBADDR[18]/
EBADDR[10]
3
GIOG[5]/EBADDR[19]/
EBADDR[11]
143
GIOG[6]/EBADDR[20]/EB
ADDR[12]
142
GIOG[7]/EBADDR[21]/
EBADDR[13]
140
GIOH[0]/EBADDR[22]/
EBADDR[14]
139
GIOH[5]/EBHOLD
125
TYPE (1)
(2)
3.3 V
CURRENT
OUTPUT
2 mA -z
INTERNAL
PULLUP/
PULLDOWN (3)
IPD (20 µA)
DESCRIPTION
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0],
GIOG[7:0], and GIOH[5,0] are multiplexed with the
expansion bus module.
GIOF[7:0]/INT[15:8] are interrupt-capable pins.
See Table 8-3.
Pin Configuration and Functions
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SM470R1B1M-HT
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
PIN
NAME
NO.
TYPE (1)
(2)
www.ti.com
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
2 mA -z
IPD (20 µA)
MibADC event input. Can be programmed as a GIO
pin.
ADEVT
101
ADIN[0]
117
ADIN[1]
116
ADIN[2]
115
ADIN[3]
114
ADIN[4]
113
ADIN[5]
108
ADIN[6]
107
ADIN[7]
106
ADIN[8]
105
ADIN[9]
104
ADIN[10]
103
ADIN[11]
102
ADREFHI
109
3.3 VREF
MibADC module high-voltage reference input
ADREFLO
110
GND REF
MibADC module low-voltage reference input
VCCAD
111
3.3-V PWR
MibADC analog supply voltage
VSSAD
112
GND
3.3 V
MibADC analog input pins
MibADC analog ground reference
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1 clock. SPI1CLK can be programmed as a GIO
pin.
SPI1CLK
4
SPI1ENA
2
SPI1SCS
1
SPI1SIMO
5
SPI1 data stream. Slave in/master out. Can be
programmed as a GIO pin.
SPI1SOMI
7
SPI1 data stream. Slave out/master in. Can be
programmed as a GIO pin.
SPI1 chip enable. Can be programmed as a GIO pin.
5-V tolerant
4 mA
SPI1 slave chip select. Can be programmed as a GIO
pin.
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2CLK
56
SPI2ENA
60
SPI2 chip enable. Can be programmed as a GIO pin.
62
SPI2 slave chip select. Can be programmed as a GIO
pin.
SPI2SCS
SPI2 clock. Can be programmed as a GIO pin.
5-V tolerant
4 mA
SPI2SIMO
59
SPI2 data stream. Slave in/master out. Can be
programmed as a GIO pin.
SPI2SOMI
57
SPI2 data stream. Slave out/master in. Can be
programmed as a GIO pin.
INTER-INTEGRATED CIRCUIT 1 (I2C1)
I2C1SDA
87
I2C1SCL
88
5-V tolerant
4 mA
I2C1 serial data pin or GIO pin
I2C1 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 2 (I2C2)
I2C2SDA
94
I2C2SCL
95
26
5-V tolerant
4 mA
I2C2 serial data pin or GIO pin
Pin Configuration and Functions
I2C2 serial clock pin or GIO pin
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PIN
NAME
NO.
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
INTER-INTEGRATED CIRCUIT 3 (I2C3)
I2C3SDA
29
I2C3SCL
28
5-V tolerant
I2C3 serial data pin or GIO pin
4 mA
I2C3 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 4 (I2C4)
I2C4SDA
41
I2C4SCL
40
5-V tolerant
I2C4 serial data pin or GIO pin
4 mA
I2C4 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 5 (I2C5)
I2C5SDA
38
I2C5SCL
37
5-V tolerant
I2C5 serial data pin or GIO pin
4 mA
I2C5 serial clock pin or GIO pin
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
OSCIN
33
OSCOUT
32
PLLDIS
97
1.8 V
Crystal connection pin or external clock input
2 mA
3.3 V
External crystal connection pin
IPD (20 µA)
Enable/disable the ZPLL. The ZPLL can be bypassed
and the oscillator becomes the system clock. If not in
bypass mode, TI recommends that this pin be
connected to ground or pulled down to ground by an
external resistor.
IPD (20 µA)
SCI1 clock. SCI1CLK can be programmed as a GIO
pin.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
SCI1CLK
48
3.3 V
2 mA -z
SCI1RX
46
5-V tolerant
4 mA
SCI1TX
45
3.3 V
2 mA -z
SCI1 data receive. SCI1RX can be programmed as a
GIO pin.
IPU (20 µA)
SCI1 data transmit. SCI1TX can be programmed as a
GIO pin.
IPD (20 µA)
SCI2 clock. SCI2CLK can be programmed as a GIO
pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
SCI2CLK
51
3.3 V
2 mA -z
SCI2RX
50
5-V tolerant
4 mA
SCI2TX
49
3.3 V
2 mA -z
SCI2 data receive. SCI2RX can be programmed as a
GIO pin.
IPU (20 µA)
SCI2 data transmit. SCI2TX can be programmed as a
GIO pin.
IPD (20 µA)
SCI3 clock. SCI3CLK can be programmed as a GIO
pin.
SERIAL COMMUNICATIONS INTERFACE 3 (SCI3)
SCI3CLK
24
3.3 V
2 mA -z
SCI3RX
22
5-V tolerant
4 mA
SCI3TX
21
3.3 V
2 mA -z
CLKOUT
81
3.3 V
8 mA
PORRST
118
3.3 V
SCI3 data receive. SCI3RX can be programmed as a
GIO pin.
IPU (20 µA)
SCI3 data transmit. SCI3TX can be programmed as a
GIO pin.
SYSTEM MODULE (SYS)
Bidirectional pin. CLKOUT can be programmed as a
GIO pin or the output of SYSCLK, ICLK, or MCLK.
IPD (20 µA)
Input master chip power-up reset. External VCC monitor
circuitry must assert a power-on reset.
Bidirectional reset. The internal circuitry can assert a
reset, and an external system reset can assert a
device reset.
RST
121
3.3 V
4 mA
IPU (20 µA)
On this pin, the output buffer is implemented as an
open drain (drives low only).
To ensure an external reset is not arbitrarily generated,
TI recommends that an external pullup resistor be
connected to this pin.
Pin Configuration and Functions
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SM470R1B1M-HT
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PIN
NAME
NO.
TYPE (1)
www.ti.com
CURRENT
OUTPUT
(2)
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
AWD
36
3.3 V
Analog watchdog reset. The AWD pin provides a
system reset if the WD KEY is not written in time by
the system, providing an external RC network circuit is
connected. If the user is not using AWD, TI
recommends that this pin be connected to ground or
pulled down to ground by an external resistor.
8 mA
For more details on the external RC network circuit,
see the TMS470R1x System Module Reference Guide
(SPNU189).
TEST/DEBUG (T/D)
TCK
76
TDI
74
TDO
75
TEST
124
TMS
17
TMS2
16
TRST
IPD (20 µA)
3.3 V
3.3 V
Test clock. TCK controls the test hardware (JTAG).
Test data in. TDI inputs serial data to the test
instruction register, test data register, and
programmable test address (JTAG).
8 mA
IPU (20 µA)
8 mA
IPD (20 µA)
Test data out. TDO outputs serial data from the test
instruction register, test data register, identification
register, and programmable test address (JTAG).
IPD (20 µA)
Test enable. Reserved for internal use only. TI
recommends that this pin be connected to ground or
pulled down to ground by an external resistor.
8 mA
IPU (20 µA)
Serial input for controlling the state of the CPU test
access port (TAP) controller (JTAG).
8 mA
IPU (20 µA)
Serial input for controlling the second TAP. TI
recommends that this pin be connected to VCCIO or
pulled up to VCCIO by an external resistor.
IPD (20 µA)
Test hardware reset to TAP1 and TAP2. IEEE
Standard 1149-1 (JTAG) Boundary-Scan Logic. TI
recommends that this pin be pulled down to ground by
an external resistor.
144
FLASH
NC
Flash test pad 2. For proper operation, this pin must
not be connected [no connect (NC)].
FLTP2
132
NC
VCCP
131
3.3-V PWR
Flash external pump voltage (3.3 V)
1.8-V PWR
Core logic supply voltage
SUPPLY VOLTAGE CORE (1.8 V)
13
31
53
VCC
92
123
130
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
25
69
VCCIO
86
3.3-V PWR
Digital I/O supply voltage
137
SUPPLY GROUND CORE
14
34
VSS
52
91
GND
Core supply ground reference
122
129
28
Pin Configuration and Functions
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PIN
NAME
NO.
TYPE (1)
(2)
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN (3)
DESCRIPTION
SUPPLY GROUND DIGITAL I/O
26
VSSIO
68
85
GND
Digital I/O supply ground reference
138
Pin Configuration and Functions
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SM470R1B1M-HT
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6 Specifications
6.1
Absolute Maximum Ratings
over operating free-air temperature range, A version (unless otherwise noted) (1)
Supply voltage
Supply voltage
Input voltage
Input clamp current
Operating free-air
temperature, TA
VCC
(2)
VCCIO, VCCAD, VCCP (flash pump)
(2)
(2)
MAX
UNIT
2.5
V
–0.3
4.1
V
All 5-V tolerant input pins
–0.3
6.0
V
All other input pins
–0.3
4.1
V
IIK (VI < 0 or VI > VCCIO)
All pins except ADIN[0:11], PORRST, TRST, TEST, and TCK
±20
mA
IIK (VI < 0 or VI > VCCAD)
ADIN[0:11]
±10
mA
HFQ/HKP package
–55
220
°C
PGE package
–55
150
°C
–55
220
°C
Storage temperature, Tstg
(1)
MIN
–0.3
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to their associated grounds.
6.2
ESD Ratings
VALUE
UNIT
SM470R1B1M-HT in CFP Package
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
750
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
750
V
SM470R1B1M-HT in LQFP Package
V(ESD)
(1)
(2)
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Recommended Operating Conditions (1)
6.3
MIN
VCC
Digital logic supply voltage (Core)
NOM
MAX UNIT
SYSCLK = 48 MHz
(pipeline mode enabled)
1.71
2.05
SYSCLK = 60 MHz
(pipeline mode enabled)
1.81
2.05
V
VCCIO
Digital logic supply voltage (I/O)
3
3.6
V
VCCAD
ADC supply voltage
3
3.6
V
VCCP
Flash pump supply voltage
3
3.6
V
VSS
Digital logic supply ground
VSSAD
TA
(1)
30
ADC supply ground
0
(1)
Operating free-air temperature
V
–0.1
0.1
HFQ/HKP package
–55
220
PGE package
–55
150
V
°C
All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.
Specifications
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6.4
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
Electrical Characteristics
Minimum and maximum parameters are characterized over the operating temperature range unless otherwise noted, but may
not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high
temperature performance. (1)
PARAMETER
Vhys
Input hysteresis
VIL
Low-level input
voltage
All inputs (3)
High-level input
voltage
All inputs
VIH
Input threshold
voltage
AWD only (4)
OSCIN with digital input
only
Low-level output voltage (5)
VOH
High-level output voltage (5)
IIC
Input clamp current (I/O pins) (6)
II
MIN
IOH = IOH MIN
IOH = 50 µA
2
VCCIO + 0. 3
1.35
1.8
0.7 VCC
VCC + 0.3
0.2 VCCIO
0.2
0.8 VCCIO
VI < VSSIO – 0. 3 or
VI > VCCIO + 0. 3
–2
IIL Pulldown
VI = VSS
–1
1
IIH Pulldown
VI = VCCIO
5
100
IIL Pullup
VI = VSS
–100
–5
IIH Pullup
VI = VCCIO
–1
1
All other pins
No pullup or pulldown
–1
1
VI = VSS
–1
1
RST
All other 3.3 V I/O
1
5
VI = 5 V
5
25
25
50
(3)
(4)
(5)
(6)
(7)
V
V
mA
µA
µA
8
4
VOL = VOL MAX
(7)
mA
2
4
CLKOUT, TDI, TDO,
TMS, TMS2
(1)
(2)
2
VI = VCCIO
5 V tolerant
High-level output
current
V
V
VCCIO – 0.2
CLKOUT, AWD, TDI,
TDO, TMS, TMS2
IOH
V
0.8
IOL = 50 µA
VI = 5.5 V
Low-level output
current
MAX UNIT
–0 .3
IOL = IOL MAX
Input current (5 V tolerant input pins)
IOL
TYP (2)
0.15
VOL
Input current
(3.3 V input pins)
TEST CONDITIONS
RST
–8
VOH = VOH MIN
–4
All other 3.3 V I/O (7)
–2
5 V tolerant
–4
mA
Source currents (out of the device) are negative while sink currents (into the device) are positive.
The typical values indicated in this table are the expected values during operation under normal operating conditions: nominal VCC,
VCCIO, or VCCAD, room temperature.
This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST Timings section.
These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(SPNU189).
VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
Parameter does not apply to input-only or output-only pins.
Some of the 2 mA buffers on this device are zero-dominant buffers, as indicated by a -z in the Output Current column of the Pin
Functions table. If two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the
resulting value will always be low.
Specifications
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Electrical Characteristics (continued)
Minimum and maximum parameters are characterized over the operating temperature range unless otherwise noted, but may
not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high
temperature performance. (1)
PARAMETER
TEST CONDITIONS
VCC Digital supply current (operating mode)
ICC
VCC Digital supply current (standby mode) (8)
VCC Digital supply current (halt mode)
ICCIO
(9)
(8) (9)
TYP (2)
MAX UNIT
SYSCLK = 48 MHz,
ICLK = 24 MHz, VCC = 2.05 V
110
mA
SYSCLK = 60 MHz,
ICLK = 30 MHz, VCC = 2.05 V
125
mA
28
mA
OSCIN = 5 MHz, VCC = 2.05 V
All frequencies, VCC = 2.05 V
700
µA
VCCIO Digital supply current (operating mode)
No DC load, VCCIO = 3.6 V (10)
20
mA
VCCIO Digital supply current (standby mode) (9)
No DC load, VCCIO = 3.6 V (10)
250
µA
No DC load, VCCIO = 3.6 V (10)
225
µA
All frequencies, VCCAD = 3.6 V
15
mA
All frequencies, VCCAD = 3.6 V
10
µA
All frequencies, VCCAD = 3.6 V
10
µA
SYSCLK = 48 MHz, VCCP = 3.6 V
read operation
45
mA
SYSCLK = 60 MHz, VCCP = 3.6 V
read operation
55
mA
VCCP = 3.6 V program and erase
70
mA
VCCP = 3.6 V standby mode
operation (8)
10
µA
VCCP = 3.6 V halt mode
operation (8)
10
µA
VCCIO Digital supply current (halt mode)
(9)
VCCAD supply current (operating mode)
ICCAD VCCAD supply current (standby mode)
VCCAD supply current (halt mode)
ICCP
MIN
VCCP pump supply current
CI
Input capacitance
2
pF
CO
Output capacitance
3
pF
(8) For flash banks/pumps in sleep mode.
(9) For reduced power consumption in low power mode, CANSRX and CANSTX should be driven output LOW.
(10) I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤0.2 V. All pullup inputs ≥ VCCIO – 0.2 V.
6.5
Thermal Characteristics
SM470R1B1M-HT
THERMAL METRIC (1)
HFQ (CQFP) OR HKP (CFP)
PGE (LQFP)
64 PINS
144 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
N/A
38.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
N/A
5.7
°C/W
RθJB
Junction-to-board thermal resistance
152.0148
19.7
°C/W
ψJT
Junction-to-top characterization parameter
N/A
0.1
°C/W
ψJB
Junction-to-board characterization parameter
N/A
19.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.4898
N/A
°C/W
(1)
32
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Specifications
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(1)
(2)
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
See data sheet for absolute maximum and minimum recommended operating conditions.
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
Figure 6-1. SM470R1B1M-HT Life Expectancy Curve (HFQ/HKP Package)
1.00E+05
Estimated Life (Hours)
1.00E+04
1.00E+03
1.00E+02
1.00E+01
125
130
135
140
145
150
155
160
165
170
175
Continuous TJ (°C)
(1)
(2)
(3)
See data sheet for absolute maximum and minimum recommended operating conditions.
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
Device is qualified for 1000 hour operation at 150°C. Device is functional at 175°C, but at reduced operating life.
Figure 6-2. SM470R1B1M-HT Wirebond Life Derating Chart (PGE Package)
Specifications
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6.6
www.ti.com
ZPLL and Clock Specifications
Table 6-1. Timing Requirements for ZPLL Circuits Enabled or Disabled (1)
MIN
ƒ(OSC)
Input clock frequency
tc(OSC)
Cycle time, OSCIN
tw(OSCIL)
TYP
MAX UNIT
4
10 MHz
100
ns
Pulse duration, OSCIN low
15
ns
tw(OSCIH)
Pulse duration, OSCIN high
15
ƒ(OSCRST)
OSC FAIL frequency (2)
(1)
(2)
ns
53
kHz
Not production tested.
Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(SPNU189).
Table 6-2. Switching Characteristics over Recommended Operating Conditions for Clocks (1) (2)
TEST CONDITIONS (5)
PARAMETER
ƒ(SYS)
System clock frequency (6)
ƒ(CONFIG)
System clock frequency - flash config mode
ƒ(ICLK)
Interface clock frequency
ƒ(ECLK)
External clock output frequency for ECP module
tc(SYS)
Cycle time, system clock
tc(CONFIG)
Cycle time, system clock - flash config mode
tc(ICLK)
Cycle time, interface clock
tc(ECLK)
Cycle time, ECP module external clock output
(1)
(2)
(3)
(4)
(5)
(6)
(7)
34
MIN
(3) (4)
MAX
UNIT
Pipeline mode enabled
60 (7)
MHz
Pipeline mode disabled
24
MHz
24
MHz
Pipeline mode enabled
30
MHz
Pipeline mode disabled
24
MHz
Pipeline mode enabled
30
MHz
Pipeline mode disabled
24
MHz
Pipeline mode enabled
16.7
ns
Pipeline mode disabled
41.6
ns
41.6
ns
Pipeline mode enabled
33.3
ns
Pipeline mode disabled
41.6
ns
Pipeline mode enabled
33.3
ns
Pipeline mode disabled
41.6
ns
Not production tested.
ƒ(SYS) = M × ƒ(OSC)/R, where M = {8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the
GLBCTRL register (GLBCTRL.3).
ƒ(SYS) = ƒ(OSC)/R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
ƒ(ICLK) = ƒ(SYS)/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]
bits in the SYS module.
ƒ(ECLK) = ƒ(ICLK)/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
Only ZPLL mode is available. FM mode must not be turned on.
Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
Flash Vread must be set to 5 V to achieve maximum system clock frequency.
Operating VCC range for this system clock frequency is 1.81 to 2.05 V.
Specifications
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
Table 6-3. Switching Characteristics over Recommended Operating Conditions for External Clocks (1) (2)
(3) (4)
(see Figure 6-3 and Figure 6-4)
PARAMETER
TEST CONDITIONS
SYSCLK or MCLK
tw(COL)
Pulse duration, CLKOUT high
0.5tc(ICLK) – tf
0.5tc(SYS) – tr
ICLK: X is even or 1 (6)
0.5tc(ICLK) – tr
Pulse duration, ECLK low
0.5tc(ECLK) – tf
Pulse duration, ECLK high
(1)
(2)
(3)
(4)
(5)
(6)
0.5tc(ECLK) – tr
N is odd and X is even
N is odd and X is odd and not 1
ns
0.5tc(ECLK) + 0.5tc(SYS) – tf
N is even and X is even or odd
tw(EOH)
ns
0.5tc(ECLK) – tf
N is odd and X is even
N is odd and X is odd and not 1
ns
0.5tc(ICLK) – 0.5tc(SYS) – tr
N is even and X is even or odd
tw(EOL)
UNIT
0.5tc(ICLK) + 0.5tc(SYS) – tf
SYSCLK or MCLK (5)
ICLK: X is odd and not 1 (6)
MAX
0.5tc(SYS) – tf
ICLK: X is even or 1 (6)
Pulse duration, CLKOUT low
ICLK: X is odd and not 1 (6)
tw(COH)
MIN
(5)
0.5tc(ECLK) – tr
ns
0.5tc(ECLK) – 0.5tc(SYS) – tr
Not production tested.
X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.
N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).
Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary).
tw(COH)
CLKOUT
tw(COL)
Figure 6-3. CLKOUT Timing Diagram
tw(EOH)
ECLK
tw(EOL)
Figure 6-4. ECLK Timing Diagram
Specifications
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6.7
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RST and PORRST Timings
Table 6-4. Timing Requirements for PORRST (1)
(see Figure 6-5)
MIN
MAX UNIT
VCCPORL
VCC low supply level when PORRST must be active during power up
VCCPORH
VCC high supply level when PORRST must remain active during power up and become
active during power down
VCCIOPORL
VCCIO low supply level when PORRST must be active during power up
VCCIOPORH
VCCIO high supply level when PORRST must remain active during power up and become
active during power down
VIL
Low-level input voltage after VCCIO > VCCIOPORH
VIL(PORRST)
Low-level input voltage of PORRST before VCCIO > VCCIOPORL
tsu(PORRST)r
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
0
ms
tsu(VCCIO)r
Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL
0
ms
th(PORRST)r
Hold time, PORRST active after VCC > VCCPORH
1
ms
tsu(PORRST)f
Setup time, PORRST active before VCC ≤ VCCPORH during power down
8
µs
th(PORRST)rio
Hold time, PORRST active after VCC > VCCIOPORH
1
ms
th(PORRST)d
Hold time, PORRST active after VCC < VCCPORL
0
ms
tsu(PORRST)fio
Setup time, PORRST active before VCC ≤ VCCIOPORH during power down
0
ns
tsu(VCCIO)f
Setup time, VCC < VCCPORL before VCCIO < VCCIOPORL
0
ns
(1)
0.6
1.5
V
V
1.1
2.75
V
V
0.2 VCCIO
0.5
V
V
Not production tested.
V CCP /VCCIO
V CC
V CCIOPORH
th(PORRST)rio
V CCPORH
V CCIOPORH
V CCIO
tsu(VCCIO)f
V CC
tsu(PORRST)f
th(PORRST)r
V CCIOPORL
V CC
VCCP/VCCIO
PORRST
V CCPORH
tsu(PORRST)fio
tsu(PORRST)f
V CCPORL
th(PORRST)r
tsu(VCCIO)r
th(PORRST)d
tsu(PORRST)r
V IL(PORRST)
V CCIOPORL
V CCPORL
V IL
VIL
VIL
V IL
V IL(PORRST)
NOTE: VCCIO > 1.1 V before VCC > 0.6 V
Figure 6-5. PORRST Timing Diagram
Table 6-5. Switching Characteristics over Recommended Operating Conditions for RST (1)
PARAMETER
tv(RST)
tfsu
(1)
(2)
36
MIN
Valid time, RST active after PORRST inactive
4112tc(OSC)
Valid time, RST active (all others)
8tc(SYS)
Flash start up time, from RST inactive to fetch of first instruction from flash (flash pump
stabilization time)
836tc(OSC)
(2)
MAX UNIT
ns
ns
Not production tested.
Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load
capacitance" table.
Specifications
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6.8
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
JTAG Scan Interface Timing
Table 6-6. JTAG Clock Specification 10-MHz and 50-pF Load on TDO Output (1)
MIN
MAX UNIT
tc(JTAG)
Cycle time, JTAG low and high period
50
ns
tsu(TDI/TMS - TCKr)
Setup time, TDI, TMS before TCK rise (TCKr)
15
ns
th(TCKr -TDI/TMS)
Hold time, TDI, TMS after TCKr
15
ns
th(TCKf -TDO)
Hold time, TDO after TCKf
10
td(TCKf -TDO)
Delay time, TDO valid after TCK fall (TCKf)
(1)
ns
45
ns
Not production tested.
Figure 6-6. JTAG Scan Timings
Specifications
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6.9
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Output Timings
Table 6-7. Switching Characteristics for Output Timings versus Load Capacitance (CL) (1)
(see Figure 6-7)
PARAMETER
tr
tf
tr
tr
tf
tr
tf
(1)
Rise time, AWD, CLKOUT, TDI, TDO, TMS, TMS2
Fall time, AWD, CLKOUT, TDI, TDO, TMS, TMS2
Rise time, RST
Rise time, 4-mA, 5-V tolerant pins
MIN
MAX
CL = 15 pF
0.5
2.5
CL = 50 pF
1.5
5.0
CL = 100 pF
3.0
9.0
CL = 150 pF
4.5
12.5
CL = 15 pF
0.5
2.5
CL = 50 pF
1.5
5.0
CL = 100 pF
3.0
9.0
CL = 150 pF
4.5
12.5
CL = 15 pF
2.5
8
CL = 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
3
10
CL = 50 pF
3.5
12
7
21
CL = 150 pF
9
28
CL = 400 pF
18
40
CL = 15 pF
2
8
CL = 50 pF
2.5
9
CL = 100 pF
8
25
CL = 150 pF
11
35
CL = 400 pF
20
45
CL = 15 pF
2.5
10
CL = 50 pF
6.0
25
CL = 100 pF
12
45
CL = 150 pF
18
65
CL = 15 pF
3
10
CL = 50 pF
8.5
25
CL = 100 pF
16
45
CL = 150 pF
23
65
CL = 100 pF
Fall time, 4-mA, 5-V tolerant pins
Rise time, all other output pins
Fall time, all other output pins
UNIT
ns
ns
ns
ns
ns
ns
ns
Not production tested.
tr
tf
80%
Output
VCC
80%
20%
20%
0
Figure 6-7. CMOS-Level Outputs
38
Specifications
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6.10
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
Input Timings
Table 6-8. Timing Requirements for Input Timings (1) (2)
(see Figure 6-8)
MIN
tpw
(1)
(2)
Input minimum pulse width
MAX UNIT
tc(ICLK) + 10
ns
Not production tested.
tc(ICLK) = interface clock cycle time = 1/ƒ(ICLK)
tpw
Input
80%
V CC
80%
20%
20%
0
Figure 6-8. CMOS-Level Inputs
6.11
Flash Timings
Table 6-9. Timing Requirements for Program Flash (1) (2)
MIN
TYP
MAX
UNIT
4
16
200
µs
8
32
s
tprog(16-bit)
Half word (16-bit) programming time
tprog(Total)
1MB programming time (3)
terase(sector)
Sector erase time, TA = –40°C to 150°C
twec
Write/erase cycles at TA = –40°C to 85°C
tfp(RST)
Flash pump settling time from RST to SLEEP
167tc(SYS)
ns
tfp(SLEEP)
Initial flash pump settling time from SLEEP to STANDBY
167tc(SYS)
ns
tfp(STANDBY)
Initial flash pump settling time from STANDBY to ACTIVE
84tc(SYS)
ns
(1)
(2)
(3)
1.7
50000
s
cycles
Not production tested.
For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.
The 1MB programming time includes overhead of state machine.
Specifications
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6.12
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SPIn Master Mode Timing Parameters
Table 6-10. SPIn Master Mode External Timing Parameters
(CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (1) (2)
NO.
1
2 (6)
3 (6)
4 (6)
5 (6)
6 (6)
7 (6)
(1)
(2)
(3)
(4)
(5)
(6)
(3) (4)
(see Figure 6-9)
MIN
tc(SPC)M
Cycle time, SPInCLK (5)
tw(SPCH)M
MAX UNIT
100
256tc(ICLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0)
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1)
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)
tc(SPC)M – 5 – tf
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)
tc(SPC)M – 5 – tr
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low (clock polarity = 0)
6
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high (clock polarity = 1)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)
4
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)
4
10
10
ns
Not production tested.
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
tc(ICLK) = interface clock cycle time = 1 / ƒ(ICLK)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t c(SPC)M ≥(PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)M = 2t c(ICLK) ≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 6-9. SPIn Master Mode External Timing (CLOCK PHASE = 0)
40
Specifications
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
Table 6-11. SPIn Master Mode External Timing Parameters (1)
(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (2)
(3) (4)
(see Figure 6-10)
NO.
1
2 (6)
3 (6)
4
5
6
7
(1)
(2)
(3)
(4)
(5)
(6)
MIN
tc(SPC)M
Cycle time, SPInCLK (5)
tw(SPCH)M
tw(SPCL)M
MAX UNIT
100
256tc(ICLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0)
0.5tc(SPC)M – 10
tv(SIMO-SPCL)M
Valid time, SPInCLK low after SPInSIMO data valid
(clock polarity = 1)
0.5tc(SPC)M – 10
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)M – 5 – tr
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
0.5tc(SPC)M – 5 – tf
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 0)
6
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 1)
6
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
4
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
4
(6)
(6)
(6)
(6)
ns
Not production tested.
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
tc(ICLK) = interface clock cycle time = 1/ƒ(ICLK)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t c(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)M = 2t c(ICLK) ≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
Data Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 6-10. SPIn Master Mode External Timing (CLOCK PHASE = 1)
Specifications
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6.13
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SPIn Slave Mode Timing Parameters
Table 6-12. SPIn Slave Mode External Timing Parameters (1)
(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (2)
NO.
1
2 (7)
3 (7)
Cycle time, SPInCLK (6)
tw(SPCH)S
(1)
(2)
(3)
(4)
(5)
(6)
(7)
42
MAX UNIT
100
256tc(ICLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
td(SPCH-SOMI)S
Delay time, SPInCLK high to SPInSOMI valid
(clock polarity = 0)
6 + tr
td(SPCL-SOMI)S
Delay time, SPInCLK low to SPInSOMI valid
(clock polarity = 1)
6 + tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
tc(SPC)S – 6 – tf
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 0)
6
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 1)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 0)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
6
5 (7)
7
(see Figure 6-11)
MIN
tc(SPC)S
4 (7)
6
(3) (4) (5)
(7)
(7)
ns
Not production tested.
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5].
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
tc(ICLK) = interface clock cycle time = 1/ƒ(ICLK)
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t c(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)S = 2t c(ICLK) ≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
Specifications
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
55
SPInSOMI
SPISOMI Data Is Valid
6
7
SPInSIMO
SPISIMO Data
Must Be Valid
Figure 6-11. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
Specifications
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Table 6-13. SPIn Slave Mode External Timing Parameters (1)
(CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (2)
NO.
1
2 (7)
3 (7)
4
5
6
7
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(3) (4) (5)
(see Figure 6-12)
MIN
tc(SPC)S
Cycle time, SPInCLK (6)
tw(SPCH)S
tw(SPCL)S
MAX UNIT
100
256tc(ICLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tv(SOMI-SPCH)S
Valid time, SPInCLK high after SPInSOMI data valid
(clock polarity = 0)
0.5tc(SPC)S – 6 – tr
tv(SOMI-SPCL)S
Valid time, SPInCLK low after SPInSOMI data valid
(clock polarity = 1)
0.5tc(SPC)S – 6 – tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
0.5tc(SPC)S – 6 – tf
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 0)
6
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 1)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
6
(7)
(7)
(7)
(7)
ns
Not production tested.
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
If the SPI is in slave mode, the following must be true: tc(SPC) ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5].
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
tc(ICLK) = interface clock cycle time = 1/ƒ(ICLK)
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t c(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)S = 2t c(ICLK) ≥ 100 ns.
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
Data Valid
6
7
SPInSIMO
SPISIMO Data Must
Be Valid
Figure 6-12. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
44
Specifications
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6.14
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
SCIN Isosynchronous Mode Timings - Internal Clock
Table 6-14. Timing Requirements for Internal Clock SCIN Isosynchronous Mode (1) (2) (3) (4)
(see Figure 6-13)
(BAUD + 1)
IS EVEN OR BAUD = 0
(BAUD + 1)
IS ODD AND BAUD ≠ 0
UNIT
MIN
MAX
MIN
MAX
2tc(ICLK)
224 tc(ICLK)
3tc(ICLK)
(224 – 1) tc(ICLK)
ns
tc(SCC)
Cycle time,
SCInCLK
tw(SCCL)
Pulse duration,
SCInCLK low
0.5tc(SCC) – tf
0.5tc(SCC) + 5
0.5tc(SCC) + 0.5tc(ICLK) – tf
0.5tc(SCC) + 0.5tc(ICLK)
ns
tw(SCCH)
Pulse duration,
SCInCLK high
0.5tc(SCC) – tr
0.5tc(SCC) + 5
0.5tc(SCC) – 0.5tc(ICLK) – tr
0.5tc(SCC) – 0.5tc(ICLK)
ns
td(SCCH-TXV)
Delay time,
SCInCLK high to
SCInTX valid
10
ns
tv(TX)
Valid time,
SCInTX data after
SCInCLK low
tsu(RX-SCCL)
tv(SCCL-RX)
(1)
(2)
(3)
(4)
10
tc(SCC) – 10
tc(SCC) – 10
ns
Setup time,
SCInRX before
SCInCLK low
tc(ICLK) + tf + 20
tc(ICLK) + tf + 20
ns
Valid time,
SCInRX data
after SCInCLK
low
–tc(ICLK) + tf + 20
–tc(ICLK) + tf + 20
ns
Not production tested.
BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
tc(ICLK) = interface clock cycle time = 1 / ƒ(ICLK)
For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
tc(SCC)
tw(SCCL)
tw(SCCH)
SCICLK
tv(TX)
td(SCCHĆTXV)
Data Valid
SCITX
tsu(RXĆSCCL)
SCIRX
tv(SCCLĆRX)
Data Valid
NOTE: Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK
falling edge.
Figure 6-13. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
Specifications
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SCIN Isosynchronous Mode Timings - External Clock
Table 6-15. Timing Requirements for External Clock SCIN Isosynchronous Mode (1) (2)
(3)
(see Figure 6-14)
MIN
MAX UNIT
tc(SCC)
Cycle time, SCInCLK (4)
tw(SCCH)
Pulse duration, SCInCLK high
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
tw(SCCL)
Pulse duration, SCInCLK low
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
td(SCCH-TXV)
Delay time, SCInCLK high to SCInTX valid
2tc(ICLK) + 12 + t r
ns
tv(TX)
Valid time, SCInTX data after SCInCLK low
tsu(RX-SCCL)
Setup time, SCInRX before SCInCLK low
tv(SCCL-RX)
Valid time, SCInRX data after SCInCLK low
(1)
(2)
(3)
(4)
8tc(ICLK)
ns
2tc(SCC) – 10
ns
0
ns
2tc(ICLK) + 10
ns
Not production tested.
tc(ICLK) = interface clock cycle time = 1/ƒ(ICLK)
For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
When driving an external SCInCLK, the following must be true: tc(SCC) ≥ 8tc(ICLK).
tc(SCC)
tw(SCCH)
tw(SCCL)
SCICLK
tv(TX)
td(SCCHĆTXV)
Data Valid
SCITX
tsu(RXĆSCCL)
SCIRX
A.
tv(SCCLĆRX)
Data Valid
Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK
falling edge.
Figure 6-14. SCIn Isosynchronous Mode Timing Diagram for External Clock
46
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I2C Timing
6.16
Table 6-16 Assumes testing over recommended operating conditions.
Table 6-16. I2C Signals (SDA and SCL) Switching Characteristics (1) (2)
STANDARD MODE
PARAMETER
MIN
MAX
150
FAST MODE
MIN
MAX
75
150
UNIT
tc(I2CCLK)
Cycle time, I2C module clock
75
tc(SCL)
Cycle time, SCL
10
2.5
µs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
0.6
µs
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated START
condition)
4
0.6
µs
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
250
100
th(SDA-SCLL)
Hold time, SDA valid after SCL low
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
tr(SCL)
Rise time, SCL
1000
20+0.1Cb
(4)
300
ns
tr(SDA)
Rise time, SDA
1000
20+0.1Cb
(4)
300
ns
300
ns
300
For I2C bus devices
0
3.45 (3)
0
4.7
tf(SCL)
Fall time, SCL
300
20+0.1Cb
tf(SDA)
Fall time, SDA
300
20+0.1Cb
(4)
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition)
tw(SP)
Pulse duration, spike (must be suppressed)
Cb
(1)
(2)
(3)
(4)
(4)
4.0
400
µs
µs
0.6
0
Capacitive load for each bus line
ns
0.9
1.3
(4)
ns
ns
µs
50
ns
400
pF
Not production tested.
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
The maximum th(SDA-SCLL) for I2C bus devices needs to be met only if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
C b = The total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.
SDA
tw(SDAH)
tw(SP)
tsu(SDA−SCLH)
tr(SCL)
tw(SCLL)
tsu(SCLH−SDAH)
tw(SCLH)
SCL
tf(SCL)
tc(SCL)
th(SCLL−SDAL)
th(SDA−SCLL)
tsu(SCLH−SDAL)
th(SCLL−SDAL)
Stop
A.
B.
C.
D.
Start
Repeated
Stop
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
The maximum th(SDA-SCLL) needs only be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL
signal.
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250
ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr max + tsu(SDA-SCLH).
Cb = total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.
Figure 6-15. I2C Timings
Specifications
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Standard Can Controller (SCC) Mode Timings
Table 6-17. Dynamic Characteristics for the CANSTX and CANSRX Pins (1)
PARAMETER
td(CANSTX)
Delay time, transmit shift register to CANSTX pin (2)
td(CANSRX)
Delay time, CANSRX pin to receive shift register
(1)
(2)
48
MIN
MAX
UNIT
15
ns
5
ns
Not production tested.
These values do not include the rise/fall times of the output buffer.
Specifications
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6.18
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
Expansion Bus Module Timing
Table 6-18. Expansion Bus Timing Parameters (1)
–55°C ≤ TA ≤ 220°C, 3.0 V ≤ V
CC
≤ 3.6 V (see Figure 6-16 and Figure 6-17)
MIN
MAX
20.8
UNIT
tc(CO)
Cycle time, CLKOUT
td(COH-EBADV)
Delay time, CLKOUT high to EBADDR valid
21.4
ns
ns
th(COH-EBADIV)
Hold time, EBADDR invalid after CLKOUT high
12.4
ns
td(COH-EBOE)
Delay time, CLKOUT high to EBOE fall
11.4
ns
th(COH-EBOEH)
Hold time, EBOE rise after CLKOUT high
11.4
ns
td(COL-EBWR)
Delay time, CLKOUT low to write strobe (EBWR) low
11.3
ns
th(COL-EBWRH)
Hold time, EBWR high after CLKOUT low
11.6
ns
tsu(EBRDATV-COH)
Setup time, EBDATA valid before CLKOUT high (READ) (2)
th(COH-EBRDATIV)
Hold time, EBDATA invalid after CLKOUT high (READ)
15.2
(3)
ns
(–14.7)
ns
td(COL-EBWDATV)
Delay time, CLKOUT low to EBDATA valid (WRITE)
16.1
ns
th(COL-EBWDATIV)
Hold time, EBDATA invalid after CLKOUT low (WRITE)
14.7
ns
td(COH-EBCS0)
Delay, CLKOUT high to EBCS0 fall
13.6
ns
th(COH-EBCS0H)
Hold, EBCS0 rise after CLKOUT high
13.2
ns
tsu(COH-EBHOLDL)
Setup time, EBHOLD low to CLKOUT high (2)
10.9
ns
tsu(COH-EBHOLDH)
Setup time, EBHOLD high to CLKOUT high (2)
10.5
ns
SECONDARY TIMES
(1)
(2)
(3)
Not production tested.
Setup time is the minimum time under worst case conditions. Data with less setup time will not work.
Valid after CLKOUT goes low for write cycles.
Specifications
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tc(CO)
CLKOUT
th(COH-EBADIV)
td(COH-EBADV)
Valid
EBADDR
tsu(EBRDATV-COH)
th(COH-EBRDATIV)
Valid
EBDATA
th(COH-EBOEH)
td(COH-EBOE)
EBOE
td(COH-EBCS0)
th(COH-EBCS0H)
EBCS0
tsu(COH-EBHOLDH)
tsu(COH-EBHOLDL)
EBHOLD
1 Hold State
Figure 6-16. Expansion Memory Signal Timing - Reads
50
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tc(CO)
CLKOUT
th(COH-EBADIV)
td(COH-EBADV)
Valid
EBADDR
th(COL-EBWDATIV)
td(COL-EBWDATV)
Valid
EBDATA
th(COL-EBWRH)
td(COL-EBWR)
EBWR
td(COH-EBCS0)
td(COH-EBCS0)
EBCS0
tsu(COH-EBHOLDH)
tsu(COH-EBHOLDL)
EBHOLD
1 Hold State
Figure 6-17. Expansion Memory Signal Timing - Writes
6.19
Multi-Buffered A-to-D Converter (MibADC)
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that
enhances the A-to-D performance by preventing digital switching noise on the logic circuitry, which could
be present on V SS and V CC , from coupling into the A-to-D analog stage. All A-to-D specifications are
given with respect to AD REFLO unless otherwise noted.
Resolution
10 bits (1024 values)
Monotonic
Assured
00h to 3FFh [00 for VAI ≤ AD REFLO ; 3FF for VAI ≥ AD REFHI ]
Output conversion code
Table 6-19. MibADC Recommended Operating Conditions (1)
MIN
MAX UNIT
ADREFHI
A-to-D high-voltage reference source
VSSAD
VCCAD
V
ADREFLO
A-to-D low-voltage reference source
VSSAD
VCCAD
V
VAI
Analog input voltage
VSSAD – 0.3
VCCAD + 0.3
V
–2
2
(2)
IAIC
(1)
(2)
Analog input clamp current
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
mA
For VCCAD and VSSAD recommended operating conditions, see the "Device Recommended Operating Conditions" table.
Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
Specifications
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Table 6-20. Operating Characteristics over Full Ranges of Recommended Operating Conditions (1) (2) (3)
PARAMETER
RI
DESCRIPTION/CONDITIONS
Analog input resistance
MAX UNIT
500
Ω
10
pF
Sampling
30
pF
250
Analog input capacitance
See Figure 6-18.
IAIL
Analog input leakage current
See Figure 6-18.
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
CR
Conversion range over which
specified accuracy is maintained
ADREFHI - ADREFLO
EDNL
Differential nonlinearity error
Difference between the actual step width
and the ideal value. See Figure 6-19.
EINL
Integral nonlinearity error
Maximum deviation from the best straight
line through the MibADC. MibADC transfer
characteristics, excluding the quantization
error. See Figure 6-20.
E TOT
Total error/Absolute accuracy
Maximum value of the difference between an
analog value and the ideal midstep value.
See Figure 6-21.
(3)
(4)
TYP
Conversion
See Figure 6-18.
CI
(1)
(2)
MIN
(4)
–1
3
1
µA
5
mA
3.6
V
±1.5
LSB
±2
LSB
±2.5
LSB
Not production tested.
INL and DNL values are valid for a max ADCCLK frequency of 15 MHz. For frequencies greater than 15 MHz missing codes are
expected at higher temperature.
VCCAD = ADREFHI
1 LSB = (ADREFHI - ADREFLO)/210 for the MibADC
External
Rs
MibADC
Input Pin
Ri
Sample Switch
Sample
Capacitor
Parasitic
Capacitance
V src
R leak
Ci
Figure 6-18. MibADC Input Equivalent Circuit
Table 6-21. Multi-Buffer ADC Timing Requirements (1)
MIN
tc(ADCLK)
Cycle time, MibADC clock
td(SH)
Delay time, sample and hold time
td(c)
td(SHC)
(1)
(2)
52
(2)
NOM
MAX UNIT
0.067
µs
1
µs
Delay time, conversion time
0.55
µs
Delay time, total sample/hold and conversion time
1.55
µs
Not production tested.
This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for
more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (SPNU206).
Specifications
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The differential nonlinearity error shown in Figure 6-19 (sometimes referred to as differential linearity) is
the difference between an actual step width and the ideal value of 1 LSB.
!
!
A.
1 LSB = (ADREFHI – ADREFLO) / 210
Figure 6-19. Differential Nonlinearity (DNL)
The integral nonlinearity error shown in Figure 6-20 (sometimes referred to as linearity error) is the
deviation of the values on the actual transfer function from a straight line.
0 ... 111
0 ... 110
Ideal
Transition
0 ... 101
Actual
Transition
0 ... 100
At Transition
011/100
(ć 1/2 LSB)
0 ... 011
0 ... 010
End-Point Lin. Error
0 ... 001
At Transition
001/010 (ć 1/4 LSB)
0 ... 000
0
A.
1
2
3
4
5
Analog Input Value (LSB)
6
7
1 LSB = (ADREFHI – ADREFLO) / 210
Figure 6-20. Integral Nonlinearity (INL) Error
The absolute accuracy or total error of an MibADC as shown in Figure 6-21 is the maximum value of the
difference between an analog value and the ideal midstep value.
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A.
1 LSB = (ADREFHI – ADREFLO) / 210
Figure 6-21. Absolute Accuracy (Total) Error
54
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7 Parameter Measurement Information
IOL
Tester Pin
Electronics
Output
Under
Test
50 Ω
V LOAD
CL
I OH
Where:
A.
B.
IOL
=
IOH
=
VLOAD =
CL
=
IOL MAX for the respective pin (A)
IOH MIN for the respective pin(A)
1.5 V
150-pF typical load-circuit capacitance(B)
For these values, see the Section 6.4.
All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 7-1. Test Load Circuit
7.1
External Reference Resonator/Crystal Oscillator Clock Option
The oscillator is enabled by connecting the appropriate fundamental 4–10 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 7-2 (a). The oscillator is a
single-stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage
test measurement and HALT mode. TI strongly encourages each customer to submit samples of the
device to the resonator/crystal vendors for validation. The vendors are equipped to determine what
load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and
operation over temperature/voltage extremes. Please note that external crystal mode is specified to
function only within the temperature ranges of –40°C to 150°C. Above this recommended
temperature range it is strongly recommended to use an external clock signal as shown in
Figure 7-2 (b).
An external oscillator source can be used by connecting a 1.8-V clock signal to the OSCIN pin and leaving
the OSCOUT pin unconnected (open) as shown in Figure 7-2b.
OSCIN
C1
(A)
OSCIN
OSCOUT
Crystal
"
C2
(A)
!External
Clock Signal
(toggling 0 - VCC)
(b)
(a)
A.
OSCOUT
The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 7-2. Crystal/Clock Connection
Parameter Measurement Information
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8 Detailed Description
8.1
Overview
8.1.1
MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal
to a 10-bit digital value.
The B1M MibADC module can function in two modes: compatibility mode, where its programmer's model
is compatible with the SM470R1x ADC module and its digital results are stored in digital result registers;
or in buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each
conversion group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be
serviced by interrupts or by the DMA.
8.1.1.1
MibADC Event Trigger Enhancements
The MibADC includes two major enhancements over the event-triggering capability of the SM470R1x
ADC.
• Both group 1 and the event group can be configured for event-triggered operation, providing up to two
event-triggered groups.
• The trigger source and polarity can be selected individually for both group1 and the event group from
the options identified in Table 8-1.
Table 8-1. MibADC Event Hookup Configuration
EVENT NO.
SOURCE SELECT BITS FOR G1 OR EVENT
(G1SRC[1:0] OR EVSRC[1:0])
SIGNAL PIN NAME
EVENT1
00
ADEVT
EVENT2
01
HET18
EVENT3
10
Reserved
EVENT4
11
Reserved
For group1, these event-triggered selections are configured via the group 1 source select bits
(G1SRC[1:0]) in the AD event source register (ADEVTSRC[5:4]). For the event group, these eventtriggered selections are configured via the event group source select bits (EVSRC[1:0]) in the AD event
source register (ADEVTSRC[1:0]).
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-toDigital Converter (MibADC) Reference Guide (SPNU206).
8.1.2
JTAG Interface
There are two main test access ports (TAPs) on the device:
• SM470R1x CPU TAP
• Device TAP for factory test
Some of the JTAG pins are shared among these two TAPs. The hookup is illustrated in Figure 8-1.
56
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TMS470R1x CPU
TCK
TCK
TRST
TRST
TMS
TMS
TDI
TDI
TDO
TDO
Factory Test
TCK
TRST
TMS2
TMS
TDI
TDO
Figure 8-1. JTAG Interface
8.1.3
High-End Timer (HET) Timings
8.1.3.1
Minimum PWM Output Pulse Width
This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution
prescale factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of
codes.
Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK
For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33 ns
8.1.3.2
Minimum Input Pulses that can be Captured
The input pulse width must be greater or equal to the low resolution clock period (LRP), that is, the HET
loop (the HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale
factor (lr), which is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2,
4, 8, 16, or 32.
Therefore, the minimum input pulse width = LRP(min) = hr(min) × lr(min)/SYSCLK = 1 × 1/SYSCLK
For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 × 1/30 = 33.33 ns
NOTE
Once the input pulse width is greater than LRP, the resolution of the measurement is still
HRP. (That is, the captured value gives the number of HRP clocks inside the pulse.)
Abbreviations:
hr = HET high resolution divide rate = 1, 2, 3,...63, 64
lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32
High resolution clock period = HRP = hr/SYSCLK
Loop resolution clock period = LRP = hr × lr/SYSCLK
Detailed Description
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8.1.4
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Interrupt Priority (IEM to CIM)
Interrupt requests originating from the B1M peripheral modules (that is, SPI1 or SPI2; SCI1 or SCI2; RTI;
and so forth) are assigned to channels within the 48-channel interrupt expansion module (IEM) where, via
programmable register mapping, these channels are then mapped to the 32-channel central interrupt
manager (CIM) portion of the SYS module.
Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM
channel between sources.
The CIM request channels are maskable so that individual channels can be selectively disabled. All
interrupt requests can be programmed in the CIM to be of either type:
• Fast interrupt request (FIQ)
• Normal interrupt request (IRQ)
The CIM prioritizes interrupts. The precedence of request channels decrease with ascending channel
order in the CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities,
and their associated modules, see Table 8-2.
Table 8-2. Interrupt Priority (IEM and CIM)
MODULES
INTERRUPT SOURCES
DEFAULT CIM INTERRUPT
LEVEL/CHANNEL
IEM CHANNEL
SPI1
SPI1 end-transfer/overrun
0
0
RTI
COMP2 interrupt
1
1
RTI
COMP1 interrupt
2
2
RTI
TAP interrupt
3
3
SPI2
SPI2 end-transfer/overrun
4
4
GIO
GIO interrupt A
5
5
6
6
Reserved
HET
HET interrupt 1
7
7
I2C1
I2C1 interrupt
8
8
SCI1/SCI2
SCI1
SCI1 or SCI2 error interrupt
9
9
SCI1 receive interrupt
10
10
11
11
I2C2 interrupt
12
12
HECC1 interrupt A
13
13
SCC interrupt A
14
14
Reserved
I2C2
HECC1
SCC
Reserved
15
15
MibADC end event conversion
16
16
SCI2
SCI2 receive interrupt
17
17
DMA
DMA interrupt 0
18
18
I2C3
I2C3 interrupt
19
19
SCI1
SCI1 transmit interrupt
20
20
SW interrupt (SSI)
21
21
MibADC
System
Reserved
22
22
HET interrupt 2
23
23
HECC1 interrupt B
24
24
SCC
SCC interrupt B
25
25
SCI2
SCI2 transmit interrupt
26
26
MibADC end Group 1 conversion
27
27
DMA
DMA Interrupt 1
28
28
GIO
GIO interrupt B
29
29
MibADC end Group 2 conversion
30
30
HET
HECC1
MibADC
MibADC
58
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Table 8-2. Interrupt Priority (IEM and CIM) (continued)
MODULES
SCI3
INTERRUPT SOURCES
DEFAULT CIM INTERRUPT
LEVEL/CHANNEL
SCI3 error interrupt
Reserved
IEM CHANNEL
31
31
31
32–37
HECC2
HECC2 interrupt A
31
38
HECC2
HECC2 interrupt B
31
39
SCI3
SCI3 receive interrupt
31
40
SCI3
SCI3 transmit interrupt
31
41
I2C4
I2C4 interrupt
31
42
I2C5
I2C5 interrupt
31
43
31
44–47
Reserved
For more detailed functional information on the IEM, see the TMS470R1x Interrupt Expansion Module
(IEM) Reference Guide (SPNU211). For more detailed functional information on the CIM, see the
TMS470R1x System Module Reference Guide (SPNU189).
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8.1.5
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Expansion Bus Module (EBM)
The expansion bus module (EBM) is a standalone module used to bond out both general-purpose
input/output pins and expansion bus interface pins. This module supports the multiplexing of the GIO and
the expansion bus interface functions. The module also supports 8- and 16- bit expansion bus memory
interface mappings as well as mapping of the following expansion bus signals:
• 27-bit address bus (EBADDR[26:0] for x8, 19-bit address bus (EBADDR[18:0] for x16
• 8- or 16-bit data bus (EBDATA[7:0] or EBDATA[15:0])
• 2 write strobes (EBWR[1:0])
• 2 memory chip selects (EBCS[6:5])
• 1 output enable (EBOE)
• 1 external hold signal for interfacing to slow memories (EBHOLD)
• 1 DMA request line (EBDMAREQ[0])
Table 8-3 shows the multiplexing of I/O signals with the expansion bus interface signals. The mapping of
these pins varies depending on the memory mode.
Table 8-3. Expansion Bus MUX Mapping (1)
EXPANSION BUS MODULE PINS
GIO
(1)
(2)
x8
(2)
x16 (2)
GIOB[0]
EBDMAREQ[0]
EBDMAREQ[0]
GIOC[0]
EBOE
EBOE
GIOC[2:1]
EBWR[1:0]
EBWR[1:0]
GIOC[4:3]
EBCS[6:5]
EBCS[6:5]
GIOD[5:0]
EBADDR[5:0]
EBADDR[5:0]
GIOE[7:0]
EBDATA[7:0]
EBDATA[7:0]
GIOF[7:0]
EBADDR[13:6]
EBDATA[15:8]
GIOG[7:0]
EBADDR[21:14]
EBADDR[13:6]
GIOH[5]
EBHOLD
EBHOLD
I2C5SDA
EBADDR[26]
EBADDR[18]
I2C5SCL
EBADDR[25]
EBADDR[17]
I2C4SCL
EBADDR[24]
EBADDR[16]
I2C4SDA
EBADDR[23]
EBADDR[15]
GIOH[0]
EBADDR[22]
EBADDR[14]
For more detailed information, see theTMS470R1x Expansion Bus Module (EBM) Reference Guide (SPNU222) and the TMS470R1x
General Purpose Input/Output Reference Guide (SPNU192).
X8 refers to size of memory in 8-bits; X16 refers to size of memory in 16-bits.
Table 8-4 lists the names of the expansion bus interface signals and their functions.
Table 8-4. Expansion Bus Pins
PIN
EBDMAREQ
60
DESCRIPTION
Expansion bus DMA request
EBOE
Expansion bus pin enable
EBWR
Expansion bus write strobe EBWR[1] controls EBDATA[15:8] and EBWR[0]
controls EBDATA[7:0]
EBCS
Expansion bus chip select
EBADDR
Expansion bus address pins
EBDATA
Expansion bus data pins
EBHOLD
Expansion bus hold: An external device may assert this signal to add wait
states to an expansion bus transaction.
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SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
Memory
Figure 8-2 shows the memory map of the B1M device.
Memory (4GB)
0xFFFF_FFFF
0xFFF8_0000
0xFFF7_FFFF
SYSTEM with PSA, CIM, RTI,
DEC, DMA, MMC, DWD
System Module Control
Registers
(512KB)
IEM
MSM
Reserved
Peripheral Control Registers
(512KB)
0xFFF0_0000
0xFFEF_FFFF
0xFFE8_C000
0xFFE8_BFFF
0xFFE8_8000
0xFFE8_7FFF
0xFFE8_4021
0xFFE8_4020
0xFFE8_4000
Reserved
Flash Control Registers
Reserved
MPU Control Registers
Reserved (1 MB)
0xFFE0_0000
0x7FFF_FFFF
RAM
(64KB)
Program
and
Data Area
FLASH
(1MB)
2 Banks
16 sectors
HET RAM
(1KB)
0x0000_0024
0x0000_0023
Exception, Interrupt, and
Reset Vectors
0x0000_0000
A.
B.
Reserved
HET
Reserved
SPI1
SCI3
SCI2
SCI1
Reserved
MibADC
ECP
Reserved
EBM
GIO
Reserved
HECC2
Reserved
HECC1
Reserved
HECC2 RAM
Reserved
HECC1 RAM
Reserved
SCC
Reserved
SCC RAM
I2C4
I2C3
I2C2
I2C1
I2C5
SPI2
Reserved
Reserved
FIQ
IRQ
Reserved
Data Abort
Prefetch Abort
Software Interrupt
Undefined Instruction
Reset
0xFFFF_FFFF
0xFFFF_FD00
0xFFFF_FC00
0xFFFF_F700
0xFFF8_0000
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F600
0xFFF7_F500
0xFFF7_F400
0xFFF7_F000
0xFFF7_EF00
0xFFF7_ED00
0xFFF7_EC00
0xFFF7_EA00
0xFFF7_E800
0xFFF7_E600
0xFFF7_E400
0xFFF7_E000
0xFFF7_DC00
0xFFF7_DB00
0xFFF7_DA00
0xFFF7_D900
0xFFF7_D800
0xFFF7_D500
0xFFF7_D400
0xFFF0_0000
0x0000_0023
0x0000_0020
0x0000_001C
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
0x0000_0004
0x0000_0000
Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
The CPU registers are not part of the memory map.
Figure 8-2. SM470R1B1M Memory Map
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Memory Selects
Memory selects allow the user to address memory arrays (that is, flash, RAM, and HET RAM) at userdefined addresses. Each memory select has its own set (low and high) of memory base address registers
(MFBAHRx and MFBALRx) that, together, define the array's starting (base) address, block size, and
protection.
The base address of each memory select is configurable to any memory address boundary that is a
multiple of the decoded block size. For more information on how to control and configure these memory
select registers, see the bus structure and memory sections of the TMS470R1x System Module Reference
Guide (SPNU189).
For the memory selection assignments and the memory selected, see Table 8-5.
Table 8-5. SM470R1B1M Memory Selection Assignment
MEMORY
MEMORY
SELECTED
SELECT
(ALL INTERNAL)
0 (fine)
FLASH/ROM
1 (fine)
FLASH/ROM
2 (fine)
RAM
3 (fine)
RAM
4 (fine)
HET RAM
MEMORY
SIZE (1)
1M
64 K (2)
MPU
MSM
MEMORY BASE ADDRESS
REGISTER
NO
YES
MFBAHR0 and MFBALR0
NO
YES
MFBAHR1 and MFBALR1
YES
YES
MFBAHR2 and MFBALR2
YES
YES
MFBAHR3 and MFBALR3
STATIC MEM
CTL REGISTER
1K
NO
NO
MFBAHR4 and MFBALR4
SMCR1
5 (coarse) CS[5]/GIOC[3]
512K x 8 (512KB)
256K x 16
(512KB)
NO
NO
MCBAHR2 and MCBALR2
SMCR5
6 (coarse) CS[6]/GIOC[4]
512K x 8 (512KB)
256K x 16
(512KB)
NO
NO
MCBAHR3 and MCBALR3
SMCR6
(1)
(2)
x8 refers to size of memory in 8-bits; x16 refers to size of memory in 16-bits.
The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block
size in the memory-base address register.
8.2.1.1
JTAG Security Module
The B1M device includes a JTAG security module to provide maximum security to the memory contents.
The visible unlock code can be in the OTP sector or in the first bank of the user-programmable memory.
For the B1M, the visible unlock code is in the OTP sector at address 0x0000_01F8.
8.2.1.2
Memory Security Module
The B1M device also includes a memory security module (MSM) to provide additional security and
flexibility to the memory contents' protection. The password for unlocking the MSM is located in the four
words just before the flash protection keys.
8.2.1.3
RAM
The B1M device contains 64KB of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This B1M RAM is implemented in one 64KB array
selected by two memory-select signals. This B1M configuration imposes an additional constraint on the
memory map for RAM; the starting addresses for both RAM memory selects cannot be offset from each
other by the multiples of the size of the physical RAM (that is, 64K bytes for the B1M device). The B1M
RAM is addressed through memory selects 2 and 3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the
user finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for
protecting an operating system while allowing access to the current task. For more detailed information on
the MPU portion of the SYS module and memory protection, see the memory section of the TMS470R1x
System Module Reference Guide (SPNU189).
62
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8.2.1.4
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
F05 Flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with
a 32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions. See the Flash read and Flash program and erase sections.
8.2.1.4.1
Flash Protection Keys
The B1M device provides flash protection keys. These four 32-bit protection keys prevent
program/erase/compaction operations from occurring until after the four protection keys have been
matched by the CPU loading the correct user keys into the FMPKEY control register. The protection keys
on the B1M are located in the last 4 words of the first 64K sector.
8.2.1.4.2
Flash Read
The B1M flash memory is configurable by the SYS module to be addressed within the range of
0x0000_0000 to 0xFFE0_0000. The flash is addressed through memory selects 0 and 1.
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and
read).
8.2.1.4.3
Flash Pipeline Mode
When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz (versus a
system clock frequency of 30 MHz in normal mode). Flash in pipeline mode is capable of accessing 64-bit
words and provides two 32-bit pipelined words to the CPU. Also, in pipeline mode the flash can be read
with no wait states when memory addresses are contiguous (after the initial 1- or 2-wait-state reads).
NOTE
After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0). In other
words, the B1M device powers up and comes out of reset in non-pipeline mode.
Furthermore, setting the flash configuration mode bit (GBLCTRL.4) will override pipeline
mode.
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Flash Program and Erase
The B1M device flash contains two 512KB memory arrays (or banks), for a total of 1MB of flash, and
consists of sixteen sectors. These sixteen sectors are sized as follows:
Table 8-6. Sectors
SECTOR
NO.
SEGMENT
LOW ADDRESS
HIGH ADDRESS
OTP
2KB
0x0000_0000
0x0000_007FF
0
64KB
0x0000_0000
0x0000_FFFF
1
64KB
0x0001_0000
0x0001_FFFF
2
64KB
0x0002_0000
0x0002_FFFF
3
64KB
0x0003_0000
0x0003_FFFF
4
64KB
0x0004_0000
0x0004_FFFF
5
64KB
0x0005_0000
0x0005_FFFF
6
64KB
0x0006_0000
0x0006_FFFF
7
64KB
0x0007_0000
0x0007_FFFF
0
64KB
0x0008_0000
0x0008_FFFF
1
64KB
0x0009_0000
0x0009_FFFF
2
64KB
0x000A_0000
0x000A_FFFF
3
64KB
0x000B_0000
0x000B_FFFF
4
64KB
0x000C_0000
0x000C_FFFF
5
64KB
0x000D_0000
0x000D_FFFF
6
64KB
0x000E_0000
0x000E_FFFF
7
64KB
0x000F_0000
0x000F_FFFF
MEMORY ARRAYS
(OR BANKS)
BANK0
(512KB)
BANK1
(512KB)
The minimum size for an erase operation is one sector. The maximum size for a program operation is one
16-bit word.
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and
read).
Execution can occur from one bank while programming/erasing any or all sectors of another bank.
However, execution cannot occur from any sector within a bank that is being programmed or erased.
NOTE
When the OTP sector is enabled, the rest of flash memory is disabled. The OTP memory
can only be read or programmed from code executed out of RAM.
8.2.1.4.5 HET RAM
The B1M device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is
configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The
HET RAM is addressed through memory select 4.
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8.2.1.4.6
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
Peripheral Selects and Base Addresses
The B1M device uses 10 of the 16 peripheral selects to decode the base addresses of the peripherals.
These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme
used by the SYS module.
Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in
Table 8-7.
Table 8-7. B1M Peripherals, System Module, and Flash Base Addresses
CONNECTING MODULE
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
PERIPHERAL SELECTS
SYSTEM
0 x FFFF_FFCC
0 x FFFF_FFFF
N/A
RESERVED
0 x FFFF_FF70
0 x FFFF_FFCB
N/A
DWD
0xFFFF_FF60
0 x FFFF_FF6F
N/A
PSA
0 x FFFF_FF40
0 x FFFF_FF5F
N/A
CIM
0 x FFFF_FF20
0 x FFFF_FF3F
N/A
RTI
0 x FFFF_FF00
0 x FFFF_FF1F
N/A
DMA
0 x FFFF_FE80
0 x FFFF_FEFF
N/A
DEC
0 x FFFF_FE00
0 x FFFF_FE7F
N/A
RESERVED
0xFFFF_FD80
0xFFFF_FDFF
N/A
MMC
0 x FFFF_FD00
0 x FFFF_FD7F
N/A
IEM
0 x FFFF_FC00
0 x FFFF_FCFF
N/A
RESERVED
0 x FFFF_Fb00
0 x FFFF_FBFF
N/A
RESERVED
0 x FFFF_Fa00
0 x FFFF_FAFF
N/A
DMA CMD BUFFER
0 x FFFF_F800
0 x FFFF_F9FF
N/A
MSM
0xFFFF_F700
0xFFFF_F7FF
N/A
RESERVED
0xFFF8_0000
0xFFFF_F6FF
N/A
RESERVED
0 x FFF7_FD00
0xFFF7_FFFF
HET
0xFFF7_FC00
0xFFF7_FCFF
RESERVED
0xFFF7_F900
0xFFF7_FBFF
SPI1
0xFFF7_F800
0xFFF7_F8FF
RESERVED
0xFFF7_F700
0xFFF7_F7FF
SCI3
0xFFF7_F600
0xFFF7_F6FF
SCI2
0XFFF7_F500
0XFFF7_F5FF
SCI1
0xFFF7_F400
0xFFF7_F4FF
RESERVED
0xFFF7_F100
0xFFF7_F3FF
MibADC
0xFFF7_F000
0xFFF7_F0FF
ECP
0xFFF7_EF00
0xFFF7_EFFF
RESERVED
0xFFF7_EE00
0xFFF7_EEFF
EBM
0xFFF7_ED00
0xFFF7_EDFF
GIO
0xFFF7_EC00
0xFFF7_ECFF
0xFFF7_EB00
0xFFF7_EBFF
0xFFF7_EA00
0xFFF7_EAFF
0xFFF7_E900
0xFFF7_E9FF
0xFFF7_E800
0xFFF7_E8FF
0xFFF7_E700
0xFFF7_E7FF
0xFFF7_E600
0xFFF7_E6FF
0xFFF7_E500
0xFFF7_E5FF
0xFFF7_E400
0xFFF7_E4FF
HECC2
HECC1
HECC2 RAM
HECC1 RAM
PS[0]
PS[1]
PS[2]
PS[3]
PS[4]
PS[5]
PS[6]
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Table 8-7. B1M Peripherals, System Module, and Flash Base Addresses (continued)
CONNECTING MODULE
66
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
RESERVED
0xFFF7_E100
0xFFF7_E3FF
SCC
0xFFF7_E000
0xFFF7_E0FF
RESERVED
0xFFF7_DD00
0xFFF7_DFFF
SCC RAM
0xFFF7_DC00
0xFFF7_DCFF
I2C4
0xFFF7_DB00
0xFFF7_DBFF
I2C3
0xFFF7_DA00
0xFFF7_DAFF
I2C2
0xFFF7_D900
0xFFF7_D9FF
I2C1
0xFFF7_D800
0xFFF7_D8FF
RESERVED
0xFFF7_D600
0xFFF7_D7FF
I2C5
0xFFF7_D500
0xFFF7_D5FF
0xFFF7_D4FF
PERIPHERAL SELECTS
PS[7]
PS[8]
PS[9]
PS[10]
SPI2
0xFFF7_D400
RESERVED
0xFFF7_CC00
0xFFF7_D3FF
PS[11] – PS[12]
RESERVED
0xFFF7_C800
0xFFF7_CBFF
PS[13]
RESERVED
0xFFF7_C000
0xFFF7_C7FF
PS[14] – PS[15]
RESERVED
0xFFF0_0000
0xFFF7_BFFF
N/A
FLASH CONTROL REGISTERS
0xFFE8_8000
0xFFE8_BFFF
N/A
RESERVED
0xFFF8_4024
0xFFF8_7FFF
N/A
MPU CONTROL REGISTERS
0xFFE8_4000
0xFFE8_4023
N/A
RESERVED
0xFFF8_0000
0xFFF8_3FFF
N/A
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8.2.1.4.7
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
Direct-Memory Access (DMA)
The direct-memory access (DMA) controller transfers data to and from any specified location in the B1M
memory map (except for restricted memory locations like the system control registers area). The DMA
manages up to 16 channels, and supports data transfer for both on-chip and off-chip memories and
peripherals. The DMA controller is connected to both the CPU and peripheral buses, enabling these data
transfers to occur in parallel with CPU activity and thus maximizing overall system performance.
Although the DMA controller has two possible configurations, for the B1M device, the DMA controller
configuration is 32 control packets and 16 channels.
For the B1M DMA request hardwired configuration, see Table 8-8.
Table 8-8. DMA Request Lines Connections (1)
MODULES
DMA REQUEST INTERRUPT SOURCES
Expansion Bus DMA request
EBDMAREQ[0]
DMAREQ[0]
SPI1/I2C4
SPI1 end-receive/I2C4 read
SPI1DMA0/I2C4DMA0
DMAREQ[1]
SPI1/I2C4
SPI1 end-transmit/I2C4 write
SPI1DMA1/I2C4DMA1
DMAREQ[2]
MibADC/I2C1
ADC EV/I2C1 read
MibADCDMA0/I2C1DMA0
DMAREQ[3]
MibADC/SCI1/I2C5
ADC G1/SCI1 end-receive/I2C5 read
MibADCDMA1/SCI1DMA0/I2C5DMA0
DMAREQ[4]
MibADC/SCI1/I2C5
ADC G2/SCI1 end-transmit/I2C5 write
MibADCDMA2/SCI1DMA1/I2C5DMA1
DMAREQ[5]
I2C1
I2C1 write
I2C1DMA1
DMAREQ[6]
SCI3/SPI2
SCI3 end-receive/SPI2 end-receive
SCI3DMA0/SPI2DMA0
DMAREQ[7]
SCI3/SPI2
SCI3 end-transmit/SPI2 end-transmit
SCI3DMA01SPI2DMA1
DMAREQ[8]
I2C2
I2C2 read end-receive
I2C2DMA0
DMAREQ[9]
I2C2
I2C2 write end-transmit
I2C2DMA1
DMAREQ[10]
I2C3
I2C3 read
I2C3DMA0
DMAREQ[11]
I2C3
I2C3 write
I2C3DMA1
DMAREQ[12]
SCI2
SCI2 end-receive
SCI2DMA0
DMAREQ[14]
SCI2
SCI2 end-transmit
SCI2DMA1
DMAREQ[15]
Reserved
(1)
DMA CHANNEL
EBM
DMAREQ[13]
For DMA channels with more than one assigned request source, only one of the sources listed can be the DMA request generator in a
given application. The device has software control to ensure that there are no conflicts between requesting modules.
Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and
generate periodic interrupts so that the data can be read by the CPU. The control packets allow for the
interrupt enable, and the channels determine the priority level of the interrupt.
DMA transfers occur in one of two modes:
• Non-request mode (used when transferring from memory to memory)
• Request mode (used when transferring from memory to peripheral)
For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory
Access (DMA) Controller Reference Guide (SPNU194).
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9 Device and Documentation Support
9.1
9.1.1
Device Support
Device Identification Code Register
The device identification code register identifies the silicon version, the technology family (TF), a ROM or
flash device, and an assigned device-specific part number (see Table 9-1). The B1M device identification
code register value is 0xnA5F.
Figure 9-1. SM470 Device ID Bit Allocation Register [offset = 0xFFFF_FFF0h]
31
30
29
28
27
26
25
24
23
Reserved
15
14
13
VERSION
R-K
12
11
TF
R-K
10
R/F
R-K
9
8
7
22
21
20
19
18
17
16
6
5
PART NUMBER
R-K
4
3
2
1
R-1
1
1
R-1
0
1
R-1
LEGEND:
For bits 3-15: R = Read only, -K = Value constant after RESET.
For bits 0-2: R = Read only, -1 = Value after RESET.
Table 9-1. SM470 Device ID Bit Allocation Register Field Descriptions
BIT
FIELD
VALUE DESCRIPTION
31-16
Reserved
Reads are undefined and writes have no effect.
15-12
VERSION
Silicon version (revision) bits
These bits identify the silicon version of the device.
TF
Technology family bit
This bit distinguishes the technology family core power supply:
11
10
0
3.3 V for F10/C10 devices
1
1.8 V for F05/C05 devices
R/F
ROM/flash bit
This bit distinguishes between ROM and flash devices:
0
Flash device
1
ROM device
9-3
PART NUMBER
Device-specific part number bits
These bits identify the assigned device-specific part number. The assigned device-specific part
number for the B1M device is 1001011.
2-0
1
Mandatory High
Bits 2, 1, and 0 are tied high by default.
9.1.2
Timing Parameter Symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
68
CM
Compaction, CMPCT
RD
Read
CO
CLKOUT
RST
Reset, RST
ER
Erase
RX
SCInRX
ICLK
Interface clock
S
Slave mode
M
Master mode
SCC
SCInCLK
OSC, OSCI OSCIN
SIMO
SPInSIMO
OSCO
OSCOUT
SOMI
SPInSOMI
P
Program, PROG
SPC
SPInCLK
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R
Ready
SYS
System clock
R0
Read margin 0, RDMRGN0
TX
SCInTX
R1
Read margin 1, RDMRGN1
Lowercase subscripts and their meanings are:
a
access time
r
rise time
c
cycle time (period)
su
setup time
d
delay time
t
transition time
f
fall time
v
valid time
h
hold time
w
pulse duration (width)
The following additional letters are used with these meanings:
9.2
H
High
X
Unknown, changing, or don't care
level
L
Low
Z
High impedance
V
Valid
Development Support
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of the SM470R1B1M-HT device applications:
Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any SM470R1B1M-HT device application.
Hardware Development Tools: Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for the SM470R1B1M-HT platform, visit the Texas
Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field
sales office or authorized distributor.
9.3
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (for example, TMS470R1B1M). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification
SM
Fully qualified production device
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Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
Figure 9-2 illustrates the numbering and symbol nomenclature for the SM470R1x family.
SM
470 R1 B
1M
KGD
S
1
1 = KGD revision
PREFIX
TMS = Fully Qualified Device
FAMILY
470 = TMS470 RISC − Embedded
Microcontroller Family
TEMPERATURE RANGE
S = −55°C − 220°C
PACKAGE TYPE
KGD = Known Good Die
ARCHITECTURE
R1 = ARM7TDM1 CPU
DEVICE TYPE B
With 1024K−Bytes Flash Memory:
60−MHZ Frequency
1.8-V Core, 3.3-V I/O
Flash Program Memory
ZPLL Clock
64K−Byte Static RAM
1K−Byte HET RAM (64 Instructions)
AWD
DWD
RTI
10−Bit, 12−Input MibADC
Two SPI Modules
Three SCI Modules
Two High−End CAN HECC
HET, 16 Channels
ECP
IEM
DMA
Five I2C Modules
EMB
MSM
REVISION CHANGE
Blank = Original
FLASH MEMORY
1M = 1024K−Bytes Flash Memory
Figure 9-2. SM470R1x Family Nomenclature
70
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9.4
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
Documentation Support
Extensive documentation supports all of the SM470 microcontroller family generation of devices. The
types of documentation available include data sheets with design specifications; complete user's guides
for all devices and development support tools; and hardware and software applications. Useful reference
documentation includes:
• Bulletin
– TMS470 Microcontroller Family Product Bulletin (SPNB086)
• User's Guides
– TMS470R1x System Module Reference Guide (SPNU189)
– TMS470R1x General Purpose Input/Output (GIO) Reference Guide (SPNU192)
– TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (SPNU194)
– TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (SPNU194)
– TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (SPNU195)
– TMS470R1x Serial Communication Interface (SCI) Reference Guide (SPNU196)
– TMS470R1x Controller Area Network (CAN) Reference Guide (SPNU197)
– TMS470R1x High End Timer (HET) Reference Guide (SPNU199)
– TMS470R1x External Clock Prescale (ECP) Reference Guide (SPNU202)
– TMS470R1x MultiBuffered Analog to Digital (MibADC) Reference Guide (SPNU206)
– TMS470R1x Zero Pin Phase Locked Loop (ZPLL) Clock Module Reference Guide (SPNU212)
– TMS470R1x Digital Watchdog Timer Reference Guide (SPNU244)
– TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (SPNU211)
– TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (SPNU214)
– TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (SPNU218)
– TMS470R1x Expansion Bus Module (EBM) Reference Guide (SPNU222)
– TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (SPNU223)
– TMS470R1x JTAG Security Module (JSM) Reference Guide (SPNU245)
– TMS470R1x Memory Security Module (MSM) Reference Guide (SPNU246)
– TMS470 Peripherals Overview Reference Guide (SPNU248)
• Errata Sheet
– TMS470R1B1M TMS470 Microcontrollers Silicon Errata (SPNZ139)
9.5
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
9.6
Trademarks
E2E is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All other trademarks are the property of their respective owners.
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9.7
www.ti.com
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.8
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
72
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10 Mechanical Packaging and Orderable Information
10.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2009–2015, Texas Instruments Incorporated
Mechanical Packaging and Orderable Information
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Jan-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SM470R1B1MHFQS
ACTIVE
CFP
HFQ
84
1
TBD
AU
N / A for Pkg Type
-55 to 220
SM470R1B1
MHFQS
SM470R1B1MHKPS
ACTIVE
CFP
HKP
84
10
TBD
Call TI
N / A for Pkg Type
-55 to 220
SM470R1B1
MHKPS
SM470R1B1MKGDS1
ACTIVE
XCEPT
KGD
0
36
Green (RoHS
& no Sb/Br)
Call TI
N / A for Pkg Type
-55 to 220
SM470R1B1MPGES
ACTIVE
LQFP
PGE
144
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-55 to 150
R1B1MPGES
SM470
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jan-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147 / C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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