Texas Instruments | TLIN1021-Q1-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake (Rev. A) | Datasheet | Texas Instruments TLIN1021-Q1-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake (Rev. A) Datasheet

Texas Instruments TLIN1021-Q1-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake (Rev. A) Datasheet
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TLIN1021-Q1
SLLSEU9A – JUNE 2019 – REVISED DECEMBER 2019
TLIN1021-Q1-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake
1 Features
3 Description
•
•
The TLIN1021-Q1 is a local interconnect network
(LIN) physical layer transceiver. LIN is a low speed
universal asynchronous receiver transmitter (UART)
communication protocol that supports automotive invehicle networking.
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•
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•
•
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•
•
•
•
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The TLIN1021-Q1 transmitter supports data rates up
to 20 kbps and the receiver supports data rates up to
100 kbps for faster end-of-line programming. The
TLIN1021-Q1 controls the state of the LIN bus via the
TXD pin and reports the state of the bus on its opendrain RXD output pin. The device has a currentlimited
wave-shaping
driver
to
reduce
electromagnetic emissions (EME).
The TLIN1021-Q1 is designed to support 12-V
applications with a wide input voltage operating range
and also supports low-power sleep mode. The device
supports wake-up from low-power mode via wake
over LIN, the WAKE pin, or the EN pin. The device
allows for system-level reductions in battery current
consumption by selectively enabling the various
power supplies that may be present on a node
through the TLIN1021-Q1 INH output pin.
The TLIN1021-Q1 integrates a resistor for LIN slave
applications, ESD protection, and fault protection
which allow for a reduced amount of external
components in the applications. The device prevents
back-feed current through LIN to the supply input in
case of a ground shift or supply voltage
disconnection.
Device Information(1)
PART NUMBER
TLIN1021-Q1
PACKAGE
BODY SIZE (NOM)
SOIC (D)
4.90 mm x 3.91 mm
VSON (DRB)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Master Node Schematic
VBAT = 12 V
SW
3k
VIN
Voltage Regulator
EN
VDD
33 k
AEC-Q100 qualified for automotive applications
Compliant to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A
and ISO 17987–4 Electrical physical layer (EPL)
specification
Compliant to SAE J2602-1 LIN Network for
Vehicle Applications and SAE J2602-2 LIN
Network for Vehicle Applications Conformance
Test
Support for 12-V applications
Wide input operational voltage range:
– VSUP range from 4.5 V to 36 V
LIN transmit data rate up to 20 kbps
LIN receive data rate up to 100 kbps
Operating modes:
– Normal mode
– Low-power standby mode
– Low-power sleep mode
Low-power mode wake-up support with source
recognition:
– Remote wake-up over the LIN bus
– Local wake-up via the WAKE pin
– Local wake-up via EN
5-V tolerant input-level support
Integrated 45-kΩ LIN pull-up resistor
Control of system-level power using the INH pin
Power-up/down glitch-free operation on LIN bus
and RXD output
Protection features: ±45-V LIN bus fault tolerant,
42-V load dump support, IEC ESD protection,
undervoltage protection on VSUP input, TXD
dominant state time-out, thermal shutdown,
unpowered node or ground disconnection fail-safe
at system level
Junction temperatures from -40ºC to 150ºC
Available in the SOIC (8) and VSON (8) package
with improved automated optical inspection (AOI)
capability
VDD
INH
VDD
2 Applications
EN
I/O
WAKE VSUP
8
3
7
2
VDD
•
•
•
•
•
Body Electronics and Lighting
Infotainment and Cluster
Hybrid Electric Vehicles and Power Train Systems
Passive Safety
Appliances
MCU
LIN Controller
or
SCI/UART
GND
1 NŸ
TLIN1021
RXD
TXD
Master Node
Pullup
LIN Bus
1
6
LIN
1
220 pF
4
5
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLIN1021-Q1
SLLSEU9A – JUNE 2019 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
9
1
1
1
2
3
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Thermal Information .................................................. 6
Recommended Operating Conditions....................... 6
Power Supply Characteristics ................................... 6
Electrical Characteristics........................................... 7
AC Switching Characteristics.................................... 8
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 11
Detailed Description ............................................ 21
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
21
22
22
26
10 Application and Implementation........................ 30
10.1 Application Information.......................................... 30
10.2 Typical Application ............................................... 30
11 Power Supply Recommendations ..................... 31
12 Layout................................................................... 32
12.1 Layout Guidelines ................................................. 32
12.2 Layout Example .................................................... 32
13 Device and Documentation Support ................. 33
13.1
13.2
13.3
13.4
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
14 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2018) to Revision A
•
2
Page
Changed the device status From: Advanced Information To: Production data ..................................................................... 1
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5 Description (continued)
The TLIN1021-Q1 also includes undervoltage detection, temperature shutdown protection, and loss-of-ground
protection. In the event of a fault condition, the transmitter is immediately switched off and remains off until the
fault condition is removed.
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SLLSEU9A – JUNE 2019 – REVISED DECEMBER 2019
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6 Pin Configuration and Functions
D Package
8-Pin (SOIC)
Top View
DRB Package
8-Pin (VSON)
Top View
RX D
1
8
INH
EN
2
7
VSUP
WAK E
3
6
LIN
TX D
4
5
GND
RX D
1
EN
2
WAK E
3
TX D
4
Th ermal
Pad
8
INH
7
VSUP
6
LIN
5
GND
No t to scale
No t to scale
Pin Functions
PIN
NAME
TYPE
NO.
DESCRIPTION
RXD
1
Digital
LIN receive data output, open-drain
EN
2
Digital
Sleep mode control input, integrated pull-down
WAKE
3
High Voltage
TXD
4
Digital
LIN transmit data input, integrated pulled down - active low after a local wake-up event
GND
5
GND
Ground connection
LIN
6
Bus IO
LIN bus input/output line
VSUP
7
Supply
High-voltage supply from the battery
INH
8
High Voltage
Thermal
Pad
4
—
Local wake-up input, high voltage
Inhibit output to control system voltage regulators and supplies, high voltage
Electrically connected to GND, connect the thermal pad to the printed circuit board
(PCB) ground plane for thermal relief
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VSUP
Supply voltage range (ISO 17987)
–0.3
45
UNIT
V
VLIN
LIN Bus input voltage (ISO 17987)
–45
45
V
VWAKE
WAKE pin input voltage
–0.3
45
V
V
V
VINH
INH pin output voltage
–0.3
45 and VO ≤
VSUP+0.3
VLOGIC_INPUT
Logic input voltage
–0.3
6
VLOGIC_OUTPUT
Logic output voltage
–0.3
6
V
IO
Digital pin output current
8
mA
IO(INH)
Inhibit output current
4
mA
IO(WAKE)
WAKE output current due to ground shift (VWAKE ≤
VGND) – 0.3 V thus current out of the WAKE pin
must be limited
3
mA
TJ
Junction Temp
–55
165
°C
Tstg
Storage temperature
-65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
VESD
Electrostatic discharge
Non-synchronous transient
injection
Human body model (HBM) classification level 3B: VSUP, INH, and WAKE with respect
to ground
±8000
Human body model (HBM) classification level 3B: LIN with respect to ground
±10000
Human body model (HBM) classification level 3A: all other pins, per AEC Q100-002 (1)
±4000
Charged device model (CDM) classification
level C5, per AEC Q100-011
All pins
±750
LIN, VSUP, WAKE terminal to GND (2)
IEC 62228-3 per ISO 10605
Contact discharge
R = 330 Ω, C = 150 pF (IEC 61000-4-2)
±8000
LIN terminal to GND (2)
IEC 62228-3 per ISO 10605
Indirect contact discharge
R = 330 Ω, C = 150 pF (IEC 61000-4-2)
±8000
LIN terminal to GND (3)
SAE J2962-1 per ISO 10605
Contact discharge
±8000
LIN terminal to GND (3)
SAE J2962-1 per ISO 10605
Air discharge
±25000
IEC 62228-3 per IEC 62215-3
12 V electrical systems
Pulse 1
-100
IEC 62228-3 per IEC 62215-3
12 V electrical systems
Pulse 2
75
IEC 62228-3 per IEC 62215-3
12 V electrical systems
Pulse 3a
-150
IEC 62228-3 per IEC 62215-3
12 V electrical systems
Pulse 3b
150
SAE J2962-1 per ISO 7637-3
DCC - Slow transient pulse
±85
LIN, VSUP, WAKE terminal to GND
VTRAN
Direct capacitor coupling
(1)
(2)
(3)
LIN terminal to GND (3)
(2)
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Results given here are specific to the IEC 62228-2 Integrated circuits – EMC evaluation of transceivers – Part 2: LIN transceivers.
Testing performed by OEM approved independent 3rd party, EMC report available upon request.
Results given here are specific to the SAE J2962-1 Communication Transceivers Qualification Requirements - LIN. Testing performed
by OEM approved independent 3rd party, EMC report available upon request.
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7.3 Thermal Information
TLIN1021-Q1
THERMAL METRIC (1)
D (SOIC)
DRB (VSON)
PINS
PINS
UNIT
53.3
°C/W
RθJA
Junction-to-ambient thermal resistance
125.3
RθJC(top)
Junction-to-case (top) thermal resistance
65.4
60
°C/W
RθJB
Junction-to-board thermal resistance
68.7
25.6
°C/W
ΨJT
Junction-to-top characterization parameter
17.6
1.8
°C/W
ΨJB
Junction-to-board characterization parameter
68.0
25.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
–
9.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Recommended Operating Conditions
parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted)
MIN
VSUP
Supply Voltage
VLIN
NOM
MAX
UNIT
4.5
36
V
LIN Bus input voltage
0
36
V
VLOGIC
Logic Pin Voltage
0
5.25
V
TJ
Operating virtual junction temperature range
-40
150
°C
TSDR
Thermal shutdown rising
160
TSDF
Thermal shutdown falling
TSD(HYS)
Thermal shutdown hysteresis
°C
150
°C
10
°C
7.5 Power Supply Characteristics
parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Voltage and Current
Operational supply voltage
ISO 17987 Param 10
VSUP
Nominal supply voltage
ISO 17987 Param 10
Supply current
Bus dominant
Supply current
Bus recessive
ISUP
Supply current
Sleep mode
Device is operational beyond the LIN
defined nominal supply voltage range
See Figure 8 and Figure 9
4.5
36
V
Normal and standby modes (1)
See Figure 8 and Figure 9
4.5
36
V
Sleep mode
4.5
36
V
Normal mode
EN = VCC, RLIN ≥ 500 Ω, CLIN ≤ 10 nF, INH =
WAKE = VSUP
1.2
6.5
mA
Standby mode
EN = 0 V, RLIN ≥ 500 Ω, CLIN ≤ 10 nF, INH =
WAKE = VSUP
1
1.7
mA
Normal mode
EN = VCC, INH = WAKE = VSUP
300
700
µA
Standby mode
EN = 0 V, INH = WAKE = VSUP
20
55
µA
9
16
µA
22
µA
4.45
V
4.5 V < VSUP ≤ 14 V, TJ = 125℃
EN = 0 V, LIN = WAKE = VSUP, TXD and
RXD floating
14 V < VSUP ≤ 36 V, TJ = 125℃
EN = 0 V, LIN = WAKE = VSUP, TXD and
RXD floating
UVSUPR
Under voltage VSUP threshold
Ramp up
UVSUPF
Under voltage VSUP threshold
Ramp down
UVHYS
Delta hysteresis voltage for VSUP under voltage threshold
(1)
6
4.15
3.5
4
V
0.13
V
Normal mode ramp VSUP while LIN signal is a 10 kHz square wave with 50% duty cycle and 18 V swing.
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7.6 Electrical Characteristics
parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RXD Output Terminal
VOL
Low-level voltage
Based upon external pull-up to VCC (1)
IOL
Low-level output current, open drain
LIN = 0 V, RXD = 0.4 V
1.5
ILKG
Leakage current, high-level
LIN = VSUP, RXD = VCC
–5
0.6
V
mA
5
µA
0.8
V
TXD Input Terminal
VIL
Low-level input voltage
VIH
High-level input voltage
ILKG
Low-level input leakage current
TXD = 0 V
–5
5
µA
ITXD(WAKE)
Local wake-up source recognition TXD (2)
Standby mode after a local wake-up event
VLIN = VSUP, WAKE = 0 V or VSUP, TXD = 1
V
1.3
8
mA
RTXD
Internal pull-down resistor value
800
kΩ
V
2
125
V
350
EN Input Terminal
VIL
Low-level input voltage
–0.3
0.8
VIH
High-level input voltage
2
5.25
V
VHYS
Hysteresis voltage
By design and characterization
30
500
mV
IIL
Low-level input current
EN = 0 V
5
µA
REN
Internal pull-down resistor
800
kΩ
–5
125
350
LIN Terminal (Referenced to VSUP)
VOH
LIN recessive high-level output voltage
TXD = VCC, IO = 0 mA, VSUP = 7 V to 36 V
0.85
VOH
LIN recessive high-level output voltage
TXD = VCC, IO = 0 mA, 4.5 V ≤ VSUP ≤ 7 V
3
VSUP
VOL
LIN dominant low-level output voltage
TXD = 0 V, VSUP = 7 V to 36 V
0.2
VSUP
VOL
LIN dominant low-level output voltage
TXD = 0 V, 4.5 V ≤ VSUP ≤ 7 V
1.2
V
VSUP_NON_OP
VSUP where impact of recessive LIN bus < 5%
ISO 17987 Param 11
TXD & RXD open LIN = 4.5 V to 45 V
42
V
IBUS(LIM)
Limiting current
ISO 17987 Param 12
TXD = 0 V, VLIN = 18 V, RMEAS = 440 Ω,
VSUP = 18 V, VBUSdom < 4.518 V
See Figure 13
40
200
mA
IBUS_PAS_dom
Receiver leakage current, dominant
ISO 17987 Param 13
Driver off/recessive, LIN = 0 V, VSUP = 12 V
See Figure 14
–1
IBUS_PAS_rec1
Receiver leakage current, recessive
ISO 17987 Param 14
Driver off/recessive, LIN ≥ VSUP, 4.5 V ≤
VSUP ≤ 36 V
See Figure 15
IBUS_PAS_rec2
Receiver leakage current, recessive
ISO 17987 Param 14
Driver off/recessive, LIN = VSUP
See Figure 15
IBUS_NO_GND
Leakage current, loss of ground
ISO 17987 Param 15
GND = VSUP = 18 V, 0 V ≤ VLIN ≤ 18 V
See Figure 16
IBUS_NO_BAT
Leakage current, loss of supply
ISO 17987 Param 16
VSUP = GND, 0 V ≤ VLIN ≤ 18 V
See Figure 17
VBUSdom
Low-level input voltage
ISO 17987 Param 17
LIN dominant (including LIN dominant for
wake up)
See Figure 10 and Figure 11
VBUSrec
High-level input voltage
ISO 17987 Param 18
Lin recessive
See Figure 10 and Figure 11
VBUS_CNT
Receiver center threshold
ISO 17987 Param 19
VBUS_CNT = (VBUSrec + VBUSdom)/2
See Figure 10 and Figure 11
VHYS
Hysteresis voltage
ISO 17987 Param 20
VHYS = VBUSrec - VBUSdom
See Figure 10 and Figure 11
VSERIAL_DIODE
Serial diode LIN termination pull-up path
ISERIAL_DIODE = 10 µA
0.4
0.7
1.0
V
RSLAVE
Pull-up resistor to VSUP
Normal and standby modes
20
45
60
kΩ
IRSLEEP
Pull-up current source to VSUP sleep mode
VSUP = 14 V, LIN = GND
–1.5
µA
CLIN
Capacitance of the LIN pin
45
pF
V
–0.3
90
mA
20
µA
–5
5
µA
–1
1
mA
5
µA
0.4
0.6
0.475
–20
VSUP
VSUP
0.5
0.525
VSUP
0.175
VSUP
INH Output Terminal
(1)
(2)
RXD uses open drain output structure therefore VOL level is based upon microcontroller supply voltage.
Open drain-drive
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Electrical Characteristics (continued)
parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ΔVH
High level voltage drop INH with respect to VSUP
IINH = - 0.5 mA
ILKG(INH)
Leakage current sleep mode
INH = 0 V
MIN
TYP
MAX
0.5
1
V
0.5
µA
–0.5
UNIT
WAKE Input Terminal
VIH
High-level input voltage
Standby and sleep mode
VIL
Low-level input voltage
Standby and sleep mode
IIH
High-level input leakage current
WAKE = VSUP - 1 V
IIL
Ligh-level input leakage current
WAKE = 1 V
tWAKE
WAKE hold time
Wake up time from sleep mode
VSUP –
1.8
V
VSUP –
3.85
–25
–12.5
15
5
V
µA
25
µA
50
µs
Duty Cycle Characteristics
Duty Cycle 1
ISO 17987 Param 27 (3)
THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 7 V to 18 V, tBIT = 50 µs (20 kbps),
D1 = tBUS_rec(min)/(2 x tBIT)
See Figure 18 and Figure 19
0.396
D112V
Duty Cycle 1
THREC(MAX) = 0.625 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 4.5 V to 7 V, tBIT = 50 µs (20 kbps),
D1 = tBUS_rec(min)/(2 x tBIT)
See Figure 18 and Figure 19
0.396
D212V
Duty Cycle 2
ISO 17987 Param 28
THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP,
VSUP = 4.5 V to 18 V, tBIT = 50 µs (20 kbps),
D2 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 18 and Figure 19
D312V
Duty Cycle 3
ISO 17987 Param 29 (4)
THREC(MAX) = 0.778 x VSUP,
THDOM(MAX) = 0.616 x VSUP,
VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps),
D3 = tBUS_rec(min)/(2 x tBIT)
See Figure 18 and Figure 19
0.417
D312V
Duty Cycle 3
THREC(MAX) = 0.645 x VSUP, THDOM(MAX) =
0.616 x VSUP, VSUP = 4.5 V to 7 V, tBIT = 96
µs (10.4 kbps),
D3 = tBUS_rec(min)/(2 x tBIT)
See Figure 18 and Figure 19
0.417
D412V
Duty Cycle 4
ISO 17987 Param 30
THREC(MIN) = 0.389 x VSUP,
THDOM(MIN) = 0.251 x VSUP,
VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps),
D4 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 18 and Figure 19
0.59
Duty Cycle 4
THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP,
VSUP = 4.5 V to 7 V, tBIT = 96 µs (10.4 kbps),
D4 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 18 and Figure 19
0.59
D112V
D412V
(3)
(4)
0.581
Duty cycle LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF; 1 kΩ / Load2 = 6.8 nF; 660 Ω / Load3 = 10 nF; 500 Ω.
Duty cycles 3 and 4 are defined for 10.4-kbps operation. The TLIN1029 meets these lower data rate requirements while it is also
capable of the higher speed 20-kbps operation as specified by duty cycles 1 and 2. SAE J2602 derives propagation delay equations
from the LIN 2.0 duty cycle definitions, for details see the SAE J2602 specification.
7.7 AC Switching Characteristics
parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Device Switching Characteristics
trx_pdr
Receiver rising propagation delay time
ISO 17987 Param 31
trx_pdf
Receiver falling propagation delay time
ISO 17987 Param 31
8
RRXD = 2.4 kΩ, CRXD = 20 pF
See Figure 20 and Figure 21
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6
µs
6
µs
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AC Switching Characteristics (continued)
parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
trs_sym
Symmetry of receiver propagation delay time
Receiver rising propagation delay time
ISO 17987 Param 32
Rising edge with respect to falling edge
trx_sym = trx_pdf – trx_pdr),
RRXD = 2.4 kΩ, CRXD = 20 pF
See Figure 20 and Figure 21
tLINBUS
Minimum dominant time on LIN bus for wake-up
See Figure 24, Figure 26 and Figure 27
tCLEAR
Time to clear false wake-up prevention logic if
LIN bus had a bus stuck dominant fault
(recessive time on LIN bus to clear bus stuck
dominant fault)
See Figure 27
8
tMODE_CHANGE
Mode change delay time
Time to change from normal mode to sleep
mode through EN pin
See Figure 22
2
tNOMINT
Normal mode initialization time
tPWR
Power-up time
tTXD_DTO
Dominant state time out
(1)
(1)
–2
25
TYP
MAX
UNIT
2
µs
65
150
µs
25
50
µs
15
µs
Time for normal mode to initialize and data
on RXD pin to be valid, includes
tMODE_CHANGE for standby to normal mode.
See Figure 22
45
µs
Time it takes for valid data on RXD upon
power-up
1.5
ms
80
ms
20
50
The transition time from sleep mode to normal mode includes both tMODE_CHANGE and tNOMINT.
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40
0.8
35
0.7
30
0.6
25
0.5
VOL (V)
VOH (V)
7.8 Typical Characteristics
20
15
0.4
0.3
10
0.2
-55
25
125
150
5
-55°C
25°C
125°C
150°C
0.1
0
0
0
5
10
15
20
25
30
35
40
Supply Voltage (V)
0
5
10
15
20
25
30
35
40
Supply Voltage (V)
VOHv
Figure 1. VOH vs VSUP and Temperature
D003
Figure 2. VOL vs VSUP and Temperature
2.5
500
2
450
1.5
400
ISUP (mA)
ISUP (mA)
-55°C
25°C
125°C
150°C
1
0.5
350
300
-55°C
25°C
125°C
150°C
0
250
0
5
10
15
20
25
30
35
40
Supply Voltage (V)
0
5
10
15
20
25
30
35
40
Supply Voltage (V)
D004
Figure 3. ISUP Dominant vs VSUP and Temperature
D005
Figure 4. ISUP Recessive vs VSUP and Temperature
1.2
26
1
24
ISUP (PA)
ISUP (mA)
0.8
0.6
22
20
0.4
18
-55°C
25°C
125°C
150°C
0.2
-55°C
25°C
125°C
150°C
0
16
0
5
10
15
20
25
30
35
Supply Voltage (V)
0
5
10
15
20
25
30
35
Supply Voltage (V)
D006
Figure 5. Standby Mode ISUP Dominant vs VSUP and
Temperature
10
40
40
D007
Figure 6. Standby Mode ISUP Recessive vs VSUP and
Temperature
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Typical Characteristics (continued)
16
ISUP (PA)
14
12
10
8
-55°C
25°C
125°C
150°C
6
0
5
10
15
20
25
30
35
40
Supply Voltage (V)
D009
Figure 7. Sleep Mode ISUP vs VSUP and Temperature
8 Parameter Measurement Information
1
INH
RXD
8
5V
2
EN
3
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
7
VSUP
WAKE
6
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
LIN
4
TXD
5
GND
Measurement Tools
O-scope:
DMM
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Figure 8. Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10
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Parameter Measurement Information (continued)
Trigger Point
Delta t = + 5 µs (tBIT = 50 µs)
RX
2 * tBIT = 100 µs (20 kBaud)
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Figure 9. RX Response: Operating Voltage Range
A
Period T = 1/f
Amplitude
(signal range)
LIN Bus Input
Frequency: f = 20 Hz
Symmetry: 50%
Copyright © 2019, Texas Instruments Incorporated
Figure 10. LIN Bus Input Signal
1
INH
RXD
8
5V
2
VSUP
EN
7
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
6
3
WAKE
4
TXD
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
LIN
5
GND
Measurement Tools
O-scope:
DMM
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Figure 11. LIN Receiver Test with RX access Param 17, 18, 19, 20
12
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Parameter Measurement Information (continued)
1
RXD
INH
EN
VSUP
8
5V
Power Supply 1
Resolution: 10mV/ 1mA
VPS1 Accuracy: 0.2%
7
2
D
3
4
6
WAKE
LIN
Power Supply 2
Resolution: 10mV/ 1mA
VPS2 Accuracy: 0.2%
5
TXD
GND
RBUS
Measurement Tools
O-scope:
DMM
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Figure 12. VSUP_NON_OP Param 11
1
RXD
INH
EN
VSUP
8
5V
2
3
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
T = 10 ms
Jitter: < 25 ns
6
WAKE
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
7
RMEAS
LIN
4
TXD
GND
5
Measurement Tools
O-scope:
DMM
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Figure 13. Test Circuit for IBUS_LIM at Dominant State (Driver on) Param 12
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Parameter Measurement Information (continued)
RXD
1
8
INH
5V
2
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
7
VSUP
EN
6
3
WAKE
4
TXD
RMEAS = 499 Ÿ
LIN
5
GND
Measurement Tools
O-scope:
DMM
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Figure 14. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V, Param 13
1
RXD
INH
Power Supply 1
Resolution: 10mV/ 1mA
VPS1
Accuracy: 0.2%
8
5V
7
2
VSUP
EN
6
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS2
5
VPS2 2 V/s ramp [8 V < 18 V]
VDROPR < 20 mV
1 kŸ
3
WAKE
4
TXD
LIN
GND
Measurement Tools
O-scope:
DMM
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Figure 15. Test Circuit for IBUS_PAS_rec Param 14
14
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Parameter Measurement Information (continued)
1
RXD
INH
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
8
5V
VPS1
2
EN
VSUP
7
1 kŸ
6
3
WAKE
4
TXD
LIN
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS2
VPS2 2 V/s ramp [0 V < 18 V]
VDROP1kŸ < 1V
5
GND
Measurement Tools
O-scope:
DMM
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Figure 16. Test Circuit for IBUS_NO_GND Loss of GND
1
INH
RXD
8
5V
7
2
EN
VSUP
10 kŸ
6
3
WAKE
4
TXD
LIN
Power Supply
Resolution: 10mV/ 1mA
VPS Accuracy: 0.2%
VPS 2 V/s ramp [0 V < 18 V]
VDROP10kŸ < 1V
5
GND
Measurement Tools
O-scope:
DMM
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Figure 17. Test Circuit for IBUS_NO_BAT Loss of Battery
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Parameter Measurement Information (continued)
1
INH
RXD
8
5V
2
VSUP
EN
3
6
WAKE
Power Supply 1
Resolution: 10mV/ 1mA
VPS1
Accuracy: 0.2%
7
RMEAS
LIN
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
4
TXD
GND
5
Power Supply 2
Resolution: 10mV/ 1mA
VPS2
Accuracy: 0.2%
Measurement Tools
O-scope:
DMM
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Figure 18. Test Circuit Slope Control and Duty Cycle Param 27, 28, 29, 30
16
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Parameter Measurement Information (continued)
TBIT
TXD (Input)
THREC(MAX)
THDOM(MAX)
LIN Bus
Signal
THREC(MIN)
THDOM(MIN)
D = 50%
D112: 0.744 * VSUP
D312: 0.778 * VSUP
D124: 0.710 * VSUP
D324: 0.744 * VSUP
D112: 0.581 * VSUP
D312: 0.616 * VSUP
D124: 0.554 * VSUP
D324: 0.581 * VSUP
D212: 0.422 * VSUP
D412: 0.389 * VSUP
D224: 0.446 * VSUP
D424: 0.422 * VSUP
D212: 0.284 * VSUP
D412: 0.251 * VSUP
D224: 0.302 * VSUP
D424: 0.284 * VSUP
tBUS_DOM(MAX)
tBUS_REC(MIN)
tBUS_DOM(MIN)
tBUS_REC(MAX)
Thresholds
RX Node 1
VSUP
Thresholds
RX Node 2
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
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Figure 19. Definition of Bus Timing Parameters
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Parameter Measurement Information (continued)
1
INH
RXD
8
5V
2
3
6
WAKE
Power Supply 1
Resolution: 10mV/ 1mA
VPS1
Accuracy: 0.2%
7
VSUP
EN
RMEAS
LIN
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
4
TXD
Frequency: 20 ppm
Jitter: < 25 ns
GND
Power Supply 2
Resolution: 10mV/ 1mA
VPS2
Accuracy: 0.2%
5
Measurement Tools
O-scope:
DMM
Copyright © 2019, Texas Instruments Incorporated
Figure 20. Propagation Delay Test Circuit; Param 31, 32
LIN Bus
Signal
THREC(MAX)
D1: 0.744 * VSUP
D3: 0.778 * VSUP
D124: 0.710 * VSUP
D324: 0.744 * VSUP
THDOM(MAX)
D1: 0.581 * VSUP
D3: 0.616 * VSUP
D124: 0.554 * VSUP
D324: 0.581 * VSUP
D2: 0.422 * VSUP
D4: 0.389 * VSUP
D224: 0.446 * VSUP
D424: 0.422 * VSUP
D2: 0.284 * VSUP
D4: 0.251 * VSUP
D224: 0.302 * VSUP
D424: 0.284 * VSUP
THREC(MIN)
THDOM(MIN)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
VSUP
Thresholds
RX Node 2
trx_pdr(1)
trx_pdf(1)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
Thresholds
RX Node 1
trx_pdr(2)
trx_pdf(2)
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Figure 21. Propagation Delay
18
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Parameter Measurement Information (continued)
Wake Event
tMODE_CHANGE
EN
tMODE_CHANGE
Normal
MODE
RXD
Mirrors Bus
tNOMINT
Transition
Sleep
Standby
Transition
Indeterminate
Ignore
Floating
Wake Request
RXD = Low
Indeterminate Ignore
Normal
Mirrors
Bus
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Figure 22. Mode Transitions
EN
TXD
Weak Internal Pulldown
Weak Internal Pulldown
VSUP
LIN
RXD
Floating
MODE
Sleep
Normal
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Figure 23. Wake-up Through EN
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Parameter Measurement Information (continued)
0.6 x VSUP
LIN
0.6 x VSUP
VSUP
0.4 x VSUP
0.4 x VSUP
t < tLINBUS
TXD
tLINBUS
Weak Internal Pull-down
EN
RXD
Floating
MODE
Sleep
Standby
Normal
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Figure 24. Wake-up through LIN
20
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9 Detailed Description
9.1 Overview
The TLIN1021-Q1 is a local interconnect network (LIN) physical layer transceiver, compliant to LIN 2.0, LIN 2.1,
LIN 2.2, LIN 2.2A, SAE J2602-1, SAE J2602-2, ISO 17987–4, and ISO 17987–7 standards. LIN is a low-speed
universal asynchronous receiver transmitter (UART) communication protocol focused on automotive in-vehicle
networking.
The TLIN1021-Q1 transmitter supports data rates from 2.4 kbps to 20 kbps and the receiver supports data rates
up to 100 kbps for end-of-line programming. The TLIN1021-Q1 controls the state of the LIN bus via the TXD pin
and reports the state of the bus via its open-drain RXD output pin. The LIN protocol data stream on the TXD
input is converted by the TLIN1021-Q1 into a LIN bus signal using an optimized electromagnetic emissions
current-limited wave-shaping driver as outlined by the LIN physical layer specification. The receiver converts the
data stream to logic-level signals that are sent to the microcontroller through the open-drain RXD pin. The LIN
bus has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the
recessive state, the LIN bus is pulled high by the transceivers internal pull-up resistor (45 kΩ) and a series diode.
No external pull-up components are required for slave applications. Master applications require an external pullup resistor (1 kΩ) plus a series diode per the LIN specification.
The TLIN1021-Q1 is designed to support 12 V applications with a wide input voltage operating range and also
supports low-power sleep mode. The device supports wake-up from low-power mode via wake over LIN, the
WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by
selectively enabling the various power supplies that may be present on a node through the TLIN1021-Q1 INH
output pin.
The TLIN1021-Q1 integrates ESD protection and fault protection which allow for a reduction in the required
external components in the applications. The device prevents back-feed current through LIN to the supply input
in case of a ground shift or supply voltage disconnection.
The TLIN1021-Q1 also include undervoltage detection, temperature shutdown protection, and loss-of-ground
protection. In the event of a fault condition, the transmitter is immediately switched off and remains off until the
fault condition is removed.
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9.2 Functional Block Diagram
INH
VSUP/2
RXD
VSUP
Comp
Filter
EN
45 NŸ
350 NŸ
Wake Up
State & Control
VSUP
WAKE
Fault Detection
& Protection
WAKE
Dominant
State
Time-Out
TXD
LIN
DR/
Slope
CTL
350 NŸ
GND
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9.3 Feature Description
9.3.1 LIN
This high voltage input/output pin is the single-wire LIN bus transmitter and receiver. The LIN pin can survive
transient voltages up to 45 V. Reverse currents from the LIN to supply (VSUP) are minimized with blocking diodes,
even in the event of a ground shift or loss of supply (VSUP).
9.3.1.1 LIN Transmitter Characteristics
The LIN transmitter has thresholds and AC switching parameters according to the LIN specification. The
transmitter is a low side transistor with internal current limitation and thermal shutdown. During a thermal
shutdown condition, the transmitter is disabled to protect the device. There is an internal pull-up resistor with a
serial diode structure to VSUP, so no external pull-up components are required for LIN slave applications. An
external pull-up resistor and series diode to VSUP must be added when the device is used for in a master
application per the LIN specification.
9.3.1.2 LIN Receiver Characteristics
The receiver’s characteristic thresholds are proportional to the device supply pin in accordance to the LIN
specification.
The receiver is capable of receiving higher data rates, > 100 kbps, than supported by LIN or SAEJ2602
specifications. This allows the TLIN1021-Q1 to be used for high-speed downloads at the end-of-line production
or other applications. The actual data rate achievable depends on system time constants (bus capacitance and
pull-up resistance) and driver characteristics used in the system.
22
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Feature Description (continued)
9.3.1.2.1 Termination
There is an internal pull-up resistor with a serial diode structure to VSUP, so no external pull-up components are
required for the LIN slave applications. An external pull-up resistor (1 kΩ) and a series diode to VSUP must be
added when the device is used for master node applications as per the LIN specification.
Figure 25 shows a Master Node configuration and how the voltage levels are defined
Simplified Transceiver
VLIN_Bus
VSUP
VSUP/2
RXD
Voltage drop across the
diodes in the pull-up path
VSUP
VBattery
VSUP
Receiver
VLIN_Recessive
Filter
1 kQ
45 kQ
LIN
LIN Bus
TXD
350 kQ
GND
Transmitter
with slope control
VLIN_Dominant
t
Copyright © 2019, Texas Instruments Incorporated
Figure 25. Master Node Configuration with Voltage Levels
9.3.2 TXD
TXD is the interface to the MCU’s LIN protocol controller or SCI and UART that is used to control the state of the
LIN output. When TXD is low the LIN output is dominant (near ground) and when TXD is high the LIN output is
recessive (near VSUP), see Figure 25.
The TXD input structure is compatible with 3.3 V and 5 V microcontroller's and integrates a weak pull-down
resistor. The LIN bus is protected from being stuck dominant through a system failure driving TXD low through
the dominant state timer-out timer. When a change of state on the WAKE pin initiates a local wake-up event the
TXD pin is pulled hard to ground indicating a local wake-up event. The hard pull to ground is released upon the
rising edge on the EN pin. If an external pull-up resistor is added to the TXD pin to the microcontollers IO voltage
then TXD is pulled high to indicate a remote wake-up event.
9.3.3 RXD
RXD is the interface to the MCU’s LIN protocol controller or SCI and UART, which reports the state of the LIN
bus voltage. LIN recessive (near VSUP) is represented by a high level on the RXD and LIN dominant (near
ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage.
This allows the device to be used with 3.3 V and 5 V microcontroller's. If the microcontrollers RXD pin does not
have an integrated pull-up, an external pull-up resistor to the microcontrolers IO supply voltage is required. In
standby mode the RXD pin is driven low to indicate a wake-up request.
9.3.4 VSUP
VSUP is the power supply pin. VSUP is connected to the battery through an external reverse-blocking diode, see
Figure 25. If there is a loss of power at the ECU level, the device has extremely low leakage from the LIN pin,
which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered
(ignition supplied) while the rest of the network remains powered (battery supplied).
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Feature Description (continued)
9.3.5 GND
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift
does not reduce the VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the
device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN
systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains
powered (battery supplied).
9.3.6 EN
EN controls the operational modes of the device. When EN is high the device is in normal operating mode
allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low the device is put into sleep
mode and there are no transmission paths available. The device can enter normal mode only after wake-up. EN
has an internal pull-down resistor to ensure the device remains in low power mode even if EN floats.
9.3.7 WAKE
The WAKE pin is a high-voltage reverse-blocked input used for the local wake-up (LWU) function. This function
is explained further in Local Wake-Up (LWU) via WAKE Input Terminal section. The pin is defaulted to
bidirectional edge trigger, meaning it recognizes a local wake-up (LWU) on a rising or falling edge of WAKE pin
transition.
9.3.8 INH
The TLIN1021-Q1 inhibit, INH, output pin can be used to control the enable of system power-management
devices allowing for a significant reduction in battery quiescent current consumption while the application is in
sleep mode. The INH pin has two states: driven high and high impedance. When the INH pin is driven high the
terminal shows VSUP minus a diode voltage drop. In the high impedance state the output is left floating. The INH
pin is high in the normal and standby modes and is low when in sleep mode. A 100 kΩ load can be added to the
INH output to ensure a fast transition time from the driven high state to the low state and to also force the pin low
when left floating.
The INH terminal should be considered a high-voltage logic terminal and not a power output. Thus should be
used to drive the EN terminal of the systems power-management device and not used as a switch for the powermanagement supply itself. This terminal is not reverse battery protected and thus should not be connected
outside the system module.
9.3.9 Local Faults
The TLIN1021-Q1 has several protection features that are described as follows.
9.3.10 TXD Dominant Time-Out (DTO)
While the LIN driver is in active mode a TXD DTO circuit prevents the local node from blocking network
communication in event of a hardware or software failure where TXD is held dominant longer than the time-out
period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising edge is seen before the
time-out constant of the circuit, tTXD_DTO, expires the LIN driver is disabled releasing the bus line to the recessive
level. This keeps the bus free for communication between other nodes on the network. The LIN driver is reactivated on the next dominant to recessive transition on the TXD terminal, thus clearing the dominant time-out.
During this fault, the transceiver remains in normal mode, the integrated LIN bus pull-up termination remains on,
and the LIN receiver and RXD terminal remain active reflecting the LIN bus data.
The TXD pin has an internal pull-down to ensure the device fails to a known state if TXD is disconnected. If EN
pin is high at power-up the TLIN1021-Q1 enters normal mode. With the internal TXD connected low, the DTO
timer starts. To avoid a tTXD_DTO fault, a recessive signal should be put onto the TXD pin before the tTXD_DTO timer
expires, or the device should be into sleep mode by connecting EN pin low.
24
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Feature Description (continued)
9.3.11 Bus Stuck Dominant System Fault: False Wake-Up Lockout
The TLIN1021-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from
waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus.
If the bus is dominant, the wake-up logic is locked out until a valid recessive on the bus clears the bus stuck
dominant fault, preventing excessive current use, see Figure 26 and Figure 27.
EN
LIN Bus
tLINBUS
< tLINBUS
< tLINBUS
Copyright © 2019, Texas Instruments Incorporated
Figure 26. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wake-up
EN
tLINBUS
tLINBUS
tLINBUS
LIN Bus
tCLEAR
< tCLEAR
Copyright © 2019, Texas Instruments Incorporated
Figure 27. Bus Fault: Entering Sleep Mode With Bus Stuck Dominant Fault, Clearing, and Wake-up
9.3.12 Thermal Shutdown
The TLIN1021-Q1 transmitter is protected by limiting the current. If the junction temperature, TJ, of the device
exceeds the thermal shutdown threshold, TJ > TSDR, the device puts the LIN transmitter into the recessive state.
Once the over temperature fault condition has been removed and the junction temperature has cooled beyond
the hysteresis temperature, the transmitter is re-enabled. During this fault, the transceiver remains in normal
mode, the integrated LIN bus pull-up termination remains on, the LIN receiver and RXD terminal remain active
reflecting the LIN bus data.
9.3.13 Under Voltage on VSUP
The TLIN1021-Q1 contains a power on reset circuit to avoid false bus messages during under voltage conditions
when VSUP is less than UVSUP.
9.3.14 Unpowered Device
In automotive applications some LIN nodes in a system can be unpowered, ignition supplied, while others in the
network remains powered by the battery. The TLIN1021-Q1 has extremely low unpowered leakage current from
the bus so an unpowered node does not affect the network or load it down.
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9.4 Device Functional Modes
The TLIN1021-Q1 has three functional modes of operation: normal, sleep, and standby. The next sections
describe these modes and how the device transitions between the different modes. Figure 28 graphically shows
the relationship while Table 1 shows the state of pins.
Table 1. Operating Modes
MODE
EN
TXD
RXD
INH
LIN BUS
TERMINATIO
N
TRANSMITT
ER
Sleep
Low
Weak pull-down
Floating
Floating
Weak current
pull-up
Off
Standby
Low
weak pull-down if LIN bus wakeup; Strong pull-down if a local
wake-up event (WAKE pin)
Low
High
45 kΩ
Off
Wake-up event detected,
waiting on MCU to set
EN
Normal
High
High: recessive state
Low: dominant state
LIN Bus Data
High
45 kΩ
On
LIN transmission up to
20 kbps
COMMENT
Unpowered System
VSUP < VSUP_UNDER
VSUP < VSUP_UNDER
VSUP > VSUP_UNDER
EN = Low
VSUP < VSUP_UNDER
VSUP > VSUP_UNDER
EN = High
Standby Mode
VSUP < VSUP_UNDER
Normal Mode
Driver: On
RXD: LIN Bus Data
TXD:
High for recessive
Low for dominant
INH: On
LIN termination: 45 kŸ
Driver: Off
RXD: Low
TXD:
weak pull-down for LIN bus wake
Hard pull-down for WAKE pin wake
INH: On
LIN termination: 45 kŸ
Sleep Mode
EN = High
LIN bus wake up or
WAKE pin wake up
EN = Low
EN = High
Driver: Off
RXD: Floating
TXD: Weak pull-down
INH: Off
LIN termination: Weak pull-up
Copyright © 2019, Texas Instruments Incorporated
Figure 28. Operating State Diagram
9.4.1 Normal Mode
The EN pin controls the mode of the device. If the EN pin is high at power-up the device powers-up in normal
mode, if the EN is low at power-up the device powers-up in standby mode. In normal mode the receiver and
transmitter fully operational. The LIN transmitter transmits data from the LIN controller to the LIN bus up to the
LIN specified maximum data rate of 20 kbps. The LIN receiver detects the data stream on the LIN bus up to data
rates of 100 kbps and outputs the data on RXD output for the LIN controller. Upon an EN pin transition from from
low to high the TLIN1021-Q1 transitions from sleep mode to normal mode in t ≥ tNOMINT.
26
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9.4.2 Sleep Mode
Sleep mode is the lowest power mode of the TLIN1021-Q1 and is only entered from normal mode when the EN
pin transitions from high to low for t > tMODE_CHANGE. In sleep mode the LIN driver and receiver are switched off,
the LIN bus is weakly pulled up, an the transceiver cannot send or receive data. The INH pin is switched to a
floating output in sleep mode causing any system power elements controlled by the INH pin to be switched off
thus reducing the system power consumption. While the device is in sleep mode, the following conditions exist:
• The LIN bus driver is disabled and the internal LIN bus termination is switched off to minimize power loss if
LIN is short circuited to ground.
• A weak current pull-up is active to prevent false wake-up events in case an external connection to the LIN
bus is lost.
• The normal receiver is disabled.
• EN input, WAKE pin and LIN wake-up receiver are active.
The TLIN1021-Q1 supports three methods for wake-up from sleep mode:
• Wake-up over the LIN bus via the LIN wake-up receiver.
• Local wake-up via the WAKE pin.
• Local wake-up via the EN pin. The EN pin must be set high for t > tNOMINT in order for the device to wake-up.
9.4.3 Standby Mode
Standby mode is entered whenever a wake-up event occurs through LIN bus or the WAKE pin while the device
is in sleep mode. In standby mode the LIN bus slave termination circuit, 45 kΩ, is on. When a wake-up event
occurs and the TLIN1021-Q1 enters standby mode the RXD pin is driven low signaling the wake-up event to the
LIN controller.
The TLIN1021-Q1 exits standby mode and transitions to normal mode when the EN pin is set high for longer
than tMODE_CHANGE where the normal LIN transmitter and receiver are fully operational and bi-directional
commincation is possible.
9.4.4 Wake-Up Events
There are three ways to wake-up the TLIN1021-Q1 from sleep mode:
• Remote wake-up initiated by the falling edge of a recessive-to-dominant state transition on the LIN bus where
the dominant state is be held than tLINBUS filter time. After the tLINBUS filter time has been met a rising edge on
the LIN bus going from dominant-to-recessive initiates a remote wake-up event. The pattern and tLINBUS filter
time used for the LIN wake-up prevents noise and bus stuck dominant faults from causing false wake
requests.
• A local wake-up event due to the EN pin being set high for t > tMODE_CHANGE.
• A local wake-up event due to a change in voltage level on the WAKE pin for t > tWAKE
9.4.4.1 Local Wake-Up (LWU) via WAKE Input Terminal
The WAKE terminal is a bi-directional high-voltage reverse battery protected input which can be used for local
wake-up (LWU) requests via a voltage transition. A LWU event is triggered on either a low-to-high or high-to-low
transition since it has bi-directional input thresholds. The WAKE pin could be used with a switch to VSUP or to
ground. If the terminal is unused it should be pulled to VSUP or ground to avoid unwanted parasitic wake-up
events. When a LWU event takes place the TXD pin is pulled hard to GND letting the LIN controller know that
the wake-up event was due to the WAKE pin and not a wake over LIN event.
The LWU circuitry is active in standby mode and sleep mode. If a valid LWU event occurs in standby mode the
device remains in standby mode and drive the RXD output low. If a valid LWU event occurs in sleep mode the
device transitions to standby mode and drive the RXD output low. The LWU circuitry is not active in normal
mode. To minimize system level current consumption, the internal bias voltages of the terminal follows the state
on the terminal with a delay of tWAKE(MIN). A constant high level on WAKE has an internal pull-up to VSUP, and a
constant low level on WAKE has an internal pull-down to GND.
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W ” WWAKE
No Wake
UP
www.ti.com
Wake
Threshold
Not Crossed
W • WWAKE
Wake UP
Wake
Local Wake Request
INH
Pull-down
TXD
Latched Low
*
RXD
Mode
Sleep Mode
Standby Mode
Figure 29. Local Wake-Up – Rising Edge
W ” WWAKE
No Wake
UP
Wake
Threshold
Not Crossed
W • WWAKE
Wake UP
Wake
Local Wake Request
INH
Pull-down
TXD
Latched Low
*
RXD
Mode
Sleep Mode
Standby Mode
Copyright © 2019, Texas Instruments Incorporated
Figure 30. Local Wake-Up – Falling Edge
28
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9.4.4.2 Wake-Up Request (RXD)
When the TLIN1021-Q1 encounters a wake-up event from the WAKE pin or the LIN bus the RXD output is driven
low until EN is asserted high and the device enters normal mode. Once the device enters normal mode the
wake-up event is cleared and the RXD output is released. The RXD output is fully operation and reflects the
receiver output from the LIN bus.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TLIN1021-Q1 can be used in both a slave application and a master application in a LIN network.
10.2 Typical Application
The device integrates a 45 kΩ pull-up resistor and series diode for slave applications. For master applications an
external 1 kΩ pull-up resistor with series blocking diode can be used. shows the device being used in both
master and slave applications.
VSUP
SW
GND
VSUP
VDD
EN
VDD
VBAT = 12 V
33 k
INH
I/O
VDD
EN
2 8
MASTER
NODE
3k
VSUP
WAKE
3
7
(4)
Master Node
Pullup(3)
MCU w/o
pullup(2)
VDD I/O
1 NŸ
MCU
TLIN1021
LIN Controller
Or
SCI/UART(1)
6
LIN
1
LIN Bus
VREG
220 pF
RXD
4
TXD
GND
5
VSUP
VREG
SW
GND
VSUP
VDD
EN
VDD
33 k
INH
VDD
I/O
EN
28
SLAVE
NODE
3k
VSUP
WAKE
3 10 µF7
(4)
MCU w/o
pullup(2)
VDD I/O
MCU
TLIN1021
LIN Controller
Or
SCI/UART(1)
1
LIN
220 pF
RXD
TXD
GND
6
4
5
(1) If RXD on MCU or LIN slave has internal pullup; no external pullup resistor is needed.
(2) If RXD on MCU or LIN slave does not have an internal pullup requires external pullup resistor.
(3) Master node applications require and external 1 NŸ SXOOXS UHVLVWRU DQG VHULDO GLRGH.
(4) Decoupling capacitor values are system dependent but usually have 100 nF, 1 —) DQG •10 µF
Copyright © 2019, Texas Instruments Incorporated
Figure 31. Typical LIN Bus
30
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Typical Application (continued)
10.2.1 Design Requirements
The RXD output structure is an open-drain output stage which allows the TLIN1021-Q1 to be used with 3.3-V
and 5-V controllers. If the RXD pin of the controller does not have an integrated pull-up, an external pull-up
resistor to the controllers IO voltage is required. The external pull-up resistor value should be between 1 kΩ to 10
kΩ. The VSUP pin of the device should be decoupled with a 100-nF capacitor by placing it close to the VSUP
supply pin. The system should include additional decoupling on the VSUP line as needed per the application
requirements.
10.2.2 Detailed Design Procedures
10.2.2.1 Normal Mode Application Note
When using the TLIN1021-Q1 in systems which are monitoring the RXD pin for a wake-up request, special care
should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition period
between states as the receivers are switched. The application software should not look for an edge on the RXD
pin indicating a wake-up request until tMODE_CHANGE has been met. This is shown in Figure 22
10.2.2.2 TXD Dominant State Time-Out Application Note
The maximum dominant TXD time allowed by the TXD dominant state time-out limits the minimum possible data
rate of the device. The LIN protocol has different constraints for master and slave applications thus there are
different maximum consecutive dominant bits for each application case thus different minimum data rates.
10.2.3 Application Curves
Figure 32 and Figure 33 show the propagation delay from the TXD pin to the LIN pin for the dominant to
recessive and recessive to dominant edges.
Figure 32. Dominant To Recessive Propagation Delay
Figure 33. Recessive to Dominant Propagation Delay
11 Power Supply Recommendations
The TLIN1021-Q1 was designed to operate directly from a car battery, or any other DC supply ranging from 4.5
V to 36 V. The VSUP pin of the device should be decoupled with a 100-nF capacitor by placing it close to the VSUP
supply pin. The system should include additional decoupling on the VSUP line as needed per the application
requirements.
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12 Layout
In order for your PCB design to be successful, start with design of the protection and filtering circuitry. Because
ESD transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high frequency layout
techniques must be applied during PCB design. Placement at the connector also prevents these noisy events
from propagating further into the PCB and system.
12.1 Layout Guidelines
•
•
•
•
•
•
•
•
Pin 1(RXD): The RXD pin is an open-drain output and requires and external pull-up resistor in the range of 1
kΩ and 10 kΩ to function properly. If the controller paired with the transceiver does not have an integrated
pull-up, an external resistor should be placed between RXD and the supply voltage for the controller.
Pin 2 (EN): EN is an input pin that is used to place the device in low-power sleep mode. If this feature is not
used the pin should be connected to the supply voltage for the controller through a series resistor using a
pull-up value between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pin to limit current
on the digital lines in the case of an over voltage fault.
Pin 3 (WAKE): SW1 is oriented in a low-side configuration which is used to implement a local WAKE event.
The series resistor R5 is needed for protection against over current conditions as it limits the current into the
WAKE pin when the ECU has lost its ground connection. The pull-up resistor R4 is required to provide
sufficient current during stimulation of a WAKE event. In this layout example R4 is set to 3 kΩ and R5 is set
to 33 kΩ.
Pin 4 (TXD): The TXD pin is the transmit input signal to the device from the controller. A series resistor can
be placed to limit the input current to the device in the case of an over-voltage on this pin. A capacitor to
ground can be placed close to the input pin of the device to help filter noise.
Pin 5 (GND): This is the ground connection for the device. This pin should be tied to the ground plane
through a short trace with the use of two vias to limit total return inductance.
Pin 6 (LIN): The LIN pin connects to the TLIN1021-Q1 to the LIN bus. For slave applications a 220 pF
capacitor to ground is implemented. For maser applications an additional series resistor and blocking diode
should be placed between the LIN pin and the VSUP pin, see Figure 31.
Pin 7 (VSUP): This is the supply pin for the device. A 100-nF capacitor should be placed close to the VSUP
supply pin for local power supply decoupling.
Pin 8 (INH):The INH pin is used for system power-management. A 100 kΩ load can be added to the INH
output to ensure a fast transition time from the driven high state to the low state and to also force the pin low
when left floating.
NOTE
All ground and power connections should be made as short as possible and use at least
two vias to minimize the total loop inductance.
12.2 Layout Example
GND
GND
VSUP
RXD
INH
EN
VSUP
R3
INH
C2
VSUP
WAKE
R1
LIN
LIN
To Switch
R2
TXD
GND
C1
Figure 34. Layout Example
32
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13 Device and Documentation Support
13.1 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.2 Trademarks
E2E is a trademark of Texas Instruments.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
PTLIN1021DRBRQ1
ACTIVE
TLIN1021DRBRQ1
TLIN1021DRQ1
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
TBD
Call TI
Call TI
-40 to 125
Device Marking
(4/5)
SON
DRB
8
3000
PREVIEW
SON
DRB
8
3000
TBD
Call TI
Call TI
-40 to 125
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL021
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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13-Dec-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLIN1021DRQ1
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLIN1021DRQ1
SOIC
D
8
2500
533.4
186.0
36.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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