Texas Instruments | TPS6612x Integrated Sink with VBUS LDO Regulator (Rev. B) | Datasheet | Texas Instruments TPS6612x Integrated Sink with VBUS LDO Regulator (Rev. B) Datasheet

Texas Instruments TPS6612x Integrated Sink with VBUS LDO Regulator (Rev. B) Datasheet
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TPS66120, TPS66121
SLVSEW9B – AUGUST 2019 – REVISED DECEMBER 2019
TPS6612x Integrated Sink with VBUS LDO Regulator
1 Features
3 Description
•
The TPS6612x contains an integrated 4-V to 22-V
Sink power path. The power path supports
overtemperature and reverse current protection.
VBUS has overvoltage protection with its level being
set by an optional external resistor divider. If no
overvoltage protection is desired, it may be disabled
by grounding the OVP terminal. The TPS6612x
supports a fault pin that indicates overtemperature
events.
1
•
•
•
•
•
•
•
•
Integrated 22 mΩ (typical), 32-V tolerant NFET 4V to 22-V sink path, up to 5 A
Built-in soft-start to limit in-rush currents
Integrated high voltage VBUS LDO regulator (3.3V or 5.0-V per device type)
Optional VBUS overvoltage protection via pin
configuration.
System supply and VBUS undervoltage protection
Overtemperature protection
Reverse-current protection
Fault pin with de-glitched fault reporting
Small footprint WCSP packaging, no HDI
required.
The TPS6612x series also supports a high voltage
VBUS LDO regulator (3.3-V or 5-V per device type)
useful for supplying power to the device and other
system components when operating in dead battery
conditions. The TPS66120 regulates to 3.3 V and the
TPS66121 regulates to 5 V.
Device Information(1)
2 Applications
•
•
•
•
•
PART NUMBER
Desktop PC/motherboard
Standard notebook PC
Chromebook and WOA
Docking station
Port/cable adapters and dongles
TPS66120
TPS66121
PACKAGE
WCSP (28)
BODY SIZE (NOM)
1.606 mm x 2.806 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Function Table
EN0
Device State
0
Sink path disabled
1
Sink path enabled
TPS6612x Block Diagram
PPHV Gate Control
and RCP
PPHV
TSD
OVP
VBUS
OVP
VBUS
VBUS
UVLO
VIN
EN0
Power
Mux
&
LDO
Control
VLDO
FLT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS66120, TPS66121
SLVSEW9B – AUGUST 2019 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
4
4
4
5
5
5
6
6
7
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Recommended Supply Load Capacitance................
Thermal Information ..................................................
PPHV Power Switch Characteristics.........................
Power Path Supervisory ...........................................
VBUS LDO Characteristics .......................................
Thermal Shutdown Characteristics ...........................
Input-output (I/O) Characteristics............................
Power Consumption Characteristics.......................
Typical Characteristics ............................................
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
17
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application ................................................. 20
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
Changes from Revision A (September 2019) to Revision B
•
Page
Changed from Advance Information to Production Data ....................................................................................................... 1
Changes from Original (August 2019) to Revision A
Page
•
Updated Applications section with links.................................................................................................................................. 1
•
Added Typical Characteristics section ................................................................................................................................... 9
•
Added Application Curves section ....................................................................................................................................... 22
2
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SLVSEW9B – AUGUST 2019 – REVISED DECEMBER 2019
5 Pin Configuration and Functions
TPS6612x YBG Package
28-Pin WCSP
Top View
A1
A2
A3
A4
FLT
VBUS
GND
GND
B1
B2
B3
B4
PPHV
VBUS
VBUS
GND
C1
C2
C3
C4
PPHV
VBUS
VBUS
GND
D1
D2
D3
D4
PPHV
VBUS
VBUS
GND
E1
E2
E3
E4
PPHV
VBUS
VBUS
GND
F1
F2
F3
F4
PPHV
VBUS
VBUS
OVP
G1
G2
G3
G4
EN0
VBUS
VLDO
VIN
Pin Functions
Pin
I/O
Reset State Description
Name
No.
PPHV
B1, C1, D1,
E1, F1
Power
Off
HV System Supply from VBUS. Bypass with capacitance CPPHV to GND.
VBUS
A2, B2, B3,
C2, C3, D2,
D3, E2, E3,
F2, F3, G2
Power
-
4V to 20V nominal input supply to PPHV. Bypass with capacitance CVBUS to
GND.
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Pin Functions (continued)
Pin
Name
I/O
No.
Reset State Description
VIN
G4
Power
-
Device input supply. Bypass with capacitance CVIN to GND.
VLDO
G3
Power
-
VIN supply or VBUS LDO regulated supply output from power multipexer. Bypass
with capacitance CVLDO to GND.
GND
A3, A4, B4,
C4, D4, E4
Ground
-
Ground. Connect all pins to ground plane.
OVP
F4
Analog
-
Selects VBUS OVP. Tie pin to VBUS resistor divider output to set desired VBUS
OVP level. Tie pin to GND to remove VBUS OVP function.
EN0
G1
Digital Input
Pull-down
Enable PPHV sink path. Internal pull-down.
A1
Digital
OUtput
Hi-Z
Fault Output Indicator. Active low. This pin is a true open-drain (no PMOS). Float
pin when unused.
FLT
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Terminal voltage range
(2)
EN0 (3), FLT, VIN, VLDO
PARAMETER
–0.3
6.2
V
Terminal voltage range
(2)
OVP
–0.3
VBUS
V
Terminal voltage range
(2)
VBUS, power path disabled (stand off voltage)
–0.5
32
V
Terminal voltage range
(2)
VBUS, power path enabled (4)
–0.5
26
V
Terminal voltage range
(2)
PPHV
–0.3
26
V
Terminal positive source current
VLDO sourced from VBUS VLDO
(1)
(2)
(3)
(4)
Internally limited
mA
50
mA
150
°C
VLDO sourced from VIN
Storage temperature
UNIT
–55
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
EN0 has an internal voltage clamp and may be driven above the absolute maximium voltage rating up to EN_CLAMP maximum
specification if current is limited to less than 100µA.
For VBUS, a TVS protection with a break down voltage falling between the Recommended and Absolute maximum ratings is
recommended, such as the TVS2200.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
(1)
VVIN
Input voltage range
VPPHV
Output voltage range
VVBUS
Input voltage range
VEN
Input voltage range
VFLT
Output voltage range
(1)
4
MIN
MAX
VIN, TPS66120 only.
2.85
3.6
UNIT
V
VIN, TPS66121 only.
4.5
5.5
V
PPHV
0
22
V
(1)
VBUS when sinking
4
22
V
(1)
EN0
0
5.5
V
FLT
0
5.5
V
(1)
(1)
All voltage values are with respect to network GND. All GND pins must be connected directly to the ground plane of the board.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
TJ = 105℃
4
TJ = 100℃
5
A
30
mA
74.25
75.75
kΩ
–10
125
°C
Maximum ramp rate on PPHV input supply
–2
2
Maximum ramp rate on VBUS input supply
–2
2
V/µs
30
mV/µs
IO_PPHV
Continuous current from VBUS to
PPHV
IO_VLDO
Output current from VBUS LDO
RIREF
External resistor current limit
reference
TJ
Operating junction temperature
RR_PPHV
RR_VBUS
RR_VIN
Maximum ramp rate on VIN input supply
75kΩ ±1% overall tolerance
A
V/µs
6.4 Recommended Supply Load Capacitance
over operating free-air temperature range (unless otherwise noted)
PARAMETER (1)
MIN
CVIN
Capacitance on VIN
CVLDO
Capacitance on VLDO
2.5
CVBUS
Capacitance on VBUS
1
CPPHV
Capacitance present on PPHV (2)
1
(1)
(2)
TYP
MAX
UNIT
4.7
10
µF
10
µF
47
100
µF
1
µF
Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by
50% at the required operating voltage, then the required external capacitor value would be 10 µF.
This capacitance represents the system side load capacitance that may be seen by the device e.g. from a typical battery charging
system. Discrete capacitance is not required for proper operation.
6.5 Thermal Information
TPS6612x
THERMAL METRIC (1)
YBG (WCSP)
UNIT
28 PINS
RθJA,EFF
Effective Junction-to-ambient thermal resistance (2)
44.3
°C/W
RθJA
Junction-to-ambient thermal resistance
62.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.4
°C/W
RθJB
Junction-to-board thermal resistance
13.8
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
13.7
°C/W
ψJB,EFF
Effective Junction-to-board characterization parameter (2)
14.5
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Models based on typical application layout.
6.6 PPHV Power Switch Characteristics
Operating under these conditions unless otherwise noted: -10 ℃ ≤ TJ ≤ 125 ℃, 2.85V ≤ VVIN ≤ 5.5V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ILOAD = 1 A, TJ = 25 ℃, SNK state.
22
26
mΩ
ILOAD = 1 A, -10 ℃ ≤ TJ ≤ 125 ℃,
SNK state.
22
45
mΩ
RPPHV
Resistance from PPHV to VBUS
VPPHV_RCP
Maximum voltage due to reverse
current during RCP response.
SNK state, VVBUS = 5.5V, ramp
VPPHV from 5.5V to 21V at 100
V/ms, CVBUS = 10µF, measure
VVBUS
5.8
V
VPPHV_OVP
Maximum voltage rise due to
reverse current during VBUS OVP
response.
SNK state, VVBUS = 5.5V, set VOVP
= 6V, ramp VVBUS from 5.5V to 21V
at 100 V/ms, CPPHV = 4.7µF,
measure VPPHV
6.2
V
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PPHV Power Switch Characteristics (continued)
Operating under these conditions unless otherwise noted: -10 ℃ ≤ TJ ≤ 125 ℃, 2.85V ≤ VVIN ≤ 5.5V
PARAMETER
VRCP_THRES_PPHV
TEST CONDITIONS
Reverse current blocking voltage
threshold for PPHV switch
SS
Soft-start slew rate
Transition from DISABLED state to
SNK state, VVBUS = 5V, CPPHV =
100µF. Measure slew rate on
PPHV.
tON_PPHV
PPHV enable time including Softstart.
RPPHV = 100Ω, VVBUS = 5V, CPPHV
= 100 µF. Transition from
DISABLED state to SNK state,
VPPHV at 90% of final value.
PPHV disable time.
RPPHV = 100Ω, VVBUS = 5V, CPPHV
= 4.7 µF. Transition from SNK state
to DISABLED state, VPPHV falls to
4.5V.
tOFF_PPHV
MIN
TYP
MAX
UNIT
2
6
10
mV
0.6
V/ms
0.2
9
15
29
ms
0.9
2.2
4.3
ms
6.7 Power Path Supervisory
Operating under these conditions unless otherwise noted: -10 ℃ ≤ TJ ≤ 125 ℃, 2.85V ≤ VVIN ≤ 5.5V, RIREF = 75 kΩ ±1%
overall tolerance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Undervoltage threshold for VIN. VBUS
LDO disables when threshold reached.
VIN rising, TPS66120 only.
2.45
2.75
V
VIN rising, TPS66121 only.
3.89
4.40
V
UV_VIN_F
Undervoltage threshold for VIN. Device
resets.
VIN falling, TPS66120 only.
2.35
2.65
V
VIN falling, TPS66121 only.
3.79
UVH_VIN
Undervoltage hysteresis for VIN.
UV_VBUS_R
Undervoltage threshold for VBUS. PPHV
VBUS rising
switch disabled unitl threshold reached.
3.35
3.75
V
UV_VBUS_F
Undervoltage threshold for VBUS. PPHV
VBUS falling
switch disables when threshold reached.
3.15
3.55
V
UVH_VBUS
Undervoltage hysteresis for VBUS
OVP_REF
OVP reference voltage.
VFWD_DROP_VIN
Forward voltage drop across
VIN to VLDO switch
tVIN_STABLE
When VIN is above UV_VIN_R for this
duration, VIN is considered valid. If
device is being powered by VBUS LDO,
it will then switch to VIN supply and
VBUS LDO will be disabled.
UV_VIN_R
4.30
100
200
0.93
1
IVLDO = 35 mA
5
V
mV
mV
1.07
V
90
mV
15
ms
6.8 VBUS LDO Characteristics
Operating under these conditions unless otherwise noted: -10 ℃ ≤ TJ ≤ 125 ℃, 2.85V ≤ VVIN ≤ 5.5V, RIREF = 75 kΩ ±1%
overall tolerance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.07
3.3
3.53
V
4.65
5.0
5.35
V
V_VBUS_LDO_3V
Output voltage of VBUS LDO
For TPS66120: VIN = 0V, VBUS
≥ 3.8V, 0 ≤ I_VBUS_LDO ≤ 30mA
V_VBUS_LDO_5V
Output voltage of VBUS LDO
For TPS66121: VIN = 0V, VBUS
≥ 5.5V, 0 ≤ I_VBUS_LDO ≤ 30mA
VDO_VBUS_LDO_3V
Drop out voltage of VDD LDO
For TPS66120: VIN = 0V, VBUS
= 3.135 V, I_VBUS_LDO = 30 mA
0.5
V
VDO_VBUS_LDO_5V
Drop out voltage of VDD LDO
For TPS66121: VIN= 0V, VBUS =
4.75V, I_VBUS_LDO = 30 mA
0.5
V
ILIMIT_VBUS_LDO
Current limit VBUS LDO.
VBUS = 5.5V, VIN= 0V, VLDO =
0V
100
mA
6
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VBUS LDO Characteristics (continued)
Operating under these conditions unless otherwise noted: -10 ℃ ≤ TJ ≤ 125 ℃, 2.85V ≤ VVIN ≤ 5.5V, RIREF = 75 kΩ ±1%
overall tolerance
PARAMETER
tEN_VBUS_LDO
TEST CONDITIONS
Turn-on time of VBUS LDO.
MIN
TYP
MAX
UNIT
For TPS66120: I_VBUS_LDO =
30mA, CVLDO = 4.7 µF, VIN =
0V. Ramp VVBUS from 0 to 5V at
≥50V/ms. Measure from VBUS =
4.5V to VLDO = 3V.
1.2
ms
For TPS66121: I_VBUS_LDO =
30mA, CVLDO = 4.7 µF, VIN =
0V. Ramp VVBUS from 0 to 7.5V at
≥50V/ms. Measure from VBUS =
7V to VLDO = 4.5V.
1.2
ms
6.9 Thermal Shutdown Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TSD_PPHV_R
Thermal Shutdown Temperature of
the PPHV power path.
Temperature rising
128
150
172
°C
TSD_PPHV_F
Thermal Shutdown Temperature of
the PPHV power path.
Temperature falling
115
140
165
°C
TSDH_PPHV
Thermal Shutdown hysteresis of
the PPHV power path.
TSD_MAIN_R
Thermal Shutdown Temperature of
the entire device.
Temperature rising
140
160
178
°C
TSD_MAIN_F
Thermal Shutdown Temperature of
the entire device.
Temperature falling
120
140
160
°C
TSDH_MAIN
Thermal Shutdown hysteresis of
the entire device.
10
°C
20
°C
6.10 Input-output (I/O) Characteristics
Operating under these conditions unless otherwise noted: -10 ℃ ≤ TJ ≤ 125 ℃, 2.85 V ≤ VVIN ≤ 5.5V, RIREF = 75 kΩ ±1%
overall tolerance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EN_Vt+
Positive going input-threshold
voltage, % of VLDO
VLDO = 2.85 - 5.5V
40
70
%
EN_Vt-
Negative going input-threshold
voltage, % of VLDO
VLDO = 2.85 - 5.5V
30
60
%
EN_HYS
Input hysteresis voltage, % of
VLDO
VLDO = 2.85 - 5.5V
EN_RPD
Pull-down resistance EN pin.
Measured with pin voltage VEN
= 3.3V
EN_CLAMP
Voltage clamp on EN pin.
IEN = 100 µA
FLT_VOL
Output Low Voltage, FLT pin
IOL = 2mA, FLT driven low.
FLT_ILKG
Leakage Current, FLT pin
FLT not driven low.
tH_FLT
Time FLT pin remains asserted
low.
4
tDG_EN
Enable deglitch filter. Pulses on
EN0 < tDG_EN(MIN) are not
propagated to the control logic.
Pulses on EN0 > tDG_EN(MAX)
are propagated to the control
logic. Pulses on
EN0 ≥ tDG_EN(MIN) and ≤
tDG_EN(MAX) may or may not
propagate to the control logic.
78
10
500
%
650
800
kΩ
6
7.1
V
–1
10
0.4
V
1
µA
16
ms
242
µs
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6.11 Power Consumption Characteristics
Operating under these conditions unless otherwise noted: -10 ℃ ≤ TJ ≤ 85 ℃, 2.85V ≤ VVIN ≤ 5.5V, RIREF = 75 kΩ ±1% overall
tolerance
PARAMETER
IVIN_DISABLE
IVIN_SNK
TEST CONDITIONS
Current consumed by
VIN (1)
Current consumed by
VIN (1)
TYP
MAX
VIN = 3.3V, VBUS = 0V, PPHV
= 0V, DISABLED state.
Measure IVIN. TPS66120 only.
19
27
µA
VIN = 5V, VBUS = 0V, PPHV
= 0V, DISABLED
state. Measure IVIN. TPS66121
only.
25
36
µA
130
µA
VIN = 5V, SNK state. Measure
IVIN. TPS66121 only.
VBUS =
5.5V/22V
215
µA
VBUS =
5.5V
12
VBUS =
22V
34
µA
VBUS =
5.5V
8
µA
VBUS =
22V
30
µA
VBUS =
5.5V
45
µA
VBUS =
22V
68
µA
VBUS =
5.5V
45
µA
VBUS =
22V
69
µA
VBUS =
5.5V
325
µA
VBUS =
22V
360
µA
VBUS =
5.5V
342
µA
VBUS =
22V
377
µA
Current consumed by
VBUS (1)
VIN = 5V, PPHV= 0V,
DISABLED state. Measure
IVBUS. TPS66121 only.
ISD_VBUS_LDO
ISD_VBUS_LDO
Current consumed by
VBUS (1)
VIN = 0V, PPHV= 0V,
DISABLED state. Measure
IVBUS.
Current consumed by
VBUS (1)
VIN = 0V, PPHV= 0V,
DISABLED state. Measure
IVBUS.
VIN = 3.3V, SNK
state. Measure IVBUS.
TPS66120 only.
IACT_VBUS
UNIT
VIN = 3.3V, SNK state. Measure VBUS =
IVIN. TPS66120 only.
5.5V/22V
VIN = 3.3V, PPHV= 0V,
DISABLED state. Measure
IVBUS. TPS66120 only.
ISD_VBUS
MIN
Current consumed by
VBUS (1)
VIN = 5V, SNK state. Measure
IVBUS. TPS66121 only.
26
µA
VOC_VBUS
Open circuit voltage,
VBUS
PPHV = 22V, DISABLED state,
no DC loading on VBUS.
Measure VVBUS under steady
state conditions.
0.8
V
VOC_PPHV
Open circuit voltage,
PPHV
VBUS = 22V, DISABLED state,
no DC loading on PPHV.
Measure VPPHV under steady
state conditions.
0.8
V
(1)
8
Measured with EN0 set to GND or VLDO levels as required for the respective state.
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6.12 Typical Characteristics
250
30
200
VOC_PPHV (mV)
27.5
25
22.5
150
100
50
20
0
17.5
-15
0
15
30
45
60
75
90
105
120
4
135
Temperature (qC)
TA = -10 qC
TA = 25 qC
TA = 85 qC
TA = 125 qC
210
195
165
PPHV, /FLT (V)
VOC_VBUS (mV)
180
150
135
120
105
90
75
60
45
30
15
0
4
5
6
7
8
9
10
12
10 11 12 13 14 15 16 17 18 19 20 21 22
VPPHV (V)
6
5.7
5.4
5.1
4.8
4.5
4.2
3.9
3.6
3.3
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
16
18
20
22
D008
PPHV
VBUS
/FLT
0
200
400
600
800
1000
1200
1400
1600
1800
Time (Ps)
D001
Figure 3. VOC_VBUS, VBUS Open Circuit Voltage versus
PPHV
14
Figure 2. VOC_PPHV, PPHV Open Circuit Voltage versus
VBUS
255
225
8
VVBUS (V)
Figure 1. RPPHV versus Temperature
240
6
D002
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2000
VBUS (V)
RPPHV (m:)
TA = -10 qC
TA = 25 qC
TA = 85 qC
TA = 125 qC
D015
Figure 4. VBUS OVP Response with 6-V Threshold
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7 Detailed Description
7.1 Overview
The TPS6612x is a fully featured integrated Sink power path with a high voltage VBUS LDO voltage regulator.
The Sink power path can support up to 5 A at 20 V controlled by a general-purpose I/O. The Sink power path
includes soft-start to minimize in-rush currents, overtemperature protection, reverse-current protection,
undervoltage protection, and an optional overvoltage protection configured in the application. See the 20-V Sink
(PPHV Power Path) section.
The VBUS low dropout voltage regulator may be used in systems that require power during dead battery
conditions and can provide up to 30 mA to the system via the VLDO pin. Once VIN power is available, VLDO pin
power is switched from the VBUS LDO regulator to the VIN pin. The TPS66120 devices VBUS LDO regulator
nominally supplies 3.3 V where the TPS66121 device VBUS LDO regulator nominally supplies 5 V. See the
Power Management and Supervisory section.
7.2 Functional Block Diagram
PPHV Gate Control
and RCP
PPHV
TSD
OVP
VBUS
OVP
VBUS
VBUS
UVLO
VIN
EN0
Power
Mux
&
LDO
Control
VLDO
FLT
7.3 Feature Description
7.3.1 20-V Sink (PPHV Power Path)
The PPHV path is a Sink only path, providing power from the VBUS terminal to the PPHV terminal when
enabled. The PPHV power path uses two back-to-back N-channel MOSFETs, and blocks current in both
directions when the power path is disabled.
7.3.1.1 PPHV Soft Start
The TPS6612x PPHV power path has soft start circuitry to control in-rush current when the PPHV power path is
enabled. DC loading should be minimized during soft start since the PPHV path may experience high power
dissipation especially at higher VBUS voltages. This may lead to a PPHV overtemperature protection event.
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Feature Description (continued)
7.3.1.2 PPHV Reverse Current Protection (RCP)
When the PPHV power path is enabled, the RCP circuitry monitors the voltage across the path. If the RCP
monitor detects VPPHV - VVBUS ≥ VRCP_THRES_PPHV, the PPHV path will be disabled preventing additional current
flow from PPHV to VBUS. The power path will be completely disabled and remain disabled as long as the RCP
condition persists. After the RCP event, the PPHV path will automatically re-enable. FLT is not asserted when a
reverse current protection event occurs on the PPHV path.
7.3.2 Overtemperature Protection
The PPHV power path has an integrated temperature sensor to protect it from excessive heating. When the
sensor in the path detects an overtemperature condition, the PPHV path will be automatically disabled (if
enabled) and cannot be enabled until the overtemperature condition has been removed. FLT is asserted when
an overtemperature event occurs.
In addition, the device has an integrated main temperature sensor. When the sensor detects an overtemperature
condition, the PPHV power pathand the VBUS LDO of the device are completely disabled until the
overtemperature condition has been removed.
7.3.3 VBUS Overvoltage Protection (OVP)
TPS6612x supports overvoltage protection on the VBUS terminal. When the voltage detected on OVP exceeds a
set level, the PPHV power path will automatically be disabled (if enabled), and will remain disabled until the OVP
event is removed. FLT is asserted when an overvoltage event occurs. The VBUS OVP threshold may be set
using a resistor divider from VBUS to GND, whose divider output is connected to the OVP terminal as shown in
Figure 5. Table 1 shows resistor divider settings for common USB Power Delivery fixed voltage supply contracts
along with the resulting nominal OVP thresholds. These thresholds may be adjusted based on desired margins
for a given application. If VBUS OVP is not required or needs to be disabled, the OVP terminal may be tied or
driven to GND as shown in Figure 6. Lastly, as one example implementation, the OVP threshold may be
controlled dynamically using outputs from a PD controller or microcontroller as shown in Figure 7. By selecting
each output, different VBUS OVP threshold settings are possible.
VBUS
PPHV
PPHV Gate Control
and RCP
R1
1%
OVP
+
OVP_REF
R2
1%
-
OVP_detect
R1 + R2 = 500 kΩ, max.
VVBUS_OVP_THRESHOLD = OVP_REF * (1 + R1/R2)
Figure 5. VBUS OVP Threshold Set by External Resistor Divider
Table 1. Typical External Resistor Divider Settings
PD Fixed Contract
R1, kΩ
R2, kΩ
Nominal VBUS OVP Threshold, V
5V
102
20
6.1
9V
182
20
10.1
15 V
309
20
16.5
20 V
432
20
22.6
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VBUS
PPHV
PPHV Gate Control
and RCP
OVP
+
OVP_REF
-
OVP_detect
Figure 6. VBUS OVP Disabled
VBUS
Controller
PPHV
PPHV Gate Control
and RCP
R1
1%
OVP
R2
1%
R3
1%
R4
1%
+
OVP_REF
-
OVP_detect
GPIO_0
GPIO_1
GPIO_2
Figure 7. Selectable VBUS OVP Thresholds
7.3.4 Power Management and Supervisory
The TPS6612x Power Management block receives power from VIN or VBUS and generates voltages to provide
power to the TPS6612x internal circuitry, as well as, provides power to VLDO. The power supply management
and supervisory block is shown in Figure 8.
12
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UVLO
VIN_GOOD
Switch Over
Logic
VBUS_GOOD
UVLO
S1
VIN
VBUS
EN
VLDO
VREF
LDO
Figure 8. Power Management and Supervisory
The VLDO terminal may be powered from either VIN or VBUS. The normal power supply input is VIN. When VIN
is present, S1 is closed and current flows from VIN to VLDO and the VBUS LDO is disabled. When VIN power is
unavailable, as in a dead battery condition, the VBUS LDO will be automatically enabled when VBUS is present,
and the VLDO terminal is powered by the VBUS LDO. The Switch Over Logic provides the decision making
capability to choose VIN or VBUS power, depending on the state of these voltages (based on their respective
UVLO comparators) and their relative levels to each other.
7.3.4.1 Supply Connections
Figure 9 shows the TPS66120 VIN being supplied from a 3.3-V supply. The VLDO output may or may not be
used to supply other circuitry in the application, for example a PD Controller. During dead battery, the internal
3.3-V VBUS LDO provides power to the TPS66120 and the VLDO output. Once VIN input supply becomes
available, the VBUS LDO is disabled and VIN provides power to the VLDO output.
Figure 10 shows the TPS66121 VIN being supplied from a 5-V supply. The VLDO output may or may not be
used to supply power to external circuitry. During dead battery, the internal 5-V VBUS LDO provides power to the
TPS66121 and the VLDO output. Once VIN input supply becomes available, the VBUS LDO is disabled and VIN
provides power to the VLDO output.
Another option is to power the TPS66120 from the VBUS LDO only as shown in Figure 11. Since VIN is tied to
GND, power to the TPS66120 is provided by the 3.3-V VBUS LDO when VBUS power is present. The VLDO
output may be used optionally to supply power to external circuitry.
Similarly, Figure 12 shows the TPS66121 being powered from the VBUS LDO only. Since VIN is tied to GND,
power to the TPS66121 is provided by the 5-V VBUS LDO when VBUS power is present. The VLDO output may
be used optionally to supply power to external circuitry.
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VBUS
PPHV
OVP
3.3V Supply
VIN
TPS66120
VLDO
Optional
EN0
FLT
GND
Figure 9. TPS66120 VIN 3.3-V Supply
VBUS
PPHV
OVP
5V Supply
VIN
TPS66121
VLDO
Optional
EN0
FLT
GND
Figure 10. TPS66121 VIN 5-V Supply
14
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VBUS
PPHV
OVP
VIN
TPS66120
VLDO
Optional
EN0
FLT
GND
Figure 11. TPS66120 VBUS Powered
VBUS
PPHV
OVP
VIN
TPS66121
VLDO
Optional
EN0
FLT
GND
Figure 12. TPS66121 VBUS Powered
7.3.4.2 Power Up Sequences
7.3.4.2.1 Normal Power Up
Figure 13 shows a typical power up sequence. During normal power up, VIN supplies power to the TPS6612x. In
this case, VBUS remains powered down. It is assumed a PD Controller is controlling the TPS6612x, and Sink
operation is being requested.
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1. Both the VBUS and VIN supplies are
powered down. VIN supply begins to rise.
5
VBUS
2. VLDO terminal begins to rise.
4
EN0
3. VLDO supplied by VIN via switch S1. VBUS
LDO remains disabled.
1
VIN
tVIN_STABLE
4. PD Controller requests Sink path to be
enabled. Since VIN supply has not been above
its UVLO threshold for tVIN_STABLE, Sink path
remains disabled. In addtion, VBUS is not
above its UVLO switch threshold, which also
keeps the Sink path disabled.
2
VLDO
3
VLDO Supply
VIN switch
6
Disabled
PPHV Path
Enabled
5. VBUS rises.
6. VIN supply remained above its UVLO
threshold for tVIN_STABLE and VBUS is above its
UVLO threshold. The Sink path enables.
VBUS LDO remains disabled since VIN supply
is available
Figure 13. Normal Power Up Sequence
7.3.4.2.2 Dead Battery Operation
Figure 14 shows the typical power up sequence during a dead battery condition. During a dead battery condition,
the TPS6612x is internally powered by the VBUS LDO. The VBUS LDO may be used to supply a limited amount
of current for use in the system during dead battery, such as supplying power to a PD controller. In this case, it is
assumed the VLDO terminal is providing power to a PD controller that is controlling the TPS6612x. Once VIN is
stable, the VLDO terminal switches from being supplied by the VBUS LDO to being supplied by the VIN terminal,
and the VBUS LDO is automatically disabled. The switch over process is completely seamless.
NOTE
Switching from VBUS LDO operation to VIN operation is seamless and no device reset
will occur. When switching from VIN power to VBUS LDO operation, the switch over
circuitry will attempt to switch over to the VBUS LDO, however it is not assured that the
VLDO level will be maintained above the VLDO UVLO threshold. In this case, a device
reset may or may not occur.
1. Device is in dead battery condition. PD
controller advertises as a Sink. Upon
connection to a Source, VBUS begins to rise.
1
VBUS
3
EN0
2. VBUS LDO is selected by the power
management logic and VLDO begins to rise.
4
VIN
3. PD Controller negotiates a contract (may be
5V or higher) and asserts EN0 to turn on the
PPHV Sink path in order to charge the system.
tVIN_STABLE
VLDO
VLDO Supply
PPHV Path
2
5
VBUS LDO
Disabled
VIN switch
4. System begins to charge and VIN begins to
rise. VIN passes its UVLO threshold.
5. If VIN supply remains above its UVLO
threshold for tVIN_STABLE, VBUS LDO is disabled
and VLDO is switched over to be supplied by
VIN via switch S1.
Enabled
Figure 14. Dead Battery Power Up Sequence
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7.4 Device Functional Modes
7.4.1 State Transitions
EN0 is used by the application to control the state of the device. Figure 15 shows the supported state transitions.
Power-on Reset
DISABLED
EN0 = 0b
EN0 = 1b
EN0 = 0b
fault
SNK
FAULT
EN0 = 1b & no faults
SNK
Figure 15. TPS6612x State Diagram
7.4.1.1 DISABLED State
In the DISABLED state, EN0 = 0. While in the DISABLED state:
• PPHV power path is disabled
• PPHV overtemperature, reverse-current, and VBUS overvoltage protections are disabled
• VIN and VBUS undervoltage lockout are enabled
• SNK state if (EN1 = 0) and (EN0 = 1) and (VBUS UVLO event not detected)
7.4.1.2 SNK State
In the SNK state, EN0 = 1. While in the SNK state:
• PPHV power path is enabled
• PPHV overtemperature, VBUS overvoltage (if OVP terminal not grounded) and reverse-current protections
are enabled
• VIN and VBUS undervoltage lockout are enabled
• DISABLED state if:
– (EN1 = 0) and (EN0 = 0)
• SNK FAULT state if:
– VBUS OVP (if OVP terminal not grounded) event detected -or– PPHV TSD event detected
7.4.2 SNK FAULT State
The SNK FAULT state is entered when any PPHV fault event is detected. Upon entering the SNK FAULT state,
the PPHV power path is disabled. The following transitions are possible from the SNK FAULT state:
• DISABLED state if:
– (EN0 = 0)
• SNK state if:
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Device Functional Modes (continued)
– PPHV TSD, VBUS OVP (if OVP terminal not grounded) events are not detected
7.4.3 Device Functional Mode Summary
Table 2 summarizes the functional modes for the TPS6612x family. As shown, the enabling and disabling of the
Sink is dependent upon the voltage present on VBUS, as well as, the current device state.
Table 2. TPS6612x Device Functional Modes (1)
EN0
VIN
VVBUS
FLT
Device State
Sink Path
0
≥ UV_VIN
X
Hi-Z
DISABLED
Disabled
Safety engaged.
Hi-Z
SNK
Enabled
RCP, OVT enabled
Hi-Z
SNK FAULT
Enabled with Blocking
RCP event.
L
SNK FAULT
Disabled
OVP (2) or OVT event.
< UV_VBUS
Hi-Z
SNK FAULT
Disabled
VBUS UVLO event.
≥ UV_VBUS
1
≥ UV_VIN
X
< UV_VIN
< UV_VBUS
Hi-Z
DISABLED
Disabled
Safety engaged.
0
< UV_VIN
≥ UV_VBUS
Hi-Z
DISABLED
Disabled
Safety engaged.
Hi-Z
SNK
Enabled
RCP, OVT enabled
Hi-Z
SNK FAULT
Enabled with Blocking
RCP event.
L
SNK FAULT
Disabled
OVP (2) or OVT event.
Hi-Z
SNK FAULT
Disabled
VBUS UVLO event.
≥ UV_VBUS (3)
1
< UV_VIN
< UV_VBUS (3)
(1)
(2)
(3)
X: do-not-care.
When OVP function used and VBUS exceeds OVP threshold, VVBUS_OVP_THRESHOLD.
If VIN supply is not available, then VIN may be tied to GND. In this case VLDO is supplying power to the device.
7.4.4 Enabling the PPHV Sink Path
The timing diagram of enabling the PPHV Sink path is shown in Figure 16.
tDG_EN
tDG_EN
Disabled
Enabled
tON_PPHV
tOFF_PPHV
EN0
VBUS to PPHV (SNK)
Disabled
Figure 16. Enabling the PPHV Sink Path
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7.4.5 Faults
The TPS6612x includes a fault pin, FLT. The FLT pin is an open-drain output and requires an external pull-up
resistor. If the FLT pin is not required, it may be tied to GND or left floating. The FLT pin will be asserted low only
under certain conditions and not all fault conditions will assert the FLT pin, see Table 3. If the FLT pin is
asserted, it will remain asserted for a minimum of tHOLD_FLT regardless if the fault condition is removed. After
tHOLD_FLT, if all fault conditions have surpassed, the FLT pin is released.
7.4.5.1 Fault Types
Table 3 summarizes the various fault types available and when the FLT shall be asserted.
Table 3. Fault Types
Fault Name
VBUS_UVLO
VBUS_OVP
(1)
VBUS_RCP
PPHV_OVT
(1)
Fault
VBUS undervoltage Lockout
VBUS overvoltage Protection
VBUS Reverse-Current
Protection
PPHV overtemperature
Protection
FLT
Description
Hi-Z
If VBUS supply is below the VBUS UVLO threshold, the PPHV
path is disabled automatically if enabled or remains disabled. If
the SNK state is selected to be entered, the device will remain
in the DISABLED state until the UVLO event is removed. If the
SNK state has been entered successfully and a UVLO event
occurs, the PPHV path is disabled automatically.
Low
If the SNK state is selected to be entered or device currently is
in the SNK state and the VBUS supply rises above the VBUS
OVP threshold, the PPHV path is disabled automatically and
the FLT pin will be asserted.
Hi-Z
If the SNK state is selected to be entered or device currently is
in the SNK state and a reverse-current condition is detected,
the PPHV path is disabled automatically, but the FLT is not
asserted.. If the reverse-current condition is removed, the PPHV
path will automatically re-enable.
Low
If the SNK state is selected to be entered or device currently is
in the SNK state and the local temperature of PPHV power path
exceeds TSD_PPHV_R, the PPHV path is disabled
automatically and the FLT pin will be asserted. PPHV power
path will remain disabled until temperature falls below
TSD_PPHV_F.
OVP terminal is not connected to GND.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The typical applications of the TPS6612x include chargers, notebooks, tablets, ultra-books, dongles and any
other product supporting USB Type-C and/or USB-PD as a power source or power sink. The typical applications
outlined in the following sections detail a Fully-Featured USB Type-C using a single 5-V supply and another
using a separate 3.3-V supply.
8.2 Typical Application
Figure 17 shows a USB Type-C single port design using a power delivery controller. For this system, a single 5-V
supply in the system is used to supply power to the external load switch, as well as, the connector VCONN
power. The VIN terminal of the TPS66121 is tied to GND and the TPS66121 is powered by the VBUS LDO once
VBUS is present. In addition, the TPS66121 supplies power to the 5-V supply of the PD controller via the VLDO
output. The PPHV integrated power path provides power to the system and battery charger from VBUS when the
TPS66121 Sink path is enabled. An external 5-V load switch is shown to provide power to VBUS when system is
configured as a Source.
VSYS
Battery
Charger
VBAT
IN
5V Load Switch
4S2P
VIN
from EC
OUT
EN
EN
Type-C
Receptacle
5V Buck
PPHV
VBUS
OVP
IN
TVS2200
VIN
GND
VCON_IN
TPS66121
5V_IN
GPIO1
Opt.
Opt.
VLDO
GPIO2
EN0
GPIO3
FLT
PD
Controller
Opt.
2
2
2
2
2
2
2
VBUS
GND
CC1
CC2
D+/D+/RX1
TX1
RX2
TX2
SBU1/2
GND
VMON
CC1
CC2
Figure 17. Single Port Type-C PD Port Using a 5-V Supply.
8.2.1 Design Requirements
For a single port notebook application, Table 4 lists the input voltage requirements and expected current
capabilities.
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Typical Application (continued)
Table 4. Single-Port Notebook Application Design Parameters
EXAMPLE VALUE(S)
POWER PATH DIRECTION
5-V Load Switch Voltage and
Current Capabilities
DESIGN PARAMETERS
5V/3A
Source from 5-V load switch to
VBUS
VCON_IN Input Voltage and
Current Capabilities
5V/300mA (1.5W)
Source to VCONN
VBUS Input Voltage and Current
Capabilities
5V/3A, 9V/3A, 15V/3A, 20V/3A
Sink from VBUS to PPHV
5V_IN Input Voltage and Current
Capabilities
4.5-5.5V/30mA
5-V PD Controller Supply
3V_IN Input Voltage and Current
Capabilities
3.0-3.6V/30mA
3.3-V PD Controller Supply
8.2.2 Detailed Design Procedure
8.2.2.1 External VLDO Capacitor (CVLDO)
For all capacitances, the DC operating voltage must be factored into the derating of ceramic capacitors.
Generally, the effective capacitance is 35-50% of the nominal capacitance with voltage applied. Assuming VLDO
= 5 V, and a minimum derated capacitance of 2.5 uF, a 10-V rated 4.7-uF capacitor is sufficient.
8.2.2.2 PPHV, VBUS Power Path Capacitance
The PPHV power path is a Sink. The capacitance on the PPHV shown in Figure 17 represents capacitance of
the charger sub-system. In a typical application, this capacitance can be in the range of 47 uF up to 100 uF, far
exceeding the 1-uF minimum specification for the TPS6612x, so no external capacitance is required to meet this
requirement in most cases. As per the PD Specification, the total capacitance on VBUS should be maximum 10
uF at connection.
The TPS6612x PPHV power path has soft start circuitry to control in-rush current when the PPHV power path is
enabled. DC loading should be minimized during soft start since the PPHV path may experience high power
dissipation especially at higher VBUS voltages. This in turn may lead to a PPHV overtemperature protection
event.
8.2.2.3 VBUS TVS Protection (Optional)
It is recommended that each VBUS port in the system have TVS protection to protect the VBUS terminal.
Inductive ringing during momentary disconnects and reconnects due to mechanical vibration or plug removal
while sinking large current loads may cause large peak voltages to be present on the VBUS terminal that may
exceed the absolute maximums of the TPS6612x. Under such events, the TVS2200 clamps the VBUS terminal
and prevents VBUS from exceeding the maximum specification. The TVS trip point should be chosen to be
safely above the normal operating ranges of the device. For this case, it is assumed VBUS voltage contracts are
less than 22-V maximum which is below the minimum breakdown voltage of the TVS2200. The maximum
clamping voltage of 28.3 V of the TVS2200 is sufficient to protect the VBUS terminal of the TPS6612x.
8.2.2.4 VBUS Schottky Diode Protection (Optional)
To prevent the possibility of large ground currents into the TPS6612x during sudden disconnects because of
inductive effects in a cable, it is recommended that a Schottky diode be placed from VBUS to GND. The
NSR20F30NXT5G or comparable device is recommended.
8.2.2.5 VBUS Overvoltage Protection (Optional)
VBUS Overvoltage Protection (OVP) is optional. If VBUS OVP is not required, then the OVP terminal should be
tied to ground as shown in Figure 6. VBUS OVP is used to detect voltages on VBUS that exceed a set threshold.
Upon detection, the PPHV power path is disabled quickly to help protect components connected downstream of
the PPHV terminal. It should be noted that VBUS OVP is not a replacement for VBUS TVS protection which is
protecting the VBUS terminal itself.
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SLVSEW9B – AUGUST 2019 – REVISED DECEMBER 2019
www.ti.com
The VBUS OVP threshold is set by a resistor divider from the VBUS terminal to ground as shown in Figure 5. For
this design, R1 and R2 are fixed values to provide VBUS OVP protection at the highest voltage contract level.
Using R1 = 432-kΩ and R2 =20-kΩ sets a nominal VBUS OVP threshold of 22.6 V. For some applications, it may
be desirable to dynamically change the VBUS OVP level based on the negotiated power contract. One possible
way is shown in Figure 7. In this case, the PD controller via GPIO, selects the proper divider ratio to set the
VBUS OVP threshold based on the negotiated voltage contract level.
8.2.2.6 Dead Battery Support
The TPS6612x integrates a high-voltage VBUS LDO that can be used to supply power to a PD Controller and
other supporting circuitry when only VBUS power is available, such as in a dead battery condition. As shown in
Figure 17 the TPS66121 VLDO output supplies power to the PD Controller's 5V_IN supply. During a dead
battery condition, the PD Controller presents its Type-C RPD pull-downs on the CC1 and CC2 lines. Upon
connection to a Type-C/PD Source, 5 V is provided to VBUS from the Source partner which powers the
TPS6612x. The 5-V VBUS LDO is enabled and provides power to the PD Controller. Once powered, the PD
Controller can decide to enable the TPS6612x PPHV Sink path by asserting EN0 high and use the 5-V VBUS to
charge the battery or it may choose to negotiate a higher voltage contract first. Either way, once the contract is
negotiated, the PD Controller will enable the PPHV Sink path and charge the system. Once the system is
sufficiently charged, the VIN terminal will rise and will exceed the VIN UVLO threshold. If VIN remains above the
UVLO threshold for tVIN_STABLE, VLDO will be supplied from VIN and the VBUS LDO will be disabled.
6
5.7
5.4
5.1
4.8
4.5
4.2
3.9
3.6
3.3
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
PPHV
VBUS
/FLT
0
200
400
600
800
1000
1200
1400
1600
1800
Time (Ps)
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2000
VBUS (V)
PPHV, /FLT (V)
8.2.3 Application Curves
D015
Figure 18. VBUS OVP Response with 6-V Threshold
22
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Product Folder Links: TPS66120 TPS66121
TPS66120, TPS66121
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SLVSEW9B – AUGUST 2019 – REVISED DECEMBER 2019
9 Power Supply Recommendations
The device has a single input supply, VIN. A 1-uF or higher ceramic bypass capacitor between VIN and GND is
recommended as close to the VIN as possible for local noise decoupling.
USB Specification Revisions 2.0 and 3.1 require VBUS voltage at the connector to be between 4.75 V to 5.5 V.
Depending on layout and routing from supply to the connector the voltage droop on VBUS has to be tightly
controlled. Locate the input supply close to the device. For all applications, a maximum 10-μF ceramic bypass
capacitor between VBUS and GND is recommended as close to the Type-C connector of the device as possible
for local noise decoupling. The input power supply should be rated higher than the current limit set to avoid
voltage droops during overcurrent and short-circuit conditions.
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Product Folder Links: TPS66120 TPS66121
23
TPS66120, TPS66121
SLVSEW9B – AUGUST 2019 – REVISED DECEMBER 2019
www.ti.com
10 Layout
10.1 Layout Guidelines
1. PPHV and VBUS traces must be as short and wide as possible to accommodate for high currents.
2. A ceramic 4.7 uF (X7R/X5R) 10-V rated capacitor is placed as close as possible to the VLDO terminal of the
TPS6612x.
10.2 Layout Example
Figure 19. Layout Example
24
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Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS66120 TPS66121
TPS66120, TPS66121
www.ti.com
SLVSEW9B – AUGUST 2019 – REVISED DECEMBER 2019
11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 5. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS66120
Click here
Click here
Click here
Click here
Click here
TPS66121
Click here
Click here
Click here
Click here
Click here
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS66120 TPS66121
25
PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS66120YBGR
ACTIVE
DSBGA
YBG
28
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-10 to 85
TPS66120
TPS66121YBGR
ACTIVE
DSBGA
YBG
28
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-10 to 85
TPS66121
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS66120YBGR
DSBGA
YBG
28
3000
330.0
12.4
TPS66121YBGR
DSBGA
YBG
28
3000
330.0
12.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.78
2.98
0.7
4.0
12.0
Q1
1.78
2.98
0.7
4.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS66120YBGR
DSBGA
YBG
28
3000
367.0
367.0
35.0
TPS66121YBGR
DSBGA
YBG
28
3000
367.0
367.0
35.0
Pack Materials-Page 2
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