Texas Instruments | TVS0500 5-V Flat-Clamp Surge Protection Device (Rev. C) | Datasheet | Texas Instruments TVS0500 5-V Flat-Clamp Surge Protection Device (Rev. C) Datasheet

Texas Instruments TVS0500 5-V Flat-Clamp Surge Protection Device (Rev. C) Datasheet
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TVS0500
SLVSED2C – DECEMBER 2017 – REVISED NOVEMBER 2019
TVS0500 5-V Flat-Clamp Surge Protection Device
1 Features
3 Description
•
The TVS0500 robustly shunts up to 43 A of IEC
61000-4-5 fault current to protect systems from high
power transients or lightning strikes. The device
offers a solution to the common industrial signal line
EMC requirement to survive up to 2 kV IEC 61000-45 open circuit voltage coupled through a 42 Ω
impedance. The TVS0500 uses a unique feedback
mechanism to ensure precise flat clamping during a
fault, assuring system exposure below 10 V. The tight
voltage regulation allows designers to confidently
select system components with a lower voltage
tolerance, lowering system costs and complexity
without sacrificing robustness.
1
•
•
•
•
•
•
•
•
Protection Against 2 kV, 42 Ω IEC 61000-4-5
Surge Test for Industrial Signal Lines
Max Clamping Voltage of 9.2 V at 43 A of 8/20 µs
Surge Current
Standoff Voltage: 5 V
Tiny 4 mm2 Footprint
Survives over 5,000 Repetitive Strikes of 35 A
8/20 µs Surge Current at 125°C
Robust Surge Protection:
– IEC61000-4-5 (8/20 µs): 43 A
– IEC61643-321 (10/1000 µs): 22 A
Low Leakage Current
– 70 pA typical at 27°C
– 6.5 nA typical at 85°C
Low Capacitance: 155 pF
Integrated Level 4 IEC 61000-4-2 ESD Protection
2 Applications
•
•
•
•
•
•
Industrial Sensors
PLC I/O Modules
5 V Power Lines
Appliances
Medical Equipment
Smart Meters
In addition, the TVS0500 is available in a small 2 mm
× 2 mm SON footprint which is ideal for space
constrained applications, offering a 70 percent
reduction in size compared to industry standard SMA
and SMB packages. The extremely low device
leakage and capacitance ensure a minimal effect on
the protected line. To ensure robust protection over
the lifetime of the product, TI tests the TVS0500
against 5000 repetitive surge strikes at high
temperature with no shift in device performance.
The TVS0500 is part of TI's Flat-Clamp family of
surge devices. For more information on the other
devices in the family, see the Device Comparison
Table
Device Information(1)
PART NUMBER
PACKAGE
TVS0500
BODY SIZE (NOM)
SON (6)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Footprint Comparison
Voltage Clamp Response to 8/20 µs Surge Event
Voltage
TVS0500 Flat-Clamp
DRV Footprint
2mm x 2mm
Conventional TVS
SMB Footprint
3.55mm x 5.3mm
10
20
30
Time ( s)
Traditional TVS
Copyright © 2018, Texas Instruments Incorporated
TI Flat-Clamp
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TVS0500
SLVSED2C – DECEMBER 2017 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings - JEDEC ..............................................
ESD Ratings - IEC ....................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Reliability Testing ...................................................... 9
8.5 Device Functional Modes ......................................... 9
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
Changes from Revision B (February 2018) to Revision C
•
Page
Fixed grammar error in the Reliability Testing section ........................................................................................................... 9
Changes from Revision A (February 2018) to Revision B
Page
•
Changed DC Breakdown Current MAX from 100 to 50 in the Specifications Absolute Maximum Ratings table ................. 5
•
Changed Break-down Voltage MIN from 7.6 to 7.5 and MAX from 8.2 to 8.4 in the Specifications Electrical
Characteristics table ............................................................................................................................................................... 5
Changes from Original (December 2017) to Revision A
•
2
Page
Changed device document status from Advance Information to Production Data................................................................. 1
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5 Device Comparison Table
Device
Vrwm
Vclamp at Ipp
Ipp (8/20 µs)
Vrwm leakage
(nA)
Package Options
Polarity
TVS0500
5
9.2
43
0.07
SON
Unidirectional
TVS1400
14
18.4
43
2
SON
Unidirectional
TVS1800
18
22.8
40
0.5
SON
Unidirectional
TVS2200
22
27.7
40
3.2
SON
Unidirectional
TVS2700
27
32.5
40
1.7
SON
Unidirectional
TVS3300
33
38
35
19
WCSP, SON
Unidirectional
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6 Pin Configuration and Functions
DRV Package
6-Pin SON
Top View
GND 1
GND
GND 2
GND 3
6
IN
5
IN
4
IN
Pin Functions
PIN
NAME
IN
GND
4
No.
TYPE
4, 5, 6
I
1, 2, 3, exposed thermal
pad
GND
DESCRIPTION
ESD and surge protected channel
Ground
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7 Specifications
7.1 Absolute Maximum Ratings
TA = 27℃ (unless otherwise noted) (1)
MIN
Maximum
Surge
Maximum
Forward Surge
MAX
UNIT
IEC 61000-4-5 Current (8/20 µs)
43
A
IEC 61000-4-5 Power (8/20 µs)
400
W
IEC 61643-321 Current (10/1000 µs)
20
A
IEC 61643-321 Power (10/1000 µs)
180
W
IEC 61000-4-5 Current (8/20 µs)
50
A
IEC 61000-4-5 Power (8/20 µs)
80
W
IEC 61643-321 Current (10/1000 µs)
23
A
W
IEC 61643-321 Power (10/1000 µs)
60
EFT
IEC 61000-4-4 EFT Protection
80
A
IBR
DC Breakdown Current
50
mA
IF
DC Forward Current
500
mA
TA
Ambient Operating Temperature
-40
125
°C
Tstg
Storage Temperature
-65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings - JEDEC
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings - IEC
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2 contact discharge
±24
IEC 61000-4-2 air-gap discharge
±30
UNIT
kV
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VRWM
MIN
NOM
Reverse Stand-off Voltage
5
MAX
UNIT
V
7.5 Thermal Information
TVS0500
THERMAL METRIC (1)
DRV (SON)
UNIT
6 PINS
RqJA
Junction-to-ambient thermal resistance
70.4
°C/W
RqJC(top)
Junction-to-case (top) thermal resistance
73.7
°C/W
RqJB
Junction-to-board thermal resistance
40
°C/W
YJT
Junction-to-top characterization parameter
2.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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Thermal Information (continued)
TVS0500
THERMAL METRIC (1)
DRV (SON)
UNIT
6 PINS
YJB
Junction-to-board characterization parameter
40.3
°C/W
RqJC(bot)
Junction-to-case (bottom) thermal resistance
11
°C/W
7.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ILEAK
Leakage Current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Measured at VIN = VRWM, TA = 27°C
0.07
5.5
nA
Measured at VIN = VRWM, TA = 85°C
6.5
220
nA
Measured at VIN = VRWM, TA = 105°C
38
755
nA
VF
Forward Voltage
IIN = 1 mA from GND to IO
0.25
0.5
0.65
V
VBR
Break-down Voltage
IIN = 1 mA from IO to GND
7.5
7.9
8.4
V
Forward Clamp Voltage
35 A IEC 61000-4-5 Surge (8/20 µs)
from GND to IO, 27°C
2
5
V
24 A IEC 61000-4-5 Surge (8/20 µs)
from IO to GND, VIN = 0 V before surge,
27°C
8.6
8.8
V
43 A IEC 61000-4-5 Surge (8/20 µs) from
IO to GND, VIN = 0 V before surge, 27°C
9.2
9.5
V
35 A IEC 61000-4-5 Surge (8/20 µs)
from IO to GND, VIN = VRWM before
surge, TA = 125°C
9.2
9.5
V
30
50
mΩ
VFCLAMP
VCLAMP
Clamp Voltage
RDYN
8/20 µs surge dynamic resistance
Calculated from VCLAMP at .5*Ipp and Ipp
surge current levels, 27°C
CIN
Input pin capacitance
VIN = 5 V, f = 1 MHz, 30 mVpp, IO to
GND
SR
Maximum Slew Rate
0-VRWM rising edge, sweep rise time and
measure slew rate when IPEAK = 1 mA,
27°C
0-VRWM rising edge, sweep rise time and
measure slew rate when IPEAK = 1 mA,
105°C
6
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155
pF
2.5
V/µs
0.7
V/µs
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45
TVS0500 Voltage
Surge Current
35
30
Voltage (V)
Voltage (V) / Surge Current (A)
40
25
20
15
10
5
0
-5
0
10
20
30
Time (Ps)
40
12
11
10
9
8
7
6
5
4
3
2
1
0
-1
0
50
10
20
D001
Figure 1. 8/20 µs Surge Response at 43 A
30
40
Time (Ps)
50
48
44
40
36
32
28
24
20
16
12
8
4
0
-4
60
D002
Figure 2. 8/20 µs Surge Response at 35 A Across
Temperature
400
200
360
175
320
150
280
Leakage (nA)
Capacitace (pF)
-40°C
Current (A)
25°C
105°C
125°C
Surge Current (A)
7.7 Typical Characteristics
240
200
160
120
80
0
-40
-20
0
20
100
75
50
25
0 V Bias
2.5 V Bias
5 V Vias
40
125
0
-25
-40
40 60 80 100 120 140 160 180
Temperature (°C)
D003
-20
0
20
40
60
80
Temperature (°C)
100
120
140
D004
f = 1 MHz, 30 mVpp, IO to GND
Figure 3. Capacitance vs Temperature Across Bias
Figure 4. Leakage Current vs Temperature at 5 V
0.0012
0.7
-40°C
25°C
105°C
125°C
0.0009
0.6
0.5
0.0003
Voltage (V)
Current (A)
0.0006
0
-0.0003
0.4
0.3
0.2
-0.0006
0.1
-0.0009
-0.0012
-1
0
1
2
3
4
5
Voltage (V)
6
7
8
9
0
-40
D005
Figure 5. I/V Curve Across Temperature
-20
0
20
40
60
80
Temperature (°C)
100
120
140
D006
Figure 6. Forward Voltage vs Temperature
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8.3
8.25
8.2
8.15
8.1
8.05
8
7.95
7.9
7.85
7.8
7.75
7.7
7.65
7.6
7.55
7.5
-40
45
40
35
30
Ipp (A)
Voltage (V)
Typical Characteristics (continued)
25
20
15
10
5
-20
0
20
40
60
80
Temperature (°C)
100
120
0
-50
140
-30
-10
D007
Figure 7. Breakdown Voltage (1 mA) vs Temperature
10
30
50
70
Temperature (°C)
90
110
130
D008
Figure 8. Max Surge Current (8/20 µs) vs Temperature
100
Leakage (-40qC)
Leakage (25qC)
Leakage (85qC)
Leakage (105qC)
Leakage (125qC)
90
Dynamic Leakage (mA)
80
70
60
50
40
30
20
10
0
0
0.3
0.6
0.9
1.2 1.5 1.8 2.1
Slew Rate (V/Ps)
2.4
2.7
3
D009
Figure 9. Dynamic Leakage vs Signal Slew Rate across Temperature
8
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8 Detailed Description
8.1 Overview
The TVS0500 is a precision clamp with a low, flat clamping voltage during transient overvoltage events like surge
and protecting the system with zero voltage overshoot.
8.2 Functional Block Diagram
IN
Voltage Level
Detection
Power FET
Driver
GND
8.3 Feature Description
The TVS0500 is a precision clamp that handles 43 A of IEC 61000-4-5 8/20 µs surge pulse. The flat clamping
feature helps keep the clamping voltage very low to keep the downstream circuits from being stressed. The flat
clamping feature can also help end-equipment designers save cost by opening up the possibility to use lowercost, lower voltage tolerant downstream ICs. The TVS0500 has minimal leakage under the standoff voltage of 5
V, making it an ideal candidate for applications where low leakage and power dissipation is a necessity. IEC
61000-4-2 and IEC 61000-4-4 ratings make it a robust protection solution for ESD and EFT events. Wide
ambient temperature range of –40°C to +125°C a good candidate for most applications. Compact packages
enable it to be used in small devices and save board area.
8.4 Reliability Testing
To ensure device reliability, the TVS0500 is characterized against 5000 repetitive pulses of 35 A IEC 61000-4-5
8/20 µs surge pulses at 125°C. The test is performed with less than 10 seconds between each pulse at high
temperature to simulate worst case scenarios for fault regulation. After each surge pulse, the TVS0500 clamping
voltage, breakdown voltage, and leakage are recorded to ensure that there is no variation or performance
degradation. By ensuring robust, reliable, high temperature protection, the TVS0500 enables fault protection in
applications that must withstand years of continuous operation with no performance change.
8.5 Device Functional Modes
8.5.1 Protection Specifications
The TVS0500 is specified according to both the IEC 61000-4-5 and IEC 61643-321 standards. This enables
usage in systems regardless of which standard is required in relevant product standards or best matches
measured fault conditions. The IEC 61000-4-5 standards requires protection against a pulse with a rise time of 8
µs and a half length of 20 µs, while the IEC 61643-321 standard requires protection against a much longer pulse
with a rise time of 10 µs and a half length of 1000 µs.
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Device Functional Modes (continued)
The positive and negative surges are imposed to the TVS0500 by a combinational waveform generator (CWG)
with a 2-Ω coupling resistor at different peak voltage levels. For powered on transient tests that need power
supply bias, inductances are usually used to decouple the transient stress and protect the power supply. The
TVS0500 is post tested by assuring that there is no shift in device breakdown or leakage at Vrwm.
In addition, the TVS0500 has been tested according to IEC 61000-4-5 to pass a ±2 kV surge test through a 42-Ω
coupling resistor and a 0.5 µF capacitor. This test is a common test requirement for industrial signal I/O lines and
the TVS0500 will serve an ideal protection solution for applications with that requirement.
The TVS0500 allow integrates IEC 61000-4-2 level 4 ESD Protection and 80 A of IEC 61000-4-4 EFT Protection.
These combine to ensure that the device can protect against most transient conditions regardless of length or
type.
For more information on TI's test methods for Surge, ESD, and EFT testing, reference TI's IEC 61000-4-x
Testing Application Note
8.5.2 Minimal Derating
Unlike traditional diodes the TVS0500 has very little derating of max power dissipation and ensures robust
performance up to 125°C, shown in Figure 8. Traditional TVS diodes lose up to 50% of their current carrying
capability when at high temperatures, so a surge pulse above 85°C ambient can cause failures that are not seen
at room temperature. The TVS0500 prevents this and ensures that you will see the same level of protection
regardless of temperature.
8.5.3 Transient Performance
During large transient swings, the TVS0500 will begin clamping the input signal to protect downstream
conditions. While this prevents damage during fault conditions, it can cause leakage when the intended input
signal has a fast slew rate. In order to keep power dissipation low and remove the chance of signal distortion, it
is recommended to keep the slew rate of any input signal on the TVS0500 below 2.5 V/µs at room temperature
and below 0.7 V/µs at 125°C shown in Figure 9. Faster slew rates will cause the device to clamp the input signal
and draw current through the device for a few microseconds, increasing the rise time of the signal. This will not
cause any harm to the system or to the device, however if the fast input voltage swings occur regularly it can
cause device overheating.
10
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TVS0500 can be used to protect any power, analog, or digital signal from transient fault conditions caused
by the environment or other electrical components.
9.2 Typical Application
Connector
IN
TPS768
OUT
B2
IN
TVS0500
GND
A2
Copyright © 2018, Texas Instruments Incorporated
Figure 10. TVS0500 Application Schematic
9.2.1 Design Requirements
A typical operation for the TVS0500 would be protecting a nominal 5 V input to an LDO similar to Figure 10. In
this example, the TVS0500 is protecting the input to a TPS768, a standard 1 A LDO with an input voltage range
of 2.7 V to 10 V. Without any input protection, if a surge event is caused by lightning, coupling, ringing, or any
other fault condition this input voltage will rise to hundreds of volts for multiple microseconds, violating the
absolute maximum input voltage and harming the device. An ideal surge protection diode will maximize the
useable voltage range while still clamping at a safe level for the system, TI's Flat-Clamp technology provides the
best protection solution.
9.2.2 Detailed Design Procedure
If the TVS0500 is in place to protect the device, during a surge event the voltage will rise to the breakdown of the
diode at 7.9 V, and then the TVS0500 will turn on, shunting the surge current to ground. With the low dynamic
resistance of the TVS0500, large amounts of surge current will have minimal impact on the clamping voltage.
The dynamic resistance of the TVS0500 is around 30 mΩ, which means 30 A of surge current will cause a
voltage raise of 30 A × 30 mΩ = 0.9 V. Because the device turns on at 7.9 V, this means the LDO input will be
exposed to a maximum of 7.9 V + 0.9 V = 8.8 V during surge pulses, well within the absolute maximum input
voltage. This ensures robust protection of your circuit.
The small size of the device also improves fault protection by lowering the effect of fault current coupling onto
neighboring traces. The small form factor of the TVS0500 allows the device to be placed extremely close to the
input connector, lowering the length of the path fault current will take through the system compared to larger
protection solutions.
Finally, the low leakage of the TVS0500 will have low input power losses. At 5 V, the device will see typical 70
pA leakage for a constant power dissipation of less than 1 nW, a negligible quantity that will not effect overall
efficiency metrics or add heating concerns.
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Typical Application (continued)
9.2.3 Configuration Options
The TVS0500 can be used in either unidirectional or bidirectional configuration. Figure 10 shows unidirectional
usage to protect an input. By placing two TVS0500's in series with reverse orientation, bidirectional operation can
be used, allowing a working voltage of ±5 V. TVS0500 operation in bidirectional will be similar to unidirectional
operation, with a minor increase in breakdown voltage and clamping voltage. The TVS3300 bidirectional
performance has been characterized in the TVS3300 Configurations Characterization. While the TVS0500 in
bidirectional configuration has not specifically been characterized, it will have similar relative changes to the
TVS3300 in bidirectional configuration.
10 Power Supply Recommendations
The TVS0500 is a clamping device so there is no need to power it. To ensure the device functions properly do
not violate the recommended VIN voltage range (0 V to 5 V) .
12
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11 Layout
11.1 Layout Guidelines
The optimum placement is close to the connector. EMI during an ESD event can couple from the trace being
struck to other nearby unprotected traces, resulting in early system failures. The PCB designer must minimize
the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are
between the TVS and the connector.
Route the protected traces straight.
Eliminate any sharp corners on the protected traces between the TVS0500 and the connector by using rounded
corners with the largest radii possible. Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
GND Plane
I/O
I/O
I/O
Connector
Input
Protected
Input
GND
GND
GND
GND
Figure 11. TVS0500 Layout
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TVS0500
PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TVS0500DRVR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WSON
DRV
6
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
1HRH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TVS0500DRVR
Package Package Pins
Type Drawing
WSON
DRV
6
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
8.4
Pack Materials-Page 1
2.3
B0
(mm)
K0
(mm)
P1
(mm)
2.3
1.15
4.0
W
Pin1
(mm) Quadrant
8.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TVS0500DRVR
WSON
DRV
6
3000
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1 0.1
EXPOSED
THERMAL PAD
3
2X
1.3
4
7
1.6 0.1
6
1
4X 0.65
PIN 1 ID
(OPTIONAL)
6X
6X
0.3
0.2
0.35
0.25
0.1
0.05
C A
C
B
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
(1)
1
7
6
6X (0.3)
(1.6)
SYMM
(1.1)
4X (0.65)
4
3
SYMM
(R0.05) TYP
( 0.2) VIA
TYP
(1.95)
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
1
SYMM
METAL
7
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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